Semiconductor structure and manufacturing method therefor, and electronic device

Abstract

Disclosed in the embodiments of the present application are a semiconductor structure and a manufacturing method therefor, and an electronic device. The semiconductor structure may be a wafer, a bare chip obtained by cutting a wafer, a chip obtained by packaging of a bare chip, etc., and is used for solving the problem of the filling of a conductive material in a substrate being insufficient, and thus expansion being prone to occurring, causing the breakup of a silicon wafer, etc. The semiconductor structure comprises a substrate, a dielectric layer, a protective layer and a conductive column, wherein the dielectric layer is stacked on the substrate; a through hole penetrating the dielectric layer and the substrate is formed in a direction from the dielectric layer to the substrate, and the through hole comprises a first portion formed in the substrate; the protective layer covers part of the inner wall of the first portion that is close to the dielectric layer; and the conductive column is arranged in the through hole and is electrically connected to an electronic element on the dielectric layer. By means of the protective layer, an under cut is prevented from being generated near the side of the first portion that is close to the dielectric layer, so that the problem of the filling of a conductive material in a substrate being insufficient, and thus expansion being prone to occurring, causing the breakup of a silicon wafer, etc., are solved.

Description

Semiconductor structure, manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on August 17, 2023, with application number 202311044401.2 and application name “Semiconductor structure, manufacturing method thereof and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for manufacturing a semiconductor structure, and an electronic device. Background Art

[0003] Taking the chip manufacturing scenario using silicon wafers as substrates as an example, the chip manufacturing process involves etching through silicon vias (TSVs) in the silicon wafer, then depositing an insulating layer (liner), an adhesion layer (barrier) and a seed on the inner wall of the TSV, and finally filling it with conductive material to form conductive columns, which are used to achieve electrical interconnection between electronic components in the chip, and between electronic components and external circuits.

[0004] Figure 1 is a schematic diagram of a TSV etching process. As shown in Figure 1, when the TSV's aspect ratio (the ratio of the TSV's depth in a first direction F1 to its width in a second direction F2) is high, overetching of the silicon wafer in the second direction F2 is likely to occur, leading to an undercut near the interface between the silicon wafer and the dielectric layer. Specifically, if the TSV is divided into a first portion located in the substrate and a second portion located in the dielectric layer, overetching occurs in the second direction F2, manifesting as a smaller bottom critical dimension (BCD) of the second portion than of the top critical dimension (TCD) of the first portion in the second direction F2.

[0005] The existence of the above-mentioned lower gap will, on the one hand, lead to discontinuous deposition of the subsequent insulating layer, adhesion layer and seed, and insufficient filling of the conductive material; on the other hand, during the annealing process after filling the conductive material, the conductive column is prone to expansion, causing the silicon wafer to crack.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a semiconductor structure, a semiconductor structure manufacturing method and an electronic device. The semiconductor structure can be a wafer, a bare chip obtained by cutting the wafer, a chip obtained by packaging the bare chip, etc., which is used to solve the problems of discontinuous deposition of the insulating layer, adhesion layer and seed on the inner wall of the through-hole, insufficient filling of the conductive material, and easy expansion of the conductive column, which causes the silicon wafer to break, etc. due to the lower notch as shown in Figure 1 generated when etching the through-hole in the substrate.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, a semiconductor structure is provided, comprising: a substrate, a dielectric layer, a protective layer, and a conductive pillar. The dielectric layer is stacked on the substrate. A through-hole is provided extending through the dielectric layer and the substrate along a first direction (herein, the first direction is from the dielectric layer to the substrate). The through-hole includes a first portion formed within the substrate. The protective layer covers a portion of the inner wall of the first portion proximate to the dielectric layer. The conductive pillar is disposed in the through-hole and electrically connected to an electronic component on the dielectric layer.

[0010] The presence of the protective layer prevents the formation of a lower notch in the first portion near the dielectric layer. This is because, during the process of etching the through hole in the substrate, before the lower notch is formed, a protective layer is formed on the upper inner wall of the first portion (the inner wall of the groove etched in the substrate will constitute the upper inner wall of the first portion in the subsequently produced finished chip). This layer protects the upper inner wall of the first portion. Subsequently, the substrate is further etched to deepen the groove. If this process is simply described as "etching the substrate and depositing the protective layer before forming the lower notch," then the desired through hole depth can be achieved by repeating this process multiple times. Furthermore, because the protective layer protects the upper inner wall of the first portion, as the etching depth increases during through hole etching in the substrate, the substrate is not overetched across the width of the through hole. Therefore, the formation of a lower notch in the first portion near the dielectric layer is avoided.

[0011] In conjunction with the first aspect, in one possible implementation, the first portion includes a first segment proximate to the dielectric layer and a second segment distal to the dielectric layer and continuous with the first segment; the minimum radial dimension of the first segment is greater than the maximum radial dimension of the second segment. The protective layer covers the inner wall of the first segment, and a surface of the protective layer proximate to the conductive pillar is flush with the inner wall surface of the second segment, thereby forming a continuous surface with the inner wall surface of the second segment.

[0012] In conjunction with the first aspect, in one possible implementation, the second segment has a contact surface facing the dielectric layer at its junction with the first segment; the protective layer is connected to the contact surface on a side proximal to the second segment; the thickness of the protective layer at the junction with the contact surface is equal to the dimension of the contact surface in a second direction; and the second direction is perpendicular to the first direction. This means that the surface of the protective layer proximal to the conductive pillar is flush with the inner wall surface of the second segment, i.e., the surface of the protective layer proximal to the conductive pillar forms a continuous surface with the inner wall surface of the second segment. Accordingly, the radial dimension of the conductive pillar decreases continuously.

[0013] In conjunction with the first aspect, in a possible implementation, the dielectric layer further includes an active region, and the active region includes the electronic component. Furthermore, the semiconductor structure constitutes a chip.

[0014] In combination with the first aspect, in a possible implementation, the semiconductor structure further includes an active layer, which is arranged on the dielectric layer and / or on a side of the substrate away from the dielectric layer; the electronic components connected to the conductive pillars are electronic components in the active layer.

[0015] In conjunction with the first aspect, in one possible implementation, the semiconductor structure further includes a chip disposed on the dielectric layer and / or on a side of the substrate away from the dielectric layer; the electronic components connected to the conductive pillars are electronic components within the chip. Thus, the semiconductor structure constitutes a chip package structure.

[0016] In conjunction with the first aspect, in one possible implementation, the through-hole further includes a second portion formed within the dielectric layer; the inner wall surface of the second portion is flush with the surface of the protective layer on the side near the conductive pillar, thereby forming a continuous surface with the surface of the protective layer on the side near the conductive pillar. Alternatively, the inner wall of the second portion is covered with a second dielectric layer, and the surface of the second dielectric layer on the side near the conductive pillar is flush with the surface of the protective layer on the side near the conductive pillar, thereby forming a continuous surface with the surface of the protective layer on the side near the conductive pillar. This means that the surface of the second dielectric layer on the side near the conductive pillar, the surface of the protective layer on the side near the conductive pillar, and the inner wall of the second section form a continuous surface, that is, there is no lower notch near the junction of the first portion and the second portion. The protective layer and the second dielectric layer can be made of the same material or different materials. The protective layer and the second dielectric layer can be connected as one, that is, there is no observable interface at the connection between the two, or there can be an observable interface.

[0017] From the above, it can be seen that since there is no lower notch near the junction of the first part and the second part, and the protective layer is located between the conductive column and the inner wall of the through hole, that is, before filling the conductive material used to form the conductive column, the surface of the protective layer on one side close to the conductive column has formed a continuous surface with the inner wall surface of the second section, so it can be ensured that the conductive material is fully filled, and then, the quality of the conductive column is guaranteed, and the chip performance is guaranteed.

[0018] In conjunction with the first aspect, in one possible implementation, the aspect ratio of the through-hole is greater than or equal to 10. Because when the aspect ratio of the through-hole is high, it is easy to over-etch the substrate in the second direction, thereby forming a lower notch near the junction of the substrate and the dielectric layer. Therefore, in the chip involved in the embodiment of the present application, the aspect ratio of the through-hole in the substrate is greater than or equal to 10. The chip structure solution involved in the embodiment of the present application is more suitable for application scenarios in which the chip size is large and the through-hole in the substrate has a high aspect ratio.

[0019] In conjunction with the first aspect, in one possible implementation, the radial dimension of the through-hole at a first location is greater than the radial dimension at a second location, and the first location is closer to the dielectric layer than the second location. Since the radial dimension of the through-hole at the first location is greater than or equal to the radial dimension at the second location, the TCD of the first portion is less than or equal to the BCD of the second portion, indicating that there is no lower notch at the junction of the first and second portions.

[0020] In combination with the first aspect, in a possible implementation, along the first direction, the radial dimension of the first part decreases in a gradient manner.

[0021] In conjunction with the first aspect, in one possible implementation, along the first direction, the thickness of the protective layer at a third position is greater than the thickness at a fourth position, and the third position is closer to the dielectric layer than the fourth position. This is because, during the process of etching a through hole in the substrate, depending on the required depth of the through hole, the aforementioned process of "etching the substrate and depositing the protective layer before forming the lower notch" may be repeated multiple times, that is, the protective layer is deposited multiple times on the sidewalls of the etched groove, resulting in the protective layer having a greater thickness closer to the dielectric layer and a smaller thickness farther away from the dielectric layer.

[0022] In combination with the first aspect, in a possible implementation, the semiconductor structure further includes an insulating layer, which covers a continuous surface formed by the protective layer and the inner wall surface of the second segment.

[0023] In conjunction with the first aspect, in one possible implementation, the semiconductor structure further includes an adhesion layer, which covers the insulating layer and is located between the conductive pillar and the insulating layer. In this way, the adhesion layer is located between the insulating layer and the conductive pillar, and serves to bond and fix the conductive pillar.

[0024] In combination with the first aspect, in a possible implementation, the protective layer includes SiCN, SiON, OX, SiN, SiOCN, SiC, or SiOC.

[0025] In combination with the first aspect, in a possible implementation, the insulating layer includes silicon oxide or other organic matter.

[0026] In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, comprising:

[0027] forming a dielectric layer on a substrate; the dielectric layer includes a conductive pattern, the conductive pattern indicating a formation position of the conductive pillar in the substrate;

[0028] According to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, the conductive pillar is prepared in the substrate, and the conductive pillar is electrically connected to the electronic component on the dielectric layer;

[0029] In which, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

[0030] In conjunction with the second aspect, in one possible implementation, the through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion; and preparing the conductive pillar in the substrate according to a formation position of the conductive pillar in the substrate indicated by the conductive pattern includes:

[0031] Etching the substrate along a first direction in an area of ​​the substrate exposed to the second portion to form a first groove in the substrate; the first groove constitutes a first section of the first portion;

[0032] forming a protection layer on the sidewall of the first groove for protecting the sidewall;

[0033] At the bottom wall of the first groove, the substrate is further etched along the first direction to form a second groove in the substrate; the second groove constitutes the second section of the first part;

[0034] A conductive column is formed in a space formed by the first segment and the second segment.

[0035] In combination with the second aspect, in a possible implementation, a protective layer for protecting the sidewalls is formed on the sidewalls of the first groove, including: forming an initial dielectric layer on the inner wall of the first groove; and removing a portion of the initial dielectric layer located on the bottom wall of the first groove.

[0036] In combination with the second aspect, in a possible implementation, a side wall surface of the first groove is flush with an inner wall surface of the second part.

[0037] In combination with the second aspect, in a possible implementation, at the junction of the first groove and the second part, the size of the first groove in the second direction is equal to the size of the second part in the second direction; and the second direction is perpendicular to the first direction.

[0038] In combination with the second aspect, in a possible implementation, a side surface of the protective layer close to the conductive pillar is flush with an inner wall surface of the second groove.

[0039] In combination with the second aspect, in a possible implementation, a minimum radial dimension of the first groove in the second direction is greater than a maximum radial dimension of the second groove in the second direction; and the second direction is perpendicular to the first direction.

[0040] In combination with the second aspect, in one possible implementation, a conductive column is formed in the space formed by the first section and the second section, including: forming an insulating layer on the inner wall surface of the protective layer and the second groove; forming an adhesion layer on the insulating layer; and forming a conductive column in the space after the insulating layer and the adhesive layer are formed.

[0041] In combination with the second aspect, in a possible implementation, forming an initial dielectric layer on the inner wall of the first groove includes: forming an initial dielectric layer on the inner wall of the second part and the inner wall of the first groove.

[0042] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a mainboard; and any one of the above-mentioned semiconductor structures electrically connected to the mainboard.

[0043] Among them, the technical effects brought about by any design method in the second to third aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of a through silicon via etching process;

[0045] FIG2 is a perspective schematic diagram of an electronic device provided in an embodiment of the present application;

[0046] FIG3 is an exploded view of an electronic device provided in an embodiment of the present application;

[0047] FIG4 is a schematic structural diagram of a chip packaging structure and a mainboard in an electronic device provided in an embodiment of the present application;

[0048] FIG5 is a schematic diagram of a chip packaging structure in an electronic device provided by an embodiment of the present application;

[0049] FIG6 is a schematic diagram of a chip provided in an embodiment of the present application;

[0050] FIG7 is a schematic diagram of another chip provided in an embodiment of the present application;

[0051] FIG8 is an exploded schematic diagram of a chip provided in an embodiment of the present application;

[0052] FIG9 is a schematic diagram of another chip provided in an embodiment of the present application;

[0053] FIG10 is a schematic diagram of a process for manufacturing a semiconductor structure according to an embodiment of the present application;

[0054] FIG11 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0055] FIG12 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0056] FIG13 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0057] FIG14 is a flow chart of another method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0058] FIG15 is another schematic diagram of a process for manufacturing a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0060] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0061] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0062] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0063] In addition, the business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0064] To address the issue of lower notches during TSV etching, as discussed in the background, related technologies, such as the Bosch process, decompose the macro-etching process into multiple cycles of micro-etching. Each cycle includes two steps: etching the silicon wafer and depositing a protective layer on the sidewalls of the etched grooves. While the macro-etching duration remains constant, the greater the number of cycles, the shorter the etching time per cycle. This shortens the etching time per cycle, while also utilizing the protective layer (e.g., carbon tetrafluoride) to protect the sidewalls of the etched grooves. This prevents excessive etching across the width of the TSV, thereby preventing the formation of lower notches.

[0065] However, due to the limitations of machine capabilities, the above solution is only applicable to the TSV etching process with a small aspect ratio, that is, the optimization space is small. When the aspect ratio is large, the formation of the lower gap cannot be completely avoided.

[0066] In view of this, embodiments of the present application provide a semiconductor structure and an electronic device including the semiconductor structure.

[0067] In some application scenarios, the semiconductor structure mentioned herein may be a wafer, a bare chip obtained by dicing the wafer, a chip obtained by packaging the bare chip, and the like. Because the TSVs in the substrate of this semiconductor structure do not have the lower notch shown in FIG1 , the insulating layer, adhesion layer, and seed layer deposited on the inner wall of the TSV are smooth and continuous, and the TSVs are fully filled with conductive material, ensuring the functionality of the semiconductor structure and electronic device.

[0068] The above-mentioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communication technology (CT), such as servers, optical communication equipment, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, notebook computers, vehicle-mounted devices, wearable devices, augmented reality (AR) glasses, AR helmets, virtual reality (VR) glasses or VR helmets, etc., which require data processing / storage / transmission and reception. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic devices. For the sake of convenience of explanation, the following examples are all taken as examples of the electronic device being a mobile phone as shown in Figure 2.

[0069] Figure 2 is a perspective view of an electronic device provided in some embodiments of the present application, and Figure 3 is an exploded view of the electronic device shown in Figure 2 . Referring to Figures 2 and 3 , electronic device 1000 is a mobile phone. Electronic device 1000 may include a screen 100, a middle frame 200, a rear housing 300, and a motherboard 400 secured to the middle frame 200, as shown in Figure 2 .

[0070] It should be understood that Figures 2 and 3 merely illustrate some components included in the electronic device 1000, and the actual shape, size, position, and configuration of these components are not limited by Figures 2 and 3. For example, in other examples, the electronic device 1000 may not include the screen 100. Alternatively, the electronic device 1000 may also include the camera 500 shown in Figure 2.

[0071] In the embodiment of the present application, the electronic device 1000 further includes a chip packaging structure 600 as shown in FIG4 . The chip packaging structure mentioned in the embodiment of the present application may also be referred to as an integrated circuit. As shown in FIG4 , the chip packaging structure 600 is disposed on the mainboard 400 and is electrically connected to the mainboard 400. For example, the chip packaging structure 600 can be electrically connected to the mainboard 400 via a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, thereby enabling the chip packaging structure 600 to transmit signals to other devices or device stacking structures on the mainboard 400.

[0072] It should be noted that the mainboard 400 may be a printed circuit board (PCB). The number of chip packaging structures 600 on the mainboard 400 may be one, two, or more than two, which is not limited in this application.

[0073] To facilitate the following description, some of the figures illustrating the embodiments of this application illustrate a three-dimensional coordinate system, namely, an X, Y, and Z coordinate system. Referring to Figure 4 , the plane on which the motherboard 400 resides is the XY plane. Taking the rectangular motherboard 400 shown in Figure 4 as an example, the X-axis can be the length of the motherboard 400, the Y-axis can be the width of the motherboard 400, and the Z-axis can be perpendicular to, or approximately perpendicular to, the motherboard 400 within manufacturing tolerances. It is understood that the width of the motherboard 400 is smaller than its length.

[0074] In different application scenarios, the semiconductor structure provided in the embodiments of the present application can be a chip package structure as shown in Figure 4, or a chip in the chip package structure as shown in Figure 4. The following first introduces a specific embodiment in which the semiconductor structure is a chip, and then introduces a specific embodiment in which the semiconductor structure is a chip package structure.

[0075] Referring to Figure 5, a chip package structure 600 includes a substrate 1 and a chip 2 disposed on the substrate 1. The substrate 1 is located between the mainboard 400 and the chip 2. The substrate 1 includes a wiring layer, and the chip 2 is electrically connected to the wiring layer. The chip 2 can be a bare chip (i.e., a single die) or a chip stack structure (i.e., multiple bare dies are stacked). This application does not limit the number of chips 2 in the chip package structure 600. The number of chips in the chip package structure 600 can be one or more.

[0076] The semiconductor structure provided in the embodiments of the present application may be the aforementioned chip 2. Specifically, the chip 2 may be a processing chip having a data processing function, such as a central processing unit (CPU), a system on chip (SOC), or a graphics processing unit (GPU). The aforementioned memory may be a random access memory (RAM) or a read-only memory (ROM).

[0077] Referring to Figure 6, the chip 2 includes a substrate 21, a dielectric layer 22, a protective layer 23, a conductive column 24, and an electronic component 25. The dielectric layer 22 is stacked on the substrate 21. Along the first direction F1 (the first direction here is the direction from the dielectric layer 22 to the substrate 21), there is a through hole that penetrates the dielectric layer 22 and the substrate 21. In the following content, in order to facilitate the description of the structure of the chip 2, the through hole is divided into a first part formed in the substrate and a second part formed in the dielectric layer. At the same time, the inner wall of the first part close to the dielectric layer is referred to as the upper inner wall. The protective layer 23 covers the upper inner wall of the first part. The conductive column 24 is arranged in the through hole and is electrically connected to the electronic component 25.

[0078] In chip 2 shown in Figure 6, the presence of protective layer 23 prevents the TCD of the first portion from being greater than the BCD of the second portion, thereby preventing the formation of a lower notch near the junction of the first and second portions. This is because, during the process of etching the through hole in substrate 21, before the lower notch is formed, protective layer 23 is formed on the upper inner wall of the first portion (the inner wall of the groove etched in substrate 21 will constitute the upper inner wall of the first portion in the subsequent finished chip). This protects the upper inner wall of the first portion. Subsequently, substrate 21 is further etched to deepen the groove. In the following description, this process is simply described as multiple cycles of "etching the substrate and depositing the protective layer before forming the lower notch" until the through hole depth meets the process requirements. Because protective layer 23 protects the upper inner wall of the first portion, as the etching depth increases during the through hole etching process in substrate 21, the substrate 21 is not overetched across the width of the through hole. Therefore, it is possible to avoid the TCD of the first portion being greater than the BCD of the second portion, that is, to avoid the lower gap being generated near the boundary between the first portion and the second portion.

[0079] In a possible implementation, the dielectric layer may further include an active region, and the electronic component 25 is an active device in the active region, as shown in FIG6 .

[0080] In another possible implementation, the chip 2 further includes an active layer 26, which is disposed on a side of the substrate 21 away from the dielectric layer 22. The electronic component 25 is an active device in the active layer 26, as shown in FIG7 . In another possible implementation, the active layer 26 may also be disposed on the dielectric layer 22. In another possible implementation, the active layer may be disposed on both the side of the substrate 21 away from the dielectric layer 22 and on the dielectric layer 22.

[0081] Of course, in other possible implementations, the electronic component 25 may also be a passive device, or other electronic devices, such as a power module.

[0082] In some embodiments, the radial dimension of the first portion decreases gradually along the first direction F1. Still taking the chip structure shown in FIG6 or FIG7 as an example, if the first portion is divided into a first segment close to the dielectric layer 22 and a second segment farther from the dielectric layer 22 and connected to the first segment, then the minimum radial dimension of the first segment is greater than the maximum radial dimension of the second segment. In other words, in the second direction F2 (a direction perpendicular to the first direction F1), the size of the first segment is greater than the size of the second segment.

[0083] Based on the above embodiment, the upper inner wall of the first part can specifically be the inner wall of the first section, and the protective layer 23 covers the inner wall of the first section. In addition, the side surface of the protective layer 23 close to the conductive column 24 is flush with the inner wall surface of the second section, thereby forming a continuous surface with the inner wall surface of the second section. Figure 8 is a decomposed schematic diagram of the chip shown in Figure 6. As a possible implementation method, the second section has a contact surface facing the dielectric layer 22 at the junction with the first section. The thickness of the protective layer 23 at the connection with the contact surface is equal to the size of the contact surface in the second direction. This means that the side surface of the protective layer close to the conductive column 24 is flush with the inner wall surface of the second section, which means that the side surface of the protective layer 23 close to the conductive column 24 forms a continuous surface with the inner wall surface of the second section. Accordingly, the radial size of the conductive column 24 decreases continuously.

[0084] Based on the above embodiment, the inner wall surface of the second part is flush with the surface of the side of the protective layer 23 close to the conductive column 24, thereby forming a continuous surface with the surface of the side of the protective layer 23 close to the conductive column 24. Alternatively, as shown in Figure 9, the protective layer 23 also covers the inner wall of the second part, which means that the surface of the side of the protective layer 23 close to the conductive column 24 forms a continuous surface with the inner wall of the second section, that is, there is no lower gap near the junction of the first part and the second part. Among them, the protective layer 23 and the dielectric layer 22 can be composed of the same material, or they can be composed of different materials. When the protective layer 23 and the dielectric layer 22 are composed of the same material, the part of the protective layer 23 covering the inner wall of the second part can be connected to the inner wall of the second part as a whole, that is, there is no observable interface at the connection between the two, or there can be an observable interface.

[0085] It can be seen from the above embodiments that since there is no lower notch near the junction of the first part and the second part, and the protective layer 23 is located between the conductive column 24 and the inner wall of the through hole, that is, before filling the conductive material used to form the conductive column 24, the side surface of the protective layer 23 close to the conductive column 24 has formed a continuous surface with the inner wall surface of the second section, so that the conductive material can be fully filled, thereby ensuring the quality of the conductive column 24 and the chip performance.

[0086] In some embodiments, the aspect ratio of the through hole is greater than or equal to 10. As described in the background art, when the aspect ratio of the through hole is high, it is easy to over-etch the substrate 21 in the second direction, thereby generating a lower notch near the junction of the substrate 21 and the dielectric layer 22. Therefore, in the chip involved in the embodiment of the present application, the aspect ratio of the through hole in the substrate 21 is greater than or equal to 10. The chip structure solution involved in the embodiment of the present application is more suitable for application scenarios in which the chip size is large and the through hole in the substrate has a high aspect ratio.

[0087] In some embodiments, the radial dimension of the through-hole at a first location is greater than the radial dimension at a second location, and the first location is closer to the dielectric layer than the second location. Generally, if a lower notch is generated near the junction of the first and second portions during chip manufacturing, this means that the TCD of the first portion is greater than the BCD of the second portion. However, in the embodiments of the present application, since the radial dimension of the through-hole at the first location is greater than or equal to the radial dimension at the second location, this means that the TCD of the first portion is less than or equal to the BCD of the second portion, indicating that there is no lower notch at the junction of the first and second portions.

[0088] In some embodiments, along the first direction, the thickness of the protective layer 23 at a third position is greater than the thickness at a fourth position, and the third position is closer to the dielectric layer 22 than the fourth position. In other words, along the first direction, the thickness of the protective layer 23 tends to decrease. This is because, during the process of etching a through hole in the substrate 21, depending on the depth requirement of the through hole, the above-mentioned process of "etching the substrate and depositing the protective layer before forming the lower notch" may be repeated multiple times. In other words, as shown in FIG10 , the dielectric may be deposited multiple times on the sidewalls of the etched groove, thereby causing the protective layer 23 to have a greater thickness the closer it is to the dielectric layer 22 and a smaller thickness the further away it is from the dielectric layer 22.

[0089] In some embodiments, the protective layer 23 also covers the inner wall of the second section, and, along the first direction, the thickness of the protective layer 23 at a third position is greater than the thickness at a fourth position, with the third position being closer to the dielectric layer 22 than the fourth position. This is because, during the chip manufacturing process, before filling with conductive material, an insulating layer and an adhesive layer may be sequentially formed on the "continuous surface formed by the surface of the protective layer near the conductive pillar and the inner wall of the second section." When the insulating layer, adhesive layer, and protective layer are made of the same material, the resulting chip structurally exhibits a protective layer 23 covering the entire inner wall of the second portion, that is, covering both the inner walls of the first section and the inner walls of the second section, with its thickness decreasing along the first direction.

[0090] In some embodiments, the continuous surface formed by the protective layer 23 and the inner wall surface of the second section is covered with an insulating layer, and the insulating layer is further covered with an adhesive layer. In this way, the adhesive layer is located between the insulating layer and the conductive pillars to bond and fix the conductive pillars.

[0091] In the above embodiment, the protective layer includes any one of a multi-element system material such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxide (OX), silicon nitride (SiN), silicon oxycarbon nitride (SiOCN), silicon carbide (SiC), and silicon oxycarbon (SiOC). The insulating layer includes silicon oxide or other organic materials, such as various resins. The adhesion layer includes a metal or a metal compound, such as TaN or TiN.

[0092] Please refer to Figure 11. In combination with the above embodiments, the semiconductor structure provided in other embodiments may include: a substrate 21, a dielectric layer 22, a protective layer 23, a conductive pillar 24 and a chip 27. Among them, the specific implementation of the substrate 21, the dielectric layer 22, the protective layer 23, and the conductive pillar 24 can refer to the embodiment of the above chip 2 and will not be repeated here. The chip 27 can be the chip 2 provided in the above embodiment of the present application, or it can be a chip of other structures. The chip 27 can be arranged on the dielectric layer 22 as shown in Figure 11, or it can be arranged on the side of the substrate 21 away from the dielectric layer 22 as shown in Figure 12. Multiple chips can also be arranged on the dielectric layer 22 and on the side of the substrate 21 away from the dielectric layer 22 respectively. Generally, in the implementation shown in Figure 11, a wiring layer 28 can be provided on the side of the substrate 21 away from the dielectric layer 22, and the chip 27 is provided on the wiring layer 28. The conductive pillar 24 can be electrically connected to the circuit in the wiring layer 28, and then electrically connected to the chip 27 through the circuit in the wiring layer 28. In the implementation shown in FIG. 11 and FIG. 12 , the semiconductor structure is specifically a chip packaging structure, wherein the substrate 21 , the dielectric layer 22 , the protective layer 23 , the conductive pillars 24 and the wiring layer 28 constitute a base plate for packaging the chip 27 .

[0093] The present application also provides a method for manufacturing a semiconductor structure, as shown in FIG13 . The method may include:

[0094] S100, forming a dielectric layer on a substrate, wherein the dielectric layer includes a conductive pattern, and the conductive pattern indicates a formation position of a conductive pillar in the substrate.

[0095] In some embodiments, a dielectric layer is first formed on a substrate, and then the exposed conductive pattern is transferred to the dielectric layer through a dielectric etching chamber to form a mask for silicon.

[0096] In some embodiments, the dielectric layer also includes an active region, in which electronic devices are formed. In S100, a dielectric layer is first formed on a substrate, and then active devices are fabricated in the dielectric layer to form the active region. The exposed conductive pattern is then transferred to the active layer through a dielectric etching chamber to form a mask for silicon.

[0097] S200: According to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, a conductive pillar is prepared in the substrate, and the conductive pillar is electrically connected to the electronic component on the dielectric layer.

[0098] In which, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

[0099] In some embodiments, the through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion.

[0100] As shown in FIG. 14 and FIG. 15 , the above-mentioned step S200 , preparing the conductive pillars in the substrate according to the formation positions of the conductive pillars in the substrate indicated by the conductive pattern, may specifically include:

[0101] S201, etching the substrate along a first direction in the area of ​​the substrate exposed to the second part to form a first groove in the substrate. The first groove subsequently constitutes the first section of the first part mentioned in the above chip structure embodiment.

[0102] In some embodiments, a sidewall surface of the first groove is flush with an inner wall surface of the second portion.

[0103] In some embodiments, at a junction between the first groove and the second portion, a size of the first groove in the second direction is equal to a size of the second portion in the second direction.

[0104] S202 , forming a protection layer on the sidewall of the first groove for protecting the sidewall.

[0105] Specifically, an initial dielectric layer is first formed on the inner wall of the first groove, and then the portion of the initial dielectric layer located on the bottom wall of the first groove is removed. The initial dielectric layer remaining on the sidewall of the first groove is the protective layer.

[0106] In some possible implementations, forming the initial dielectric layer on the inner wall of the first groove specifically includes: forming the initial dielectric layer on the inner wall of the second portion and the inner wall of the first groove.

[0107] S203: Continue etching the substrate along the first direction at the bottom wall of the first groove to form a second groove in the substrate. The first groove subsequently constitutes the second section of the first part mentioned in the above chip structure embodiment.

[0108] In some embodiments, a surface of the protection layer away from the inner wall of the substrate is flush with the inner wall surface of the second groove.

[0109] In some embodiments, a minimum radial dimension of the first groove in the second direction is greater than a maximum radial dimension of the second groove in the second direction.

[0110] It should be noted that S202 and S203 above constitute one cycle of "etching the substrate and depositing a protective layer before forming the lower notch" mentioned in the above chip structure embodiment. Depending on the required through-hole depth, this process may be repeated multiple times until the through-hole reaches the desired depth.

[0111] S204: forming a conductive column in the etched inner space of the substrate. The inner space of the substrate here is the space formed by the first section and the second section, or the space formed by the first groove connecting the second groove.

[0112] Specifically, an insulating layer is first formed on the protective layer and the inner wall surface of the second groove; an adhesive layer is then formed on the insulating layer; the space between the insulating layer and the adhesive layer is then filled with a conductive material and subjected to annealing and other treatments to form a conductive pillar. Finally, the side of the substrate away from the dielectric layer is polished to ensure that the dimensions of the conductive pillar along the first direction meet process requirements and that the end away from the dielectric layer is exposed outside the substrate.

[0113] Through the above S100 and S200 , the semiconductor structure shown in FIG. 6 can be obtained.

[0114] In some embodiments, the method for manufacturing the semiconductor structure further includes: forming an active layer on a side of the substrate away from the dielectric layer, and electrically connecting the electronic components in the active layer to the conductive pillars.

[0115] Through the above manufacturing method, the semiconductor structure shown in FIG. 7 can be obtained.

[0116] In some embodiments, the method for manufacturing the semiconductor structure further includes: mounting a chip on the dielectric layer and / or on a side of the substrate away from the dielectric layer.

[0117] In one possible process implementation, a wiring layer is first formed on the side of the substrate away from the dielectric layer, and the circuitry in the wiring layer is electrically connected to the conductive pillars. A chip is then mounted on the wiring layer and electrically connected to the circuitry in the wiring layer. In this way, the chip and the conductive pillars are electrically connected through the wiring layer, resulting in the chip package structure shown in Figure 12.

[0118] As can be seen from the above manufacturing method, during the process of etching a through hole in the substrate, before the lower notch is formed, a protective layer is formed on the upper inner wall of the first portion (the inner wall of the groove etched in the substrate will constitute the upper inner wall of the first portion in the subsequently produced finished chip) to protect the upper inner wall of the first portion. Subsequently, the substrate is further etched to deepen the groove. If this process is simply described as "etching the substrate and depositing the protective layer before forming the lower notch," then by repeating this process multiple times, the required through hole depth can be achieved. Furthermore, because the protective layer protects the upper inner wall of the first portion, as the etching depth increases during the through hole etching process, the substrate is not overetched across the width of the through hole. Therefore, the TCD of the first portion is prevented from being greater than the BCD of the second portion, thereby preventing the formation of a lower notch near the junction of the first and second portions.

[0119] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0120] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A dielectric layer is stacked on the substrate; along a first direction, there is a through hole penetrating the dielectric layer and the substrate, the through hole includes a first part formed in the substrate; the first direction is the direction from the dielectric layer to the substrate; A protective layer covering a portion of the inner wall of the first part close to the dielectric layer; A conductive column, disposed in the through hole; The electronic component is electrically connected to the conductive column.

2. The semiconductor structure according to claim 1, characterized in that: The first part includes a first segment close to the dielectric layer and a second segment far from the dielectric layer and continuous with the first segment; the minimum radial dimension of the first segment is greater than the maximum radial dimension of the second segment; The protective layer covers the inner wall of the first section; and a surface of one side of the protective layer close to the conductive column is flush with the inner wall surface of the second section.

3. The semiconductor structure according to claim 2, characterized in that: The second section has a contact surface facing the dielectric layer at the junction with the first section; The side of the protective layer close to the second section is connected to the contact surface; the thickness of the protective layer at the connection with the contact surface is equal to the size of the contact surface in the second direction; the second direction is a direction perpendicular to the first direction.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The dielectric layer also includes an active region, and the active region includes the electronic component.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure further comprises: An active layer is arranged on the dielectric layer and / or on a side of the substrate away from the dielectric layer; the active layer includes the electronic component.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The semiconductor structure further comprises: A chip, arranged on the dielectric layer and / or on a side of the substrate away from the dielectric layer; The chip includes the electronic component.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The aspect ratio of the through hole is greater than or equal to 10:

1.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: A radial dimension of the through hole at a first position is greater than a radial dimension of the through hole at a second position, and the first position is closer to the dielectric layer than the second position.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: Along the first direction, the radial dimension of the conductive column decreases continuously.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that: Along the first direction, the radial dimension of the first part decreases gradually.

11. The semiconductor structure according to any one of claims 1 to 10, characterized in that: Along the first direction, the thickness of the protection layer at a third position is greater than the thickness at a fourth position, and the third position is closer to the dielectric layer than the fourth position.

12. The semiconductor structure according to any one of claims 1 to 11, characterized in that: The through hole further includes a second portion formed in the dielectric layer; an inner wall surface of the second portion is flush with a surface of one side of the protection layer close to the conductive column.

13. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The through hole further includes a second portion formed in the dielectric layer; the protection layer further covers an inner wall of the second portion.

14. The semiconductor structure according to claim 2 or 3, characterized in that: Also includes: An insulating layer covers a continuous surface formed by the protective layer and the inner wall surface of the second section.

15. The semiconductor structure according to claim 14, characterized in that: Also includes: The adhesion layer covers the insulating layer and is located between the conductive pillar and the insulating layer.

16. The semiconductor structure according to any one of claims 1 to 15, characterized in that: The protective layer includes silicon carbon nitride SiCN, silicon oxynitride SiON, silicon oxide OX, silicon nitride SiN, silicon oxycarbon nitride SiOCN, silicon carbide SiC or silicon oxycarbon SiOC.

17. The semiconductor structure according to any one of claims 14 to 15, characterized in that: The insulating layer includes silicon dioxide or other organic matter.

18. A method for manufacturing a semiconductor structure, characterized in that: include: forming a dielectric layer on a substrate; The dielectric layer includes a conductive pattern, the conductive pattern indicating a formation position of a conductive pillar in the substrate; According to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, the conductive pillar is prepared in the substrate, and the conductive pillar is placed in the substrate. The conductive pillars are electrically connected to the electronic components on the dielectric layer; Wherein, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; a portion of the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

19. The method for manufacturing a semiconductor structure according to claim 18, wherein: The through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion; The forming position of the conductive pillar in the substrate according to the conductive pattern indicates that the conductive pillar is formed in the substrate, and the conductive pillar is prepared in the substrate, comprising: In the area of ​​the substrate exposed to the second part, the substrate is etched along the first direction to form a first groove in the substrate; the first groove constitutes a first section of the first part; forming a protection layer on the sidewall of the first groove for protecting the sidewall; At the bottom wall of the first groove, the substrate is further etched along the first direction to form a second groove in the substrate; the second groove constitutes a second section of the first part; The conductive column is formed in a space formed by the first segment and the second segment.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein: The step of forming a protection layer on the sidewall of the first groove for protecting the sidewall comprises: forming an initial dielectric layer on an inner wall of the first groove; A portion of the initial dielectric layer located on the bottom wall of the first groove is removed.

21. The method for manufacturing a semiconductor structure according to claim 19, wherein: The side wall surface of the first groove is flush with the inner wall surface of the second portion.

22. The method for manufacturing a semiconductor structure according to claim 19, wherein: At the junction of the first groove and the second part, the size of the first groove in the second direction is equal to the size of the second part in the second direction; the second direction is perpendicular to the first direction.

23. The method for manufacturing a semiconductor structure according to claim 19, wherein: A side surface of the protection layer close to the conductive column is flush with an inner wall surface of the second groove.

24. The method for manufacturing a semiconductor structure according to claim 19, wherein: The minimum radial dimension of the first groove in the second direction is greater than the maximum radial dimension of the second groove in the second direction; and the second direction is perpendicular to the first direction.

25. The method for manufacturing a semiconductor structure according to claim 19, wherein: The forming of the conductive column in the space formed by the first segment and the second segment comprises: forming an insulating layer on the protective layer and the inner wall surface of the second groove; forming an adhesive layer on the insulating layer; The conductive column is formed in the space after the insulating layer and the adhesive layer are formed.

26. The method for manufacturing a semiconductor structure according to claim 20, wherein: The forming of an initial dielectric layer on the inner wall of the first groove comprises: The initial dielectric layer is formed on the inner wall of the second portion and the inner wall of the first groove.

27. An electronic device, characterized in that: include: Motherboard; A semiconductor structure as claimed in any one of claims 1 to 17 electrically connected to the mainboard.

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