Electronic component–embedded substrate
Patent Information
- Application Number
- PCT/JP2024/022980
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-08-11
- Filing Date
- 2024-06-25
- Publication Date
- 2025-02-20
Smart Images

Figure JP2024022980_20022025_PF_FP_ABST
Abstract
Description
Electronic component embedded board
[0001] The present disclosure relates to a substrate with built-in electronic components, and more particularly to a substrate with built-in electronic components having terminal electrodes on the front and back surfaces embedded therein.
[0002] Patent Document 1 discloses a substrate with built-in electronic components, which has a structure in which electronic components having terminal electrodes on the front and back sides are embedded.
[0003] Japanese Patent Application Laid-Open No. 2020-031082
[0004] Terminal electrodes provided on the front and back surfaces of the electronic component are connected to conductor layers included in the substrate through via conductors.
[0005] This disclosure describes a technique for improving the reliability of an electronic component built-in substrate in which an electronic component having terminal electrodes on its front and back surfaces is embedded.
[0006] An electronic component-embedded substrate according to one aspect of the present disclosure includes a core layer having a first main surface, a second main surface opposite the first main surface, and a through hole formed from the first main surface to the second main surface; an electronic component housed in the through hole and having an element part having a third main surface and a fourth main surface opposite the third main surface; a first insulating resin layer covering the first main surface of the core layer and the third main surface of the element part; a second insulating resin layer covering the second main surface of the core layer and the fourth main surface of the element part; a first conductor layer covering, via the first insulating resin layer, at least a portion of the first main surface of the core layer and at least a portion of the third main surface of the element part; and a second insulating resin layer covering, via the second insulating resin layer, at least a portion of the second main surface of the core layer and at least a portion of the fourth main surface of the element part. and a second conductor layer covering the base portion, wherein the electronic component further has a first coil conductor pattern embedded in the base portion, a first terminal electrode electrically connected to one end of the first coil conductor pattern and exposed from the third main surface, and a second terminal electrode electrically connected to the other end of the first coil conductor pattern and exposed from the fourth main surface, wherein the first terminal electrode is connected to the first conductor pattern included in the first conductor layer through a first via conductor provided to penetrate the first insulating resin layer, and the second terminal electrode is connected to the second conductor pattern included in the second conductor layer through a second via conductor provided to penetrate the second insulating resin layer, and the first terminal electrode and the second terminal electrode do not overlap in a plan view.
[0007] According to the present disclosure, a technique for improving the reliability of an electronic component built-in substrate in which an electronic component having terminal electrodes on its front and back surfaces is embedded is provided.
[0008] FIG. 1 is a schematic cross-sectional view of an electronic component built-in substrate 100 according to an embodiment of the technology disclosed herein. FIG. 2 is a schematic perspective view showing the appearance of the electronic component 10. FIGS. 3(a) to 3(e) are schematic plan views showing the pattern shapes of conductor patterns embedded in the element body portion 20. FIGS. 4(a) to 4(d) are schematic plan views showing examples of the pattern shapes of conductor layers L1 to L4, respectively. FIGS. 5(a) to 5(d) are process diagrams for explaining a method for manufacturing the electronic component built-in substrate 100. FIGS. 6(a) to 6(c) are process diagrams for explaining a method for manufacturing the electronic component built-in substrate 100.
[0009] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.
[0010] FIG. 1 is a schematic cross-sectional view of an electronic component built-in substrate 100 according to an embodiment of the technology disclosed herein.
[0011] The electronic component-embedded substrate 100 of the example shown in FIG. 1 includes a core layer 110 having a through hole 113, an insulating resin layer 121 provided on one main surface 111 of the core layer 110, and an insulating resin layer 122 provided on the other main surface 112 of the core layer 110. The core layer 110 is a high-strength insulating layer in which a core material such as glass cloth is impregnated with a resin material. In contrast, the insulating resin layers 121 and 122 are insulating layers made of a resin material that does not contain a core material such as glass cloth and are highly flexible. An electronic component 10 is housed in the through hole 113.
[0012] FIG. 2 is a schematic perspective view showing the appearance of the electronic component 10. As shown in FIG.
[0013] The electronic component 10 shown in FIG. 2 includes an element body 20 and terminal electrodes 31-34 exposed from the element body 20. The element body 20 may be made of a composite magnetic material in which a magnetic filler made of a high-permeability material such as ferrite or permalloy is solidified with a resin binder. The element body 20 has opposing main surfaces 21 and 22, opposing side surfaces 23 and 24, and opposing side surfaces 25 and 26. For ease of explanation, in the embodiment shown in FIG. 2, the direction from the main surface 22 toward the main surface 21 is referred to as the Z direction, the direction from the side surface 24 toward the side edge 23 is referred to as the X direction, and the direction from the side surface 25 toward the side surface 26 is referred to as the Y direction. The main surfaces 21 and 22 form an XY plane, the side surfaces 23 and 24 form a YZ plane, and the side surfaces 25 and 26 form an XZ plane.
[0014] Terminal electrode 31 may be exposed in the plane of main surface 21 of element body part 20 at a position offset in the X direction to the vicinity of side surface 23 and offset in the Y direction to the vicinity of side surface 26. Terminal electrode 32 may be exposed in the plane of main surface 22 of element body part 20 at a position offset in the X direction slightly from approximately the center toward side surface 23 and offset in the Y direction to the vicinity of side surface 26. Terminal electrode 33 may be exposed in the plane of main surface 21 of element body part 20 at a position offset in the X direction to the vicinity of side surface 24 and offset in the Y direction to the vicinity of side surface 25. Terminal electrode 34 may be exposed in the plane of main surface 22 of element body part 20 at a position offset in the X direction slightly from approximately the center toward side surface 24 and offset in the Y direction to the vicinity of side surface 25.
[0015] 2, terminal electrodes 31 and 32 do not overlap in plan view from the Z direction, and terminal electrodes 33 and 34 do not overlap in plan view from the Z direction. Terminal electrodes 31 and 34 also do not overlap in plan view, and terminal electrodes 33 and 32 also do not overlap in plan view. In FIG. 1, terminal electrodes 31 and 32 are shown overlapping, and terminal electrodes 33 and 34 are shown overlapping, but FIG. 1 is a schematic diagram, and as shown in FIG. 2, terminal electrodes 31 and 32 do not actually overlap, and terminal electrodes 33 and 34 do not actually overlap, either.
[0016] 3(a) to 3(e) are schematic plan views showing the pattern shapes of the conductor patterns embedded in the element body 20. FIG.
[0017] 3( a) to 3(e), three conductor layers M2 to M4 are embedded inside the element body 20, with the conductor layer M1 exposed on the main surface 21 of the element body 20 and the conductor layer M5 exposed on the main surface 22 of the element body 20. In the example shown in Figures 3(a) to 3(e), the conductor layer M1 includes terminal electrodes 31 and 33, the conductor layer M2 includes coil conductor patterns 41 and 51, the conductor layer M3 includes coil conductor patterns 42 and 52, the conductor layer M4 includes coil conductor patterns 43 and 53, and the conductor layer M5 includes terminal electrodes 32 and 34. The terminal electrodes 31 and 33 are connected to one ends of the coil conductor patterns 41 and 51 via via conductors 61 and 71, respectively. The other ends of the coil conductor patterns 41 and 51 are connected to one ends of the coil conductor patterns 42 and 52 via via conductors 62 and 72, respectively. The other ends of the coil conductor patterns 42 and 52 are connected to one ends of the coil conductor patterns 43 and 53 via via conductors 63 and 73. The other ends of the coil conductor patterns 43 and 53 are connected to the terminal electrodes 32 and 34 via via conductors 64 and 74, respectively.
[0018] With this configuration, the coil conductor patterns 41 to 43 are connected in series between the terminal electrodes 31 and 32, and the coil conductor patterns 51 to 53 are connected in series between the terminal electrodes 33 and 34. In other words, the electronic component 10 according to this embodiment has a configuration in which two independent coil conductor patterns are embedded in the element body part 20, with the terminal electrodes 31 and 33 constituting one ends of the two coil conductor patterns exposed on the main surface 21 of the element body part 20, and the terminal electrodes 32 and 34 constituting the other ends of the two coil conductor patterns exposed on the main surface 22 of the element body part 20.
[0019] In the example shown in Figure 1, the electronic component 10 is housed in the through hole 113 of the core layer 110 so that the main surface 21 of the body portion 20 and the terminal electrodes 31, 33 are covered with the insulating resin layer 121, and the main surface 22 of the body portion 20 and the terminal electrodes 32, 34 are covered with the insulating resin layer 122.
[0020] In the example shown in FIG. 1 , insulating resin layer 121 is thicker than insulating resin layer 122. Furthermore, in the example shown in FIG. 1 , the thickness of electronic component 10 in the Z direction is thicker than the thickness of core layer 110 in the Z direction, and main surface 21 of element body 20 of electronic component 10 protrudes from main surface 111 of core layer 110. In contrast, main surface 22 of element body 20 of electronic component 10 may be flush with main surface 112 of core layer 110. The thickness of electronic component 10 in the Z direction is not particularly limited, but may be, for example, 0.5 mm or more, or approximately 0.8 mm. This reduces the thickness of insulating resin layer 121 in the portions covering terminal electrodes 31 and 33, thereby improving the processing accuracy of vias that expose terminal electrodes 31 and 33. At the same time, the shallower via depth reduces the increase in via resistance, thereby suppressing deterioration of the characteristics of electronic component 10 during embedding. Furthermore, the insulating resin layer 122 does not become excessively thin in the portions covering the terminal electrodes 32, 34, thereby ensuring sufficient insulation properties of the insulating resin layer 122. Furthermore, by covering the electronic component 10 with the insulating resin layer 121 having a relatively large thickness and the insulating resin layer 122 having a relatively small thickness, it is possible to form the electronic component-embedded substrate 100 having a relatively thick component, for example, about 0.8 mm thick, built in.
[0021] Conductor layers L1 and L2 are formed on the front and back sides of the insulating resin layer 121. The conductor layer L1 is exposed on one surface of the electronic component-embedded substrate 100, and a portion of the conductor layer L1 is covered with a solder resist 131. Furthermore, the conductor layer L1 covers at least a portion of the main surface 111 of the core layer 110 and at least a portion of the main surface 21 of the element body 20 of the electronic component 10 via the insulating resin layer 121. Of the conductor patterns 141-144 located on the conductor layer L1, the portions not covered with the solder resist 131 constitute external terminals. Furthermore, the conductor pattern 141 located on the conductor layer L1 is connected to the terminal electrode 31 of the electronic component 10 via a via conductor 151 that penetrates the insulating resin layer 121. Furthermore, the conductor pattern 143 located on the conductor layer L1 is connected to the terminal electrode 33 of the electronic component 10 via a via conductor 153 that penetrates the insulating resin layer 121. An example of the pattern shape of the conductor layer L1 is shown in FIG. 4( a). 4(a), two via conductors 151 are provided to be connected to the terminal electrode 31, thereby reducing the connection resistance to the terminal electrode 31. Similarly, in the example shown in FIG. 4(a), two via conductors 153 are provided to be connected to the terminal electrode 33, thereby reducing the connection resistance to the terminal electrode 33.
[0022] The conductor layer L2 is located between the insulating resin layer 121 and the core layer 110. In the example shown in Fig. 1, the conductor layer L2 includes conductor patterns 162 and 164. The conductor pattern 142 located on the conductor layer L1 is connected to the conductor pattern 162 located on the conductor layer L2 through a via conductor 152 that penetrates the insulating resin layer 121. Furthermore, the conductor pattern 144 located on the conductor layer L1 is connected to the conductor pattern 164 located on the conductor layer L2 through a via conductor 154 that penetrates the insulating resin layer 121. Fig. 4(b) shows an example of the pattern shape of the conductor layer L2.
[0023] Conductor layers L3 and L4 are formed on the front and back surfaces of the insulating resin layer 122. The conductor layer L4 is exposed on the other surface of the electronic component-embedded substrate 100, and a portion of the conductor layer L4 is covered with a solder resist 132. Furthermore, the conductor layer L4 covers at least a portion of the main surface 112 of the core layer 110 and at least a portion of the main surface 22 of the element body 20 of the electronic component 10 via the insulating resin layer 122. Of the conductor patterns 171-174 located on the conductor layer L4, the portions not covered with the solder resist 132 form external terminals. Furthermore, the conductor pattern 172 located on the conductor layer L4 is connected to the terminal electrode 32 of the electronic component 10 via a via conductor 182 that penetrates the insulating resin layer 122. Furthermore, the conductor pattern 174 located on the conductor layer L4 is connected to the terminal electrode 34 of the electronic component 10 via a via conductor 184 that penetrates the insulating resin layer 122. An example of the pattern shape of the conductor layer L4 is shown in FIG. 4( d ). In the example shown in Fig. 4(d), two via conductors 182 are provided to be connected to the terminal electrode 32, thereby reducing the connection resistance to the terminal electrode 32. Similarly, in the example shown in Fig. 4(d), two via conductors 184 are provided to be connected to the terminal electrode 34, thereby reducing the connection resistance to the terminal electrode 34.
[0024] The conductor layer L3 is located between the insulating resin layer 122 and the core layer 110. In the example shown in Fig. 1, the conductor layer L3 includes conductor patterns 191 and 193. The conductor pattern 171 located on the conductor layer L4 is connected to the conductor pattern 191 located on the conductor layer L3 through a via conductor 181 that penetrates the insulating resin layer 122. Furthermore, the conductor pattern 173 located on the conductor layer L4 is connected to the conductor pattern 193 located on the conductor layer L3 through a via conductor 183 that penetrates the insulating resin layer 122. Fig. 4(c) shows an example of the pattern shape of the conductor layer L3.
[0025] 2 , terminal electrode 31 and terminal electrode 32 do not overlap in plan view when viewed from the Z direction, so even if an external force is applied to terminal electrode 31 through via conductor 151, this external force is less likely to be transmitted to terminal electrode 32 and via conductor 182. Conversely, even if an external force is applied to terminal electrode 32 through via conductor 182, this external force is less likely to be transmitted to terminal electrode 31 and via conductor 151. Similarly, in the example shown in FIG. 2 , terminal electrode 33 and terminal electrode 34 do not overlap in plan view when viewed from the Z direction, so even if an external force is applied to terminal electrode 33 through via conductor 153, this external force is less likely to be transmitted to terminal electrode 34 and via conductor 184. Conversely, even if an external force is applied to terminal electrode 34 through via conductor 184, this external force is less likely to be transmitted to terminal electrode 33 and via conductor 153. This makes it possible to improve the reliability of the product.
[0026] 4(b) and 4(c) show the planar position of electronic component 10 housed in through-hole 113. Here, 4(b) and 4(c) show the positions of side surfaces 23 to 26 of element body 20 constituting electronic component 10.
[0027] As shown in FIG. 1 , a plurality of through-hole conductors 114 are provided in the core layer 110. Each of these through-hole conductors 114 penetrates the core layer 110 and interconnects the conductor pattern located on the conductor layer L2 with the conductor pattern located on the conductor layer L3. Some of these through-hole conductors 114 form a through-hole conductor group TH1 arranged along the side surfaces 23 and 26 in a plan view, and a through-hole conductor group TH2 arranged along the side surfaces 24 and 25 in a plan view. The plurality of through-hole conductors 114 belonging to the through-hole conductor group TH1 electrically connect the conductor pattern 162 located on the conductor layer L2 with the conductor pattern 191 located on the conductor layer L3. The plurality of through-hole conductors 114 belonging to the through-hole conductor group TH2 electrically connect the conductor pattern 164 located on the conductor layer L2 with the conductor pattern 193 located on the conductor layer L3. The conductor patterns 162, 164, 191, and 193 may be, for example, ground patterns.
[0028] Furthermore, another portion of the plurality of through-hole conductors 114 constitutes a through-hole conductor group TH3 arranged along side surfaces 23 and 25, and a through-hole conductor group TH4 arranged along side surfaces 24 and 26 in plan view. The plurality of through-hole conductors belonging to the through-hole conductor group TH3 electrically connect the plurality of conductor patterns 168 located on conductor layer L2 to the plurality of conductor patterns 198 located on conductor layer L3. The plurality of through-hole conductors belonging to the through-hole conductor group TH4 electrically connect the plurality of conductor patterns 169 located on conductor layer L2 to the plurality of conductor patterns 199 located on conductor layer L3. The conductor patterns 168, 169, 198, and 199 may be, for example, signal wiring patterns.
[0029] With this configuration, the electronic component 10 accommodated in the through hole 113 is surrounded by the through-hole conductor groups TH1 to TH4 in a plan view. The through-hole conductor groups TH1 to TH4 also function as a heat dissipation path for heat generated by the electronic component 10.
[0030] 4B and 4C, the through-hole conductor group TH1 includes an arrangement portion TH11 arranged in two rows in the X direction along the side surface 26, and an arrangement portion TH12 arranged in two rows in the Y direction along the side surface 23. In plan view, the terminal electrodes 31, 32 and the via conductors 151, 182 overlap with the arrangement portion TH11 of the through-hole conductor group TH1 in the Y direction and also overlap with the arrangement portion TH12 of the through-hole conductor group TH1 in the X direction. In other words, if the region in which the arrangement portion TH11 of the through-hole conductor group TH1 is formed (in plan view) is imagined as a virtual region (temporarily referred to as a first virtual region V1) extending in the −Y direction, the terminal electrodes 31, 32 and the via conductors 151, 182 are located in the first virtual region V1. Similarly, if the region where the arrangement portion TH12 of the through-hole conductor group TH1 is formed is imagined as a virtual region (temporarily referred to as a second virtual region V2) extending in the −X direction, the terminal electrodes 31, 32 and the via conductors 151, 182 are located in the second virtual region V2. The terminal electrodes 31, 32 and the via conductors 151, 182 may be included in the region where the first virtual region V1 and the second virtual region V2 overlap. In other words, the terminal electrodes 31, 32 and the via conductors 151, 182 are covered from the +X direction side and the +Y direction side by the through-hole conductor group TH1, which is laid out in an L-shape in plan view.
[0031] 4B and 4C, the through-hole conductor group TH2 includes an arrangement portion TH23 arranged in two rows in the X direction along the side surface 25 and an arrangement portion TH24 arranged in two rows in the Y direction along the side surface 24. In plan view, the terminal electrodes 33, 34 and the via conductors 153, 184 overlap with the arrangement portion TH23 of the through-hole conductor group TH2 in the Y direction and also overlap with the arrangement portion TH24 of the through-hole conductor group TH2 in the X direction. In other words, if the region where the arrangement portion TH23 of the through-hole conductor group TH2 is formed (in plan view) is imagined as a virtual region (temporarily referred to as a third virtual region V3) extending in the +Y direction, the terminal electrodes 33, 34 and the via conductors 153, 184 are located in the third virtual region V3. Similarly, if we imagine a virtual region (temporarily referred to as a fourth virtual region V4) extending in the +X direction from the region where the arrangement portion TH24 of the through-hole conductor group TH2 is formed, the terminal electrodes 33, 34 and the via conductors 153, 184 are located in the fourth virtual region V4. The terminal electrodes 33, 34 and the via conductors 153, 184 may be included in the region where the third virtual region V3 and the fourth virtual region V4 overlap. In other words, the terminal electrodes 33, 34 and the via conductors 153, 184 are covered from the −X direction and the −Y direction by the through-hole conductor group TH2, which is laid out in an L-shape in plan view.
[0032] With this configuration, heat generated by current flowing through coil conductor patterns 41 to 43 is dissipated mainly via through-hole conductor group TH1, and heat generated by current flowing through coil conductor patterns 51 to 53 is dissipated mainly via through-hole conductor group TH2. In particular, when conductor patterns 162, 164, 191, and 193 connected to through-hole conductor groups TH1 and TH2 are ground patterns, high heat dissipation characteristics can be achieved.
[0033] Furthermore, in the examples shown in Figures 4(b) and (c), the through-hole conductor groups TH1 and TH2 are both arranged in two rows in an L-shape, which means that the electronic component 10 is doubly surrounded by multiple through-hole conductors, making it possible to obtain better heat dissipation characteristics.
[0034] Furthermore, since a plurality of via conductors 151, 182, 153, and 184 are provided to be connected to the terminal electrodes 31 to 34, the connection resistance to the terminal electrodes 31 to 34 can be reduced. Alternatively, instead of providing a plurality of via conductors 151, 182, 153, and 184, the planar area in the XY cross section of the via conductors 151, 182, 153, and 184 may be designed to be larger than the planar area in the XY cross section of each of the through-hole conductors constituting the through-hole conductor groups TH1 to TH4. This can further reduce the connection resistance to the terminal electrodes 31 to 34.
[0035] For example, if the thickness (thickness in the Z direction) of electronic component 10 is relatively large, thermal stress in the Z direction generated by the difference in thermal expansion coefficient between electronic component 10 and insulating resin layer 121 disposed around electronic component 10 may affect the reliability of via conductors (151, 182, 153, 184) in electronic component 10. In response to this, for example, by providing through-hole conductor groups TH1 to TH4 in core layer 110 located near through hole 113 and connecting through holes 114 included therein to via conductors (e.g., via conductors 152, 154, etc.), thermal expansion and contraction can be suppressed and the reliability required of via conductors (e.g., via conductors 151, 182, 153, 184) can be satisfied.
[0036] 5(a) to 5(d) and 6(a) to 6(c) are process diagrams for explaining a method for manufacturing the electronic component built-in substrate 100. FIG.
[0037] First, as shown in FIG. 5( a), a carrier substrate 300 is prepared, with copper foils 301 and 302 formed on both sides. Next, as shown in FIG. 5( b), an insulating resin layer 122 is formed on the surface of the copper foil 301. Next, as shown in FIG. 5( c), a core layer 110 is prepared, with a through hole 113, conductor layers L2 and L3, and multiple through-hole conductors 114 formed therein. The core layer 110 is placed on the carrier substrate 300 so that the conductor layer L3 faces the insulating resin layer 122. In this state, an electronic component 10 is inserted into the through hole 113. As a result, the terminal electrodes 32 and 34 are covered with the insulating resin layer 122. Next, as shown in FIG. 5( d), a laminate of the copper foil 303 and the insulating resin layer 121 is formed so as to cover the conductor layer L2, and the laminate is heat-pressed. As a result, the terminal electrodes 31 and 33 are covered with the insulating resin layer 121. Furthermore, the gap between the through-hole 113 and the electronic component 10 is filled with the insulating resin layer 121 by the heat press.
[0038] Next, as shown in FIG. 6( a), the carrier substrate 300 is peeled off. Next, as shown in FIG. 6( b), the copper foils 301, 303 are patterned, and the insulating resin layers 121, 122 exposed from the copper foils 301, 303 are removed by laser processing, blasting, or the like. At this time, if the main surface 21 of the element body 20 of the electronic component 10 protrudes from the main surface 111 of the core layer 110, the insulating resin layer 121 is thinner in the portion covering the main surface 21 of the element body 20, thereby improving the processing accuracy of the vias that expose the terminal electrodes 31, 33. Furthermore, a thinner insulating layer is equivalent to a shallower via depth, which can reduce the increase in via resistance and suppress deterioration of the characteristics of the electronic component 10 when it is built in.
[0039] Next, as shown in Figure 6(c), after forming conductors inside the vias using electroless and electrolytic plating, conductor layers L1 and L4 are formed using a photolithography process commonly used in the manufacture of printed circuit boards. Then, solder resists 131 and 132 are formed to cover portions of conductor layers L1 and L4, respectively, completing the electronic component-embedded substrate 100 shown in Figure 1. If the planar positions of terminal electrodes 31 and 33 are misaligned from the planar positions of terminal electrodes 32 and 34, the stress in the Z direction applied during the formation of terminal electrodes 31 to 34 is dispersed, making it possible to reduce process errors due to stress concentration.
[0040] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.
[0041] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.
[0042] An electronic component-embedded substrate according to one aspect of the present disclosure includes a core layer having a first main surface, a second main surface opposite the first main surface, and a through hole formed from the first main surface to the second main surface; an electronic component housed in the through hole and having an element part having a third main surface and a fourth main surface opposite the third main surface; a first insulating resin layer covering the first main surface of the core layer and the third main surface of the element part; a second insulating resin layer covering the second main surface of the core layer and the fourth main surface of the element part; a first conductor layer covering, via the first insulating resin layer, at least a portion of the first main surface of the core layer and at least a portion of the third main surface of the element part; and a second insulating resin layer covering, via the second insulating resin layer, at least a portion of the second main surface of the core layer and at least a portion of the fourth main surface of the element part. and a second conductor layer covering the base portion, wherein the electronic component further includes a first coil conductor pattern embedded in the base portion, a first terminal electrode electrically connected to one end of the first coil conductor pattern and exposed from the third main surface, and a second terminal electrode electrically connected to the other end of the first coil conductor pattern and exposed from the fourth main surface, wherein the first terminal electrode is connected to the first conductor pattern included in the first conductor layer through a first via conductor provided to penetrate the first insulating resin layer, and the second terminal electrode is connected to the second conductor pattern included in the second conductor layer through a second via conductor provided to penetrate the second insulating resin layer, and the first terminal electrode and the second terminal electrode do not overlap in a plan view. This makes it difficult for an external force applied to the first terminal electrode to be transmitted to the second terminal electrode, and makes it difficult for an external force applied to the second terminal electrode to be transmitted to the first terminal electrode, thereby improving product reliability.
[0043] In the electronic component-embedded substrate, the electronic component may be thicker than the core layer, and the third main surface of the element body may protrude from the first main surface of the core layer. This allows the thickness of the first insulating resin layer to be reduced in the portion covering the third main surface of the element body, thereby improving the processing accuracy of the first via conductors. Furthermore, since the depth of the first via conductors is reduced, the resistance value of the first via conductors can be reduced, and deterioration of the characteristics of the electronic component during embedding can be suppressed.
[0044] In the electronic component-embedded substrate, the first insulating resin layer may be thicker than the second insulating resin layer. This allows the total thickness of the electronic component-embedded substrate to be reduced while ensuring that the amount of resin constituting the first insulating resin layer is sufficient to embed the electronic components, thereby suppressing the occurrence of voids and improving smoothness, thereby ensuring the quality of the substrate.
[0045] In the electronic component-embedded substrate, the fourth main surface of the element body may be flush with the second main surface of the core layer, thereby ensuring sufficient insulation of the second insulating resin layer.
[0046] In the electronic component-embedded substrate, the electronic component further includes a second coil conductor pattern embedded in the element body portion, a third terminal electrode electrically connected to one end of the second coil conductor pattern and exposed from the third main surface, and a fourth terminal electrode electrically connected to the other end of the second coil conductor pattern and exposed from the fourth main surface, wherein the third terminal electrode is connected to the third conductor pattern included in the first conductor layer through a third via conductor provided to penetrate the first insulating resin layer, and the fourth terminal electrode is connected to the fourth conductor pattern included in the second conductor layer through a fourth via conductor provided to penetrate the second insulating resin layer, and the third terminal electrode and the fourth terminal electrode do not have to overlap in a plan view. This makes it difficult for an external force applied to the third terminal electrode to be transmitted to the fourth terminal electrode, and therefore improves product reliability.
[0047] In the above-described electronic component-embedded substrate, the third and fourth main surfaces of the element body extend in a first direction and a second direction orthogonal to the first direction, and the element body further has first and second side surfaces orthogonal to the first direction and positioned opposite to each other, and third and fourth side surfaces orthogonal to the second direction and positioned opposite to each other, and the core layer further has a plurality of through-hole conductors formed from the first main surface to the second main surface, the plurality of through-hole conductors including a first through-hole conductor group and a second through-hole conductor group, and the first through-hole conductor group has a first arrangement portion arranged along the first side surface and a third arrangement portion The electronic component may include a second arrangement portion arranged along the side surface, the second through-hole conductor group including a third arrangement portion arranged along the second side surface and a fourth arrangement portion arranged along the fourth side surface, the first and second terminal electrodes and the first and second via conductors overlap with the first arrangement portion of the first through-hole conductor group in a first direction and with the second arrangement portion of the first through-hole conductor group in a second direction in a plan view, and the third and fourth terminal electrodes and the third and fourth via conductors overlap with the third arrangement portion of the second through-hole conductor group in the first direction and with the fourth arrangement portion of the second through-hole conductor group in a second direction in a plan view. This allows heat generated from the electronic component to be dissipated via the first and second through-hole conductor groups.
[0048] The electronic component-embedded substrate may further include a third conductor layer provided on the first main surface of the core layer and a fourth conductor layer provided on the second main surface of the core layer, the third conductor layer including first and second ground patterns, the fourth conductor layer including third and fourth ground patterns, the first group of through-hole conductors electrically connecting the first ground pattern and the third ground pattern, and the second group of through-hole conductors electrically connecting the second ground pattern and the fourth ground pattern. This makes it possible to obtain even better heat dissipation characteristics.
[0049] In the above-described electronic component-embedded substrate, the first, second, third, and fourth via conductors may each be provided in plural, thereby reducing connection resistance to the first, second, third, and fourth via conductors.
[0050] In the electronic component-embedded substrate, the planar area of each of the first, second, third, and fourth via conductors may be larger than the planar area of each of the plurality of through-hole conductors, thereby further reducing the connection resistance to the first, second, third, and fourth via conductors.
[0051] This application claims the benefit of Japanese Patent Application No. 2023-131685, filed on August 11, 2023, the entire disclosure of which is incorporated herein by reference.
[0052] REFERENCE SIGNS LIST 10 Electronic component 20 Body portion 21, 22 Main surface 23 to 26 Side surface 31 to 34 Terminal electrode 41 to 43, 51 to 53 Coil conductor pattern 61 to 64, 71 to 74 Via conductor 100 Electronic component built-in substrate 110 Core layer 111, 112 Main surface 113 Through hole 114 Through-hole conductor 121, 122 Insulating resin layer 131, 132 Solder resist 141 to 144 Conductive pattern 151 to 154 Via conductor 162, 164, 168, 169 Conductive pattern 171 to 174 Conductive pattern 181 to 184 Via conductor 191, 193, 198, 199 Conductive pattern 300 Carrier substrate 301 to 303 Copper foil L1 to L4 Conductive layer M1 to M5: Conductor layers TH1 to TH4: Through-hole conductor group TH11, TH12, TH23, TH24: Array section
Claims
1. An electronic component comprising: a core layer having a first main surface, a second main surface opposite the first main surface, and a through hole formed from the first main surface to the second main surface; an element part housed in the through hole and having a third main surface and a fourth main surface opposite the third main surface; a first insulating resin layer covering the first main surface of the core layer and the third main surface of the element part; a second insulating resin layer covering the second main surface of the core layer and the fourth main surface of the element part; a first conductor layer covering at least a portion of the first main surface of the core layer and at least a portion of the third main surface of the element part via the first insulating resin layer; and a second conductor layer covering at least a portion of the second main surface of the core layer and at least a portion of the fourth main surface of the element part via the second insulating resin layer, wherein the electronic component comprises: a first coil conductor pattern embedded in the element part; a first terminal electrode electrically connected to one end of the first coil conductor pattern and exposed from the third main surface; a second terminal electrode electrically connected to the other end of the first coil conductor pattern and exposed from the fourth main surface, wherein the first terminal electrode is connected to a first conductor pattern included in the first conductor layer through a first via conductor provided to penetrate the first insulating resin layer, and the second terminal electrode is connected to a second conductor pattern included in the second conductor layer through a second via conductor provided to penetrate the second insulating resin layer, and the first terminal electrode and the second terminal electrode do not overlap in a planar view.
2. The electronic component-embedded substrate according to claim 1, wherein the electronic component is thicker than the core layer, and the third main surface of the element portion protrudes beyond the first main surface of the core layer.
3. The electronic component embedded substrate according to claim 2, wherein the first insulating resin layer is thicker than the second insulating resin layer.
4. The electronic component built-in substrate according to claim 3, wherein the fourth main surface of the element portion is flush with the second main surface of the core layer.
5. The electronic component built-in substrate according to any one of claims 1 to 4, wherein the electronic component further comprises: a second coil conductor pattern embedded in the base portion; a third terminal electrode electrically connected to one end of the second coil conductor pattern and exposed from the third main surface; and a fourth terminal electrode electrically connected to the other end of the second coil conductor pattern and exposed from the fourth main surface, wherein the third terminal electrode is connected to the third conductor pattern included in the first conductor layer via a third via conductor provided to penetrate the first insulating resin layer, and the fourth terminal electrode is connected to the fourth conductor pattern included in the second conductor layer via a fourth via conductor provided to penetrate the second insulating resin layer, and the third terminal electrode and the fourth terminal electrode do not overlap in a planar view.
6. The third and fourth main surfaces of the body portion extend in a first direction and a second direction perpendicular to the first direction, the body portion further having first and second side surfaces perpendicular to the first direction and positioned opposite each other, and third and fourth side surfaces perpendicular to the second direction and positioned opposite each other, the core layer further having a plurality of through-hole conductors formed from the first main surface to the second main surface, the plurality of through-hole conductors including a first through-hole conductor group and a second through-hole conductor group, the first through-hole conductor group including a first arrangement portion arranged along the first side surface and a second arrangement portion arranged along the third side surface, the second through-hole conductor group including a third arrangement portion arranged along the second side surface and a fourth arrangement portion arranged along the fourth side surface, 6. The electronic component embedded substrate according to claim 5, wherein the first and second terminal electrodes and the first and second via conductors overlap, in a planar view, the first arrangement portion of the first through hole conductor group in the first direction and overlap with the second arrangement portion of the first through hole conductor group in the second direction, and the third and fourth terminal electrodes and the third and fourth via conductors overlap, in a planar view, the third arrangement portion of the second through hole conductor group in the first direction and overlap with the fourth arrangement portion of the second through hole conductor group in the second direction.
7. The electronic component embedded substrate as described in claim 6, further comprising: a third conductor layer provided on the first main surface of the core layer; and a fourth conductor layer provided on the second main surface of the core layer, wherein the third conductor layer includes first and second ground patterns, the fourth conductor layer includes third and fourth ground patterns, the first group of through-hole conductors electrically connects the first ground pattern and the third ground pattern, and the second group of through-hole conductors electrically connects the second ground pattern and the fourth ground pattern.
8. The electronic component built-in substrate according to claim 5, wherein the first, second, third and fourth via conductors are each provided in multiples.
9. The electronic component-embedded substrate according to claim 6, wherein the plane area of each of the first, second, third and fourth via conductors is greater than the plane area of each of the plurality of through-hole conductors.
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