Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a body region formed in a surface layer portion of the main surface; a plurality of gate electrodes disposed on both sides of the body region on the main surface; and a connection electrode formed in a region between the plurality of gate electrodes on the main surface so as to overlap the body region in the thickness direction, and connected to the plurality of gate electrodes.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-132222 filed with the Japan Patent Office on August 15, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (WO2016 / 143099A1) discloses a SiC power MISFET including multiple p-type body regions and gate electrodes. In Figures 1 and 3 of the patent document, the multiple p-type body regions are formed at intervals, and a lattice-shaped gate electrode surrounds the multiple p-type body regions. In Figure 4 of the patent document, the multiple p-type body regions extend in one direction, and multiple gate structures extend in one direction between adjacent p-type body regions.

[0003] International Publication No. 2016 / 143099

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a body region formed in a surface layer portion of the main surface, a plurality of gate electrodes arranged on both sides of the body region on the main surface, and a connection electrode formed in a region between the plurality of gate electrodes on the main surface so as to overlap the body region in the thickness direction, and connected to adjacent plurality of the gate electrodes.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a plurality of body regions formed on a surface layer portion of the main surface at intervals in a first direction X and extending in stripes in a second direction Y intersecting the first direction X; a plurality of gate electrodes arranged on the main surface at intervals in the first direction X so as to straddle the plurality of body regions and extending in stripes in the second direction Y; and a plurality of connection electrodes formed in regions between the plurality of gate electrodes on the main surface, each extending in the first direction X to be connected to the plurality of gate electrodes and overlapping the body regions corresponding to the plurality of connection electrodes in a thickness direction.

[0007] The above and further objects, features and advantages will become more apparent from the accompanying drawings and detailed description.

[0008] FIG. 1 is a plan view showing a semiconductor device according to one embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing a layout example of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region together with a planar structure according to a first layout example. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4 . FIG. 8 is an enlarged cross-sectional view of a region shown in FIG. 5 . FIG. 9 is an enlarged cross-sectional view of a region shown in FIG. 7 . FIG. 10 is a cutaway perspective view showing a main portion of an active region. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 1 . FIG. 12 is an enlarged cross-sectional view of a region shown in FIG. 11 . FIG. 13 is an enlarged plan view showing a main portion of an active region together with a planar structure according to a second layout example. FIG. 14 is a cross-sectional view showing a semiconductor device according to a first modification. FIG. 15 is a cross-sectional view showing a semiconductor device according to a second modification. FIG. 16 is a cross-sectional view showing a semiconductor device according to a third modification.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to one embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing a layout example of a first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of an active region 8 together with a planar structure 14 according to a first layout example. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4.

[0013] Fig. 8 is an enlarged cross-sectional view of a region shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view of a region shown in Fig. 7. Fig. 10 is a cutaway cross-sectional perspective view showing a main part of the active region 8. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 1. Fig. 12 is an enlarged cross-sectional view of a region shown in Fig. 11.

[0014] 1 to 12, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate vertical structure.

[0015] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0016] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0017] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0018] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0019] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0020] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0021] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0022] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0023] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0024] The off angle is preferably 5° or less. The off angle is preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0025] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor region 6 as a first potential (high potential). The first semiconductor region 6 may also be referred to as a "base region (layer)", a "semiconductor region (layer)", a "drain region (layer)", or the like.

[0026] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0027] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0028] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0029] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer stacked on the first semiconductor region 6 (substrate). Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0030] The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 may be greater than that of the first semiconductor region 6.

[0031] The thickness of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0032] The semiconductor device 1 includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0033] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0034] The semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view. The peripheral region 9 extends in a strip shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring shape in this embodiment) that surrounds the active region 8.

[0035] The semiconductor device 1 includes a plurality of p-type body regions 10 formed in a surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 10 may also be referred to as "impurity regions," "channel regions," or the like. A source potential is applied to the plurality of body regions 10 as a second potential different from the first potential. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0036] The multiple body regions 10 are arranged at intervals in the first direction X and extend in a strip-like manner in the second direction Y. That is, the multiple body regions 10 are arranged in a stripe-like manner extending in the second direction Y. The extending direction of the multiple body regions 10 coincides with the off-direction of the SiC single crystal. Of course, the multiple body regions 10 may also be arranged at intervals in the second direction Y and extend in a strip-like manner in the first direction X. In this case, the extending direction of the multiple body regions 10 intersects (is perpendicular to) the off-direction of the SiC single crystal.

[0037] The plurality of body regions 10 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of body regions 10 are preferably formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3. The plurality of body regions 10 are exposed from the first main surface 3.

[0038] The body region 10 may have a width of 1 μm to 10 μm in the first direction X. The width of the body region 10 may have a value belonging to at least one of the ranges of 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the body region 10 is preferably 2 μm to 5 μm.

[0039] The semiconductor device 1 includes a plurality of n-type source regions 11 (impurity regions) formed in the surface layer portions of the plurality of body regions 10. A source potential is applied to the plurality of source regions 11. Each of the plurality of source regions 11 has an n-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 10, thereby converting the conductivity type of the corresponding body region 10 from p-type to n-type. The n-type impurity concentration of the plurality of source regions 11 is higher than the n-type impurity concentration of the second semiconductor region 7.

[0040] In this embodiment, the source regions 11 are formed in one-to-one correspondence with the body regions 10. The source regions 11 are formed spaced apart from each other inward from both sides of the corresponding body region 10 in the first direction X, and extend in a strip-like shape along the extension direction (second direction Y) of the corresponding body region 10. Of course, when the extension direction of the body regions 10 is the first direction X, the source regions 11 may also extend in a strip-like shape in the first direction X.

[0041] The plurality of source regions 11 are formed at intervals from the bottoms of the corresponding body regions 10 toward the first main surface 3, and face the second semiconductor region 7 in the thickness direction with a part of the corresponding body region 10 sandwiched therebetween. The plurality of source regions 11 are exposed from the first main surface 3.

[0042] The source region 11 may have a width of 1 μm to 10 μm in the first direction X. The width of the source region 11 may have a value belonging to at least one of the ranges of 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the source region 11 is preferably 2 μm to 5 μm.

[0043] The semiconductor device 1 includes a plurality of n-type surface drift regions 12 that are partitioned into regions between a plurality of body regions 10 in a surface portion of the second semiconductor region 7. The surface drift regions 12 may also be referred to as "JFET regions."

[0044] In this embodiment, each of the plurality of surface drift regions 12 is made up of a part of the second semiconductor region 7. Of course, the plurality of surface drift regions 12 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7, or may have an n-type impurity concentration lower than the n-type impurity concentration of the second semiconductor region 7.

[0045] The surface drift regions 12 are arranged at intervals in the first direction X according to the layout of the body regions 10, and are each formed in a band shape extending in the second direction Y. The surface drift regions 12 are also formed in a stripe shape extending in the second direction Y. Of course, when the extension direction of the body regions 10 is the first direction X, the surface drift regions 12 may each extend in a band shape in the first direction X. The surface drift region 12 forms a pnp-type JFET structure together with the body regions 10 located on both sides.

[0046] The semiconductor device 1 includes a plurality of p-type channel regions 13 defined in surface layer portions of a plurality of body regions 10. The plurality of channel regions 13 are defined in regions between a plurality of source regions 11 and a plurality of surface drift regions 12 (second semiconductor regions 7) in the surface layer portions of the plurality of body regions 10. The plurality of channel regions 13 form a current path extending horizontally along the first main surface 3.

[0047] The semiconductor device 1 includes a planar structure 14 disposed on the first main surface 3 in the active region 8. The planar structure 14 includes a plurality of gate structures 15. The plurality of gate structures 15 are disposed on both sides of the plurality of body regions 10 on the first main surface 3, respectively.

[0048] The multiple gate structures 15 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate structures 15 are arranged in a strip shape extending in the second direction Y. The extending direction of the multiple gate structures 15 also coincides with the off-direction of the SiC single crystal. Of course, when the extending direction of the multiple body regions 10 is the first direction X, the multiple gate structures 15 may each extend in a strip shape in the first direction X.

[0049] The plurality of gate structures 15 each cover at least one channel region 13 (periphery of the body region 10). The plurality of gate structures 15 are positioned on at least one channel region 13, and each cover at least one peripheral portion of the body region 10, at least one source region 11, and one surface drift region 12.

[0050] In this embodiment, the plurality of gate structures 15 cross one surface drift region 12 in the first direction X and extend across the peripheral portions of two adjacent body regions 10. Specifically, the plurality of gate structures 15 extend across the peripheral portion of the source region 11 in one body region 10 and the peripheral portion of the source region 11 in the other body region 10, and cover the two source regions 11, one surface drift region 12, and two channel regions 13, respectively.

[0051] Each of the plurality of gate structures 15 has a stacked structure including a gate insulating film 16 and a gate electrode 17. The gate insulating film 16 may be referred to as a "first insulating film" or the like. The gate electrode 17 may be referred to as a "first gate electrode" or the like.

[0052] The gate insulating films 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating films 16 have a single-layer structure made of a silicon oxide film. The gate insulating films 16 preferably include a silicon oxide film made of an oxide of the chip 2.

[0053] The plurality of gate insulating films 16 are disposed on both sides of the plurality of body regions 10 on the first main surface 3, respectively, and cover the first main surface 3 in a film-like manner. The plurality of gate insulating films 16 are arranged at intervals in the first direction X, and are each formed in a strip-like shape extending in the second direction Y along the body region 10. In other words, the plurality of gate insulating films 16 are arranged in a strip-like shape extending in the second direction Y. Furthermore, the extending direction of the plurality of gate insulating films 16 coincides with the off-direction of the SiC single crystal.

[0054] The plurality of gate insulating films 16 each cover at least one channel region 13 (periphery of the body region 10). The plurality of gate insulating films 16 are positioned on at least one channel region 13, and each cover at least one peripheral portion of the body region 10, at least one source region 11, and one surface drift region 12.

[0055] In this embodiment, the multiple gate insulating films 16 cross one surface drift region 12 and extend over the peripheral portions of two adjacent body regions 10. Specifically, the multiple gate insulating films 16 extend over the peripheral portion of the source region 11 in one body region 10 and the peripheral portion of the source region 11 in the other body region 10, and cover the two source regions 11, one surface drift region 12, and two channel regions 13, respectively.

[0056] The multiple gate insulating films 16 are formed at intervals from the centers of the multiple source regions 11 (the centers of the multiple body regions 10) toward the surface drift region 12 in the first direction X, exposing the centers of the multiple source regions 11.

[0057] The thickness of the gate insulating film 16 may be 10 nm or more and 150 nm or less. The thickness of the gate insulating film 16 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0058] The plurality of gate electrodes 17 are arranged on both sides of the plurality of body regions 10 on the first main surface 3. A gate potential as a control potential is applied to the plurality of gate electrodes 17. The plurality of gate electrodes 17 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0059] The multiple gate electrodes 17 are respectively arranged in the form of a film on the multiple gate insulating films 16. The multiple gate electrodes 17 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y along the body region 10. That is, the multiple gate electrodes 17 are arranged in the form of stripes extending in the second direction Y. The extending direction of the multiple gate electrodes 17 also coincides with the off-direction of the SiC single crystal. In this embodiment, the multiple gate electrodes 17 are formed at intervals inward from both ends of the corresponding gate insulating film 16 in the first direction X, exposing both ends of the corresponding gate insulating film 16.

[0060] The plurality of gate electrodes 17 each face at least one channel region 13 (periphery of the body region 10) with a corresponding gate insulating film 16 interposed therebetween. The plurality of gate electrodes 17 each cover at least one peripheral portion of the body region 10, at least one source region 11, and one surface drift region 12 with a corresponding gate insulating film 16 interposed therebetween so as to face at least one channel region 13.

[0061] In this embodiment, the multiple gate electrodes 17 cross one surface drift region 12 and extend over the peripheral portions of two adjacent body regions 10. Specifically, the multiple gate electrodes 17 extend over the peripheral portion of the source region 11 in one body region 10 and the peripheral portion of the source region 11 in the other body region 10, and face the two source regions 11, one surface drift region 12, and two channel regions 13, respectively, with the corresponding gate insulating film 16 sandwiched therebetween.

[0062] When the distance in the first direction X between the centers of the plurality of gate electrodes 17 (the plurality of gate structures 15) is defined as a first pitch P1, the first pitch P1 may be 1 μm or more and 6 μm or less. The first pitch P1 may have a value belonging to at least one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The first pitch P1 is preferably 2.5 μm or more and 4.5 μm or less.

[0063] The width W1 of the gate electrode 17 in the first direction X may be 1 μm or more and 5 μm or less. The width W1 of the gate electrode 17 may have a value belonging to at least one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The width W1 of the gate electrode 17 is preferably 1.5 μm or more and 2.5 μm or less.

[0064] The thickness of the gate electrode 17 may be 0.1 μm or more and 2 μm or less. The thickness of the gate electrode 17 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0065] The planar structure 14 includes a plurality of gate connection structures 20. The plurality of gate connection structures 20 are formed in regions between the plurality of gate structures 15 on the first main surface 3, and are respectively connected to two adjacent gate structures 15. That is, each of the plurality of gate connection structures 20 has one end connected to one gate structure 15 and the other end connected to the other gate structure 15. The plurality of gate connection structures 20 form a current path connecting the two adjacent gate structures 15 in the first direction X.

[0066] The number of gate connection structures 20 located in the region between two adjacent gate structures 15 is arbitrary. A single gate connection structure 20 may be located in each region between two adjacent gate structures 15. In this embodiment, a plurality of gate connection structures 20 are located in the regions between two adjacent gate structures 15.

[0067] The plurality of gate connection structures 20 overlap the corresponding body regions 10 in the thickness direction. In this embodiment, the plurality of gate connection structures 20 have portions that cover the corresponding source regions 11, and overlap the body regions 10 with the corresponding source regions 11 sandwiched between them. The plurality of gate connection structures 20 expose the corresponding source regions 11 on both sides in the second direction Y.

[0068] The plurality of gate connection structures 20 are formed at intervals from the plurality of surface drift regions 12 toward the inner side of the corresponding body regions 10 in the first direction X. Therefore, the plurality of gate connection structures 20 are positioned inward of both ends of the corresponding body regions 10 in the first direction X, and do not overlap the plurality of surface drift regions 12 in the thickness direction.

[0069] The multiple gate connection structures 20 extend in a strip-like manner in the first direction X in the regions between the multiple gate structures 15, and are arranged at intervals in the second direction Y. Of course, when the extension direction of the multiple gate structures 15 (body region 10) is the first direction X, the multiple gate structures 15 may also extend in a strip-like manner in the second direction Y, and be arranged at intervals in the first direction X.

[0070] The multiple gate connection structures 20 are respectively connected to the multiple gate structures 15 in a T-shape, and form T-shaped current paths together with the multiple gate structures 15. Specifically, with respect to the multiple gate connection structures 20 arranged on both sides of the multiple gate structures 15, the multiple gate connection structures 20 on one side in the first direction X are shifted in the second direction Y relative to the multiple gate connection structures 20 on the other side in the first direction X. In other words, the multiple gate connection structures 20 on one side face the region between the multiple gate connection structures 20 on the other side in the first direction X.

[0071] Each of the multiple gate connection structures 20 has a stacked structure including a connection insulating film 21 and a connection electrode 22. The connection insulating film 21 may be referred to as a "gate connection insulating film," a "second insulating film," etc. The connection electrode 22 may be referred to as a "gate connection electrode," a "second gate electrode," etc.

[0072] The plurality of connection insulating films 21 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The plurality of connection insulating films 21 preferably include the same type of insulating material as the plurality of gate insulating films 16. In this embodiment, the plurality of connection insulating films 21 have a single-layer structure made of a silicon oxide film. The plurality of connection insulating films 21 preferably include a silicon oxide film made of an oxide of the chip 2.

[0073] The plurality of connection insulating films 21 are formed in film form in regions between the plurality of gate insulating films 16 on the first main surface 3, and are connected to each of two adjacent gate insulating films 16. That is, each of the plurality of connection insulating films 21 has one end connected to one gate insulating film 16 and the other end connected to the other gate insulating film 16. In this embodiment, the plurality of connection insulating films 21 are formed integrally with the plurality of gate insulating films 16, and together with the plurality of gate insulating films 16 form a single insulating film.

[0074] The multiple connection insulating films 21 overlap the corresponding body regions 10 in the thickness direction. In this embodiment, the multiple connection insulating films 21 have portions that cover the corresponding source regions 11, and overlap the body regions 10 with the corresponding source regions 11 sandwiched between them. The multiple connection insulating films 21 are formed at intervals from the multiple surface drift regions 12 toward the inward side of the corresponding body regions 10 in the first direction X. Therefore, the connection insulating films 21 are positioned inward from both ends of the corresponding body regions 10 in the first direction X, and do not overlap the multiple surface drift regions 12 in the thickness direction.

[0075] The multiple connection insulating films 21 extend in a strip shape in the first direction X in regions between the multiple gate insulating films 16 and are arranged at intervals in the second direction Y. The multiple connection insulating films 21 are connected to the multiple gate insulating films 16 in a T-shape. Specifically, with respect to the multiple connection insulating films 21 arranged on both sides of the multiple gate insulating films 16, the multiple connection insulating films 21 on one side in the first direction X are shifted in the second direction Y relative to the multiple connection insulating films 21 on the other side in the first direction X. In other words, the multiple connection insulating films 21 on one side face the regions between the multiple connection insulating films 21 on the other side in the first direction X.

[0076] It is preferable that the thickness of the connection insulating film 21 is approximately equal to the thickness of the gate insulating film 16. Of course, the thickness of the connection insulating film 21 may be greater than the thickness of the gate insulating film 16 or may be smaller than the thickness of the gate insulating film 16.

[0077] The thickness of the connection insulating film 21 may be 10 nm or more and 150 nm or less. The thickness of the connection insulating film 21 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0078] The plurality of connection electrodes 22 transmit a gate potential to the plurality of gate electrodes 17. The plurality of connection electrodes 22 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The plurality of connection electrodes 22 preferably include the same type of conductive material as the plurality of gate electrodes 17.

[0079] The multiple connection electrodes 22 are formed in the form of a film in a region between the multiple gate electrodes 17 on the first main surface 3, and are connected to each of two adjacent gate electrodes 17. That is, each of the multiple connection electrodes 22 has one end connected to one gate electrode 17 and the other end connected to the other gate electrode 17. In this embodiment, the multiple connection electrodes 22 are formed integrally with the multiple gate electrodes 17, and together with the multiple gate electrodes 17 form one electrode.

[0080] The plurality of connection electrodes 22 are formed in the form of films on the plurality of connection insulating films 21. The plurality of connection electrodes 22 extend in strip shapes in the first direction X in regions between the plurality of gate electrodes 17, and are arranged at intervals in the second direction Y. In this embodiment, the plurality of connection electrodes 22 are formed at intervals inward from both ends of the corresponding connection insulating films 21 in the second direction Y, exposing both ends of the corresponding connection insulating films 21.

[0081] The plurality of connection electrodes 22 are opposed to the corresponding body regions 10 with the corresponding connection insulating films 21 interposed therebetween. In this embodiment, the plurality of connection electrodes 22 have portions that are opposed to the corresponding source regions 11 with the corresponding connection insulating films 21 interposed therebetween.

[0082] The multiple connection electrodes 22 are formed at intervals from the multiple surface drift regions 12 toward the inside of the corresponding body regions 10 in the first direction X. Therefore, the connection electrodes 22 are positioned more inward than both ends of the corresponding body regions 10 in the first direction X, and do not overlap the multiple surface drift regions 12 in the thickness direction.

[0083] The multiple connection electrodes 22 are connected in a T-shape to the multiple gate electrodes 17. Specifically, with respect to the multiple connection electrodes 22 arranged on both sides of the multiple gate electrodes 17, the multiple connection electrodes 22 on one side in the first direction X are shifted in the second direction Y relative to the multiple connection electrodes 22 on the other side in the first direction X. In other words, the multiple connection electrodes 22 on one side face the region between the multiple connection electrodes 22 on the other side in the first direction X.

[0084] When the distance in the second direction Y between the centers of the plurality of connection electrodes 22 (the plurality of gate connection structures 20) is defined as a second pitch P2, the second pitch P2 is preferably equal to or greater than the first pitch P1. The second pitch P2 is preferably larger than the first pitch P1. Of course, the second pitch P2 may be approximately equal to the first pitch P1 or may be smaller than the first pitch P1.

[0085] The pitch ratio P2 / P1 of the second pitch P2 to the first pitch P1 may be 0.5 or greater and 20 or less. The pitch ratio P2 / P1 may have a value belonging to at least one of the ranges of 0.5 or greater and 1 or less, 1 or greater and 2.5 or less, 2.5 or greater and 5 or less, 5 or greater and 7.5 or less, 7.5 or greater and 10 or less, 10 or greater and 12.5 or less, 12.5 or greater and 15 or less, 15 or greater and 17.5 or less, and 17.5 or greater and 20 or less. The pitch ratio P2 / P1 is preferably 1 or greater and 10 or less.

[0086] The width W2 of the connection electrode 22 in the second direction Y is preferably not less than the width W1 of the gate electrode 17 in the first direction X. That is, the width W2 of the connection electrode 22 is preferably equal to or greater than the width W1 of the gate electrode 17. The width W2 of the connection electrode 22 may be greater than the width W1 of the gate electrode 17. The width W2 of the connection electrode 22 may be approximately equal to the width W1 of the gate electrode 17. Of course, this specification does not exclude an embodiment in which the width W2 of the connection electrode 22 is less than the width W1 of the gate electrode 17.

[0087] The width ratio W2 / W1 of the width W2 of the connection electrode 22 to the width W1 of the gate electrode 17 may be 0.5 or more and 3 or less. The width ratio W2 / W1 may have a value belonging to at least one of the ranges of 0.5 or more and 1 or less, 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, and 2.5 or more and 3 or less. The width ratio W2 / W1 is preferably 1 or more and 2 or less.

[0088] The width W2 of the connection electrode 22 may be 1 μm or more and 10 μm or less. The width W2 of the connection electrode 22 may have a value belonging to at least one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The width W2 of the connection electrode 22 is preferably 1.5 μm or more and 5 μm or less.

[0089] The thickness of the connection electrode 22 is preferably approximately equal to the thickness of the gate electrode 17. Of course, the thickness of the connection electrode 22 may be greater than the thickness of the gate electrode 17 or may be smaller than the thickness of the gate electrode 17.

[0090] The thickness of the connection electrode 22 may be 0.1 μm or more and 2 μm or less. The thickness of the connection electrode 22 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0091] The semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer portions of the plurality of body regions 10. The plurality of contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 10.

[0092] The plurality of contact regions 25 may have a p-type impurity concentration higher than the n-type impurity concentration of the plurality of source regions 11, thereby converting the conductivity type of the plurality of source regions 11 from n-type to p-type. Of course, the plurality of contact regions 25 may be formed in regions outside the source regions 11 in the surface layer portions of the corresponding body regions 10, thereby increasing the p-type impurity concentration of the corresponding body regions 10.

[0093] Each of the plurality of contact regions 25 has a width W3 in the first direction X that is less than the width of the corresponding body region 10, and is formed in the center of the corresponding body region 10 with a gap between both ends of the corresponding body region 10. The plurality of contact regions 25 are surrounded by the corresponding source region 11. Specifically, the plurality of contact regions 25 are surrounded on all sides (in four directions) by the corresponding source region 11.

[0094] The width W3 of the contact region 25 is less than the distance between two adjacent gate electrodes 17 (gate structures 15). In other words, the width W3 of the contact region 25 is less than the length of the connection electrode 22 (gate connection structure 20) in the first direction X. The width W3 of the contact region 25 is preferably less than the width W1 of the gate electrode 17 in the first direction X. The width W3 of the contact region 25 is preferably less than the width W2 of the connection electrode 22 in the second direction Y.

[0095] The width W3 of the contact region 25 may be 0.1 μm or more and 5 μm or less. The width W3 of the contact region 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The width W3 of the contact region 25 is preferably 0.5 μm or more and 2 μm or less.

[0096] The plurality of contact regions 25 are formed at intervals in the second direction Y in the surface layer portion of the corresponding body region 10. In this embodiment, the plurality of contact regions 25 are arranged in a line in the second direction Y and face each other in the second direction Y with a part of the corresponding source region 11 interposed therebetween. In this embodiment, the plurality of contact regions 25 are each formed in a strip shape extending in the second direction Y.

[0097] The contact regions 25 have a length L in the second direction Y that is greater than the width W1 in the first direction X of the gate electrodes 17 (gate structures 15). The length L of the contact regions 25 is preferably greater than the width W2 in the second direction Y of the connection electrodes 22 (gate connection structures 20).

[0098] The length ratio L / W2 of the length L of the contact region 25 to the width W2 of the connection electrode 22 (gate connection structure 20) may be greater than 1 and less than or equal to 4. The length ratio L / W2 may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, 2.75 to 3, 3 to 3.25, 3.25 to 3.5, 3.5 to 3.75, and 3.75 to 4. The length ratio is preferably greater than 1 and less than or equal to 2.

[0099] The length L of the contact region 25 may be 1 μm or more and 10 μm or less. The length L of the contact region 25 may have a value belonging to at least one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The length L of the contact region 25 is preferably 1.5 μm or more and 5 μm or less.

[0100] The plurality of contact regions 25 are formed at intervals from the bottoms of the corresponding body regions 10 toward the first main surface 3, and face the second semiconductor region 7 in the thickness direction across a part of the corresponding body region 10. The plurality of contact regions 25 each have a bottom located closer to the bottom of the corresponding body region 10 than the bottom of the corresponding source region 11.

[0101] That is, the plurality of contact regions 25 are formed deeper than the corresponding source regions 11, and are electrically connected to the corresponding body regions 10 in regions below the depth position of the bottoms of the corresponding source regions 11. The plurality of contact regions 25 are exposed from the first main surface 3.

[0102] In this embodiment, the plurality of contact regions 25 are formed in regions directly below (below) the plurality of gate connection structures 20. In this embodiment, the plurality of contact regions 25 are formed in a one-to-one correspondence with the plurality of gate connection structures 20, and each face the corresponding gate connection structure 20 in the thickness direction (stacking direction). In other words, the plurality of contact regions 25 face the corresponding connection electrode 22 with the corresponding connection insulating film 21 sandwiched therebetween.

[0103] When the distance between the centers of the plurality of contact regions 25 in the second direction Y is defined as a third pitch P3, the third pitch P3 is approximately equal to the second pitch P2 of the plurality of gate connection structures 20. Of course, the third pitch P3 may be larger or smaller than the second pitch P2.

[0104] Each of the contact regions 25 has a concealed portion 26, a first lead portion 27, and a second lead portion 28. Each of the concealed portions 26 is formed by a portion that is concealed by the gate connection structures 20.

[0105] The first lead portions 27 are led out from the concealed portions 26 to one side in the second direction Y and are each formed of a portion exposed from the gate connection structures 20. The first lead portions 27 face each other in the first direction X, with the gate electrodes 17 interposed therebetween.

[0106] The second lead portions 28 are led out from the concealed portions 26 to the other side in the second direction Y, and are each made up of a portion exposed from the gate connection structures 20. The second lead portions 28 face each other in the first direction X, with the gate electrodes 17 interposed therebetween.

[0107] The second lead portions 28 may face the first lead portions 27 in the first direction X, with the gate electrodes 17 interposed therebetween. Of course, the second lead portions 28 may face regions between the first lead portions 27 and the second lead portions 28 in the first direction X, with the gate electrodes 17 interposed therebetween.

[0108] With respect to one and the other contact regions 25 adjacent to each other in the second direction Y, the first draw-out portion 27 of one contact region 25 is formed at a distance in the second direction Y from the second draw-out portion 28 of the other contact region 25, and faces the second draw-out portion 28 of the other contact region 25 in the second direction Y, sandwiching a portion of the corresponding source region 11 therebetween.

[0109] Such a configuration is effective in ensuring the connection area of ​​the external electrode with respect to the source region 11. Furthermore, such a configuration is effective when a plurality of gate electrodes 17 are arranged at a narrow pitch. For example, in a region surrounded by two gate electrodes 17 and two connection electrodes 22, the area occupied by the plurality of contact regions 25 (the total planar area of ​​the first lead portion 27 and the second lead portion 28) is preferably less than the area occupied by the source region 11 (planar area).

[0110] The planar area of ​​the first drawer portion 27 may be less than the planar area of ​​the concealing portion 26. Of course, the planar area of ​​the first drawer portion 27 may be greater than the planar area of ​​the concealing portion 26. The planar area of ​​the second drawer portion 28 may be less than the planar area of ​​the concealing portion 26. Of course, the planar area of ​​the second drawer portion 28 may be greater than the planar area of ​​the concealing portion 26.

[0111] It is preferable that the amount of extension of the second extension portion 28 in the second direction Y be approximately equal to the amount of extension of the first extension portion 27 in the second direction Y. Of course, the amount of extension of the second extension portion 28 may be greater than the amount of extension of the first extension portion 27, or may be smaller than the amount of extension of the first extension portion 27.

[0112] The extension length of the first extension portion 27 (second extension portion 28) may be 0.1 μm or more and 2 μm or less. The extension length of the first extension portion 27 (second extension portion 28) may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or more, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0113] 11 and 12 , semiconductor device 1 includes a p-type well region 30 formed in a surface layer portion of first main surface 3 in peripheral region 9. Well region 30 is formed in a surface layer portion of second semiconductor region 7. Well region 30 has a p-type impurity concentration that is higher than the n-type impurity concentration of second semiconductor region 7.

[0114] The well region 30 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 10. Of course, the p-type impurity concentration of the well region 30 may be lower than the p-type impurity concentration of the body region 10, or may be higher than the p-type impurity concentration of the body region 10.

[0115] The well region 30 is formed in a surface layer portion of the second semiconductor region 7 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the inside (active region 8 side) of the first main surface 3, and extends in a strip shape along the active region 8. The well region 30 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view, and defines a plurality of body regions 10 (active regions 8) from a plurality of directions.

[0116] In this embodiment, the well region 30 collectively surrounds the plurality of body regions 10 (active regions 8) in a plan view and is partitioned into a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the well region 30 forms the boundary between the active regions 8 and the outer peripheral region 9. The well region 30 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view.

[0117] The well region 30 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The well region 30 is preferably formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3. The well region 30 is exposed from the first main surface 3.

[0118] The well region 30 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the well region 30 is connected to the plurality of body regions 10 in a portion extending in the first direction X. In other words, the well region 30 is electrically connected to the plurality of body regions 10 in the surface layer portion of the second semiconductor region 7, and separates the plurality of body regions 10 from the plurality of surface drift regions 12.

[0119] As a result, a source potential is applied to the well region 30 via the plurality of body regions 10. The well region 30 forms a pn junction with the second semiconductor region 7, and expands a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied.

[0120] The well region 30 is connected to the body regions 10 at intervals in the second direction Y from the source regions 11. Therefore, the well region 30 does not have the source regions 11 in the surface layer portion. Furthermore, the well region 30 is connected to the body regions 10 at intervals in the second direction Y from the contact regions 25. Therefore, the well region 30 does not have the contact regions 25 in the surface layer portion.

[0121] The well region 30 preferably has a width greater than that of the body region 10. The width of the well region 30 is the width in a direction perpendicular to the extending direction. Of course, the width of the well region 30 may be approximately equal to the width of the body region 10 or may be less than the thickness of the body region 10.

[0122] The ratio of the width of the well region 30 to the width of the body region 10 may be equal to or greater than 1 and equal to or less than 50. The width ratio may have a value belonging to at least one of the ranges of 1 to 5, 5 to 10, 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, and 45 to 50.

[0123] The well region 30 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 10. Of course, the thickness of the well region 30 may be less than the thickness of the body region 10 or may be greater than the thickness of the body region 10.

[0124] The semiconductor device 1 includes a p-type termination region 31 formed on the first main surface 3 in the peripheral region 9. The termination region 31 may also be referred to as a "termination well region" or a "JTE region (Junction Termination Extension region)." The termination region 31 is formed in a surface layer portion of the second semiconductor region 7 in the peripheral region 9.

[0125] Termination region 31 has a p-type impurity concentration different from the p-type impurity concentrations of the plurality of body regions 10. The p-type impurity concentration of termination region 31 may be higher than the p-type impurity concentration of body region 10, or may be lower than the p-type impurity concentration of body region 10. Of course, the p-type impurity concentration of termination region 31 may be approximately equal to the p-type impurity concentration of body region 10.

[0126] The termination region 31 has a p-type impurity concentration that is different from the p-type impurity concentration of the well region 30. The p-type impurity concentration of the termination region 31 may be higher than the p-type impurity concentration of the well region 30, or may be lower than the p-type impurity concentration of the well region 30. Of course, the p-type impurity concentration of the termination region 31 may be approximately equal to the p-type impurity concentration of the well region 30.

[0127] The termination region 31 is formed in a region between the periphery of the first main surface 3 and the well region 30, with a space inward from the periphery of the first main surface 3. The termination region 31 extends in a band shape along the well region 30 in a plan view. The termination region 31 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0128] In this embodiment, termination region 31 surrounds well region 30 (active region 8 and multiple body regions 10) in plan view and is defined in the shape of a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of first main surface 3. Termination region 31 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in plan view in an arc shape (preferably a quadrant arc shape).

[0129] The termination region 31 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The termination region 31 is preferably formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3. The termination region 31 may have a thickness (depth) substantially equal to the thickness (depth) of the well region 30. The thickness of the termination region 31 may be greater than or less than the thickness of the well region 30.

[0130] The termination region 31 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the termination region 31 is connected to the outer edge portion of the well region 30. In this way, the termination region 31 is electrically connected to the well region 30. The termination region 31 is also electrically connected to a plurality of body regions 10 via the well region 30.

[0131] In this embodiment, the inner edge of the termination region 31 is connected to the outer edge of the well region 30 along the entire periphery. When the termination region 31 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the well region 30, the termination region 31 may be considered to be part of the well region 30. The termination region 31 forms a pn junction with the second semiconductor region 7, and expands a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied.

[0132] The termination region 31 (inner edge portion) has an overlap region 32 that overlaps the outer edge portion of the well region 30 in the surface layer portion of the second semiconductor region 7. The overlap region 32 is a high-concentration region that includes the outer edge portion of the well region 30 and the inner edge portion of the termination region 31. In other words, the overlap region 32 includes both the p-type impurity of the well region 30 and the p-type impurity of the termination region 31, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the well region 30 and the p-type impurity concentration of the termination region 31.

[0133] The p-type impurity concentration of the overlap region 32 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the overlap region 32 may be lower than the p-type impurity concentrations of the multiple contact regions 25. Of course, the p-type impurity concentration of the overlap region 32 may be higher than the p-type impurity concentrations of the multiple contact regions 25.

[0134] The overlap region 32 extends in a band shape along the well region 30 in a plan view. The overlap region 32 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the overlap region 32 is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The width of the overlap region 32 is preferably greater than the width of the body region 10. Of course, the width of the overlap region 32 may be equal to or less than the width of the body region 10.

[0135] The semiconductor device 1 may have a relatively high-concentration p-type termination contact region (32) instead of the overlap region 32. In this case, the termination contact region (32) has a p-type impurity concentration higher than both the p-type impurity concentration of the well region 30 and the p-type impurity concentration of the termination region 31. The p-type impurity concentration of the termination contact region (32) is higher than the p-type impurity concentration of the body region 10.

[0136] The p-type impurity concentration of the termination contact region (32) may be approximately equal to the p-type impurity concentration of the plurality of contact regions 25. Of course, the p-type impurity concentration of the termination contact region (32) may be less than the p-type impurity concentration of the plurality of contact regions 25, or may be higher than the p-type impurity concentration of the plurality of contact regions 25.

[0137] The termination contact region (32) may be formed in either or both of the surface layer portion of the well region 30 and the surface layer portion of the termination region 31. Such a configuration is effective when the termination region 31 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the well region 30 and is formed as part of the well region 30 (a drawn-out portion).

[0138] The semiconductor device 1 includes at least one p-type field region 33 formed in the surface layer portion of the first main surface 3 in the peripheral region 9. The plurality of field regions 33 may be formed in an electrically floating state. The plurality of field regions 33 may be fixed to the source potential.

[0139] The number of field regions 33 is arbitrary. The number of field regions 33 may be 1 or more and 20 or less. The number of field regions 33 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 33 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes three field regions 33.

[0140] The field regions 33 are formed at intervals from one another in a surface layer portion of the second semiconductor region 7. The field regions 33 are formed in a region between the periphery of the first main surface 3 and the body regions 10 (active regions 8) at intervals inward from the periphery of the first main surface 3. Specifically, the field regions 33 are formed in a region between the periphery of the first main surface 3 and the well region 30. More specifically, the field regions 33 are arranged at intervals from the outer edge of the termination region 31 toward the periphery of the first main surface 3 in the region between the periphery of the first main surface 3 and the termination region 31.

[0141] The field regions 33 are formed in a strip shape extending along the body regions 10 (termination regions 31) in a plan view. Each of the field regions 33 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0142] In this embodiment, the plurality of field regions 33 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the plurality of body regions 10 (termination regions 31) in a plan view. The plurality of field regions 33 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0143] The plurality of field regions 33 are formed at intervals from a depth position of the bottom of the second semiconductor region 7 toward the first main surface 3. The plurality of field regions 33 are formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3. The plurality of field regions 33 each form a pn junction with the second semiconductor region 7, and expand a depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied.

[0144] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 33 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 33 may be approximately constant or may be non-uniform. The width of the multiple field regions 33 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 33 may gradually decrease toward the periphery of the first main surface 3.

[0145] The depth of the multiple field regions 33 may be approximately constant or may be non-uniform. The depth of the multiple field regions 33 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 33 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 33 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0146] The spacing between the multiple field regions 33 may be approximately constant or may be non-uniform. The spacing between the multiple field regions 33 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 33 may gradually decrease toward the periphery of the first main surface 3.

[0147] The p-type impurity concentrations of the plurality of field regions 33 may be approximately constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 33 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 33 may gradually decrease toward the periphery of the first main surface 3.

[0148] The plurality of field regions 33 may have a p-type impurity concentration approximately equal to the p-type impurity concentration of the plurality of body regions 10. The p-type impurity concentration of the plurality of field regions 33 may be higher than the p-type impurity concentration of the plurality of body regions 10, or may be lower than the p-type impurity concentration of the plurality of body regions 10.

[0149] The plurality of field regions 33 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the well region 30. The p-type impurity concentration of the plurality of field regions 33 may be higher than the p-type impurity concentration of the well region 30, or may be lower than the p-type impurity concentration of the well region 30.

[0150] The p-type impurity concentrations of the plurality of field regions 33 may be approximately equal to the p-type impurity concentration of the termination region 31. The p-type impurity concentrations of the plurality of field regions 33 may be higher than the p-type impurity concentration of the termination region 31, or may be lower than the p-type impurity concentration of the termination region 31.

[0151] The semiconductor device 1 includes a main surface insulating film 34 covering the first main surface 3. The main surface insulating film 34 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 34 preferably includes the same type of insulating material as either or both of the insulating material of the gate insulating film 16 and the insulating material of the connection insulating film 21.

[0152] In this embodiment, the main surface insulating film 34 has a single-layer structure made of a silicon oxide film. The main surface insulating film 34 preferably includes a silicon oxide film made of an oxide of the chip 2. The main surface insulating film 34 preferably has a thickness approximately equal to the thickness of either or both of the gate insulating film 16 and the connection insulating film 21.

[0153] The main surface insulating film 34 collectively covers the second semiconductor region 7, the well region 30, the termination region 31, and the plurality of field regions 33 in the peripheral region 9. The main surface insulating film 34 has a portion connected to the plurality of gate insulating films 16 on the active region 8 side. In this embodiment, the main surface insulating film 34 has a portion connected to the plurality of connection insulating films 21 on the active region 8 side. In this embodiment, the main surface insulating film 34 is formed integrally with the plurality of gate insulating films 16 and the plurality of connection insulating films 21, and forms a single insulating film together with the plurality of gate insulating films 16 and the plurality of connection insulating films 21.

[0154] The semiconductor device 1 includes a gate wiring 35 arranged on the first main surface 3 in the peripheral region 9. The gate wiring 35 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 17. The gate wiring 35 is connected to the multiple gate electrodes 17 and applies gate signals to the multiple gate electrodes 17. The gate wiring 35 may also be referred to as a "third gate electrode" or the like.

[0155] The gate wiring 35 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 35 preferably includes the same type of conductive material as either or both of the conductive material of the plurality of gate electrodes 17 and the conductive material of the plurality of connection electrodes 22.

[0156] The gate wiring 35 is arranged on the main surface insulating film 34 at a distance from the periphery of the first main surface 3 to the inside of the first main surface 3 (toward the active region 8) in the outer periphery region 9. The gate wiring 35 is arranged at a distance from the innermost field region 33 toward the active region 8, exposing all of the field region 33. In this embodiment, the gate wiring 35 is arranged at a distance from the termination region 31 toward the active region 8, and is arranged on a portion of the main surface insulating film 34 that covers the well region 30.

[0157] That is, the gate wiring 35 faces the well region 30 with the main surface insulating film 34 sandwiched therebetween. In this embodiment, the gate wiring 35 is formed narrower than the well region 30 in a plan view and is disposed on the well region 30 at a distance from the inner and outer edges of the well region 30. The gate wiring 35 is disposed at a distance from the overlap region 32 of the termination region 31 toward the active region 8. The gate wiring 35 may have a portion facing the termination region 31 in the stacking direction.

[0158] The gate wiring 35 extends in a strip shape along the multiple gate electrodes 17 (active regions 8) in a plan view. The gate wiring 35 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view, and defines the multiple body regions 10 (active regions 8) from multiple directions. In this embodiment, the gate wiring 35 is defined in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the multiple body regions 10 (multiple gate structures 15). The gate wiring 35 may be either terminated or endless.

[0159] In this embodiment, the gate wiring 35 extends in a strip shape (annular shape in this embodiment) along the well region 30 in plan view, and faces the well region 30 across the main surface insulating film 34 over the entire area in the stacking direction. The gate wiring 35 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in plan view in an arc shape (preferably a quarter arc shape).

[0160] The gate wiring 35 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 35 is connected to the multiple gate electrodes 17 in a portion extending in the first direction X. As a result, the gate wiring 35 transmits a gate potential to the multiple gate electrodes 17.

[0161] In this embodiment, the inner edge of the gate wiring 35 has a portion that extends in the second direction Y and is connected to the plurality of connection electrodes 22. As a result, the gate wiring 35 transmits a gate potential to the plurality of gate electrodes 17 via the plurality of connection electrodes 22. The gate wiring 35 has a thickness that is approximately equal to either or both of the thickness of the gate electrode 17 and the thickness of the connection electrodes 22 (both in this embodiment). In this embodiment, the gate wiring 35 is formed integrally with the plurality of gate electrodes 17 and the plurality of connection electrodes 22, and forms a single electrode together with the plurality of gate electrodes 17 and the plurality of connection electrodes 22.

[0162] The width of the gate wiring 35 is preferably larger than the width of the gate electrode 17. The width of the gate wiring 35 is the width of the gate wiring 35 in a direction perpendicular to the direction in which the gate wiring 35 extends. Of course, the width of the gate wiring 35 may be equal to or smaller than the width of the gate electrode 17. The width of the gate wiring 35 is preferably larger than the width of the connection electrode 22. Of course, the width of the gate wiring 35 may be equal to or smaller than the width of the connection electrode 22.

[0163] For example, the wiring width ratio of the width of the gate wiring 35 to the width of the gate electrode 17 may be 1 or more and 50 or less. The wiring width ratio may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, 15 or more and 20 or less, 20 or more and 25 or less, 25 or more and 30 or less, 30 or more and 35 or less, 35 or more and 40 or less, 40 or more and 45 or less, and 45 or more and 50 or less.

[0164] The semiconductor device 1 includes an insulating interlayer film 40 that covers the first main surface 3. The interlayer film 40 may also be referred to as an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 40 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0165] The interlayer film 40 covers the plurality of gate structures 15 and the plurality of gate connection structures 20 in the active region 8. The interlayer film 40 collectively covers the second semiconductor region 7, the well region 30, the termination region 31, and the plurality of field regions 33 in the peripheral region 9, with the main surface insulating film 34 sandwiched therebetween.

[0166] The interlayer film 40 covers the gate wiring 35 in the peripheral region 9. The interlayer film 40 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 40 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0167] In this embodiment, the interlayer film 40 has a layered structure including a first interlayer film 41 and a second interlayer film 42, which are layered in this order from the first main surface 3 side. The first interlayer film 41 has a single-layer structure made of a silicon oxide film with no impurities added. The first interlayer film 41 may also be called an NSG film (nondoped silicate glass film).

[0168] The first interlayer film 41 has a thickness greater than that of the gate insulating film 16. In this embodiment, the thickness of the first interlayer film 41 is less than that of the gate electrode 17. The thickness of the first interlayer film 41 may be greater than that of the gate electrode 17. In this embodiment, the thickness of the first interlayer film 41 is less than that of the connection electrode 22. The thickness of the first interlayer film 41 may be greater than that of the connection electrode 22.

[0169] The first interlayer film 41 collectively covers the active region 8 and the peripheral region 9. The first interlayer film 41 collectively covers the plurality of gate structures 15 and the plurality of gate connection structures 20 in the active region 8.

[0170] The first interlayer film 41 coats both the gate insulating films 16 and the gate electrodes 17 of the gate structures 15. The first interlayer film 41 has a portion that coats the gate insulating films 16 in the horizontal direction, a portion that coats the side walls of the gate electrodes 17 in the stacking direction, and a portion that coats the electrode surfaces of the gate electrodes 17 in the horizontal direction.

[0171] The first interlayer film 41 coats both the plurality of connection insulating films 21 and the plurality of connection electrodes 22 in a film form for the plurality of gate connection structures 20. The first interlayer film 41 has a portion that coats the plurality of connection insulating films 21 in a film form along the horizontal direction, a portion that coats the side walls of the plurality of connection electrodes 22 in a film form along the stacking direction, and a portion that coats the electrode surfaces of the plurality of connection electrodes 22 in a film form along the horizontal direction.

[0172] The first interlayer film 41 collectively covers the second semiconductor region 7, the well region 30, the termination region 31, and the plurality of field regions 33 with the main surface insulating film 34 sandwiched therebetween in the peripheral region 9. The first interlayer film 41 covers the gate wiring 35 in a film-like manner in the peripheral region 9. The first interlayer film 41 has a portion that covers the main surface insulating film 34 in a film-like manner along the horizontal direction, a portion that covers the sidewall of the gate wiring 35 in a film-like manner along the stacking direction, and a portion that covers the electrode surface of the gate wiring 35 in a film-like manner along the horizontal direction.

[0173] The second interlayer film 42 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0174] The second interlayer film 42 may have a single layer structure made of a PSG film or a BPSG film laminated on the first interlayer film 41. The second interlayer film 42 may have a layered structure including a PSG film laminated on the first interlayer film 41 and a BPSG film laminated on the PSG film. The second interlayer film 42 may have a layered structure including a BPSG film laminated on the first interlayer film 41 and a PSG film laminated on the BPSG film.

[0175] In this embodiment, the second interlayer film 42 has a single-layer structure made of, for example, a PSG film. The second interlayer film 42 has a thickness greater than that of the gate insulating film 16. The thickness of the second interlayer film 42 may be greater than that of the first interlayer film 41. The thickness of the second interlayer film 42 may be less than that of the first interlayer film 41.

[0176] The thickness of the second interlayer film 42 may be less than the thickness of the gate electrode 17. The thickness of the second interlayer film 42 may be greater than the thickness of the gate electrode 17. In this embodiment, the thickness of the second interlayer film 42 may be less than the thickness of the connection electrode 22. The thickness of the second interlayer film 42 may be greater than the thickness of the connection electrode 22.

[0177] The second interlayer film 42 covers the first interlayer film 41 in a film form, and collectively covers the active region 8 and the peripheral region 9 with the first interlayer film 41 in between. The second interlayer film 42 collectively covers the plurality of gate structures 15 and the plurality of gate connection structures 20 in the active region 8 with the first interlayer film 41 in between.

[0178] The second interlayer film 42 covers both the gate insulating films 16 and the gate electrodes 17 of the gate structures 15 with the first interlayer film 41 sandwiched therebetween. The second interlayer film 42 has a portion that covers the gate insulating films 16 with the first interlayer film 41 sandwiched therebetween, a portion that covers the side walls of the gate electrodes 17 with the first interlayer film 41 sandwiched therebetween, and a portion that covers the electrode surfaces of the gate electrodes 17 with the first interlayer film 41 sandwiched therebetween.

[0179] The second interlayer film 42 extends from a region directly above the gate insulating films 16 along the side walls of the gate electrodes 17. Of course, the second interlayer film 42 may have a portion extending horizontally along the gate insulating films 16 in the region directly above the gate insulating films 16.

[0180] The second interlayer film 42 covers both the plurality of connection insulating films 21 and the plurality of connection electrodes 22 with the first interlayer film 41 interposed therebetween for the plurality of gate connection structures 20. The second interlayer film 42 has a portion that covers the plurality of connection insulating films 21 with the first interlayer film 41 interposed therebetween, a portion that covers the side walls of the plurality of connection electrodes 22 with the first interlayer film 41 interposed therebetween, and a portion that covers the electrode surfaces of the plurality of connection electrodes 22 with the first interlayer film 41 interposed therebetween.

[0181] The second interlayer film 42 collectively covers the second semiconductor region 7, well region 30, termination region 31, and multiple field regions 33 in the peripheral region 9, sandwiching the main surface insulating film 34 and the first interlayer film 41 therebetween. The second interlayer film 42 covers the gate wiring 35 in the peripheral region 9, sandwiching the first interlayer film 41 therebetween. The second interlayer film 42 has a portion that covers the main surface insulating film 34 with the first interlayer film 41 therebetween, a portion that covers the sidewall of the gate wiring 35 with the first interlayer film 41 therebetween, and a portion that covers the electrode surface of the gate wiring 35 with the first interlayer film 41 therebetween.

[0182] The second interlayer film 42 is smoothed by reflow to form an insulating surface with reduced unevenness. Diffusion of impurities in the second interlayer film 42 into the gate electrodes 17 is suppressed by the first interlayer film 41. This suppresses fluctuations in the electrical characteristics (e.g., resistance value) of the gate electrodes 17.

[0183] The first interlayer film 41 suppresses the diffusion of impurities in the second interlayer film 42 into the plurality of connection electrodes 22, thereby suppressing fluctuations in the electrical characteristics (e.g., resistance value) of the plurality of connection electrodes 22. The first interlayer film 41 suppresses the diffusion of impurities in the second interlayer film 42 into the gate wiring 35, thereby suppressing fluctuations in the electrical characteristics (e.g., resistance value) of the gate wiring 35.

[0184] The semiconductor device 1 includes a plurality of source openings 45 formed in the interlayer film 40 in the active region 8. The plurality of source openings 45 are formed at intervals from the plurality of gate electrodes 17 and the plurality of connection electrodes 22, respectively, and are formed in a line in the second direction Y at intervals in a region between the plurality of adjacent gate electrodes 17.

[0185] Specifically, the source openings 45 are formed in regions defined by the gate electrodes 17 and the connection electrodes 22. Each of the source openings 45 is defined in a quadrangular shape in plan view. In this embodiment, each of the source openings 45 is defined in a strip shape (rectangular shape) extending in the second direction Y.

[0186] In this embodiment, the source openings 45 are formed in a staggered pattern in plan view at intervals in the first direction X and the second direction Y. Specifically, with respect to the source openings 45 arranged on both sides of the gate structures 15, the source openings 45 on one side in the first direction X are shifted in the second direction Y relative to the source openings 45 on the other side in the first direction X.

[0187] That is, the plurality of source openings 45 on one side face regions between the plurality of source openings 45 on the other side in the first direction X. In this embodiment, the plurality of source openings 45 face the plurality of gate connection structures 20 (connection electrodes 22), one end of the source openings 45 on one side in the second direction Y, and the other end of the source openings 45 on the other side in the second direction Y in the first direction X.

[0188] The plurality of source openings 45 penetrate the gate insulating film 16, the connection insulating film 21, and the interlayer film 40 to expose the corresponding source regions 11 and the corresponding plurality of contact regions 25. The plurality of source openings 45 expose the first lead-out portion 27 of one contact region 25 in the second direction Y and the second lead-out portion 28 of the other contact region 25 in the second direction Y. The plurality of source openings 45 have opening ends defined in an arc shape by the interlayer film 40 (second interlayer film 42).

[0189] The source openings 45 may have an opening width WO of 0.1 μm to 3 μm in the first direction X. The opening width WO may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm. The opening width WO is preferably 0.75 μm to 2.25 μm.

[0190] The source openings 45 may have an opening depth DO of 0.1 μm to 2 μm. The opening depth DO may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The opening depth DO is preferably 0.5 μm to 1.5 μm.

[0191] The source opening 45 preferably has an aspect ratio DO / WO of 0.5 to 3. The aspect ratio DO / WO is defined as the ratio of the opening depth DO to the opening width WO. The aspect ratio DO / WO may have a value belonging to at least one of the ranges of 0.5 to 1, 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0192] The aspect ratio DO / WO is preferably greater than 1. That is, the source openings 45 are preferably each formed in a vertically elongated shape in a cross-sectional view. Such a configuration contributes to a narrow pitch arrangement of the body regions 10 and the gate structures 15.

[0193] The layout of the plurality of gate connection structures 20 increases the number of current paths in such a narrow pitch arrangement, which is effective in reducing the resistance of the entire planar structure 14. Furthermore, the layout of the plurality of source regions 11 and the plurality of contact regions 25 provides appropriate connections with external electrodes in such a narrow pitch arrangement, which is effective in improving the electrical response characteristics.

[0194] The aspect ratio DO / WO of the elongated source opening 45 may have a value belonging to at least one of the ranges of greater than 1 and less than 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio DO / WO is preferably 2 or less.

[0195] The semiconductor device 1 includes a plurality of source recesses 46 formed in the first main surface 3 in portions exposed from the plurality of source openings 45. The semiconductor device 1 does not necessarily have to have the source recesses 46. Therefore, a configuration not including the source recesses 46 may be employed.

[0196] The plurality of source recesses 46 each have a planar shape that matches the planar shape of the corresponding source opening 45, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 46 are formed at intervals from the bottoms of the corresponding body regions 10 toward the first main surface 3. The plurality of source recesses 46 are formed at intervals from the bottoms of the corresponding source regions 11 and the bottoms of the corresponding plurality of contact regions 25 toward the first main surface 3.

[0197] The plurality of source recesses 46 expose the corresponding source regions 11 and the corresponding plurality of contact regions 25. The plurality of source recesses 46 expose the first lead-out portion 27 of one of the contact regions 25 in the second direction Y and the second lead-out portion 28 of the other of the contact regions 25 in the second direction Y.

[0198] The semiconductor device 1 includes at least one (in this embodiment, multiple) outer openings 47 formed in the interlayer film 40 in the peripheral region 9. The multiple outer openings 47 are formed in a portion of the interlayer film 40 that covers the termination region 31. The multiple outer openings 47 penetrate the main surface insulating film 34 and the interlayer film 40, exposing the termination region 31.

[0199] In this embodiment, the outer openings 47 expose the overlap region 32 of the termination region 31. The outer openings 47 may expose the well region 30 instead of or in addition to the termination region 31 (overlap region 32). The outer openings 47 each have an opening end defined in an arc shape by the interlayer film 40 (second interlayer film 42).

[0200] The outer openings 47 are spaced apart along the terminal region 31 (overlap region 32). The outer openings 47 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The outer openings 47 may be formed in a strip shape extending along the terminal region 31 (overlap region 32) in plan view.

[0201] The semiconductor device 1 may have a single outer opening 47. The single outer opening 47 may be formed in a strip shape extending along the termination region 31 (overlap region 32). The single outer opening 47 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0202] The single outer opening 47 may be formed in the shape of an ended or endless polygonal ring (for example, a square ring) having four sides parallel to the periphery of the first main surface 3. The single outer opening 47 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 31 (overlapping region 32) in a plan view.

[0203] The semiconductor device 1 includes a plurality of outer recesses 48 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 47. The semiconductor device 1 does not necessarily have to have the outer recesses 48. Therefore, a configuration not having the outer recesses 48 may be employed.

[0204] The multiple outer recesses 48 each have a planar shape that matches the planar shape of the corresponding outer opening 47, and are recessed from the first main surface 3 toward the second main surface 4. The multiple outer recesses 48 are formed at intervals from the bottom of the termination region 31 (overlap region 32) toward the first main surface 3, and each exposes the termination region 31 (overlap region 32). When a single outer opening 47 is formed, a single outer recess 48 that matches the planar shape of the single outer opening 47 is formed. The outer recesses 48 may have a depth approximately equal to the depth of the source recess 46.

[0205] The semiconductor device 1 includes a plurality of gate openings 49 formed in the interlayer film 40 in the peripheral region 9. In this embodiment, the plurality of gate openings 49 includes one or more (a plurality in this embodiment) gate openings 49 formed in the portion of the interlayer film 40 covering the gate wiring 35 and a plurality of gate openings 49 formed in the portion of the interlayer film 40 covering the plurality of gate electrodes 17.

[0206] The plurality of gate openings 49 are formed at intervals along the gate wiring 35 on the peripheral region 9 side. The plurality of gate openings 49 penetrate the interlayer film 40 and expose a portion of the gate wiring 35. The plurality of gate openings 49 are formed at intervals along the gate wiring 35.

[0207] The plurality of gate openings 49 penetrate the interlayer film 40 on the active region 8 side, and expose the inner portions (intermediate portions in this embodiment) of the plurality of gate electrodes 17. The plurality of gate openings 49 each have an opening end defined in an arc shape by the interlayer film 40 (second interlayer film 42).

[0208] The multiple gate openings 49 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The semiconductor device 1 may have a single gate opening 49 on the outer periphery region 9 side. The single gate opening 49 may be formed in a strip shape extending along the gate wiring 35. The single gate opening 49 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0209] The single gate opening 49 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 49 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the gate wiring 35 in a plan view.

[0210] The semiconductor device 1 includes a source pad electrode 50 disposed on the first main surface 3. The source pad electrode 50 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 50 may also be referred to as a "source pad," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0211] The source pad electrode 50 is disposed on a portion of the interlayer film 40 that covers the active region 8. The source pad electrode 50 covers the plurality of gate electrodes 17 and the plurality of connection electrodes 22 with the interlayer film 40 in between, and is electrically isolated from the plurality of gate electrodes 17 and the plurality of connection electrodes 22 by the interlayer film 40.

[0212] The source pad electrode 50 extends into the plurality of source openings 45 from above the interlayer film 40, and is electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 within the plurality of source openings 45. The source pad electrode 50 is electrically connected to the first lead-out portion 27 of one contact region 25 in the second direction Y and the second lead-out portion 28 of the other contact region 25 in the second direction Y within the plurality of source openings 45.

[0213] In this embodiment, the source pad electrode 50 includes a notch 51 extending in a strip shape from the central peripheral edge of the third side surface 5C toward the fourth side surface 5D in the first direction X. The source pad electrode 50 has a first pad portion 50a and a second pad portion 50b partitioned by the notch 51 onto one side and the other side in the second direction Y.

[0214] The first pad portion 50a is disposed on the first side surface 5A side of the central portion of the first main surface 3 (specifically, the plurality of gate openings 49), and is formed in a strip shape extending in the first direction X. The second pad portion 50b is disposed on the second side surface 5B side of the central portion of the first main surface 3 (specifically, the plurality of gate openings 49), and is formed in a strip shape extending in the first direction X. The second pad portion 50b is connected to the first pad portion 50a in a region on the fourth side surface 5D side.

[0215] The plane area of ​​the second pad portion 50b is approximately equal to that of the first pad portion 50a. Of course, the plane area of ​​the second pad portion 50b may be larger or smaller than that of the first pad portion 50a. Either one or both of one end of the first pad portion 50a and one end of the second pad portion 50b may be used as a terminal portion for monitoring current.

[0216] In this embodiment, the source pad electrode 50 (first pad portion 50a and second pad portion 50b) has a laminated structure including a lower electrode film 52, multiple buried electrodes 53, and a main electrode film 54, which are laminated in this order from the chip 2 side.

[0217] In this embodiment, the lower electrode film 52 has a laminated structure including a first electrode film 55 and a second electrode film 56. In this embodiment, the first electrode film 55 includes a Ti film, and the second electrode film 56 includes a TiN film. The lower electrode film 52 does not necessarily have to have a laminated structure, and may have a single-layer structure including either the first electrode film 55 (Ti film) or the second electrode film 56 (TiN film).

[0218] The first electrode film 55 has a thickness less than the thickness of the interlayer film 40. The thickness of the first electrode film 55 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 55 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0219] The second electrode film 56 has a thickness less than that of the interlayer film 40. The thickness of the second electrode film 56 is preferably greater than that of the first electrode film 55. The thickness of the second electrode film 56 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 56 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0220] The first electrode film 55 collectively covers the region of the interlayer film 40 where the plurality of source openings 45 are formed, and extends into the plurality of source openings 45 from above the interlayer film 40. The first electrode film 55 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 45 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner.

[0221] In this embodiment, the first electrode film 55 has a portion that covers the source recesses 46 in a film-like manner on the bottom walls of the source openings 45. The first electrode film 55 may cover the source recesses 46 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the source recesses 46. The first electrode film 55 may have a portion located on the bottom side of the source recesses 46 relative to the height position of the first main surface 3, and a portion located on the insulating surface side of the interlayer film 40 relative to the height position of the first main surface 3.

[0222] The first electrode film 55 is electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 within the plurality of source openings 45. The first electrode film 55 is electrically connected to the first lead portion 27 of one contact region 25 in the second direction Y and the second lead portion 28 of the other contact region 25 in the second direction Y within the plurality of source openings 45.

[0223] The second electrode film 56 directly covers the first electrode film 55. The second electrode film 56 collectively covers the region of the interlayer film 40 in which the multiple source openings 45 are formed, sandwiching the first electrode film 55 therebetween, and extends into the multiple source openings 45 from above the interlayer film 40. The second electrode film 56 has a portion that sandwiches the first electrode film 55 and coats the insulating surface of the interlayer film 40 in a film-like manner, a portion that sandwiches the first electrode film 55 and coats the wall surfaces of the multiple source openings 45 in a film-like manner, and a portion that sandwiches the first electrode film 55 and coats the first main surface 3 in a film-like manner.

[0224] In this embodiment, the second electrode film 56 has a portion that covers the source recesses 46 in a film-like manner on the bottom walls of the source openings 45, sandwiching the first electrode film 55. When the first electrode film 55 is located on the bottom side of the source recesses 46 with respect to the first main surface 3, the second electrode film 56 has a portion that is located within the source recesses 46. When the first electrode film 55 has a portion that is located above the first main surface 3, the entire second electrode film 56 is located on the insulating surface side of the interlayer film 40 with respect to the source recesses 46.

[0225] The second electrode film 56 is electrically connected to the source regions 11 and the contact regions 25 via the first electrode film 55 in the source openings 45. The second electrode film 56 is electrically connected to the first lead-out portion 27 of one contact region 25 in the second direction Y and the second lead-out portion 28 of the other contact region 25 in the second direction Y via the first electrode film 55 in the source openings 45.

[0226] The plurality of buried electrodes 53 are buried in the plurality of source openings 45, with the lower electrode film 52 sandwiched therebetween. The buried electrodes 53 contain a conductive material different from the conductive material of the lower electrode film 52. The buried electrodes 53 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the buried electrodes 53 contain tungsten.

[0227] In this embodiment, the multiple buried electrodes 53 are buried in a one-to-one correspondence with the multiple source openings 45 via the lower electrode film 52. The multiple buried electrodes 53 are electrically connected to the multiple source regions 11 and the multiple contact regions 25 via the lower electrode film 52 within the multiple source openings 45. The multiple buried electrodes 53 are electrically connected to the first lead portion 27 of one contact region 25 in the second direction Y and the second lead portion 28 of the other contact region 25 in the second direction Y via the lower electrode film 52 within the multiple source openings 45.

[0228] When the lower electrode film 52 is located on the bottom side of the source recess 46 relative to the height position of the first main surface 3, the multiple buried electrodes 53 may have portions located within the multiple source recesses 46. When the lower electrode film 52 has portions located on the insulating surface side of the interlayer film 40 relative to the height position of the first main surface 3, the multiple buried electrodes 53 are all located above the source recess 46.

[0229] The multiple buried electrodes 53 each have an electrode surface positioned on the bottom wall (bottom of the source recess 46) side of the multiple source openings 45 relative to the insulating surface of the interlayer film 40, and expose the portion of the lower electrode film 52 that covers the insulating surface of the interlayer film 40.

[0230] The electrode surfaces of the plurality of buried electrodes 53 are preferably located closer to the insulating surface of the interlayer film 40 than the height positions of the electrode surfaces of the plurality of gate electrodes 17 and the plurality of connection electrodes 22. Of course, the electrode surfaces of the plurality of buried electrodes 53 may also be located closer to the bottom walls of the plurality of source openings 45 than the height positions of the electrode surfaces of the plurality of gate electrodes 17 and the plurality of connection electrodes 22.

[0231] When a plurality of source openings 45 are formed in a longitudinally elongated shape with a relatively high aspect ratio DO / WO (>1), the plurality of buried electrodes 53 are effective in improving the embeddability of the plurality of source openings 45. That is, the plurality of buried electrodes 53 are effective in a configuration in which a plurality of body regions 10 and a plurality of gate structures 15 are arranged at a narrow pitch.

[0232] The main electrode film 54 contains a different conductive material from the lower electrode film 52 (the first electrode film 55 and the second electrode film 56). The main electrode film 54 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 54 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. The thickness of the main electrode film 54 is preferably greater than the thickness of the interlayer film 40.

[0233] The thickness of the main electrode film 54 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 54 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0234] The main electrode film 54 directly covers the lower electrode film 52 (second electrode film 56) and the plurality of buried electrodes 53. The main electrode film 54 has a portion that covers the insulating surface of the interlayer film 40 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the plurality of source openings 45 with the plurality of buried electrodes 53 sandwiched therebetween. The main electrode film 54 is electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 via the lower electrode film 52 and the plurality of buried electrodes 53.

[0235] The semiconductor device 1 includes a plurality of first source silicides 57 formed on the surface portions of the first main surface 3 that are exposed from the plurality of source openings 45. The plurality of first source silicides 57 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 46, and are mechanically and electrically connected to the corresponding source regions 11 and the corresponding plurality of contact regions 25.

[0236] The first source silicide 57 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first source silicide 57 is preferably made of Ti silicide, Ni silicide, or Co silicide.

[0237] The semiconductor device 1 does not necessarily need to include the first source silicide 57. In this case, the lower electrode film 52 is mechanically and electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 in the plurality of source openings 45 (the plurality of source recesses 46).

[0238] The semiconductor device 1 includes a source finger electrode 58 selectively routed over a portion of the interlayer film 40 that covers the peripheral region 9. The source finger electrode 58 may also be referred to as a "source finger," a "first finger electrode," or the like.

[0239] In this embodiment, the source finger electrodes 58 are arranged around the source pad electrode 50 and are connected to the ends of the source pad electrode 50 (first pad portion 50 a and second pad portion 50 b) on the fourth side surface 5D side. The source finger electrodes 58 have a wiring width less than the electrode width of the source pad electrode 50 and extend in a strip shape along the periphery of the source pad electrode 50.

[0240] In this embodiment, the source finger electrode 58 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the source pad electrode 50. The source finger electrode 58 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). The source finger electrode 58 may be either ended or endless.

[0241] Source finger electrodes 58 are formed at intervals from the periphery of first main surface 3 inward (toward active region 8) of first main surface 3. Source finger electrodes 58 are formed at intervals inward from the innermost field region 33. In other words, source finger electrodes 58 do not face multiple field regions 33 across interlayer film 40. Source finger electrodes 58 are formed at intervals inward from the outer edge of termination region 31, and face termination region 31 across interlayer film 40.

[0242] Source finger electrodes 58 extend into the outer openings 47 from above interlayer film 40 and are electrically connected to termination region 31 (overlap region 32) within the outer openings 47. In this embodiment, source finger electrodes 58 cover termination region 31 (overlap region 32) over the entire periphery.

[0243] Similar to the source pad electrode 50, the source finger electrode 58 has a laminated structure including a lower electrode film 52, a buried electrode 53, and a main electrode film 54, which are laminated in this order from the chip 2 side. The lower electrode film 52 has a laminated structure including a first electrode film 55 and a second electrode film 56.

[0244] The first electrode film 55 collectively covers the regions of the interlayer film 40 where the multiple outer openings 47 are formed, and extends into the multiple outer openings 47 from above the interlayer film 40. The first electrode film 55 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surfaces of the multiple outer openings 47 in a film-like manner, and a portion that covers the first main surface 3 within the multiple outer openings 47 in a film-like manner.

[0245] In this embodiment, the first electrode film 55 has a portion that covers the outer recess 48 in a film-like manner on the bottom wall of the plurality of outer openings 47. The first electrode film 55 may cover the outer recess 48 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 48.

[0246] The first electrode film 55 may have a portion located on the bottom side of the outer recess 48 relative to the height position of the first main surface 3, and a portion located on the insulating surface side of the interlayer film 40 relative to the height position of the first main surface 3. The first electrode film 55 is mechanically and electrically connected to the termination region 31 (overlap region 32) within the multiple outer openings 47.

[0247] The second electrode film 56 directly covers the first electrode film 55. The second electrode film 56 collectively covers the region of the interlayer film 40 where the multiple outer openings 47 are formed, sandwiching the first electrode film 55 therebetween, and extends from above the interlayer film 40 into the multiple outer openings 47.

[0248] The second electrode film 56 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner with the first electrode film 55 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of outer openings 47 in a film-like manner with the first electrode film 55 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 55 sandwiched therebetween. In this embodiment, the second electrode film 56 has portions that cover the outer recesses 48 in a film-like manner on the bottom walls of the plurality of outer openings 47 with the first electrode film 55 sandwiched therebetween.

[0249] When the first electrode film 55 is located on the bottom side of the outer recess 48 relative to the first main surface 3, the second electrode film 56 has a portion located within the outer recess 48. When the first electrode film 55 has a portion located above the first main surface 3, the entire second electrode film 56 is located on the insulating surface side of the interlayer film 40 relative to the outer recess 48. The second electrode film 56 is electrically connected to the termination region 31 (overlap region 32) via the first electrode film 55 within the multiple outer openings 47.

[0250] The buried electrodes 53 are buried in the outer openings 47 with the lower electrode film 52 sandwiched therebetween. The buried electrodes 53 are electrically connected to the termination region 31 (overlap region 32) within the outer openings 47 via the lower electrode film 52.

[0251] When the lower electrode film 52 is located on the bottom side of the outer recess 48 relative to the height position of the first main surface 3, the multiple embedded electrodes 53 may have portions located within the outer recess 48. When the lower electrode film 52 has portions located on the insulating surface side of the interlayer film 40 relative to the height position of the first main surface 3, the multiple embedded electrodes 53 are all located above the outer recess 48.

[0252] The buried electrodes 53 each have an electrode surface positioned on the bottom wall (bottom of the outer recess 48) side of the multiple outer openings 47 relative to the insulating surface of the interlayer film 40, and expose the portion of the lower electrode film 52 that covers the insulating surface of the interlayer film 40.

[0253] The electrode surface of the buried electrode 53 is preferably located closer to the insulating surface of the interlayer film 40 than the height positions of the electrode surfaces of the plurality of gate electrodes 17 and the plurality of connection electrodes 22. Of course, the electrode surface of the buried electrode 53 may also be located closer to the bottom walls of the plurality of outer openings 47 than the height positions of the electrode surfaces of the plurality of gate electrodes 17 and the plurality of connection electrodes 22.

[0254] The main electrode film 54 directly covers the lower electrode film 52 (second electrode film 56) and the buried electrode 53. The main electrode film 54 has a portion that covers the insulating surface of the interlayer film 40 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the outer openings 47 with the buried electrode 53 sandwiched therebetween. The main electrode film 54 is electrically connected to the termination region 31 (overlap region 32) via the lower electrode film 52 and the buried electrode 53.

[0255] The semiconductor device 1 includes a plurality of second source silicides 59 formed on the surface portions of the first main surface 3 that are exposed from the plurality of outer openings 47. The plurality of second source silicides 59 are formed in film form along the wall surfaces (side walls and bottom wall) of the outer recess 48, and are mechanically and electrically connected to the termination region 31 (overlap region 32).

[0256] The second source silicide 59 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second source silicide 59 is preferably made of Ti silicide, Ni silicide, or Co silicide. The second source silicide 59 preferably includes the same type of silicide as the first source silicide 57.

[0257] The semiconductor device 1 does not necessarily need to include the second source silicide 59. In this case, the lower electrode film 52 is mechanically and electrically connected to the termination region 31 (overlap region 32) within the multiple outer openings 47 (outer recesses 48).

[0258] The semiconductor device 1 includes a gate pad electrode 60 disposed on the first main surface 3. The gate pad electrode 60 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 60 is a terminal electrode to which a gate potential is applied from the outside. Although not shown, the gate pad electrode 60, like the source pad electrode 50, includes a lower electrode film 52 that covers the interlayer film 40 in a film-like manner, and a main electrode film 54 that covers the lower electrode film 52 in a film-like manner.

[0259] The gate pad electrode 60 is disposed on a portion of the interlayer film 40 that covers the active region 8, with a gap between it and the source pad electrode 50. In this embodiment, the gate pad electrode 60 is disposed in a region between one end of the first pad portion 50a and one end of the second pad portion 50b, and faces the first pad portion 50a and the second pad portion 50b in the second direction Y.

[0260] The gate pad electrode 60 is formed in a polygonal shape (a quadrilateral shape in this embodiment) in a plan view having four sides parallel to the periphery of the chip 2. The gate pad electrode 60 has a planar area smaller than the planar area of ​​the source pad electrode 50. The gate pad electrode 60 has a planar area smaller than the planar area of ​​the first pad portion 50a and the planar area of ​​the second pad portion 50b.

[0261] The gate pad electrode 60 faces the plurality of gate electrodes 17 and the plurality of connection electrodes 22 across the interlayer film 40. Specifically, the gate pad electrode 60 is disposed inwardly from both ends of the plurality of gate electrodes 17 at a distance, and faces the inner parts of the plurality of gate electrodes 17 across the interlayer film 40. In this embodiment, the gate pad electrode 60 does not have direct electrical connections to the plurality of gate electrodes 17 and the plurality of connection electrodes 22.

[0262] Of course, the gate pad electrode 60 may be electrically connected to the plurality of gate electrodes 17 via the plurality of gate openings 49 (buried electrodes 53). Of course, the portions of the plurality of gate electrodes 17 located directly below the gate pad electrode 60 and the portions of the plurality of connection electrodes 22 located directly below the gate pad electrode 60 may be removed. In this case, the gate pad electrode 60 may face the body region 10 with the main surface insulating film 34 and the interlayer film 40 sandwiched therebetween.

[0263] The semiconductor device 1 includes a plurality of gate finger electrodes 61 extending from the gate pad electrode 60 onto the first main surface 3. The gate finger electrodes 61 may also be referred to as "gate fingers," "second finger electrodes," etc. The gate finger electrodes 61 transmit a gate potential applied to the gate pad electrode 60 to the plurality of gate electrodes 17 and the plurality of connection electrodes 22.

[0264] The multiple gate finger electrodes 61 include a first gate finger electrode 61 a, a second gate finger electrode 61 b, and a third gate finger electrode 61 c. The first gate finger electrode 61 a is drawn out from the gate pad electrode 60 toward the first side surface 5A and extends in a strip shape with ends along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D. The first gate finger electrode 61 a has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0265] The first gate finger electrode 61 a enters the plurality of gate openings 49 from above the interlayer film 40, and is electrically connected to the gate wiring 35 within the plurality of gate openings 49. As a result, the gate potential applied to the gate pad electrode 60 is applied to the plurality of gate electrodes 17 and the plurality of connection electrodes 22 via the first gate finger electrode 61 a.

[0266] The second gate finger electrode 61b is drawn out from the gate pad electrode 60 toward the second side surface 5B, and extends in a strip shape with ends along the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The second gate finger electrode 61b has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0267] The second gate finger electrode 61b enters the plurality of gate openings 49 from above the interlayer film 40, and is electrically connected to the gate wiring 35 within the plurality of gate openings 49. As a result, the gate potential applied to the gate pad electrode 60 is applied to the plurality of gate electrodes 17 and the plurality of connection electrodes 22 via the second gate finger electrode 61b.

[0268] The third gate finger electrode 61c is drawn out in a strip shape extending in the first direction X from the gate pad electrode 60 toward the inside of the active region 8. Specifically, the third gate finger electrode 61c is disposed in the cutout portion 51 at a distance from the first pad portion 50a and the second pad portion 50b, and extends in a strip shape along the cutout portion 51 in the first direction X.

[0269] The third gate finger electrode 61c enters the plurality of gate openings 49 from above the interlayer film 40, and is electrically connected to the plurality of gate electrodes 17 within the plurality of gate openings 49. As a result, the gate potential applied to the gate pad electrode 60 is applied to the plurality of gate electrodes 17 and the plurality of connection electrodes 22 via the third gate finger electrode 61c.

[0270] Similar to the source pad electrode 50, the multiple gate finger electrodes 61 have a laminated structure including a lower electrode film 52, multiple buried electrodes 53, and a main electrode film 54, which are laminated in this order from the chip 2 side. The lower electrode film 52 has a laminated structure including a first electrode film 55 and a second electrode film 56.

[0271] The first electrode film 55 collectively covers the region of the interlayer film 40 where the multiple gate openings 49 are formed, and extends into the multiple gate openings 49 from above the interlayer film 40. The first electrode film 55 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surfaces of the multiple gate openings 49 in a film-like manner, and a portion that covers the multiple gate electrodes 17 and gate wiring 35 in a film-like manner. The first electrode film 55 is electrically connected to the multiple gate electrodes 17 and gate wiring 35 within the multiple gate openings 49.

[0272] The second electrode film 56 directly covers the first electrode film 55. The second electrode film 56 collectively covers the region of the interlayer film 40 where the multiple gate openings 49 are formed, sandwiching the first electrode film 55 therebetween, and extends from above the interlayer film 40 into the multiple gate openings 49.

[0273] The second electrode film 56 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner with the first electrode film 55 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 49 in a film-like manner with the first electrode film 55 sandwiched therebetween, and a portion that covers the plurality of gate electrodes 17 and gate wiring 35 in a film-like manner with the first electrode film 55 sandwiched therebetween. The second electrode film 56 is electrically connected to the plurality of gate electrodes 17 and gate wiring 35 via the first electrode film 55 within the plurality of gate openings 49.

[0274] The plurality of buried electrodes 53 are buried in the plurality of gate openings 49 with the lower electrode film 52 sandwiched therebetween. The plurality of buried electrodes 53 are electrically connected to the plurality of gate electrodes 17 and gate wiring 35 within the plurality of gate openings 49 via the lower electrode film 52. The plurality of buried electrodes 53 each have an electrode surface positioned on the bottom wall side of the plurality of gate openings 49 with respect to the insulating surface of the interlayer film 40, and a portion of the lower electrode film 52 covering the insulating surface of the interlayer film 40 is exposed.

[0275] The main electrode film 54 directly covers the lower electrode film 52 (second electrode film 56) and the plurality of buried electrodes 53. The main electrode film 54 has a portion that covers the insulating surface of the interlayer film 40 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the plurality of gate openings 49 with the buried electrodes 53 sandwiched therebetween. The main electrode film 54 is electrically connected to the plurality of gate electrodes 17 and gate wiring 35 via the lower electrode film 52 and the plurality of buried electrodes 53.

[0276] The semiconductor device 1 includes a drain electrode 62 covering the second main surface 4. The drain electrode 62 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 62 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0277] The drain electrode 62 is electrically connected to the first semiconductor region 6. The drain electrode 62 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 62 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0278] A breakdown voltage that can be applied between source pad electrode 50 and drain electrode 62 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or less and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0279] Other layout examples of the planar structure 14 are shown below. Figure 13 is an enlarged plan view showing a main portion of the active region 8 together with the planar structure 14 according to the second layout example. In the planar structure 14 according to the first layout example, the multiple gate connection structures 20 are connected to the multiple gate structures 15 in a T-shape.

[0280] In contrast, in the planar structure 14 according to the second layout example, the plurality of gate connection structures 20 are respectively connected to the plurality of gate structures 15 in a cross shape, and form cross-shaped current paths together with the plurality of gate structures 15. Specifically, with respect to the plurality of gate connection structures 20 arranged on both sides of the plurality of gate structures 15, the plurality of gate connection structures 20 on one side in the first direction X face the plurality of gate connection structures 20 on the other side in the first direction X, respectively.

[0281] That is, the plurality of connection insulating films 21 are connected in a cross shape to the plurality of gate insulating films 16 in regions between the plurality of gate insulating films 16. Specifically, with respect to the plurality of connection insulating films 21 arranged on both sides of the plurality of gate insulating films 16, the plurality of connection insulating films 21 on one side in the first direction X face the plurality of connection insulating films 21 on the other side in the first direction X in a one-to-one correspondence in the first direction X.

[0282] Furthermore, the plurality of connection electrodes 22 are connected in a cross shape to the plurality of gate electrodes 17 in regions between the plurality of gate electrodes 17. Specifically, with respect to the plurality of connection electrodes 22 arranged on both sides of the plurality of gate electrodes 17, the plurality of connection electrodes 22 on one side in the first direction X face the plurality of connection electrodes 22 on the other side in the first direction X in a one-to-one correspondence in the first direction X.

[0283] In this embodiment, the source openings 45 are formed in a matrix in plan view at intervals in the first direction X and the second direction Y. Specifically, with respect to the source openings 45 arranged on both sides of the gate electrodes 17, the source openings 45 on one side in the first direction X face the source openings 45 on the other side in the first direction X in a one-to-one correspondence in the first direction X.

[0284] Of course, the plurality of source openings 45 may face one or both of one end of the plurality of gate connection structures 20 (connection electrodes 22) and the other end of the plurality of gate connection structures 20 (connection electrodes 22) in the first direction X. As in the first layout example, the plurality of source openings 45 penetrate the gate insulating film 16, the connecting insulating film 21, and the interlayer film 40 to expose the corresponding source regions 11 and the corresponding plurality of contact regions 25, respectively.

[0285] Of course, the semiconductor device 1 may also include one or more gate connection structures 20 connected in a T-shape to the plurality of gate structures 15 (see FIG. 4), and one or more gate connection structures 20 connected in a cross shape to the plurality of gate structures 15 (see FIG. 13).

[0286] As described above, the semiconductor device 1 includes the chip 2, the body region 10, the plurality of gate electrodes 17, and the connection electrode 22. The chip 2 has a first main surface 3. The body region 10 is formed in a surface layer portion of the first main surface 3. The plurality of gate electrodes 17 are arranged on both sides of the body region 10 on the first main surface 3. The connection electrode 22 is formed in a region between the plurality of gate electrodes 17 on the first main surface 3 so as to overlap the body region 10 in the thickness direction, and is connected to the plurality of gate electrodes 17.

[0287] This configuration provides a semiconductor device 1 with a novel layout. For example, in this semiconductor device 1, a current path connecting multiple gate electrodes 17 is formed by the connection electrode 22. This expands the current path, reducing the resistance of the electrodes including the multiple gate electrodes 17 and the connection electrode 22. As a result, the switching response characteristics of the semiconductor device 1 are improved.

[0288] The chip 2 may include SiC. This configuration provides the semiconductor device 1 as a SiC semiconductor device having a novel layout. The physical properties of SiC improve the breakdown voltage of the SiC semiconductor device. In particular, since the SiC semiconductor device is used in a high-voltage and high-current environment, the resistance reduction effect (improvement of switching response characteristics) provided by the connection electrodes 22 is also effective in reducing power consumption.

[0289] The body region 10 may extend in a strip shape in one direction (second direction Y) in a plan view. The multiple gate electrodes 17 may each extend in a strip shape in one direction in a plan view. The connection electrode 22 may extend in a strip shape in an intersecting direction (first direction X) that intersects with the one direction in a plan view. This configuration allows the multiple gate electrodes 17 to be arranged with a narrow pitch, thereby improving the current processing capacity per unit area. This configuration is also effective in reducing on-resistance.

[0290] The connection electrode 22 may have a width equal to or greater than the width of the plurality of gate electrodes 17. With this configuration, current confinement by the connection electrode 22 is appropriately suppressed in the region between the plurality of gate electrodes 17. As a result, the resistance value is appropriately reduced by the connection electrode 22.

[0291] The width of the connection electrode 22 may be three times or less the width of the plurality of gate electrodes 17. This configuration suppresses an increase in the area of ​​the body region 10 covered by the connection electrode 22, and suppresses a decrease in the channel area caused by the connection electrode 22. As a result, the effect of reducing the resistance value by the connection electrode 22 is achieved, and an increase in the on-resistance is suppressed.

[0292] A plurality of connection electrodes 22 may be formed on the first main surface 3 in regions between the plurality of gate electrodes 17 so as to overlap the body region 10 in the thickness direction, and may be connected to the plurality of gate electrodes 17, respectively. According to this configuration, the current path is expanded by the plurality of connection electrodes 22 connecting the plurality of gate electrodes 17. This reduces the resistance value of the electrodes including the plurality of gate electrodes 17 and the connection electrodes 22.

[0293] The semiconductor device 1 may include a source region 11 (impurity region) and a contact region 25. The source region 11 may have a conductivity type different from that of the body region 10 and may be formed in a surface layer portion of the body region 10. The contact region 25 may have the same conductivity type as the body region 10 and a higher impurity concentration than the impurity concentration of the body region 10 and may be formed in a surface layer portion of the body region 10.

[0294] The connection electrode 22 may be disposed on the body region 10 so as to expose the source region 11. The contact region 25 may be formed in a region directly below the connection electrode 22 in the surface layer portion of the body region 10.

[0295] This configuration reduces the area occupied by the contact region 25 and increases the area occupied by the source region 11 in the region outside the connection electrode 22. This configuration is effective in ensuring the connection area of ​​the external electrode to the source region 11. This configuration is also effective when a plurality of gate electrodes 17 are arranged at a narrow pitch.

[0296] In this case, contact region 25 preferably has a concealed portion 26 that is concealed by connection electrode 22, and either or both of a first lead portion 27 and a second lead portion 28 that are led from concealed portion 26 to a region outside connection electrode 22. According to this configuration, the connection portion of the external electrode to contact region 25 can be appropriately secured by either or both of first lead portion 27 and second lead portion 28.

[0297] The semiconductor device 1 may include a source pad electrode 50 (main surface electrode) as an external electrode electrically connected to the source region 11 and the contact region 25 on the first main surface 3. The semiconductor device 1 may include an interlayer film 40 covering the plurality of gate electrodes 17 and the connection electrode 22 on the first main surface 3. The semiconductor device 1 may include a source opening 45 formed in the interlayer film 40 and exposing the source region 11 and the contact region 25.

[0298] In this case, the source pad electrode 50 may be disposed on the interlayer film 40 and electrically connected to the source region 11 and the contact region 25 within the source opening 45. According to this configuration, the electrical connection to the source region 11 and the contact region 25 is appropriately ensured by the interlayer film 40 and the source opening 45.

[0299] From another perspective, the semiconductor device 1 may include a chip 2, a body region 10, a plurality of gate electrodes 17, and a plurality of connection electrodes 22. The chip 2 may have a first main surface 3. The plurality of body regions 10 may be formed in a surface layer portion of the first main surface 3 at intervals in the first direction X and extend in a stripe pattern in a second direction Y intersecting the first direction X.

[0300] The multiple gate electrodes 17 may be arranged on the first main surface 3 at intervals in the first direction X so as to straddle the multiple body regions 10, and may extend in stripes in the second direction Y. The multiple connection electrodes 22 may be formed in regions between the multiple gate electrodes 17 on the first main surface 3, extend in the first direction X so as to be connected to the multiple gate electrodes 17, and overlap the corresponding body regions 10 in the thickness direction.

[0301] This configuration provides a semiconductor device 1 with a novel layout. For example, in this semiconductor device 1, a current path is formed by the multiple connection electrodes 22 connecting the multiple gate electrodes 17. This expands the current path, reducing the resistance of the electrodes including the multiple gate electrodes 17 and the multiple connection electrodes 22. As a result, the switching response characteristics of the semiconductor device 1 are improved.

[0302] The chip 2 may include SiC. This configuration provides the semiconductor device 1 as a SiC semiconductor device having a novel layout. The physical properties of SiC further improve the breakdown voltage of the SiC semiconductor device. In particular, since SiC semiconductor devices are used in high-voltage and high-current environments, the resistance reduction effect (improvement of switching response characteristics) provided by the multiple connection electrodes 22 is also effective in reducing power consumption.

[0303] The multiple connection electrodes 22 may be formed at intervals in the second direction Y in regions between the multiple gate electrodes 17. According to this configuration, a mesh-like current path extending in the first direction X and the second direction Y is formed by the multiple gate electrodes 17 and the multiple connection electrodes 22. As a result, the resistance value of the electrodes including the multiple gate electrodes 17 and the multiple connection electrodes 22 is reduced by the mesh-like current path.

[0304] The plurality of gate electrodes 17 may be formed at a first pitch P1 in the first direction X. The plurality of connection electrodes 22 may be formed at a second pitch P2 that is equal to or greater than the first pitch P1 in the second direction Y. This configuration suppresses an increase in the area of ​​the body region 10 that is hidden by the plurality of connection electrodes 22, and suppresses a decrease in the channel area caused by the plurality of connection electrodes 22. This achieves the effect of reducing the resistance value by the plurality of connection electrodes 22, and also suppresses an increase in on-resistance.

[0305] The first pitch P1 may be 6 μm or less. With this configuration, the plurality of gate electrodes 17 are arranged at a narrow pitch. This allows the area occupied by the plurality of gate electrodes 17 on the first main surface 3 to be increased. This configuration is effective in reducing the on-resistance while achieving the resistance reduction effect achieved by the plurality of connection electrodes 22.

[0306] The plurality of connection electrodes 22 may each have a width equal to or greater than the width of the plurality of gate electrodes 17. With this configuration, current constriction by the plurality of connection electrodes 22 is appropriately suppressed in the region between the plurality of gate electrodes 17. As a result, the resistance value is appropriately reduced by the plurality of connection electrodes 22.

[0307] The width of the plurality of connection electrodes 22 may be three times or less the width of the plurality of gate electrodes 17. This configuration can suppress an increase in the area of ​​the plurality of body regions 10 hidden by the plurality of connection electrodes 22, and can suppress a decrease in the channel area caused by the plurality of connection electrodes 22. As a result, the effect of reducing the resistance value by the plurality of connection electrodes 22 is achieved, and an increase in on-resistance is suppressed.

[0308] The plurality of connection electrodes 22 may form a current path including either or both of T-junctions and crosses with the plurality of gate electrodes 17 in a plan view. With this configuration, the resistance value of the electrode including the plurality of gate electrodes 17 and the plurality of connection electrodes 22 is reduced by the mesh-like current path including either or both of T-junctions and crosses.

[0309] The semiconductor device 1 may include a plurality of source regions 11 (impurity regions) and a plurality of contact regions 25. The plurality of source regions 11 may have a conductivity type different from that of the plurality of body regions 10 and may be formed in the surface layer portions of the plurality of body regions 10. The plurality of contact regions 25 may have the same conductivity type as the plurality of body regions 10 and a higher impurity concentration than the impurity concentration of the plurality of body regions 10 and may be formed in the surface layer portions of the plurality of body regions 10 in regions directly below the plurality of connection electrodes 22.

[0310] This configuration reduces the area occupied by the contact regions 25 and increases the area occupied by the source regions 11 in the region outside the connection electrodes 22. This configuration is effective in ensuring the connection area of ​​the external electrodes to the source regions 11. This configuration is also effective when the gate electrodes 17 are arranged at a narrow pitch.

[0311] In this case, it is preferable that each of the plurality of contact regions 25 has a concealed portion 26 that is concealed by the corresponding connection electrode 22, and either or both of a first lead portion 27 and a second lead portion 28 that are led out from the concealed portion 26 to an area outside the corresponding connection electrode 22. According to this configuration, the connection portion of the external electrode to the plurality of contact regions 25 can be appropriately secured by either or both of the first lead portion 27 and the second lead portion 28.

[0312] The semiconductor device 1 may include a source pad electrode 50 (main surface electrode) as an external electrode electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 on the first main surface 3. The semiconductor device 1 may include an interlayer film 40 covering the plurality of gate electrodes 17 and the plurality of connection electrodes 22 on the first main surface 3. The semiconductor device 1 may include a plurality of source openings 45 formed in the interlayer film 40 and exposing the corresponding source regions 11 and the corresponding contact regions 25, respectively.

[0313] In this case, the source pad electrode 50 may be disposed on the interlayer film 40 and electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 within the plurality of source openings 45. According to this configuration, electrical connections to the plurality of source regions 11 and the plurality of contact regions 25 are appropriately ensured by the interlayer film 40 and the plurality of source openings 45.

[0314] Below, first to third modified examples of the semiconductor device 1 are shown. Fig. 14 is an enlarged plan view showing a main portion of the semiconductor device 1 according to the first modified example. Although Fig. 14 shows a planar structure 14 according to the first layout example, the configuration of the semiconductor device 1 according to the first modified example is also applicable to the second layout example.

[0315] The above-described plurality of contact regions 25 are formed in the surface layer portion of the body region 10 so as to face the plurality of gate connection structures 20 (connection electrodes 22) in a one-to-one correspondence in the thickness direction. However, the plurality of contact regions 25 may be formed in the surface layer portion of the body region 10 so as to face the plurality of gate connection structures 20 (connection electrodes 22) in a one-to-many correspondence in the thickness direction.

[0316] In this case, the multiple contact regions 25 may include a first contact region 25a formed on one side of the second direction Y in the region directly below the corresponding gate connection structure 20, and a second contact region 25b formed on the other side of the second direction Y in the region directly below the corresponding gate connection structure 20.

[0317] The first contact region 25a has a first concealing portion 71 and a first leading portion 72. The first concealing portion 71 is made up of a portion that is concealed by the corresponding gate connection structure 20. The first leading portion 72 is made up of a portion that is led out from the first concealing portion 71 to one side in the second direction Y and is exposed from the corresponding gate connection structure 20.

[0318] The second contact region 25b is formed in a region directly below the corresponding gate connection structure 20 at a distance from the first contact region 25a on the other side in the second direction Y, and faces the first contact region 25a across a portion of the source region 11.

[0319] The second contact region 25b has a second concealing portion 73 and a second leading portion 74. The second concealing portion 73 is made up of a portion that is concealed by the corresponding gate connection structure 20. The second leading portion 74 is made up of a portion that is led out from the second concealing portion 73 to the other side in the second direction Y and is exposed from the corresponding gate connection structure 20.

[0320] The second lead portion 74 of the second contact region 25b faces the first lead portion 72 of the first contact region 25a in the second direction Y in an area outside the connection structure (connection electrode 22), sandwiching a part of the source region 11 therebetween.

[0321] In this embodiment, the length L of the contact region 25 corresponds to the distance in the second direction Y between the first lead-out portion 72 of the first contact region 25 a and the second lead-out portion 74 of the second contact region 25 b. The lead-out amount of the first lead-out portion 72 (second lead-out portion 74) in the second direction Y corresponds to the lead-out amount of the first lead-out portion 27 (second lead-out portion 28) in the second direction Y.

[0322] In this embodiment, the aforementioned plurality of source openings 45 expose the corresponding source regions 11, the first lead portion 72 of the first contact region 25a, and the second lead portion 74 of the second contact region 25b.

[0323] The aforementioned source pad electrode 50 is electrically connected to the plurality of source regions 11, the first lead portions 72 of the plurality of first contact regions 25a, and the second lead portions 74 of the plurality of second contact regions 25b within the plurality of source openings 45. In other words, the lower electrode film 52 is electrically connected to the plurality of source regions 11, the first lead portions 72 of the plurality of first contact regions 25a, and the second lead portions 74 of the plurality of second contact regions 25b within the plurality of source openings 45.

[0324] The buried electrodes 53 are electrically connected to the corresponding source regions 11, the first lead portions 72 of the corresponding first contact regions 25a, and the second lead portions 74 of the corresponding second contact regions 25b, respectively, with the lower electrode film 52 sandwiched therebetween in the source openings 45. The main electrode film 54 is electrically connected to the source regions 11, the first lead portions 72 of the plurality of first contact regions 25a, and the second lead portions 74 of the plurality of second contact regions 25b via the lower electrode film 52 and the buried electrodes 53.

[0325] 15 is a cross-sectional view showing a semiconductor device 1 according to a second modification. The configuration of the semiconductor device 1 according to the second modification is also applicable to the second layout example. The configuration of the semiconductor device 1 according to the second modification may be applied to the configuration of the semiconductor device 1 according to the first modification. The source pad electrode 50 described above has a plurality of buried electrodes 53. However, as shown in FIG. 15, the source pad electrode 50 may include an intermediate electrode film 75 instead of the plurality of buried electrodes 53.

[0326] The intermediate electrode film 75 includes a conductive material different from the conductive material of the lower electrode film 52. The buried electrode 53 includes at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the buried electrode 53 includes tungsten.

[0327] The intermediate electrode film 75 directly covers the lower electrode film 52 (second electrode film 56) and backfills the multiple source openings 45. The intermediate electrode film 75 collectively covers the region of the interlayer film 40 where the multiple source openings 45 are formed, sandwiching the lower electrode film 52 between them, and extends from above the interlayer film 40 into the multiple source openings 45.

[0328] The intermediate electrode film 75 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, sandwiching the lower electrode film 52 therebetween, and portions that are embedded in the plurality of source openings 45, sandwiching the lower electrode film 52 therebetween. The portions of the intermediate electrode film 75 that are embedded in the plurality of source openings 45 correspond to the plurality of embedded electrodes 53 described above, respectively.

[0329] The intermediate electrode film 75 is electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 via the lower electrode film 52 in the plurality of source openings 45. The intermediate electrode film 75 is electrically connected to the first lead portion 27 of one contact region 25 in the second direction Y and the second lead portion 28 of the other contact region 25 in the second direction Y via the lower electrode film 52 in the plurality of source openings 45.

[0330] In this embodiment, the main electrode film 54 directly covers the intermediate electrode film 75. The main electrode film 54 has a portion that covers the insulating surface of the interlayer film 40 with the intermediate electrode film 75 sandwiched therebetween, and a portion that covers the plurality of source openings 45 with the intermediate electrode film 75 sandwiched therebetween. The main electrode film 54 is electrically connected to the plurality of source regions 11 and the plurality of contact regions 25 via the lower electrode film 52 and the intermediate electrode film 75.

[0331] Of course, like the source pad electrode 50 , the source finger electrode 58 , the gate pad electrode 60 and the plurality of gate finger electrodes 61 may also have a laminated structure including the lower electrode film 52 , the intermediate electrode film 75 and the main electrode film 54 .

[0332] The intermediate electrode film 75 of the source finger electrode 58 extends from above the interlayer film 40 into the outer openings 47 and is electrically connected to the termination region 31 (overlap region 32) within the outer openings 47. The main electrode film 54 of the source finger electrode 58 directly covers the intermediate electrode film 75 and is electrically connected to the termination region 31 (overlap region 32) via the intermediate electrode film 75.

[0333] The intermediate electrode films 75 of the multiple gate finger electrodes 61 extend from above the interlayer film 40 into the multiple gate openings 49, and are electrically connected to the multiple gate electrodes 17 and gate wiring 35 within the multiple gate openings 49. The main electrode films 54 of the gate finger electrodes 61 directly cover the intermediate electrode film 75, and are electrically connected to the multiple gate electrodes 17 and gate wiring 35 via the intermediate electrode film 75.

[0334] 16 is a cross-sectional view showing a semiconductor device 1 according to a third modification. The configuration of the semiconductor device 1 according to the third modification is also applicable to the second layout example. The configuration of the semiconductor device 1 according to the third modification may be applied to the configuration of the semiconductor device 1 according to the first modification. The source pad electrode 50 described above has multiple buried electrodes 53. However, as shown in FIG. 16, the source pad electrode 50 does not have multiple buried electrodes 53, and has a layered structure including a lower electrode film 52 and a main electrode film 54.

[0335] In this embodiment, the main electrode film 54 of the source pad electrode 50 extends from above the interlayer film 40 into the multiple source openings 45, and is electrically connected to the multiple source regions 11 and the multiple contact regions 25 within the multiple source openings 45 via the lower electrode film 52.

[0336] Of course, like the source pad electrode 50, the source finger electrode 58, the gate pad electrode 60 and the plurality of gate finger electrodes 61 may also have a laminated structure including the lower electrode film 52 and the main electrode film 54 without having the plurality of buried electrodes 53.

[0337] The main electrode film 54 of the source finger electrodes 58 enters the outer openings 47 from above the interlayer film 40 and is electrically connected to the termination region 31 (overlapping region 32) via the lower electrode film 52 within the outer openings 47. The main electrode films 54 of the gate finger electrodes 61 enters the gate openings 49 from above the interlayer film 40 and is electrically connected to the gate electrodes 17 and gate wiring 35 via the lower electrode film 52 within the gate openings 49.

[0338] The above-described embodiment (including its modified examples) may be implemented in other forms. For example, in the above-described embodiment, the third gate finger electrode 61c is formed. However, the third gate finger electrode 61c is not necessarily required and may be removed. In this case, the notch 51 of the source pad electrode 50 is removed, and the first pad portion 50a and the second pad portion 50b of the source pad electrode 50 are integrally formed.

[0339] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0340] In the above-described embodiments, a structure may be adopted in which the conductivity type of the “n-type” semiconductor region is inverted to “p-type” and the conductivity type of the “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0341] In the above-described embodiment, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0342] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0343] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a body region (10) formed in a surface layer portion of the main surface (3); a plurality of gate electrodes (17) arranged on both sides of the body region (10) on the main surface (3); and connection electrodes (22) formed in a region between the plurality of gate electrodes (17) on the main surface (3) so as to overlap the body region (10) in a thickness direction (Z), and connected to the plurality of gate electrodes (17).

[0344] [A2] The semiconductor device (1) according to A1, wherein the chip (2) includes SiC.

[0345] [A3] A semiconductor device (1) according to A1 or A2, wherein the body region (10) extends in a strip shape in one direction in a planar view, the plurality of gate electrodes (17) each extend in a strip shape in the one direction in a planar view, and the connection electrode (22) extends in a strip shape in an intersecting direction that intersects the one direction in a planar view.

[0346] [A4] The semiconductor device (1) according to any one of A1 to A3, wherein the connection electrode (22) has a width (W2) equal to or greater than the width (W1) of the plurality of gate electrodes (17).

[0347] [A5] The semiconductor device (1) according to any one of A1 to A4, wherein a plurality of the connection electrodes (22) are connected to a plurality of the gate electrodes (17).

[0348] [A6] The semiconductor device (1) according to any one of A1 to A5, further comprising: an impurity region (11) having a conductivity type (n-type) different from the conductivity type (p-type) of the body region (10) and formed in a surface layer portion of the body region (10); and a contact region (25) having the same conductivity type (p-type) as the conductivity type (p-type) of the body region (10) and an impurity concentration higher than the impurity concentration of the body region (10), formed in a surface layer portion of the body region (10).

[0349] [A7] The semiconductor device (1) described in A6, wherein the connection electrode (22) is arranged on the body region (10) so as to expose the impurity region (11), and the contact region (25) is formed in a region directly below the connection electrode (22) in the surface layer portion of the body region (10).

[0350] [A8] The semiconductor device (1) described in A7, wherein the contact region (25) has a concealed portion (26, 71, 73) that is concealed by the connection electrode (22), and an extension portion (27, 28, 72, 74) that is extended from the concealed portion (26, 71, 73) to a region outside the connection electrode (22).

[0351] [A9] The semiconductor device (1) according to any one of A6 to A8, further comprising a main surface electrode (50) electrically connected to the impurity region (11) and the contact region (25) on the main surface (3).

[0352] [A10] The semiconductor device (1) according to A9, further comprising an interlayer film (40) covering the plurality of gate electrodes (17) and the connection electrodes (22) on the main surface (3), and an opening (45) formed in the interlayer film (40) exposing the impurity region (11) and the contact region (25), wherein the main surface electrode (50) is disposed on the interlayer film (40) and is electrically connected to the impurity region (11) and the contact region (25) within the opening (45).

[0353] [A11] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a plurality of body regions (10) formed on a surface layer of the main surface (3) at intervals in a first direction (X) and extending in a stripe pattern in a second direction (Y) intersecting the first direction (X); a plurality of gate electrodes (17) arranged on the main surface (3) at intervals in the first direction (X) so as to straddle the plurality of body regions (10) and extending in a stripe pattern in the second direction (Y); and a plurality of connection electrodes (22) formed in regions between the plurality of gate electrodes (17) on the main surface (3), each extending in the first direction (X) so as to be connected to the plurality of gate electrodes (17), and each overlapping the body region (10) corresponding to the thickness direction (Z).

[0354] [A12] The semiconductor device (1) according to A11, wherein the chip (2) includes SiC.

[0355] [A13] The semiconductor device (1) according to A11 or A12, wherein the plurality of connection electrodes (22) are formed at intervals in the second direction (Y) in regions between the plurality of gate electrodes (17).

[0356] [A14] A semiconductor device (1) described in A13, wherein the plurality of gate electrodes (17) are formed at a first pitch (P1) in the first direction (X), and the plurality of connection electrodes (22) are formed at a second pitch (P2) in the second direction (Y) that is equal to or greater than the first pitch (P1).

[0357] [A15] The semiconductor device (1) according to A14, wherein the first pitch (P1) is 6 μm or less.

[0358] [A16] A semiconductor device (1) according to any one of A11 to A15, wherein the plurality of connection electrodes (22) each have a width (W2) greater than or equal to the width (W1) of the plurality of gate electrodes (17).

[0359] [A17] A semiconductor device (1) according to any one of A11 to A16, wherein the plurality of connection electrodes (22) form a current path including a T-junction and / or a cross with the plurality of gate electrodes (17) in a planar view.

[0360] [A18] The semiconductor device (1) according to any one of A11 to A17, further including: a plurality of impurity regions (11) having a conductivity type (n-type) different from the conductivity type (p-type) of the plurality of body regions (10), and formed in the surface layer portions of the plurality of body regions (10), respectively; and a plurality of contact regions (25) having the same conductivity type (p-type) as the conductivity type (p-type) of the plurality of body regions (10) and an impurity concentration higher than the impurity concentration of the plurality of body regions (10), and formed in the surface layer portions of the plurality of body regions (10) in regions directly below the plurality of connection electrodes (22), respectively.

[0361] [A19] A semiconductor device (1) according to A18, wherein the plurality of contact regions (25) each have a concealed portion (26, 71, 73) that is concealed by the corresponding connection electrode (22), and an extended portion (27, 28, 72, 74) that is extended from the concealed portion (26, 71, 73) to a region outside the corresponding connection electrode (22).

[0362] [A20] The semiconductor device (1) according to A19 further includes an interlayer film (40) covering the plurality of gate electrodes (17) and the plurality of connection electrodes (22) on the main surface (3), a plurality of openings (45) formed in the interlayer film (40) exposing the corresponding impurity regions (11) and the corresponding contact regions (25), and a plurality of buried electrodes (53) buried in the plurality of openings (45) and electrically connected to the corresponding impurity regions (11) and the corresponding contact regions (25).

[0363] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification and the accompanying drawings can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0364] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 10 body region 11 source region (impurity region) 17 gate electrode 22 connection electrode 25 contact region 26 concealed portion 27 first lead portion 28 second lead portion 40 interlayer film 45 source opening 50 source pad electrode (main surface electrode) 53 buried electrode 71 first concealed portion 72 first lead portion 73 second concealed portion 74 second lead portion P1 first pitch P2 second pitch W1 width of gate electrode W2 width of connection electrode X first direction Y second direction Z vertical direction (thickness direction)

Claims

1. A semiconductor device comprising: a chip having a main surface; a body region formed in a surface portion of the main surface; a plurality of gate electrodes arranged on both sides of the body region on the main surface; and a connection electrode formed in a region between the plurality of gate electrodes on the main surface so as to overlap the body region in the thickness direction, and connected to the plurality of gate electrodes.

2. The semiconductor device according to claim 1, wherein the chip comprises SiC.

3. The semiconductor device according to claim 1 or 2, wherein the body region extends in a band shape in one direction in a planar view, the plurality of gate electrodes each extend in a band shape in the one direction in a planar view, and the connection electrodes extend in a band shape in an intersecting direction that intersects the one direction in a planar view.

4. The semiconductor device according to claim 1, wherein the connection electrode has a width equal to or greater than the width of the gate electrodes.

5. The semiconductor device according to any one of claims 1 to 4, wherein a plurality of said connection electrodes are connected to a plurality of said gate electrodes.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: an impurity region having a conductivity type different from that of the body region and formed in a surface layer portion of the body region; and a contact region having the same conductivity type as the body region and a higher impurity concentration than the impurity concentration of the body region, formed in a surface layer portion of the body region.

7. The semiconductor device according to claim 6, wherein the connection electrode is disposed on the body region so as to expose the impurity region, and the contact region is formed in a region directly below the connection electrode in a surface portion of the body region.

8. The semiconductor device according to claim 7, wherein said contact region has a concealed portion concealed by said connection electrode, and a drawn portion drawn from said concealed portion to a region outside said connection electrode.

9. The semiconductor device according to claim 6, further comprising a main surface electrode electrically connected to said impurity region and said contact region on said main surface.

10. The semiconductor device according to claim 9, further comprising: an interlayer film covering a plurality of said gate electrodes and said connection electrodes on said main surface; and an opening formed in said interlayer film to expose said impurity region and said contact region, wherein said main surface electrode is disposed on said interlayer film and is electrically connected to said impurity region and said contact region within said opening.

11. A semiconductor device comprising: a chip having a main surface; a plurality of body regions formed on a surface layer portion of the main surface at intervals in a first direction X and extending in a stripe pattern in a second direction Y intersecting the first direction X; a plurality of gate electrodes arranged on the main surface at intervals in the first direction X so as to straddle the plurality of body regions and extending in a stripe pattern in the second direction Y; and a plurality of connection electrodes formed in regions between the plurality of gate electrodes on the main surface, each extending in the first direction X to be connected to the plurality of gate electrodes, and overlapping a corresponding one of the body regions in a thickness direction.

12. The semiconductor device according to claim 11, wherein the chip comprises SiC.

13. The semiconductor device according to claim 11 or 12, wherein the plurality of connection electrodes are formed at intervals in the second direction Y in regions between the plurality of gate electrodes.

14. The semiconductor device according to claim 13, wherein the plurality of gate electrodes are formed at a first pitch in the first direction X, and the plurality of connection electrodes are formed at a second pitch in the second direction Y that is equal to or greater than the first pitch.

15. The semiconductor device according to claim 14, wherein the first pitch is 6 μm or less.

16. The semiconductor device according to any one of claims 11 to 15, wherein each of the plurality of connection electrodes has a width equal to or greater than the width of each of the plurality of gate electrodes.

17. The semiconductor device according to any one of claims 11 to 16, wherein the multiple connection electrodes form a current path including a T-junction and / or a cross with the multiple gate electrodes in a plan view.

18. A semiconductor device according to any one of claims 11 to 17, further comprising: a plurality of impurity regions having a conductivity type different from that of the plurality of body regions, the impurity regions being formed in a surface layer portion of the plurality of body regions; and a plurality of contact regions having the same conductivity type as the plurality of body regions and a higher impurity concentration than the impurity concentration of the plurality of body regions, the contact regions being formed in the surface layer portion of the plurality of body regions in regions directly below the plurality of connection electrodes, respectively.

19. The semiconductor device according to claim 18, wherein each of the contact regions has a concealed portion that is concealed by the corresponding connection electrode, and a drawn-out portion that is drawn out from the concealed portion to a region outside the corresponding connection electrode.

20. The semiconductor device according to claim 19, further comprising: an interlayer film covering a plurality of the gate electrodes and a plurality of the connection electrodes on the main surface; a plurality of openings formed in the interlayer film exposing the corresponding impurity regions and the corresponding contact regions, respectively; and a plurality of buried electrodes buried in the plurality of openings, respectively, and electrically connected to the corresponding impurity regions and the corresponding contact regions.

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