Display panel and display device

Abstract

The present disclosure belongs to the technical field of display. Provided are a display panel and a display device, which can solve the problem of lower frames of existing display panels being relatively wide. The display panel of the present disclosure comprises: a substrate, and a driving chip which is located on the substrate and arranged in a binding area, wherein the driving chip comprises a plurality of binding pads. The display panel further comprises: a plurality of fan-out traces which are located on the substrate, wherein one end of each fan-out trace is connected to the binding pad, and extends to a pixel area through a fan-out area. The distance between some of the binding pads and a first edge of the driving chip gradually increases in a direction parallel to the first edge. The driving chip has a plurality of supporting areas which are arranged on the side of some of the binding pads close to the fan-out area. The driving chip further comprises: redundant pads which are located in the supporting areas. Some of the fan-out traces pass through an area between adjacent supporting areas; and some of the fan-out traces pass through the supporting areas and are insulated from the redundant pads.

Description

Display panel and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, in addition to achieving higher display quality, display panels also have higher requirements for other aspects of display panels, one of which is a narrow border and a design with equal width on all four sides. The narrow borders on the left and right sides of the display panel can be achieved by driving the array substrate row (Gate Driver on Array, GOA), and the gate signal lines of the pixel area are turned on row by row by a combination of thin film transistors. One of the ways to achieve the lower border of the display panel is to use a sinking driver chip (Driver IC). By using the sinking driver chip, the space occupied by the fan-out wiring between the pixel area and the driver chip can be effectively shortened. However, the binding pads of the sinking driver chip (mainly the output pads for transmitting signals to the pixel area of ​​the display panel) are arranged in an inclined direction, and there will be a problem of poor attachment at the upper left and upper right edge positions of the driver chip. Therefore, redundant pads are set in the support area of ​​the upper left and upper right positions of the driver chip to ensure the tightness of attachment.

[0003] Since redundant pads need to be placed in the support area, in order to avoid short circuits between the fan-out traces and the redundant pads, the fan-out traces need to avoid the redundant pads in the support area. The fan-out traces will be bent in the support area to avoid connection between the fan-out traces and the redundant pads in the support area, causing short circuits. This bending will increase the longitudinal routing space, thereby increasing the lower frame and affecting the display effect of the display panel.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a display panel and a display device.

[0006] In a first aspect, embodiments of the present disclosure provide a display panel comprising a pixel region, a fan-out region and a bonding region disposed on one side of the pixel region and sequentially disposed in a direction away from the pixel region; the display panel comprising: a substrate; a driver chip disposed on the substrate and disposed in the bonding region; the driver chip comprising: a plurality of bonding pads; the display panel further comprising: a plurality of fan-out traces disposed on the substrate; one end of each fan-out trace being connected to the bonding pad and extending through the fan-out region to the pixel region;

[0007] The distance between some of the binding pads and the first edge of the driver chip gradually increases along a direction parallel to the first edge; the driver chip has a plurality of support areas arranged on a side of some of the binding pads close to the fan-out area; the driver chip further includes: redundant pads located in the support areas;

[0008] Part of the fan-out lines passes through the area between adjacent support areas; part of the fan-out lines passes through the support area and is insulated from the redundant pad.

[0009] Optionally, the redundant pad includes: a first insulating layer, a second insulating layer, and a first transparent electrode layer, which are located on the substrate and arranged in sequence in a direction away from the substrate;

[0010] The fan-out routing includes: a first sub-fan-out routing; the first sub-fan-out routing is located on the side of the substrate close to the first insulating layer.

[0011] Optionally, the redundant pad further includes: a first metal layer located on a side of the substrate close to the first insulating layer;

[0012] The first metal layer includes: a plurality of first metal strips arranged at intervals; and the first sub-fan-out wiring is located between adjacent first metal strips.

[0013] Optionally, the redundant pad further includes: a second metal layer located between the first insulating layer and the second insulating layer;

[0014] The second metal layer overlaps with the supporting area.

[0015] Optionally, the redundant pad further includes: a second metal layer located between the first insulating layer and the second insulating layer;

[0016] The second metal layer is connected between adjacent support areas to form an integrated structure.

[0017] Optionally, the redundant pad further comprises: a second metal layer located between the first insulating layer and the second insulating layer; the second metal layer comprises: a plurality of second metal strips arranged at intervals;

[0018] The fan-out routing further includes: a second sub-fan-out routing; the second sub-fan-out routing is located between adjacent second metal strips.

[0019] Optionally, the orthographic projection of the first sub-fan-out trace on the substrate is located between the orthographic projections of adjacent second sub-fan-out traces on the substrate;

[0020] The orthographic projection of the first metal strip on the substrate is located between the orthographic projections of adjacent second metal strips on the substrate.

[0021] Optionally, an orthographic projection of the first sub-fan-out trace on the substrate coincides with an orthographic projection of the second sub-fan-out trace on the substrate;

[0022] The orthographic projection of the first metal strip on the substrate coincides with the orthographic projection of the second metal strip on the substrate.

[0023] Optionally, the lengths of the first metal strip and the second metal strip along a direction parallel to the fan-out wiring are both equal to the length of the support area along the direction parallel to the fan-out wiring.

[0024] Optionally, an area of ​​the first metal strip and the second metal strip in each supporting region is greater than or equal to 70% of an area of ​​the supporting region.

[0025] Optionally, the redundant pad further includes: a second transparent electrode layer located between the first insulating layer and the second insulating layer;

[0026] The second transparent electrode layer overlaps with the supporting area.

[0027] Optionally, the redundant pad further includes: a second transparent electrode layer located between the first insulating layer and the second insulating layer;

[0028] The second transparent electrode layer is connected between adjacent support areas to form an integrated structure.

[0029] Optionally, the first transparent electrode layer overlaps with the supporting area.

[0030] Optionally, the first transparent electrode layer is connected between adjacent support areas to form an integrated structure.

[0031] Optionally, the first insulating layer and the second insulating layer are connected to form an integral structure between adjacent supporting areas.

[0032] In a second aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes the display panel provided as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of an exemplary display panel.

[0034] FIG. 2 is a schematic structural diagram of a driver chip in the display panel shown in FIG. 1 .

[0035] FIG3 is a schematic structural diagram of another exemplary display panel.

[0036] FIG. 4 is a schematic structural diagram of a driver chip in the display panel shown in FIG. 3 .

[0037] FIG5 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.

[0038] FIG. 6 is a schematic diagram of a first partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0039] FIG. 7 is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 6 along the AA′ direction.

[0040] FIG8 is a schematic diagram of a second partial structure of redundant pads and fan-out wiring in the display panel shown in FIG5 .

[0041] FIG9 is a schematic diagram of a cross-sectional structure of the structure shown in FIG8 along the BB′ direction.

[0042] FIG. 10 is a schematic diagram of a third partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0043] FIG11 is a schematic diagram of a cross-sectional structure of the structure shown in FIG10 along the CC′ direction.

[0044] FIG. 12 is a schematic diagram of a fourth partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0045] FIG13 is a schematic diagram of a cross-sectional structure of the structure shown in FIG12 along the DD′ direction.

[0046] FIG. 14 is a schematic diagram of a fourth partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0047] FIG15 is a schematic diagram of the cross-sectional structure of the structure shown in FIG14 along the EE′ direction.

[0048] FIG16 is a schematic diagram of a fifth partial structure of redundant pads and fan-out wiring in the display panel shown in FIG5 .

[0049] FIG17 is a schematic diagram of the cross-sectional structure of the structure shown in FIG16 along the FF′ direction.

[0050] FIG. 18 is a schematic diagram of a sixth partial structure of redundant pads and fan-out traces in the display panel shown in FIG. 5 .

[0051] FIG19 is a schematic diagram of the cross-sectional structure of the structure shown in FIG18 along the GG′ direction.

[0052] FIG. 20 is a schematic diagram of a seventh partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0053] FIG21 is a schematic diagram of the cross-sectional structure of the structure shown in FIG20 along the HH′ direction.

[0054] FIG. 22 is a schematic diagram of a seventh partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0055] FIG. 23 is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 22 along the II′ direction.

[0056] FIG. 24 is a schematic diagram of an eighth partial structure of redundant pads and fan-out wiring in the display panel shown in FIG. 5 .

[0057] FIG25 is a schematic diagram of the cross-sectional structure of the structure shown in FIG24 along the JJ′ direction. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] FIG1 is a schematic diagram of the structure of an exemplary display panel. As shown in FIG1 , the display panel comprises a pixel area A1, a fan-out area A2 and a bonding area A3 disposed to one side of the pixel area A1 and arranged sequentially away from the pixel area A1. The display panel includes a substrate 101, gate lines 102, data lines 103, a driver chip 104, and fan-out traces 105 disposed on the substrate 101.

[0061] The gate line 102 and the data line 103 are located in the pixel area A1 and are arranged to intersect. A plurality of pixel units (not shown in the figure) are formed in the area defined by the intersection of the gate line 102 and the data line 103. A pixel circuit is set in each pixel unit. The gate line 102 and the data line 103 are connected to the pixel circuit to control the driving signal input into the pixel circuit to realize the display function.

[0062] The driver chip 104 is located in the binding area A3 and can provide data signals for the data lines 103 in the pixel area A1. Figure 2 is a schematic structural diagram of the driver chip in the display panel shown in Figure 1. As shown in Figure 2, the driver chip 104 includes: a plurality of binding pads 1041; the plurality of binding pads 1041 are arranged along a first edge direction parallel to the driver chip 104. The first edge can be the output lead bump (OLB) side of the driver chip 104, which is the edge where most of the output pads of the driver chip 104 are set. Correspondingly, the driver chip 104 also has a second edge, which is opposite to the first edge. The second edge can be the input lead bump (ILB) side of the driver chip 104, which is the edge where most of the input pads of the driver chip 104 are set.

[0063] One end of the fan-out trace 105 is connected to the bonding pad 1041 (i.e., the output pad), and the other end is connected to the data line 103. The fan-out trace 105 can extend from the bonding area A3 through the fan-out area A2 to the display area A1 to transmit the drive signal provided by the driver chip 104 in the bonding area A3 to the data line 103 in the pixel area A1. Generally speaking, due to the layout design rules such as the line width and line spacing of the fan-out trace 105, the width w1 of the fan-out area A2 can be reduced to a limited extent. Based on the limitation of the width w1 of the fan-out area A2, the reduction of the bezel width of the display panel is also limited, and a narrow bezel and a design with equal width on all four sides cannot be achieved.

[0064] Although the width w1 of the fan-out area A2 cannot be further reduced, if the driver chip 104 is positioned further toward the display area A1 , the distance between the driver chip 104 and the display area A1 can be reduced, which can help reduce the border of the display panel.

[0065] FIG3 is a schematic diagram of the structure of another exemplary display panel. As shown in FIG3 , the display panel has a pixel area A1, a fan-out area A2 and a binding area A3 arranged on one side of the pixel area A1 and arranged in sequence in a direction away from the pixel area A1; the display panel includes: a substrate 101, a driver chip 104 located on the substrate 101 and arranged in the binding area A3 (the structure in the pixel area A1 is the same as the structure in FIG1 above, not shown in FIG3 ). FIG4 is a schematic diagram of the structure of the driver chip in the display panel shown in FIG3 . As shown in FIG4 , the driver chip 104 includes: a plurality of binding pads 1041. The difference from the structure of the driver chip 104 shown in FIG2 is that some of the binding pads 1041 are arranged along the first edge direction parallel to the driver chip 104, and some of the binding pads 1041 are not arranged along the direction of the first edge, but have a certain angle with the first edge direction and are arranged in an inclined direction. The distance between the partial binding pads 1041 and the first edge of the driver chip 104 gradually increases along a direction parallel to the first edge. Since the arrangement of the partial binding pads 1041 in the driver chip 104 appears to sink toward the fan-out area A2 (as shown in Figure 4), this configuration of the driver chip 104 can be called a "sunken driver chip."

[0066] Because some of the bonding pads 1041 on the driver chip 104 are sunken toward the fan-out area A2, the driver chip 104 can be positioned further toward the fan-out area A2 of the display panel. This allows the distance w2 between the driver chip 104 and the pixel area A1 of the display panel to be smaller than the width w1 of the fan-out area A2. This reduction in distance w2 between the driver chip 104 and the pixel area A1 of the display panel further reduces the bezel of the display panel.

[0067] However, the binding pads 1041 of the driver chip 104 (mainly output pads for transmitting signals to the pixel area of ​​the display panel) are arranged in an inclined direction, and there will be problems of poor adhesion at the upper left and upper right edge positions of the driver chip 104. Therefore, redundant pads 1042 will be set in the support area A4 at the upper left and upper right positions of the driver chip to ensure the tightness of adhesion.

[0068] Since redundant pads 1042 need to be placed in support area A4, in order to avoid a short circuit between the fan-out trace 105 and the redundant pad 1042, the fan-out trace 105 needs to avoid the redundant pad 1042 in support area A4. The fan-out trace 105 will be bent in support area A4 to avoid the fan-out trace 105 being connected to the redundant pad 1042 in support area A4, causing a short circuit. This bending will increase the longitudinal routing space, thereby leading to an increase in the lower frame, affecting the display effect of the display panel.

[0069] In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a display panel and a display device. The display panel and the display device provided by the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0070] In the first aspect, an embodiment of the present disclosure provides a display panel. Figure 5 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in Figure 5, the display panel has a pixel area A1, a fan-out area A2 and a binding area A3 arranged on one side of the pixel area A1 and arranged in sequence along a direction away from the pixel area A1; wherein, the display panel includes: a substrate 101, a driver chip 104 located on the substrate 101 and arranged in the binding area A3 (the structure in the pixel area A1 is the same as the structure in the above-mentioned Figure 1); the driver chip 104 (the structure of the driver chip 104 is the same as the structure of the driver chip 104 shown in Figure 4) includes: a plurality of binding pads 1041; the display panel also includes: a plurality of fan-out traces 105 located on the substrate 101; one end of each fan-out trace 105 is connected to the binding pad 1041, and extends to the pixel area A1 through the fan-out area A2. The distance between the partial binding pad 1041 and the first edge of the driver chip 104 gradually increases along a direction parallel to the first edge; the driver chip 104 has a plurality of support areas A4 arranged on the side of the partial binding pad 1041 close to the fan-out area A2; the driver chip 104 also includes: a redundant pad 1042 located in the support area A4; a partial fan-out trace 105 passes through the area between adjacent support areas A4; the partial fan-out trace 105 passes through the support area A4 and is insulated from the redundant pad 1042.

[0071] The substrate 101 can be made of a rigid material such as glass to improve the substrate 101's ability to support other film layers thereon. Alternatively, the substrate 101 can be made of a flexible material such as polyimide (PI) to improve the overall bending and stretching resistance of the display substrate, thereby preventing stress generated during bending, stretching, and twisting from causing the substrate 101 to break and cause a short circuit. In practical applications, the material of the substrate 101 can be appropriately selected based on actual needs to ensure that the display substrate has good performance.

[0072] The driver chip 104 can specifically be a sunken driver chip (its structure can be as shown above and will not be described in detail here), which can provide data signals for the data lines 103 in the pixel area A1. The binding pads 1041 in the driver chip 104 can specifically be output pads, which can be made of a metal material with good electrical conductivity. It can form a single-layer structure made of a single material, or a multi-layer structure made of a variety of different materials. The redundant pads 1042 in the driver chip 104 can be made of the same material as the binding pads 1041 and form the same structure, so that the redundant pads 1042 and the binding pads 1041 have approximately the same thickness, ensuring that they have a good support effect, thereby ensuring the tightness of the attachment.

[0073] Fan-out traces 105 may serve as connecting lines between data lines 103 and driver chip 104 to transmit data signals. Fan-out traces 105 may be made of a metal material, such as molybdenum (Mo), aluminum (Al), titanium (Ti), or alloys thereof, and may have a single-layer or multi-layer structure.

[0074] In the display panel provided by the embodiment of the present disclosure, some fan-out traces 105 pass through the area between adjacent support areas A4, and some fan-out traces 105 pass through the support areas A4 and are insulated from the redundant pads 1042. Thus, the fan-out traces 105 do not need to be routed in a zigzag manner in the support areas A4, thus avoiding the increase in longitudinal routing space. This reduces the width of the bottom bezel of the display panel, achieving a narrow bezel and a design with equal widths on all four sides, thereby improving the display quality of the display panel.

[0075] Figure 6 is a schematic diagram of a first partial structure of redundant pads and fan-out traces in the display panel shown in Figure 5, and Figure 7 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 6 along the A-A' direction. As shown in Figures 6 and 7, the redundant pad 1042 includes: a first insulating layer 1042a, a second insulating layer 1042b, and a first transparent electrode layer 1042c located on the substrate 101 and arranged in sequence along a direction away from the substrate 101; the fan-out trace 105 includes: a first sub-fan-out trace 1051; the first sub-fan-out trace 1051 is located on the side of the substrate 101 close to the first insulating layer 1042a.

[0076] The first insulating layer 1042a and the second insulating layer 1042b can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2), and can form a single-layer structure made of a single material, or a multi-layer structure made of a plurality of different materials. In practical applications, if only for the purpose of insulation, only one layer of the first insulating layer 1042a and the second insulating layer 1042b can be provided, but in order to ensure the overall thickness of the redundant pad 104 in the support area A4, two insulating layers are generally provided, namely the first insulating layer 1042a and the second insulating layer 1042b. Specifically, the first insulating layer 1042a can be provided in the same layer as the gate insulating layer (not shown in the figure) covering the gate of the pixel area A1 in the display panel, and the second insulating layer 1042b can be provided in the same layer as the interlayer insulating layer side of the source and drain electrode layer (not shown in the figure) covering the thin film transistor of the pixel area A1 in the display panel. During the preparation process, the first insulating layer 1042a in the redundant pad 1042 can be formed using the same material and the same process as the gate insulating layer in the pixel area A1, and the second insulating layer 1042b can be formed using the same material and the same process as the interlayer insulating layer in the pixel area A1, which can reduce the process steps and save preparation costs.

[0077] The first transparent electrode layer 1042c can be made of a transparent conductive material such as indium tin oxide (ITO). Specifically, the first transparent electrode 1042c can be provided in the same layer as the pixel electrode (not shown) in pixel area A1 of the display panel. During the manufacturing process, the first transparent electrode layer 1042c can be formed using the same material and process as the pixel electrode in pixel area A1, thereby reducing the number of process steps and saving manufacturing costs.

[0078] The fan-out routing 105 can adopt a single-layer structure, which includes: a first sub-fan-out routing 1051. The first sub-fan-out routing 1051 can be arranged on the side of the substrate 101 close to the first insulating layer 1042a, so that the first sub-fan-out routing 1051 and other conductive layers in the redundant pad 1041 (such as the first transparent electrode layer 1042c) are insulated by the first insulating layer 1042a and the second insulating layer 1042b, which can avoid the first sub-fan-out routing 1051 and the first transparent electrode layer 1042c from being connected and short-circuited. Therefore, the first sub-fan-out routing 1051 can directly pass through the support area A4, and the first sub-fan-out routing 1051 does not need to be routed in a bending manner, thereby avoiding increasing the longitudinal routing space, and can reduce the width of the lower frame of the display panel, realizing a narrow frame and a design with equal width on all four sides, which is beneficial to improving the display effect of the display panel.

[0079] Figure 8 is a schematic diagram of a second partial structure of the redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 9 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 8 along the BB' direction. As shown in Figures 8 and 9, the difference from the structure shown in Figures 6 and 7 is that the redundant pad 1042 also includes: a first metal layer 1042d located on the side of the substrate 101 close to the first insulating layer 1041; the first metal layer 1042d includes: a plurality of first metal strips 1042d' arranged at intervals; and the first sub-fan-out routing 1051 is located between adjacent first metal strips 1042d'.

[0080] The first metal layer 1042d can be made of a metal material with good conductivity, such as one of molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy of the above materials. It can be a single-layer structure or a multi-layer structure. In the embodiment of the present application, the first metal layer 1042d is a single-layer structure. In each support area A4, the first metal layer 1042d is divided into a plurality of first metal strips 1042d' arranged at intervals. The fan-out trace 105 can adopt a single-layer structure, which includes: a first sub-fan-out trace 1051. The first sub-fan-out trace 1051 can pass through the gap between adjacent first metal strips 1042d'. This disconnects the first sub-fan-out trace 1051 from the first metal layer 1042d and is insulated from other conductive layers (e.g., the first transparent electrode layer 1042c) in the redundant pad 1041 by the first insulating layer 1042a and the second insulating layer 1042b. This prevents short circuits between the first sub-fan-out trace 1051 and the first transparent electrode layer 1042c and the first metal layer 1042d. Therefore, the first sub-fan-out trace 1051 can pass directly through the support area A4, eliminating the need for a zigzag routing pattern, thus avoiding increased longitudinal routing space. This reduces the width of the display panel's bottom bezel, achieving a narrow bezel and a design with equal widths on all four sides, thereby improving the display quality of the display panel. Furthermore, the first metal strip 1042d' increases the support area, ensuring the overall support of the redundant pad 1042.

[0081] Figure 10 is a schematic diagram of a third partial structure of the redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 11 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 10 along the C-C' direction. As shown in Figures 10 and 11, the difference between it and the structure shown in Figures 6 and 7 is that the redundant pad 1042 also includes: a second metal layer 1042e located between the first insulating layer 1042a and the second insulating layer 1042b; the second metal layer 1042e overlaps with the support area A4.

[0082] The second metal layer 1042e can be made of a highly conductive metal material, such as molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy of these materials. It can be a single-layer structure or a multi-layer structure. In the embodiment of the present application, the second metal layer 1042e is a single-layer structure. The second metal layer 1042e covers the entire support area A2, further enhancing the overall support effect of the redundant pad 1042.

[0083] Figure 12 is a schematic diagram of the fourth local structure of the redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 13 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 12 along the D-D' direction. As shown in Figures 12 and 13, the difference between it and the structure shown in Figures 10 and 11 is that the redundant pad 1042 also includes: a second metal layer 1042e located between the first insulating layer 1042a and the second insulating layer 1042b; the second metal layer 1042e is connected between adjacent support areas A4 to form an integrated structure.

[0084] In the embodiment of the present application, the second metal layer 1042e is a single-layer structure. The second metal layer 1042e is connected between adjacent support areas A4 to form an integrated structure, which can further enhance the overall support effect of the redundant pad 1042.

[0085] Figure 14 is a schematic diagram of a fourth local structure of the redundant pad and fan-out routing in the display panel shown in Figure 5, and Figure 15 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 14 along the E-E' direction. As shown in Figures 14 and 15, the difference from the structure shown in Figures 12 and 13 is that the redundant pad 1042 also includes: a second metal layer 1042e located between the first insulating layer 1042a and the second insulating layer 1042b; the second metal layer 1042e includes: a plurality of second metal strips 1042e' arranged at intervals; the fan-out routing 105 also includes: a second sub-fan-out routing 1052; the second sub-fan-out routing 1052 is located between adjacent second metal strips 1042e'.

[0086] In the structures shown in Figures 14 and 15 , fan-out trace 105 employs a dual-layer structure, including a first sub-fan-out trace 1051 and a second sub-fan-out trace 1052. The first metal layer 1042d is a single-layer structure, and the second metal layer 1042e is a single-layer structure. Within each support area A4, the first metal layer 1042d is divided into a plurality of spaced-apart first metal strips 1042d', and the second metal layer 1042e is divided into a plurality of spaced-apart second metal strips 1042e'. The first sub-fan-out trace 1051 can pass through the gap between adjacent first metal strips 1042d', and the second sub-fan-out trace 1052 can pass through the gap between adjacent second metal strips 1042e'. In this way, the first sub-fan-out trace 1051 is disconnected from the first metal layer 1042d, and the second sub-fan-out trace 1052 is disconnected from the second metal layer 1042e. They are insulated from other conductive layers (for example, the first transparent electrode layer 1042c) in the redundant pad 1041 by the first insulating layer 1042a and the second insulating layer 1042b. This can prevent the first sub-fan-out trace 1051, the second sub-fan-out trace 1052 from being connected to the first transparent electrode layer 1042c, the first metal layer 1042d, and the second metal layer 1042e, thereby preventing a short circuit. Therefore, the first sub-fan-out routing 1051 and the second sub-fan-out routing 1052 can directly pass through the support area A4, and the first sub-fan-out routing 1051 and the second sub-fan-out routing 1052 do not need to be routed in a bending manner, thereby avoiding increasing the longitudinal routing space, and can reduce the width of the lower frame of the display panel, realizing a narrow frame and a design of equal width on all four sides, which is beneficial to improving the display effect of the display panel.

[0087] In some embodiments, as shown in FIG15 , the orthographic projection of the first sub-fan-out trace 1051 on the substrate 101 is located between the orthographic projections of adjacent second sub-fan-out traces 1052 on the substrate 101 ; the orthographic projection of the first metal strip 1042 d ′ on the substrate 101 is located between the orthographic projections of adjacent second metal strips 1042 e ′ on the substrate 101 .

[0088] The staggered arrangement of first sub-fan-out traces 1051 and second sub-fan-out traces 1052 increases the distance between them, preventing large parasitic capacitance from forming between them during drive signal transmission and ensuring stable drive signal transmission. Accordingly, first metal strips 1042d' and second metal strips 1042e' are also staggered.

[0089] Figure 16 is a schematic diagram of a fifth local structure of redundant pads and fan-out traces in the display panel shown in Figure 5, and Figure 17 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 16 along the F-F' direction. As shown in Figures 16 and 17, the difference between it and the structure shown in Figures 14 and 15 is that the orthographic projection of the first sub-fan-out trace 1051 on the substrate 101 coincides with the orthographic projection of the second sub-fan-out trace 1052 on the substrate 101; the orthographic projection of the first metal strip 1042d' on the substrate 101 coincides with the orthographic projection of the second metal strip 1042e' on the substrate 101.

[0090] The first sub-fan-out trace 1051 and the second sub-fan-out trace 1052 are arranged opposite each other, which can reduce the difficulty of manufacturing and save manufacturing costs during the manufacturing process. Correspondingly, the first metal strip 1042d' and the second metal strip 1042e' are also arranged opposite each other.

[0091] In some embodiments, the lengths of the first metal strip 1042d' and the second metal strip 1042e' in a direction parallel to the fan-out trace 105 are equal to the length of the support area A4 in the direction parallel to the fan-out trace 105. The area of ​​the first metal strip 1042d' and the second metal strip 1042e' in each support area A4 is greater than or equal to 70% of the area of ​​the support area A4. This ensures that the first metal strip 1042d' and the second metal strip 1042e' provide good support.

[0092] In some embodiments, Figure 18 is a schematic diagram of a sixth partial structure of the redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 19 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 18 along the G-G' direction. As shown in Figures 18 and 19, the difference between it and the structure shown in Figures 10 and 11 is that the redundant pad 1042 also includes: a second transparent electrode layer 1042f located between the first insulating layer 1042a and the second insulating layer 1042b; the second transparent electrode layer 1042f overlaps with the support area A4.

[0093] The second transparent electrode layer 1042f can replace the second metal layer 1042e mentioned above, and also plays a supporting role. In addition, the thickness of the second transparent electrode layer 1042f can be controlled to ensure the supporting effect.

[0094] In some embodiments, Figure 20 is a schematic diagram of a seventh local structure of the redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 21 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 20 along the H-H' direction. As shown in Figures 20 and 21, the difference between it and the structure shown in Figures 18 and 19 is that the redundant pad 1042 also includes: a second transparent electrode layer 1042f located between the first insulating layer 1042a and the second insulating layer 1042b; the second transparent electrode layer 1042f is connected between adjacent support areas A4 as an integrated structure.

[0095] The second transparent electrode layer 1042 f is connected between adjacent support areas A4 to form an integrated structure, which can increase the support area and ensure the overall support effect of the redundant pad 1042 .

[0096] In some embodiments, as shown in FIG. 6 to FIG. 21 , the first transparent electrode layer 1042 c overlaps with the support area A4 .

[0097] The first transparent electrode layer 1042c may only cover each supporting area 1042, which can reduce the process difficulty and save the production cost during the preparation process.

[0098] In some embodiments, Figure 22 is a schematic diagram of a seventh local structure of redundant pads and fan-out routing in the display panel shown in Figure 5, and Figure 23 is a schematic diagram of the cross-sectional structure of the structure shown in Figure 22 along the I-I' direction. As shown in Figures 22 and 23, the difference between it and the structure of Figures 6 to 21 above is that the first transparent electrode layer 1042c is connected as an integrated structure between adjacent support areas A4.

[0099] The first transparent electrode layer 1042 c is connected between adjacent support areas A4 to form an integrated structure, which can increase the support area and ensure the overall support effect of the redundant pad 1042 .

[0100] In some embodiments, as shown in FIG. 6 to FIG. 23 , the first insulating layer 1042 a and the second insulating layer 1042 b are connected as an integral structure between adjacent support areas A4 .

[0101] The first insulating layer 1042 a and the second insulating layer 1042 b are connected as an integral structure between adjacent supporting areas A4 , which can increase the supporting area and ensure the overall supporting effect of the redundant pad 1042 .

[0102] In some embodiments, FIG24 is a schematic diagram of an eighth partial structure of redundant pads and fan-out traces in the display panel shown in FIG5 , and FIG25 is a schematic diagram of a cross-sectional structure of the structure shown in FIG24 along the J-J' direction. As shown in FIG24 and FIG25 , the structure differs from the structure of FIG22 to FIG23 described above in that redundant pad 1042 further includes: a first metal layer 1042d located on the side of substrate 101 near first insulating layer 1041; first metal layer 1042d includes: a plurality of first metal strips 1042d' spaced apart; and first sub-fan-out trace 1051 is located between adjacent first metal strips 1042d'. First metal strips 1042d' can increase the support area, ensuring the overall support effect of redundant pad 1042.

[0103] In a second aspect, embodiments of the present disclosure provide a display device comprising a display panel as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, mobile phone, monitor, laptop computer, digital photo frame, or navigation system. Its implementation principles are similar to those of the aforementioned display panels and will not be further elaborated here.

[0104] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a pixel region, a fan-out region and a binding region arranged on one side of the pixel region and arranged in sequence in a direction away from the pixel region; wherein: The display panel comprises: a substrate, a driving chip located on the substrate and arranged in the binding area; the driving chip comprises: a plurality of binding pads; the display panel further comprises: a plurality of fan-out traces located on the substrate; one end of each of the fan-out traces is connected to the binding pad and extends to the pixel area through the fan-out area; The distance between part of the binding pads and the first edge of the driver chip gradually increases along a direction parallel to the first edge; the driver chip has a plurality of support areas arranged on a side of part of the binding pads close to the fan-out area; the driver chip further includes: redundant pads located in the support areas; Part of the fan-out routing passes through the area between the adjacent support areas; part of the fan-out routing passes through the support area and is insulated from the redundant pad.

2. The display panel according to claim 1, wherein: The redundant pad comprises: a first insulating layer, a second insulating layer, and a first transparent electrode layer which are located on the substrate and are sequentially arranged in a direction away from the substrate; The fan-out routing includes: a first sub-fan-out routing; the first sub-fan-out routing is located on the side of the substrate close to the first insulating layer.

3. The display panel according to claim 2, wherein: The redundant pad further includes: a first metal layer located on a side of the substrate close to the first insulating layer; The first metal layer includes: a plurality of first metal strips arranged at intervals; and the first sub-fan-out wiring is located between adjacent first metal strips.

4. The display panel according to claim 3, wherein: The redundant pad further includes: a second metal layer located between the first insulating layer and the second insulating layer; The second metal layer overlaps with the supporting area.

5. The display panel according to claim 3, wherein: The redundant pad further includes: a second metal layer located between the first insulating layer and the second insulating layer; The second metal layer is connected between adjacent support areas to form an integrated structure.

6. The display panel according to claim 3, wherein: The redundant pad further comprises: a second metal layer located between the first insulating layer and the second insulating layer; the second metal layer comprises: a plurality of second metal strips arranged at intervals; The fan-out routing further includes: a second sub-fan-out routing; the second sub-fan-out routing is located between adjacent second metal strips.

7. The display panel according to claim 6, wherein: The orthographic projection of the first sub-fan-out routing on the substrate is located between the orthographic projections of adjacent second sub-fan-out routings on the substrate; The orthographic projection of the first metal strip on the substrate is located between the orthographic projections of adjacent second metal strips on the substrate.

8. The display panel according to claim 6, wherein: The orthographic projection of the first sub-fan-out routing on the substrate coincides with the orthographic projection of the second sub-fan-out routing on the substrate; The orthographic projection of the first metal strip on the substrate coincides with the orthographic projection of the second metal strip on the substrate.

9. The display panel according to claim 6, wherein: The lengths of the first metal strip and the second metal strip along a direction parallel to the fan-out wiring are both equal to the length of the support area along a direction parallel to the fan-out wiring.

10. The display panel according to claim 6, wherein: The areas of the first metal strip and the second metal strip in each of the supporting regions are greater than or equal to 70% of the area of ​​the supporting region.

11. The display panel according to claim 3, wherein: The redundant pad further includes: a second transparent electrode layer located between the first insulating layer and the second insulating layer; The second transparent electrode layer overlaps with the supporting area.

12. The display panel according to claim 3, wherein: The redundant pad further includes: a second transparent electrode layer located between the first insulating layer and the second insulating layer; The second transparent electrode layer is connected between adjacent support areas to form an integrated structure.

13. The display panel according to any one of claims 2 to 12, wherein: The first transparent electrode layer overlaps with the supporting area.

14. The display panel according to any one of claims 2 to 12, wherein: The first transparent electrode layer is connected between adjacent support areas to form an integrated structure.

15. The display panel according to any one of claims 2 to 12, wherein: The first insulating layer and the second insulating layer are connected to form an integral structure between adjacent supporting areas.

16. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 15.

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