Low-power and radiation hardened FLIP flops

Abstract

Novel flip flops are taught which have reduced clock loads to reduce power consumption by the flip flop. In one aspect, the flip flop includes a master latch with first and second logic gates that operate to only charge a pre-charge node in the master latch when the clock input is a logic low and the data input is a logic high. In another aspect, the flip flop includes a first interlocked cell in the master latch and a second interlocked cell in the slave latch wherein the second interlocked cell is the complement of the first interlocked cell to reduce the number of transistors which must be clocked in the flip flop.

Description

LOW-POWER AND RADIATION HARDENED FLIP FLOPSFIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor integrated circuits and devices. More specifically, the present invention relates to flip-flops and integrated circuits and devices which employ them.BACKGROUND OF THE INVENTION

[0002] A complex System on Chip ("SoC”) or VLSI integrated circuit can contain more than several million registers which consume a substantial amount of power and energy which also results in waste heat which must be removed from the device. Further, environmental radiation such as high energy neutrons can upset the stored data resulting in soft errors and poor reliability.

[0003] Flip-flops (“FFs”) are extensively used in digital designs and are a fundamental building block of sequential logic that are used to implement many other more sophisticated circuit elements, such as registers, clock pipelines, etc. FFs are typically edge-triggered by a clock (“CK”) and are generally designed based on a master-slave configuration as shown in Figure 1.

[0004] In a positive edge-triggered flip-flop, when CK is low the master latch samples the input data (“D”), and when CK is high, the slave latch samples the output (“Q*”) of the master latch. Thus, a new data is available at the output (“Q”) in next clock cycle as shown in the timing diagram of Figure 2.

[0005] Flip-flop power and energy efficiency is crucial to design low-power digital systems. Moreover, power- and energy-efficient circuits are necessary for battery-operated systems to increase their battery life. Flip-flops are a fundamental part of many digital circuits, and their operating speed and the power they consume have a large influence on how well a digital system works as a whole. In particular, the energy (“clock power”) used to process each clock transition in the FF can be a significant portion of the total energy used in the semiconductor device.

[0006] Flip-flops are typically used to store state information. Scaled technologies frequently choose static flip-flops because of their simpler timing, relative robustness, and superior reliability. Flip-flop research in recent years has been motivated by power and / or energy-efficient designs. Specifically, on each clock transition, the circuitry of the FF must determine if the state of its inputs have changed and must update its output state if necessary. When a clock edge occurs and no change has occurred at the inputs, the circuitry of the FF still uses power as it determines that no change to its output is required.

[0007] Flip-flop power consumption efficiency is related to data activity (“DA”), which signifies the probability of data transition along with the clock transition. For example, a 5 % DA suggests that data is changing once in every 20 clock cycles. In many applications the DA is less than 20%. In such cases, a substantial amount of clock power and energy is wasted without performing any useful task.

[0008] Moreover, a clock distribution network in a complex SoC or VLSI device consumes a substantial amount of power. The power used by the FFs and clock distribution networks in a typical digital system design can account for 20% to 45% of the system's overall power. Additionally, pipelines are frequently employed to increase system throughput, which adds to the load on the clock network.

[0009] Conventionally, a Transmission Gate Flip-Flop (“TGFF”) is used in VLSI and other semiconductor integrated circuit devices. Internally, a TGFF requires CLK, and its complement (“CLKN”) as shown in Figure 3. A TGFF often requires up to twelve transistors for processing CK (and CLKN) inside TGFF resulting in substantial clock power consumption. As a result, several circuit approaches have been proposed to reduce the number of clocked transistorsand thus the total power consumption of flip-flops.

[0010] Some recent prior art flip-flops employ conditional clocking to decrease clock power consumption. This technique reduces clock power consumption but increases the total number of transistors and the die area required to layout the FF.

[0011] Researchers have also employed pre-charging of internal node(s) in a flip-flop to reduce its clock power consumption. This approach helps to eliminate some clock and data transistors and lowers the overall transistor count, but the drawback with this technique is that it charges and discharges internal nodes with the clock frequency, which degrades the power-efficiency of the FF at low DAs.

[0012] A better technique which has been proposed is to reduce the clock related transistors as much as possible without a pre-charging node in a flip-flop. Unfortunately, this often increases the Data to Output (“D-Q”) delay of the FF, and the data power consumption at higher DAs.

[0013] A dual-edge-triggered (DET) flip-flop can improve energy efficiency by latching input data at both clock edge. Therefore, for the same data throughput, the clock frequency of the DET is 50% that of the conventional single edge triggered flip-flop. Therefore, DET flip-flops are used for low-power designs. Different techniques like Latch-Multiplexer, Pulsed-Latch, and C- element are used to design DET flip-flops. Figure 14 illustrates prior art Fully Static True Single Phase DET (FS-TSPC-DET) flip-flop based on Latch-Multiplexer. However, a DET requires clock duty cycle to be 50%.

[0014] As an additional challenge to the design and implementation of FFs, ionizing radiation can upset the data value stored in the master and slave latches of a flip-flop. Cosmic neutrons and alpha particles are two examples of ionizing radiation. These particles have the ability to produce plenty of electron hole pairs in the silicon substrate, which might be accumulated by the storage nodes and lead to a data upset or soft error (“SE”). This is especially true for nano-scaled semiconductor circuits, where the charge corresponding to a data state on a storage node is very small due to low node capacitance and supply voltage.

[0015] To deal with this issue, in Radiation Hardened by Design (“RHBD”), soft-error tolerant cells are used to improve the SE immunity of FFs. Dual Interlocked Cell (“DICE”) and Quatro are two popular tolerant storage cells used in this regard. In soft error tolerant flip-flops, sensitive nodes are implemented with tolerant storage cells. Figure 9 and Figure 10, illustrate prior art DICE and Quatro based master-slave RHBD flip-flops.

[0016] These types of flip-flops require duplicating the hardware to generate same -phase and out-of-phase data signals, as required for DICE and Quatro cells, respectively. Therefore, a large number of clock and other transistors are used, which not only results in increased die areas, but also requires increased power, energy, and D-Q delay. As a result, these known designs are not suitable for low-power, low-energy, and high-performance applications.

[0017] As integrated circuit technology continues to scale to smaller sizes, and as demand for portable, battery or solar powered devices increases, there is a constant push to reduce their power and energy consumption. Thus, research in low-power, low-energy, and high-performance flip-flops using new architectures and techniques continues. Furthermore, semiconductor process scaling suggests that when a value saved in storage components like flip-flops is reversed, soft errors become a critical concern, o degrading the reliability of an integrated circuit. Therefore, new flip-flop designs are required not only to reduce soft-error penalties, but also to fit in low- power, low-energy, and low die-area systems.SUMMARY OF THE INVENTION

[0018] It is an object of the present invention to provide a novel flip flop and circuits which employ it, which obviates or mitigates at least one disadvantage of the prior art.

[0019] According to a first aspect of the present invention, there is provided a flip flop responsive to an input clock and input data to produce a corresponding output, the flip flop comprising: a master latch having a pre-charge node, a first logic gate responsive to the clock input and the data input to generate at least two outputs and a second logic gate responsive to the at least two outputs to apply a charge to the pre-charge node only when the clock input is a logic low and the data input is a logic high; and a slave latch responsive to the input clock and the precharge node to produce the corresponding output.

[0020] Preferably, the flip flop is implemented in CMOS.

[0021] According to another aspect of the present invention, there is provided a low power hardened flip flop responsive to a clock input and a data input and comprising: a master latch with a first interlocked cell; and a slave latch with a second interlocked cell, the second interlocked cell being the complement of the first interlocked cell, and wherein the interlocked cells provide redundancy against radiation-induced errors.BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the present invention will now be described by way of example only with reference to the following drawings in which:Figure 1 is a block diagram of a prior art Master-slave Flip-flop;Figure 2 is a timing diagram of the positive Edge-triggered Flip-flop of Figure 1 ;Figure 3 is a schematic drawing of a prior art Transmission Gate Flip-flop;Figure 4 is a schematic drawing of a prior art 18-transistor Contention-free, Static, Single-phase Clocked Flip-flop;Figure 5 is a schematic drawing of a Very Eow-power Flip-flop in accordance with an aspect of the present invention;Figure 6 is a schematic drawing of a Very Eow-power Flip-flop in accordance with another aspect of the present invention;Figure 7 is a schematic drawing of a Very Eow-power Flip-flop in accordance with another aspect of the present invention;Figure 8 is a schematic drawing of a prior art standard Master-slave D Flip-flop;Figure 9 is a schematic drawing of a prior art soft error robust (SER) DICE Master-slave Flipflop;Figure 10 is a schematic drawing of a prior art SER QUATRO Master-slave flip-flop;Figure 11 is a schematic drawing of a novel SER Radiation Hardened by Design Quatro Flipflop with 34 transistors in accordance with an aspect of the present invention;Figure 12 is a schematic drawing of a novel SER Radiation Hardened by Design DICE Flip-flop in accordance with another aspect of the present invention;Figure 13 is a schematic drawing of a novel SER Radiation Hardened by Design Quatro Flipflop with 35 transistors in accordance with an aspect of the present invention;Figure 14 is a schematic drawing of a prior art DET Fully-Static TSPC (FS-TSPC-DET) flipflop;Figure 15 is a schematic drawing of a novel DET 9C-TSPC Flip-flop (9CTSPC-DET) in accordance with an aspect of the present invention;Figure 16 is a schematic drawing of a novel DET 8C-TSPC Flip-flop (8CTSPC-DET) in accordance with an aspect of the present invention;Figure 17 illustrates total average power consumption versus DA for low-power flip-flops at supply voltage (“VDD”) = 1 V, CK = 1 GHz;Figure 18 illustrates total average power consumption versus DA for low-power flip-flops at VDD = 0.6 V, CK = 50 MHz;Figure 19 illustrates total average power consumption versus DA for SER flip-flops at VDD = 1 V, CK = 1 GHz;Figure 20 illustrates total average power consumption versus DA for SER flip-flops at VDD = 0.5 V, CK = 50 MHz;Figure 21 illustrates power-delay-product (PDP) versus DA for SER flip-flops at VDD = 1 V, CK = 1 GHz;Figure 22 illustrates PDP versus DA for SER flip-flops at VDD = 0.5 V, CK = 50 MHz;Figure 23 illustrates comparison of D-to-Q delay for SER flip-flops at VDD = 1 V, CK = 1 GHz;Figure 24 illustrates comparison of D-to-Q delay for SER flip-flops at VDD = 0.5 V, CK = 50 MHz;Figure 25 illustrates comparison of critical charge for SER flip-flops at VDD = 1 V, CK = 1 GHz.Figure 26 illustrates total average power consumption versus DA for DET low-power TSPC flip-flops at VDD = 1 V, CK = 1 GHz;Figure 27 illustrates power-delay-product (PDP) versus DA for DET low -power TSPC flip-flops at VDD = 1 V, CK = 1 GHz; andFigure 28 illustrates comparison of D-to-Q delay for DET low -power TSPC flip-flops at VDD = 1 V, CK = 1 GHz.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023] Transmission Gate Flip-flops, as shown in Figure 3, have been a common implementation choice in the past because of their robust operation and relatively high- performance. The internal nodes of the TGFF are always connected to either the power supply (“VDD”) or ground (“VSS”), which results in a fully static operation that leads to its robustness. Additionally, its operation is free of contention, meaning that internal nodes' pull-up and pulldown pathways do not compete with one another. These features also help the TGFF to work in the near-threshold voltage (“NTV”) region and ultimately at low supply voltage.

[0024] However, a TGFF consumes a considerable amount of unnecessary power because of the transitions of the large number of clock transistors at every cycle, particularity at low data activity. As apparent from Figure 3, the TGFF requires the CEK and its complement, CEKN, to be applied to eight transistors arranged in a transmission gate arrangement. In addition, four transistors are needed to produce the CEK and CEKN signal. Therefore, a total of twelve transistors are needed for clocking in this flip-flop design.

[0025] Figure 4 shows a prior art 18-transistor, contention-free, fully static, single -phase clocked flip-flop (“18TSPC”) which has a clock load of four clock transistors (Ml, M8, M9, M10). This flip-flop significantly improves power-efficiency at high DA, compared to the TGFF, but at low DA it consumes relatively more power. As can be seen, the node X in the flip-flop is pre-charged to logic high, or 1, when the clock, CK, makes a negative transition irrespective of the data, D, value. For example, if the D is logic low, or 0, for multiple clock cycles, the node X is pre-charged to 1 at the negative clock transition and discharged to 0 when clock makes a positive clock transition. Consequently, it results in unnecessary power consumption, decreasing power efficiency of the design.

[0026] As is known, the dynamic power consumption of a flip-flop is proportional to the inputDA, and a typical DA range for flip-flops is between 5 to 15 %. Therefore, the motivation is to design a flip-flop with low-power utilization in the aforementioned range of data activity. One of the ways to accomplish this objective is by lowering the clock transistor count in the flip-flop, as they toggle at the clock frequency.

[0027] Figure 5 shows a novel single-phase clocked flip-flop 500 developed by the present inventors which only requires a single-phase clock and only two clock transistors Ml and MIO.

[0028] Flip-flop 500, referred to herein as the Very Low-power Flip-flop with only Two Clock Transistors (“2C_19TSPC”), as shown in Figure 5 employs the master-slave configuration. The master latch node LI, samples the complement of data D when CK is low, and the slave latch node L2 samples LI when CK is high. Its logical behavior can be described as, LI = D’.CK’ + Ll.CK, L2 = Ll.CK + L2.CK’. The master latch consists of a first complex logic gate depicted by 502, and a second logic gate 504. Logic gate 502 has clock, CK, and data, D, inputs; and has more than one output. Specifically, nodes LI, Yl, and XI are the outputs of gate 502. These outputs serve as inputs to logic gate 504 in master latch. As will be apparent to the person skilled in art, the node nl is pre-charged to 1 only when the CK = 0, and D = 1. In other words, the nl node is not pre-charged when the CK = 0, and D = 0. Hence, pre-charging of node nl is data dependent.

[0029] Assuming initially, Q = "0". When CK = "0" and D = "0", node LI goes high; and node nl is in high impedance state and holds its previous value. When CK changes from "0" to " 1" (low to high), node nl discharges to ground through M9 and M10, which turns on M3, thus driving node LI high. Thereafter, L2 goes high and, as a result, Q is driven low.

[0030] In contrast, when CK = "0" and D = " 1", the node nl which is charged to a supply voltage less than threshold turns on M4 to discharge LI to ground. As a result, M7 turns on, which restores node nl to full supply voltage. However, node L2 remains isolated until CK next goes high to turn on M10. Subsequently, L2 changes from " 1" to "0" through M13, M15, and M10, which in turn causes Q to change from "0" to " 1".

[0031] The 2C_19TSPC will show transient contention when D = 1, previous D = 0, and CK is making a positive transition. The L2 node is pulled down by the path consisting of M13, M15,and MIO. The transistor M12 is also on, however an appropriately sized aforementioned pulled down path and a M12 can resolve the transient contention such that node L2 is discharged which results in n4 being pulled high and thus turning off transistor Ml 2.

[0032] Figure 6 shows another novel flip flop 600 which is which is a very low -power flip-flop with only three clock transistors (“3C_20TSPC”) in accordance with another aspect of present invention. The 3C_20TSPC 600 is similar to the above described 2C_19TSPC 500 of Figure 5. However, in this embodiment, transient contention which is seen in the 2C_19TSPC when: D = 1; previous D = 0; and CK is making a positive transition, is avoided by adding one more clock transistor M20 without necessitating the upsizing of any of the transistors. As a result, flip flop 600 has total of three clock transistors and works in master-slave configuration and has the same working mechanism as flip flop 500.

[0033] Specifically, flip-flop 600, similar to 500, consists of a master latch and a slave latch. The master latch consists of a first complex logic gate 602, and a second logic gate 604. Complex logic gate 602 has multiple outputs (LI, XI) that serve as inputs to second logic gate 604. In a manner similar to that of flip flop 500, the pre-charging of node nl in gate 604 is data dependent and is only charged when CK = 0, and D = 1.

[0034] Figure 7 shows another novel flip flop 700, which is another very low-power flip-flop with only three clock transistors (“3C_21TSPC”) in accordance with an aspect of present invention. Flip flop 700 is similar to flip flop 500 discussed above. However, the transient contention which is seen in flip flop 500 when D = 1, previous D = 0, and CK is making a positive transition is eliminated in this embodiment by adding one more clock transistor M20. As a result, flip flop 700 has a total of three clock transistors.

[0035] Flip flop 700 employs a P-type transistor M8 in its pull-up network to eliminate the unnecessary pre-charge, as described above with respect to the flip flop shown in Figure 4, at node nl. In this embodiment, P-type data transistor M21 is added between Ml and M5 to generate a data complement at node XI, which is connected to the gate of transistor M8. As will now be apparent, flip flop 700 works in a master-slave configuration and has a similar working mechanism as flip flops 50 Oand 600 and, in addition, works at low-voltage. The master latch in 700 consists of a first complex logic gate 702, and a second logic gate 704. First complex logicgate 702 has multiple outputs (LI, XI) that serve as inputs to logic gate 704. In a manner similar flip flop 500, the pre-charging of node nl in logic gate 704 is data dependant and is only precharged when CK = 0, and D = 1.

[0036] As mentioned above, an increasingly common challenge to the design of FFs is the effect of ionizing radiation and it is desired to have effective radiation hardened FF designs. A prior art master-slave D Flip-flop 800 (“MS-DFF”) is shown in Figure 8, and has a clock load of ten clock transistors and a total of 24 transistors. This flip-flop uses cross-coupled inverters as a storage element depicted in master circuit 802, and in slave circuit 804. Flip flop 800 is used herein as a reference flip-flop to be compared with the novel radiation hardened flip-flops described below.

[0037] As is well known, nanoscale integrated circuits are highly vulnerable to particle-induced single event transients (“SETs”) because of low signal charge and lower noise margin. Alpha particles and cosmic neutrons, which come from intergalactic rays and packing materials, respectively, are the main contributors of SETs. These particles produce excess charge in silicon by direct or indirect ionization, which is collected by sensitive nodes and results in voltage transients at those nodes. If collected charge is higher than a threshold, critical charge, the data stored in a memory cell, or a flip-flop can get upset. As it does not result in long-term device damage, it is sometimes known as a “soft error”.

[0038] In a soft error tolerant flip-flops, various circuit techniques are conventionally used to reduce the probability of data from being upset. A prior art SER Master-slave DICE (“MS- DICE”) flip-flop 900 is shown in Figure 9. “DICE” stands for Dual Interlocking CE11 where the data is stored on multiple nodes. In flip-flop 900, 902 illustrates a DICE cell of 8 transistors with four nodes, XI, X2, X3, and X4 which are used as a storage element that is capable of tolerating radiation induced single node upsets. In a master-slave flip-flop configuration, the DICE cell is used both in the master and slave latches and the DICE cell in the slave latch is indicated at 904. These DICE nodes store duplications of data and this redundancy enables the flip flop to tolerate a data upset on a given node.

[0039] As can be seen, flip-flop 900 has a clock load of ten clock transistors, and requires a total of 36 transistors, and thus consumes relatively high levels of power and energy. Flip-flop 900 also struggles with low-voltage performance.

[0040] Another prior art SER Master-slave Quatro (“MS-Quatro”) flip-flop 1000 is shown in Figure 10. Flip-flop 1000 dual interlocking radiation tolerant Quatro cell 1002 and 1004 of 8 transistors are used as storage elements. Quatro cell 1002 is used in the master and Quattro cell 1004 is used as the slave latch. Overall, flip-flop 1000 requires a clock load of ten clock transistors, and a total of 38 transistors, again consuming relatively high levels of power and energy.

[0041] A novel SER very low-power and low-energy flip-flop 1100 (“RHBD-34T-Quatro”) in accordance with an aspect of the present invention is shown in Figure 11. Flip-flop 1100 employs a Quatro cell 1106 which is used as a storage element in the master latch 1102. In the slave latch 1104, an alternative Quatro cell configuration 1108 is employed which is complementary to Quattro cell 1106. This design enables flip-flop 1100 to use only a single clock phase (CK) and to have only four clock transistors.

[0042] In master latch 1102, the data D or its complement, turns on either transistor M2 or transistor M14, the Sources of which are connected to the Drain of the P-type transistor Ml whose gate is connected, in turn, to the CK input. N-type transistors M7 or M10 are turned on depending on if the data is high or low and this facilitates the write operation in Quatro cell 1106. When CK = 0, and D = 0, transistors M4, M9, and M10 are turned on, causing the node X and X2 to discharge to ground. As a result, node X causes transistors M5 and M12 to turn on while node X2 causes transistors M6 and M13 to turn off. Hence, nodes XI and Xn stay at logic high, and nodes X and X2 stay at logic low. In this way, a logic low is written in master latch 1102. Slave latch 1104 accepts new data from master latch 1102 when CK = 1. Depending on nodes X2 or XI being high, N-type transistors M20 or M27 is turned on, and both of these transistors are connected to the drain of the N-type transistor M28 whose gate is connected to the CK.

[0043] Flip-flop 1100 employs a master-slave configuration, and both master and slave are complemented to each other with respect to the clock. Flip-flop 1100 is fully static, contention- free, and needs a total of 32 transistors, which makes it power and energy-efficient flip-flop.

[0044] Another novel SER very-low power, low-energy, and high-performance, master-slave flip-flop 1200 (“RHBD-DICE”) is shown in Figure 12. Flip-flop 1200 employs a DICE cell1206, consisting of transistors M6 through M13, in the master latch 1202 and a DICE cell 1208, consisting of transistors M20 through M27, in the slave latch 1204, as storage elements.

[0045] In master latch 1202, the data D turns on P-type transistor pair M2 and M3 while the data complement turns on P-type transistor pair M4 and M5. Sources of transistors M2 through M5 are connected to the drain of a P-type transistor M 1 whose gate is connected to the CK.

[0046] Depending on whether data D is a logic high or low, N-type transistor M15 or N-type transistor M16 is turned and facilitates the write operation into DICE cell 1206. When the CK = 0, and D = 0, transistors M6 and M10 are turned off while transistors M7 and Ml 1 are tuned on. Transistor Ml 6 is also tuned on which causes nodes X and X2 to be discharged to ground, and nodes XI and Xn are pulled to a logic high. In this way, a logic low is written into master latch 1202. Slave latch 1204 accepts new data from master latch 1202 when the CK = 1. Depending on X2 or XI being high, N-type transistor pairs M28 and M29 or M30 and M31 are turned on. Transistors M28 through M31 are connected to the Drain of the N-type transistor M32 whose gate is connected to the clock signal CK. As will now be apparent flip flop 1200 has a clock load of four clock transistors and requires a total of 36 transistors and is a static, and contention-free.

[0047] Another novel SER very-low power, low-energy, and high-performance, master-slave flip-flop 1300 (“RHBD-35T-Quatro”) is shown in Figure 13. Flip-flop 1300 employs a Quatro cell 1306, consisting of transistors M4 through Mi l, in the master latch 1302 and a Quatro cell 1308, consisting of transistors M18 through M25, in the slave latch 1304, as storage elements.

[0048] A prior art DET fully static TSPC (“FS-TSPC-DET”) flip-flop 1400 is shown in Figure 14. Negative latch 1402 is used to the sample the data when clock is low, and positive latch 1404 is used to sample the data when clock is high. A 2: 1 Multiplexer 1406 is used to send the 1402 sampled data at output, Q when clock is high, and 1404 sampled data when clock is low. Overall, flip-flop 1400 requires ten clock transistors, and a total of 36 transistors, again consuming relatively high levels of power and energy.

[0049] A novel DET very low-power, low-energy, and high-performance flip-flop 1500 (“9CTSPC-DET”) is shown in Figure 15. Flip-flop 1500 employs a negative latch 1502 which is used to sample the data when clock is low, a positive latch 1504 which is used to sample the datawhen clock is high, and a single-phase clock 2: 1 multiplexer 1506 to send the 1502 and 1504 data at output, Q on rising and falling clock edge, respectively. This design enables flip-flop 1500 to use only single clock phase (CK) and to have only nine clock transistors, and overall, 33 transistors.

[0050] Another novel DET very low-power flip-flop 1600 (“8CTSPC-DET”) is shown in Figure 16. Flip-flop 1600 employs a negative latch 1602 which is used to sample the data when clock is low, a positive latch 1604 which is used to sample the data when clock is high, and a singlephase clock 2: 1 multiplexer 1606 to send the 1602 and 1604 data at output, Q on rising and falling clock edge, respectively. This design enables flip-flop 1600 to use only single clock phase (CK) and to have only eight clock transistors, and overall, 34 transistors.

[0051] Total average power versus DA is shown in Figure 17 (for VDD = 1 V and CK= 1 GHz) and Figure 18 (for VDD = 0.6 V and CK= 50 MHz) comparing prior art flip-flops to the novel flip-flops disclosed herein. As can be seen, the novel 2C_19TSPC has a good power-efficiency around 45 % of DA, the 3C_20TSPC has good power-efficiency around 50 % of DA, and the novel 3C_21TSPC has good power-efficiency around 30 % of DA compared to the other state- of-the-art regular low-power True Single -phase Clocked (“TSPC”) flip-flops.

[0052] Total average power versus DA is shown in Figure 19 (for VDD = 1 V and CK= 1 GHz) and Figure 20 (for VDD = 0.5 V and CK= 50 MHz) for SER flip-flops. As can be seen, the novel RHBD-34T-Quatro, RHBD-35T-Quatro, and RHBD-DICE flip-flops are more power-efficient for all DAs compared to the prior art SER flip-flops.

[0053] The Power-delay-product (“PDP”) versus DA is shown in Figure 21 (for VDD = 1 V and CK= 1 GHz) and Figure 22 (for VDD = 0.5 V and CK= 50 MHz) for SER flip-flops at two different supply voltages and clock rates. As can be seen, the novel RHBD-34T-Quatro, RHBD- 35T-Quatro, and RHBD-DICE flip-flops are more energy-efficient for all DAs compared to the prior art SER flip-flops.

[0054] The D-to-Q delay is shown in Figure 23 (for VDD = 1 V and CK= 1 GHz) and Figure 24 (for VDD = 0.5 V and CK= 50 MHz) for SER flip-flops at two different supply voltages andclock rates. As can be seen, the novel RHBD-DICE, RHBD-34T-Quatro, and RHBD-35T- Quatro are the fastest amongst the tested SER flip-flops.

[0055] Critical charge (“Qc”) is shown in Figure 25 (for VDD = 1 V) for the novel and the prior art SER flip-flops. Typically, a critical charge of 21-24 fC is good for single node soft-error immunity. As can be seen in Figure, MS-Quatro has a critical charge of 36 fC. The novel RHBD- 34T-Quatro, RHBD-DICE, and RHBD-35T-Quatro flip-flops have a critical charge of 34 fC, 29 fC, and 28 fC respectively.

[0056] Total average power versus DA is shown in Figure 26 (for VDD = 1 V and CK= 1 GHz) for TSPC DET flip-flops. As can be seen, the novel 8CTSPC is more power-efficient for low DAs, and 9CTSPC is more power-efficient for low and high DAs compared to the prior art DET flip-flop.

[0057] The Power-delay-product (“PDP”) versus DA is shown in Figure 27 (for VDD = 1 V and CK= 1 GHz) for DET TSPC flip-flops. As can be seen, the novel 9CTSPC is more energyefficient for all DAs compared to the prior art DET flip-flop.

[0058] The D-to-Q delay is shown in Figure 28 (for VDD = 1 V and CK= 1 GHz) for DET TSPC flip-flops. As can be seen, the novel 9CTSPC is the fastest amongst the tested DET flipflops.

[0059] As will be apparent to those of skill in the art, while the examples and discussion above have generally employed CMOS circuits, the present invention is not so limited and the novel flip flops can be implemented in a variety of other transistor and logic technologies as may be desired.

[0060] Accordingly, it will be appreciated by a person of ordinary skill in the art that the present invention can provide very low-power and radiation hardened TSPC flip-flops and registers with reduced numbers of clock transistors resulting in reduced power and energy operating requirements and improved performance. Further, although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

WE CLAIM:

1. A single -phase clocked flip flop responsive to an input clock and input data to produce a corresponding output, the flip flop comprising: a master latch having a pre-charge node, a first logic gate responsive to the input clock and the input data to generate at least two outputs and a second logic gate responsive to the at least two outputs to apply a charge to the pre-charge node only when the clock input is a logic low and the data input is a logic high; and a slave latch responsive to the input clock and the pre-charge node to produce the corresponding output.

2. The flip flop according to claim 1 implemented in CMOS.

3. The flip-flop according to claim 1 where the pre-charge node is pre-charged by an N-type transistor.

4. The flip flop according to claim 1 which includes only two clock transistors.

5. The flip flop according to claim 1 which includes only three clock transisotrs.

6. A flip flop requiring only a single -phase clock and only two clock transistors.

7. The flip flop according to claim 6 comprising a master latch and a slave latch where the master latch consists of a first complex logic gate having at least two outputs and a second logic gate.

8. The flip flop according to claim 7 wherein the second logic gate is responsive to the at least two outputs to apply a charge to the pre-charge node only when the clock input is a logic low and the data input is a logic high.

9. A low power, hardened single-phase clocked flip flop responsive to an input clock and input data and comprising:a master latch with a first interlocked cell; and a slave latch with a second interlocked cell, the second interlocked cell being the complement of the first interlocked cell, and wherein the interlocked cells provide redundancy against radiation-induced errors.

10. The low power, hardened flip flop according to claim 9 wherein the interlocked cells are Quatro cells.

11. A dual edge triggered single -phase clocked flip-flop responsive to an input clock and input data, comprising: a negative latch to sample input data when the input clock is low; a positive latch to sample input data when the input clock is high; a single-phase clock 2: 1 multiplexer 1506 to produce an output corresponding to the respective output of the negative latch and the positive latch on the respective edge of the input clock.

12. The dual edge triggered, single-phase clocked flip flop of claim 11 which only includes nine clock transistors.

13. The dual edge triggered, single-phase clocked flip flop of claim 11 which only includes ten clock transistors.

Images