Memory and preparation method therefor, storage system, and electronic device

Abstract

The present application relates to the technical field of semiconductors and provides a memory and a preparation method therefor, a storage system, and an electronic device, used for saving the layout space of a peripheral circuit layer in a memory, reducing the size and load of storage blocks in the memory, and improving the read-write operation performance of the memory. The memory (100) comprises a first substrate (10), a storage array (20), a first interconnection layer (30), a second substrate (40), a peripheral circuit layer (50), a second interconnection layer (60), and a voltage conversion circuit (70). The first interconnection layer (30) is located on the side of the storage array (20) facing away from the first substrate (10). The second interconnection layer (60) is located on the side of the peripheral circuit layer (50) facing away from the second substrate (40). The first interconnection layer (30) and the second interconnection layer (60) are both prepared in a back-end-of-the-line process. The first interconnection layer (30) is bonded to the second interconnection layer (60). The voltage conversion circuit (70) comprises a passive device (71). The passive device (71) is provided on at least one of the side of the first substrate (10) facing away from the storage array (20), or the side of the second substrate (40) facing away from the peripheral circuit layer (50). The memory is applied to an electronic device so as to improve the performance of the electronic device.

Description

Memory and preparation method thereof, storage system, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] NAND flash memory chips have the advantages of low power consumption and high reliability compared to traditional hard disk drives (HDDs), and therefore have become the mainstream application medium in the field of data storage.

[0003] NAND flash memory chips primarily consist of a memory array and peripheral circuits. The peripheral circuits control the read and write operations of the memory cells within the memory array and provide power supply voltage for the memory array. Current NAND flash memory chips based on floating gate or charge trapping principles typically incorporate voltage conversion circuits to provide the various high-voltage power supplies required for memory array operations. For example, capacitor-based charge pumps may be integrated within the peripheral circuits, or inductor-based boost converters may be integrated off-chip or in advanced packaging.

[0004] In the future evolution of NAND flash memory chips, the number of stacked layers in the memory array will increase at a rate of approximately 30% per generation. To accommodate the mainstream high-density architectures of vertically arranged memory arrays and peripheral circuits (CMOS Under Array, CUA) and vertically bonded memory arrays and peripheral circuits (CMOS Bonding Array, CBA), the area of ​​the peripheral circuits in the NAND flash memory chip must be rationally designed. Furthermore, the number of sub-blocks or cell strings within a single memory block in a NAND flash memory chip is also increasing with each generation, leading to a continuous increase in the overall read and write load of the memory array.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a memory and a preparation method thereof, a storage system, and an electronic device for freeing up layout space of the peripheral circuit layer in the memory, reducing the size of the storage block in the memory, reducing the load of the read and write operations of the storage array, and improving the read and write operation performance of the memory.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, a memory is provided, which includes a first substrate, a memory array, a first interconnection layer, a second substrate, a peripheral circuit layer, a second interconnection layer, and a voltage conversion circuit.

[0009] The memory array and first interconnect layer are located on a first substrate, with the first interconnect layer located on a side of the memory array facing away from the first substrate. The peripheral circuit layer and second interconnect layer are located on a second substrate, with the second interconnect layer located on a side of the peripheral circuit layer facing away from the second substrate. Both the first and second interconnect layers are fabricated using a back-end process. The first interconnect layer is bonded to the second interconnect layer. The voltage conversion circuit includes passive components, which are located on at least one of the side of the first substrate facing away from the memory array or the side of the second substrate facing away from the peripheral circuit layer.

[0010] In the memory provided in the embodiment of the present application, the passive components are arranged at least one of the side of the first substrate facing away from the memory array or the side of the second substrate facing away from the peripheral circuit layer, thereby effectively utilizing the space on the side of the first substrate facing away from the memory array or the space on the side of the second substrate facing away from the peripheral circuit layer. Compared with the solution of integrating the voltage conversion circuit into the peripheral circuit layer in the related art, the embodiment of the present application does not need to reserve space for the passive components of the voltage conversion circuit in the peripheral circuit layer, freeing up the layout space of the peripheral circuit layer in the memory, so that more driving devices (for example, gate drivers) can be arranged in the peripheral circuit layer, which is conducive to reducing the size of the storage block in the memory, reducing the load of the read and write operations of the storage array, and improving the read and write operation performance of the memory.

[0011] In some embodiments, the voltage conversion circuit further includes an active device electrically connected to the passive device, wherein the active device is disposed in any one of the peripheral circuit layer, a side of the first substrate facing away from the memory array, and a side of the second substrate facing away from the peripheral circuit layer.

[0012] When the active devices are located in the peripheral circuit layer, the active devices can be manufactured together with the multiple transistors in the peripheral circuit layer. In this way, in the process of manufacturing the memory provided by the embodiments of the present application, no additional process steps are required to prepare the active devices, which helps to simplify the memory manufacturing process and improve the memory manufacturing efficiency.

[0013] When the active device is located on the side of the first substrate facing away from the memory array, or the active device is located on the side of the second substrate facing away from the peripheral circuit layer, a larger space can be reserved in the peripheral circuit layer of the memory provided in the embodiment of the present application, so that more driving devices can be set up in the peripheral circuit layer, which is conducive to further reducing the size of the storage block in the memory, reducing the load of the read and write operations of the storage array, and improving the read and write operation performance of the memory.

[0014] In some embodiments, the passive device is set at a side of the first substrate facing away from the memory array, the active device is set at a peripheral circuit layer, the memory further includes a first connection structure, the first connection structure runs through the first substrate and the memory array; the passive device and the active device are electrically connected through the first connection structure, the first interconnection layer and the second interconnection layer.

[0015] The active components of the voltage conversion circuit provided in the embodiments of the present application are disposed in a peripheral circuit layer, while the passive components are disposed on a side of the first substrate facing away from the memory array. The active and passive components are connected via a first connection structure, a first interconnect layer, and a second interconnect layer. Compared to related art solutions that integrate both the active and passive components of the voltage conversion circuit in the peripheral circuit layer, the embodiments of the present application do not require space in the peripheral circuit layer to accommodate the passive components of the voltage conversion circuit. This allows for the provision of more drive devices in the peripheral circuit layer to control the read and write operations of the memory array, thereby reducing the size of the memory blocks, reducing the memory load, and improving the read and write performance of the memory array within the memory.

[0016] In some embodiments, the passive device is set at a side of the second substrate away from the peripheral circuit layer, and the active device is set in the peripheral circuit layer. The memory also includes a second connection structure, which passes through the second substrate, and the passive device and the active device are electrically connected through the second connection structure.

[0017] The active components of the voltage conversion circuit provided in the embodiment of the present application are arranged in the peripheral circuit layer, while the passive components are arranged on the side of the first substrate facing away from the memory array, and the active components and the passive components are connected via a second connection structure. Compared with the solution in the related art that integrates both the active components and the passive components of the voltage conversion circuit in the peripheral circuit layer, the embodiment of the present application does not require reserved space in the peripheral circuit layer to accommodate the passive components of the voltage conversion circuit, so that more drive devices can be arranged in the peripheral circuit layer to control the read and write operations of the memory array, thereby reducing the size of the memory block, reducing the load of the memory, and improving the read and write performance of the memory array in the memory.

[0018] In some embodiments, the passive device includes a capacitor or an inductor. When the passive device of the voltage conversion circuit provided in the embodiment of the present application includes a capacitor, the design of the voltage conversion circuit can be relatively simple, and the area occupied by the voltage conversion circuit can be relatively small, which is conducive to simplifying the design of the memory and further reducing the size of the memory. When the passive device of the voltage conversion circuit is an inductor, the voltage conversion circuit can have a higher power conversion efficiency, which is conducive to improving the power supply efficiency and driving capability of the memory and reducing the operating power consumption of the memory.

[0019] In some embodiments, the passive device includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, and the active device includes a first diode, a second diode, a third diode, a fourth diode, and a fifth diode.

[0020] The input end of the first diode is connected to the voltage source, and the output end of the first diode is connected to the first electrode of the first capacitor. The input end of the second diode is connected to the first electrode of the first capacitor, and the output end of the second diode is connected to the first electrode of the second capacitor. The input end of the third diode is connected to the first electrode of the second capacitor, and the output end of the third diode is connected to the first electrode of the third capacitor. The input end of the fourth diode is connected to the first electrode of the third capacitor, and the output end of the fourth diode is connected to the first electrode of the fourth capacitor. The input end of the fifth diode is connected to the first electrode of the fourth capacitor, and the output end of the fifth diode is connected to the load.

[0021] Among them, the second pole of the first capacitor and the second pole of the third capacitor are both coupled to the first clock signal source, the second pole of the second capacitor and the second pole of the fourth capacitor are both coupled to the second clock signal source, and the signal output by the first clock signal source is inverted to the signal output by the second clock signal source.

[0022] When the passive components of the voltage conversion circuit provided in the embodiments of the present application include capacitors, the design of the voltage conversion circuit can be relatively simple, and the area occupied by the voltage conversion circuit can be relatively small, thereby simplifying the design of the memory and further reducing the size of the memory. Furthermore, when the passive components are disposed on the side of the first substrate facing away from the memory array, or on the side of the second substrate facing away from the peripheral circuit layer, the capacitor plates can be larger, thereby increasing the energy storage capacity of the capacitor and improving the performance of the voltage conversion circuit.

[0023] In some embodiments, the passive device includes an inductor, the input end of the inductor being connected to a voltage source, and the active device includes a switching transistor and a sixth diode. The switching transistor includes a first electrode, a second electrode, and a gate. The first electrode of the switching transistor is coupled to the output end of the inductor, the second electrode of the switching transistor is grounded, and the gate of the switching transistor is coupled to a third clock signal source. The input end of the sixth diode is coupled to the output end of the inductor, and the output end of the sixth diode is coupled to a load.

[0024] When the passive component of the voltage conversion circuit is an inductor, the voltage conversion circuit can have a higher power conversion efficiency, which is beneficial to improving the power supply efficiency and driving capability of the memory and reducing the operating power consumption of the memory.

[0025] In some embodiments, the passive device includes an inductor, and the inductor is a thin film inductor. In this case, the size of the passive device can be smaller, and the space occupied by the passive device can be smaller, which is conducive to further reducing the size of the memory.

[0026] In some embodiments, the memory further includes a buried power rail located in the peripheral circuit layer and coupled to the transistor in the peripheral circuit layer.

[0027] In an embodiment of the present application, an embedded power rail is provided in the memory. The embedded power rail is coupled to multiple transistors in the peripheral circuit layer to provide voltage signals to the multiple transistors. This eliminates the need to provide wiring in the second interconnect layer to provide voltage signals to the transistors. This effectively simplifies the layout design of the wiring in the second interconnect layer, frees up layout resources in the second interconnect layer, and makes it possible to further reduce the size of the memory.

[0028] In some embodiments, the passive device is disposed on a side of the first substrate facing away from the memory array, the memory further includes a third connection structure, a fourth connection structure, and a first pad, the third connection structure connects the embedded power rail and the second interconnection layer, the fourth connection structure runs through the memory array and the first substrate, the first pad is located on a side of the first substrate facing away from the memory array, and the first pad is electrically connected to the embedded power rail through the third connection structure, the fourth connection structure, the first interconnection layer, and the second interconnection layer.

[0029] In the memory provided in the embodiment of the present application, the first pad and the passive device are both located on the side of the first substrate facing away from the memory array. In this way, when preparing the first pad and the passive device, only the first substrate can be thinned, which is beneficial to simplifying the preparation process of the memory, improving the preparation efficiency of the memory, and reducing the preparation cost of the memory.

[0030] In some embodiments, the passive device is disposed on a side of the second substrate facing away from the peripheral circuit layer, the memory further includes a fifth connection structure and a second pad, the fifth connection structure passes through the second substrate and is in electrical contact with the embedded power rail, the second pad is located on a side of the second substrate facing away from the peripheral circuit layer, and the second pad is electrically connected to the embedded power rail through the fifth connection structure.

[0031] In the memory provided in the embodiments of the present application, the second pads and passive components are located on the side of the second substrate facing away from the peripheral circuit layer. Thus, when manufacturing the second pads and passive components, only the second substrate needs to be thinned, which simplifies the memory manufacturing process, improves memory manufacturing efficiency, and reduces memory manufacturing costs.

[0032] If the passive components are located on the side of the second substrate facing away from the peripheral circuit layer, the memory device may also include a backside power supply network. This backside power supply network can be located on the side of the second substrate facing away from the peripheral circuit layer. This backside power supply network, combined with the embedded power rail, can effectively shorten the power supply line and reduce resistance and capacitance delays along the power supply line, thereby reducing memory device power consumption.

[0033] In some embodiments, the storage array includes multiple layers of gate layers and multiple layers of dielectric layers stacked alternately, and the projection of the passive device on the first substrate at least partially overlaps with the projection of the gate layer on the first substrate; the peripheral circuit layer includes multiple transistors, and the projection of the passive device on the second substrate partially overlaps with the projection of the multiple transistors on the second substrate.

[0034] In this way, the additional area occupied by the passive devices is smaller, or no additional area is required, the total area of ​​the projections of the passive devices and the memory array on the first substrate is smaller, the total area occupied by the passive devices and the memory array is smaller, the total area of ​​the projections of the passive devices and the multiple transistors in the peripheral circuit layer on the second substrate is smaller, and the total area occupied by the passive devices and the multiple transistors in the peripheral circuit layer is smaller, which is conducive to further reducing the size of the memory.

[0035] In some embodiments, the memory further includes a passivation layer, wherein the passivation layer covers the passive device and can be used to protect the passive device.

[0036] In a second aspect, a method for preparing a memory is provided, the method comprising: forming a memory array on a first substrate; forming a first interconnection layer on a side of the memory array facing away from the first substrate; the first interconnection layer being prepared by a back-end process; forming a peripheral circuit layer on a second substrate; forming a second interconnection layer on a side of the peripheral circuit layer facing away from the second substrate; the second interconnection layer being prepared by a back-end process; bonding the first interconnection layer and the second interconnection layer; and forming passive devices of a voltage conversion circuit, wherein the passive devices are arranged at a position including at least one of a side of the first substrate facing away from the memory array or a side of the second substrate facing away from the peripheral circuit layer.

[0037] In some embodiments, the voltage conversion circuit also includes active devices, which are electrically connected to the passive devices; the preparation method also includes: forming active devices during the process of forming a peripheral circuit layer on the second substrate; or forming active devices on the side of the first substrate facing away from the storage array; or forming active devices on the side of the second substrate facing away from the peripheral circuit layer.

[0038] In some embodiments, the preparation method further includes: forming an embedded power rail during the process of forming a peripheral circuit layer on the second substrate; the embedded power rail is coupled to the transistor in the peripheral circuit layer. Forming a third connection structure, the embedded power rail is electrically connected to the second interconnect layer via the third connection structure. Thinning the first substrate. Forming a fourth connection structure that extends through the first substrate and the memory array; the fourth connection structure is electrically connected to the first interconnect layer. Forming a first solder pad on a side of the first substrate facing away from the memory array; the first solder pad is electrically connected to the embedded power rail via the third connection structure, the fourth connection structure, the first interconnect layer, and the second interconnect layer. After forming the first solder pad on the side of the first substrate facing away from the memory array, passive components of the voltage conversion circuit are formed on the side of the first substrate facing away from the memory array.

[0039] In some embodiments, the manufacturing method further includes: forming an embedded power rail during the process of forming the peripheral circuit layer on the second substrate; the embedded power rail is coupled to the transistor in the peripheral circuit layer. Thinning the second substrate. Forming a fifth connection structure extending through the second substrate, the fifth connection structure being electrically connected to the embedded power rail. Forming a second solder pad on a side of the second substrate facing away from the peripheral circuit layer, the second solder pad being electrically connected to the embedded power rail via the fifth connection structure. After forming the second solder pad on the side of the second substrate facing away from the peripheral circuit layer, passive components of the voltage conversion circuit are formed on the side of the second substrate facing away from the peripheral circuit layer.

[0040] In some embodiments, the preparation method further includes forming a passivation layer, wherein the passivation layer covers the passive device.

[0041] In a third aspect, a storage system is provided, which includes a controller and a memory as described in any of the above embodiments, wherein the controller is electrically connected to the memory.

[0042] In a fourth aspect, an electronic device is provided, which includes a circuit board and the storage system described in any one of the above embodiments, wherein the storage system is electrically connected to the circuit board.

[0043] Among them, the technical effects brought about by any design method in the second to fourth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0045] FIG1 is a schematic diagram of a three-dimensional structure of a memory provided in an embodiment of the present application;

[0046] FIG2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0047] FIG3 is a schematic diagram of the three-dimensional structure of another memory provided in an embodiment of the present application;

[0048] FIG4 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0049] FIG5 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0050] FIG6 is a schematic diagram of a three-dimensional structure of another memory provided in an embodiment of the present application;

[0051] FIG7 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0052] FIG8 is a schematic diagram of a three-dimensional structure of another memory provided in an embodiment of the present application;

[0053] FIG9 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0054] FIG10 is a schematic diagram of a circuit structure of a voltage conversion circuit provided in an embodiment of the present application;

[0055] FIG11 is a schematic diagram of the circuit structure of another voltage conversion circuit provided in an embodiment of the present application;

[0056] FIG12 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0057] FIG13 is a flow chart of a method for preparing a memory provided in an embodiment of the present application;

[0058] 14 to 19 are structural diagrams of memories corresponding to the steps in the flowchart shown in FIG13 ;

[0059] FIG20 is a flow chart of another method for preparing a memory provided in an embodiment of the present application;

[0060] FIG21 is a structural diagram of a memory corresponding to step S103 in the flowchart shown in FIG20 ;

[0061] FIG22 is a structural diagram of a memory corresponding to step S104 and step S105 in the flowchart shown in FIG20 ;

[0062] FIG23 is a flow chart of a method for preparing another memory provided in an embodiment of the present application;

[0063] FIG24 is a structural diagram of the memory corresponding to step S202 in the flowchart shown in FIG23 ;

[0064] FIG25 is a structural diagram of a memory corresponding to step S203 and step S204 in the flowchart shown in FIG23 ;

[0065] FIG26 is a flow chart of another method for preparing a memory provided in an embodiment of the present application;

[0066] FIG27 is a schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0067] FIG28 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0069] To facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish between identical or similar items having substantially the same functions and effects. Those skilled in the art will appreciate that terms such as "first" and "second" do not limit the quantity or order of execution, and that terms such as "first" and "second" do not necessarily imply differences.

[0070] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0071] Figure 1 is a schematic diagram of the three-dimensional structure of a memory 100 provided in an embodiment of the present application, Figure 2 is a schematic diagram of the cross-section of a memory 100 provided in an embodiment of the present application, Figure 3 is a schematic diagram of the three-dimensional structure of another memory 100 provided in an embodiment of the present application, and Figure 4 is a schematic diagram of the cross-section of another memory 100 provided in an embodiment of the present application. Figure 5 is a schematic diagram of the cross-section of yet another memory 100 provided in an embodiment of the present application.

[0072] As shown in Figures 1 and 2, an embodiment of the present application provides a memory 100, which includes a first substrate 10, a memory array 20, a first interconnection layer 30, a second substrate 40, a peripheral circuit layer 50, a second interconnection layer 60 and a voltage conversion circuit 70.

[0073] The memory array 20 and the first interconnect layer 30 are both located on the first substrate 10, with the first interconnect layer 30 located on the side of the memory array 20 facing away from the first substrate 10. The peripheral circuit layer 50 and the second interconnect layer 60 are both located on the second substrate 40, with the second interconnect layer 60 located on the side of the peripheral circuit layer 50 facing away from the second substrate 40. The first interconnect layer 30 is bonded to the second interconnect layer 60. The voltage conversion circuit 70 includes passive components 71.

[0074] The passive device 71 may be disposed on at least one of the side of the first substrate 10 facing away from the memory array 20 or the side of the second substrate 40 facing away from the peripheral circuit layer 50. That is, in the memory 100 provided in the embodiment of the present application, as shown in FIG1 and FIG2 , the passive device 71 may be disposed on the side of the first substrate 10 facing away from the memory array 20; as shown in FIG3 and FIG4 , the passive device 71 may also be disposed on the side of the second substrate 40 facing away from the peripheral circuit layer 50; and as shown in FIG5 , the passive device 71 may also be partially disposed on the side of the first substrate 10 facing away from the memory array 20 and partially disposed on the side of the second substrate 40 facing away from the peripheral circuit layer 50.

[0075] It can be understood that the above-mentioned “the passive device 71 can also be partially arranged on the side of the first substrate 10 away from the memory array 20, and partially arranged on the side of the second substrate 40 away from the peripheral circuit layer 50” includes the situation where different parts of the same passive device 71 are respectively arranged on the side of the first substrate 10 away from the memory array 20 and the side of the second substrate 40 away from the peripheral circuit layer 50, and also includes the situation where the voltage conversion circuit 70 includes multiple passive devices, some of the multiple passive devices are arranged on the side of the first substrate 10 away from the memory array 20, and another part of the multiple passive devices 71 are arranged on the side of the second substrate 40 away from the peripheral circuit layer 50.

[0076] In some examples, the first substrate 10 and the second substrate 40 can be made of the same material. For example, the first substrate 10 and the second substrate 40 can be made of silicon (Si). Of course, the materials of the first substrate 10 and the second substrate 40 are not limited to these. For example, the first substrate 10 and the second substrate 40 can both be silicon wafers.

[0077] In some examples, as shown in FIG2 , the memory array 20 may include multiple layers of gate layers 21 and multiple layers of dielectric layers 22 that are alternately stacked. In the embodiments of the present application, there is no limit on the number of gate layers 21 and dielectric layers 22, and they can be designed based on the storage requirements of the memory. It will be understood that FIG1 only uses four layers of gate layers as an example, and does not limit the structure of the memory array 20 in the embodiments of the present application. For example, the number of gate layers 21 in the memory array 20 may be 32 layers, 64 layers, 128 layers, 256 layers, or even more.

[0078] Continuing with FIG. 2 , the memory array 20 may further include a plurality of gate contacts 23, and the gate layer 21 may be electrically connected to at least one gate contact 23. For example, the gate contact 23 may extend from the surface of the memory array 20 in contact with the first interconnect layer 30 toward the gate layer 21, connecting to the corresponding gate layer 21. The end of the gate contact 23 facing away from the gate layer 21 is electrically connected to the first interconnect layer 30. The gate contact 23 is used to transmit control signals to the gate layer 21.

[0079] For example, the gate layer 21 and the gate contact 23 may be made of metal, such as tungsten, aluminum, copper, etc. The dielectric layer 22 may be made of insulating material, such as silicon oxide or silicon nitride.

[0080] 2 , the peripheral circuit layer 50 may include a plurality of transistors 51, and the plurality of transistors 51 may constitute a plurality of circuits in the peripheral circuit layer 50. Exemplarily, the plurality of transistors 51 in the peripheral circuit layer 50 may form an analog circuit, a logic circuit, a datapath, and a core circuit.

[0081] The analog circuits are primarily responsible for powering the circuits and arrays. The logic circuits are the components within the memory responsible for parsing instructions and generating control signals. The data path is responsible for transmitting and controlling data, addresses, instructions, and clock signals between the memory array and the interface. The data path also enables interaction between the logic circuits and other modules. The core circuits primarily include the page buffers and row / column decoders, which are responsible for reading, writing, and erasing the memory array.

[0082] As shown in FIG. 2 , FIG. 4 and FIG. 5 , the first interconnection layer 30 and the second interconnection layer 60 are bonded to form a bonding interface 301 .

[0083] In some examples, wafer bonding technology can be used to bond the first interconnect layer 30 to the second interconnect layer 60. Wafer bonding technology involves tightly bonding two mirror-polished homogeneous or heterogeneous wafers together through chemical or physical action. After the wafers are bonded, the atoms at the interface react under the action of external forces to form covalent bonds, thereby bonding the wafers together and achieving a specific bonding strength at the interface.

[0084] The Xtacking bonding process is a type of wafer bonding technology. For example, the Xtacking bonding process can be used to bond the first interconnect layer 30 to the second interconnect layer 60. The Xtacking bonding process refers to the alignment of the bonding structures between different devices in the same process step, thereby achieving electrical connection between the two devices. By using the Xtacking bonding process, it is beneficial to use a more advanced manufacturing process to manufacture the two devices separately, reduce the complexity of the manufacturing process, and enable the memory to have better I / O interface speed and more operating functions.

[0085] In the semiconductor manufacturing process, the preparation of each semiconductor device requires multiple steps, which are mainly divided into the front end of line (FEOL) and the back end of line (BEOL). Among them, the front end process is used to form multiple devices (for example, transistors) on the active side of the semiconductor material, and the back end process is used to form metal wire interconnections. Metal wire interconnections include multi-layer metal connections and metal vias. The number of metal connection layers is usually not fixed depending on actual needs.

[0086] In some examples, the memory array 20 can be fabricated on the first substrate 10 by a front-end process. The first interconnect layer 30 can be fabricated on the side of the memory array 20 facing away from the first substrate 10 by a back-end process. The peripheral circuit layer 50 can be fabricated on the second substrate 40 by a front-end process. The second interconnect layer 60 can also be fabricated by a back-end process, thereby being formed on the side of the peripheral circuit layer 50 facing away from the second substrate 40.

[0087] For example, the first interconnect layer 30 and the second interconnect layer 60 may include multiple conductive layers and an insulating layer separating two adjacent conductive layers. Each conductive layer may include a trace, and the traces in two adjacent conductive layers may be electrically connected via a connection portion penetrating the insulating layer.

[0088] In the memory 100 provided in the embodiment of the present application, the first interconnect layer 30 is electrically connected to the memory array 20, the second interconnect layer 60 is electrically connected to the peripheral circuit layer 50, and the first interconnect layer 30 and the second interconnect layer 60 are bonded together, thereby electrically connecting the memory array 20 and the peripheral circuit layer 50. The peripheral circuit layer 50 can be used to control the memory array 20 and the input and output of data. For example, the signal output by the peripheral circuit layer 50 can be transmitted to the memory array 20 through the second interconnect layer 60, the first interconnect layer 30, and the gate contact 23, thereby controlling the memory array 20.

[0089] In the memory 100 provided in the embodiment of the present application, the passive device 71 is disposed on at least one of the side of the first substrate 10 facing away from the memory array 20 or the side of the second substrate 40 facing away from the peripheral circuit layer 50, thereby effectively utilizing the space on the side of the first substrate 10 facing away from the memory array 20 or the space on the side of the second substrate 40 facing away from the peripheral circuit layer 50. Compared with the solution of integrating the voltage conversion circuit into the peripheral circuit layer in the related art, the embodiment of the present application does not need to reserve space in the peripheral circuit layer 50 for the passive device 71 of the voltage conversion circuit 70, freeing up the layout space of the peripheral circuit layer 50 in the memory 100, so that more driving devices (e.g., gate drivers) can be disposed in the peripheral circuit layer 50, thereby reducing the size of the memory blocks in the memory 100, reducing the load of the read and write operations of the memory array 20, and improving the read and write performance of the memory 100.

[0090] In some embodiments, referring to FIG. 2 , a projection of the passive device 71 on the first substrate 10 at least partially overlaps with a projection of the gate layer 21 on the first substrate 10 .

[0091] Among them, “the projection of the passive device 71 on the first substrate 10 at least partially overlaps with the projection of the gate layer 21 on the first substrate 10” includes both the situation where the projection of the passive device 71 on the first substrate 10 partially overlaps with the projection of the gate layer 21 on the first substrate 10, and the situation where the projection of the passive device 71 on the first substrate 10 completely overlaps with the projection of the gate layer 21 on the first substrate 10.

[0092] In this way, the passive device 71 occupies a smaller additional area, or does not need to occupy additional area, the total projection area of ​​the passive device 71 and the storage array 20 on the first substrate 10 is smaller, and the total area occupied by the passive device 71 and the storage array 20 is smaller, which is conducive to further reducing the size of the memory 100.

[0093] 4 , the projection of the passive device 71 on the second substrate 40 partially overlaps with the projections of the plurality of transistors 51 in the peripheral circuit layer 50 on the second substrate 40. Thus, the passive device 71 occupies little additional area, or no additional area is required. The total area of ​​the projections of the passive device 71 and the plurality of transistors 51 in the peripheral circuit layer 50 on the second substrate 40 is small, and the total area occupied by the passive device 71 and the plurality of transistors 51 in the peripheral circuit layer 50 is small, thereby facilitating a reduction in the size of the memory 100.

[0094] Figure 6 is a schematic diagram of the three-dimensional structure of another memory 100 provided in an embodiment of the present application, Figure 7 is a schematic diagram of the cross-section of another memory 100 provided in an embodiment of the present application, Figure 8 is a schematic diagram of the three-dimensional structure of another memory 100 provided in an embodiment of the present application, and Figure 9 is a schematic diagram of the cross-section of another memory 100 provided in an embodiment of the present application.

[0095] 1 , 3 , 7 , and 9 , in addition to the passive components 71, the voltage conversion circuit 70 may further include active components 72. The active components 72 are electrically connected to the passive components 71. In the embodiment of the present application, there is no limit on the number of active components 72, and the number can be designed based on actual conditions.

[0096] The multiple active devices 72 in the voltage conversion circuit 70 can form a switch network, and store the electrical energy input by the voltage source in passive devices (eg, capacitors, inductors) through high-frequency switching actions.

[0097] The active device 72 may be located in any of the following locations: in the peripheral circuit layer 50, on the side of the first substrate 10 facing away from the memory array 20, or on the side of the second substrate 40 facing away from the peripheral circuit layer 50. That is, in the memory 100 provided in the embodiments of the present application, as shown in Figures 7 and 9 , the active device 72 may be located in the peripheral circuit layer 50. As shown in Figure 1 , the active device 72 may also be located on the side of the first substrate 10 facing away from the memory array 20. As shown in Figures 3 and 4 , the active device 72 may also be located on the side of the second substrate 40 facing away from the peripheral circuit layer 50.

[0098] When the active device 72 is located in the peripheral circuit layer 50, the active device 72 can be manufactured together with the plurality of transistors 51 in the peripheral circuit layer 50. For example, both the active device 72 and the peripheral circuit layer 50 can be manufactured using a front-end process. In this way, during the manufacture of the memory 100 provided in the embodiment of the present application, no additional process steps are required to manufacture the active device 72, thereby simplifying the manufacturing process of the memory 100 and improving the manufacturing efficiency of the memory 100.

[0099] When the active device 72 is located on the side of the first substrate 10 facing away from the memory array 20, or the active device 72 is located on the side of the second substrate 40 facing away from the peripheral circuit layer 50, a larger space can be reserved in the peripheral circuit layer 50 of the memory 100 provided in the embodiment of the present application, so that more driving devices can be set in the peripheral circuit layer 50, which is conducive to further reducing the size of the storage block in the memory 100, reducing the load of the read and write operations of the storage array, and improving the read and write operation performance of the memory 100.

[0100] In some examples, as shown in Figures 6 and 7 , the passive device 71 is disposed on a side of the first substrate 10 facing away from the memory array 20, and the active device 72 is disposed in the peripheral circuit layer 50. That is, the passive device 71 is located on a side of the first substrate 10 facing away from the memory array 20, and the active device 72 is located in the peripheral circuit layer 50.

[0101] At this time, the memory 100 may further include a first connection structure 11 that penetrates the first substrate 10 and the memory array 20 . The passive device 71 and the active device 72 are electrically connected through the first connection structure 11 , the first interconnection layer 30 , and the second interconnection layer 60 .

[0102] The active devices 72 of the voltage conversion circuit 70 provided in the embodiment of the present application are disposed in the peripheral circuit layer 50, and the passive devices 71 are disposed on the side of the first substrate 10 facing away from the memory array 20. The active devices 72 and the passive devices 71 are connected via the first connection structure 11, the first interconnect layer 30, and the second interconnect layer 60. Compared to the related art solution in which both the active and passive devices of the voltage conversion circuit are integrated into the peripheral circuit layer, the embodiment of the present application does not require space to accommodate the passive devices 71 of the voltage conversion circuit 70 in the peripheral circuit layer 50. This allows for more drive devices to be provided in the peripheral circuit layer 50 to control the read and write operations of the memory array, thereby reducing the size of the memory blocks in the memory, reducing the memory load, and improving the read and write performance of the memory array in the memory 100.

[0103] In other examples, as shown in Figures 8 and 9, the passive device 71 is disposed on a side of the second substrate 40 facing away from the peripheral circuit layer 50, and the active device 72 is disposed within the peripheral circuit layer 50. That is, the passive device 71 is located on a side of the second substrate 40 facing away from the peripheral circuit layer 50, and the active device 72 is located within the peripheral circuit layer 50.

[0104] At this time, the memory 100 further includes a second connection structure 12 . The second connection structure 12 passes through the second substrate 40 . The passive device 71 and the active device 72 are electrically connected via the second connection structure 12 .

[0105] The active devices 72 of the voltage conversion circuit 70 provided in the embodiment of the present application are disposed in the peripheral circuit layer 50, while the passive devices 71 are disposed on the side of the first substrate 10 facing away from the memory array 20. The active devices 72 and the passive devices 71 are connected via a second connection structure 12. Compared to the solution in the related art in which both the active and passive devices of the voltage conversion circuit are integrated in the peripheral circuit layer, the embodiment of the present application does not require reserved space in the peripheral circuit layer 50 to accommodate the passive devices 71 of the voltage conversion circuit 70. This allows for more drive devices to be disposed in the peripheral circuit layer 50 to control the read and write operations of the memory array, thereby reducing the size of the memory blocks in the memory, reducing the memory load, and improving the read and write performance of the memory array in the memory 100.

[0106] 1 , the passive device 71 and the active device 72 may both be located on the side of the first substrate 10 facing away from the memory array 20. That is, the passive device 71 and the active device 72 may both be located on the side of the first substrate 10 facing away from the memory array 20.

[0107] 3 and 4 , the passive device 71 and the active device 72 may both be located on the side of the second substrate 40 facing away from the peripheral circuit layer 50. In other words, the passive device 71 and the active device 72 may both be located on the side of the second substrate 40 facing away from the peripheral circuit layer 50.

[0108] When the passive devices 71 and the active devices 72 are both located on the side of the first substrate 10 away from the storage array 20, or when the passive devices 71 and the active devices 72 are both located on the side of the second substrate 40 away from the peripheral circuit layer 50, the distribution positions of the passive devices 71 and the active devices 72 are not restricted in the embodiment of the present application and can be designed according to actual conditions.

[0109] The passive devices 71 and active devices 72 in the embodiment of the present application are both located on the side of the first substrate 10 away from the storage array 20, or are both located on the side of the second substrate 40 away from the peripheral circuit layer 50. Compared with the solution in the related art in which the active devices and passive devices of the voltage conversion circuit are integrated in the peripheral circuit layer, the peripheral circuit layer 50 provided by the embodiment of the present application does not require reserved space for accommodating the passive devices 71 and active devices 72 of the voltage conversion circuit 70, so that more driving devices can be set in the peripheral circuit layer 50 to control the read and write operations of the storage array, which is conducive to further reducing the size of the storage array, reducing the load of the memory, and improving the read and write operation performance of the storage array in the memory 100.

[0110] In some embodiments, the passive device 71 may include a capacitor. In this case, the voltage conversion circuit 70 may be a capacitor-based charge pump.

[0111] When the passive device 71 of the voltage conversion circuit 70 provided in the embodiment of the present application includes a capacitor, the design scheme of the voltage conversion circuit 70 can be relatively simple, and the occupied area of ​​the voltage conversion circuit 70 can be smaller, which is conducive to simplifying the design scheme of the memory 100 and further reducing the size of the memory 100.

[0112] In other embodiments, the passive device 71 may include an inductor. In this case, the voltage conversion circuit 70 may be an inductor-based boost converter.

[0113] When the passive device 71 of the voltage conversion circuit 70 provided in the embodiment of the present application includes an inductor, the voltage conversion circuit 70 can have a higher power conversion efficiency (80% to 90%), which is beneficial to improving the power supply efficiency and driving capability of the memory 100 and reducing the operating power consumption of the memory 100.

[0114] FIG10 provides a schematic diagram of the circuit structure of the voltage conversion circuit 70. FIG10 illustrates an example in which the passive component 71 in the voltage conversion circuit 70 includes a capacitor. The circuit structure of the voltage conversion circuit 70 provided in the embodiment of the present application is described below with reference to FIG10.

[0115] As shown in FIG10 , the passive device 71 in the voltage conversion circuit 70 may include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, and the active device 72 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a fifth diode D5.

[0116] The input end of the first diode D1 is connected to the voltage source VDD, and the output end of the first diode D1 is connected to the first electrode of the first capacitor C1. The input end of the second diode D2 is connected to the first electrode of the first capacitor C1, and the output end of the second diode D2 is connected to the first electrode of the second capacitor C2. The input end of the third diode D3 is connected to the first electrode of the second capacitor C2, and the output end of the third diode D3 is connected to the first electrode of the third capacitor C3. The input end of the fourth diode D4 is connected to the first electrode of the third capacitor C3, and the output end of the fourth diode D4 is connected to the first electrode of the fourth capacitor C4. The input end of the fifth diode D5 is connected to the first electrode of the fourth capacitor C4, and the output end of the fifth diode D5 is connected to the load Vout.

[0117] The second electrode of the first capacitor C1 and the second electrode of the third capacitor C3 are both coupled to the first clock signal source CLK1, the second electrode of the second capacitor C2 and the second electrode of the fourth capacitor C4 are coupled to the second clock signal source CLK2, and the signal output by the first clock signal source CLK1 is inverted to the signal output by the second clock signal source CLK2.

[0118] The voltage source VDD is used to provide an input voltage supply. The first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 serve as energy storage devices. The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, and the fifth diode D5 can be used to prevent voltage backflow. The first clock signal source CLK1 and the second clock signal source CLK2 can be controlled by a pulse width modulation (PWM) circuit.

[0119] In the above circuit structure, the first capacitor C1 and the third capacitor C3 can store electrical energy when the first clock signal source CLK1 outputs a low-level voltage, and increase the voltage value of their first terminals when the first clock signal source CLK1 outputs a high-level voltage. Similarly, the second capacitor C2 and the fourth capacitor C4 can store electrical energy when the second clock signal source CLK2 outputs a low-level voltage, and increase the voltage value of their first terminals when the second clock signal source CLK2 outputs a high-level voltage. Thus, under the control of the signals output by the first clock signal source CLK1 and the second clock signal source CLK2, the voltage at the output terminal of the fifth diode D5 (i.e., the voltage provided to the load Vout) can be higher than the input power supply voltage provided by the voltage source VDD.

[0120] As shown in FIG10 , when the passive device 71 of the voltage conversion circuit 70 provided in the embodiment of the present application includes a capacitor, the design of the voltage conversion circuit 70 can be relatively simple, and the area occupied by the voltage conversion circuit 70 can be relatively small, thereby simplifying the design of the memory 100 and further reducing the size of the memory 100. Furthermore, when the passive device 71 is disposed on the side of the first substrate 10 facing away from the memory array 20, or when the passive device 71 is disposed on the side of the second substrate 40 facing away from the peripheral circuit layer 50, the size of the capacitor plate can be larger, thereby increasing the energy storage capacity of the capacitor and improving the performance of the voltage conversion circuit 70.

[0121] It can be understood that when the passive device 71 includes a capacitor (or when the voltage conversion circuit is a capacitor-based charge pump), the circuit structure of the voltage conversion circuit 70 provided in the embodiment of the present application is not limited to the circuit structure shown in Figure 10.

[0122] FIG11 provides a schematic diagram of the circuit structure of another voltage conversion circuit 70. FIG11 illustrates an example in which the passive components in the voltage conversion circuit 70 include capacitors. The circuit structure of another voltage conversion circuit 70 provided in an embodiment of the present application is described below with reference to FIG11.

[0123] As shown in FIG11 , the passive device 71 includes an inductor L, the input end of which is connected to a voltage source VDD. The active device 72 includes a switching transistor T and a sixth diode D6. The switching transistor T includes a first electrode, a second electrode, and a gate. The first electrode of the switching transistor T is coupled to the output end of the inductor L, the second electrode of the switching transistor T is grounded, and the gate of the switching transistor T is coupled to a third clock signal source CLK3. The input end of the sixth diode D6 is coupled to the output end of the inductor L, and the output end of the sixth diode D6 is coupled to a load Vout.

[0124] The switch transistor T may be a triode or a metal oxide semiconductor (MOS) transistor.

[0125] The voltage source VDD is used to provide the input power supply voltage, the inductor L is used as an energy storage element, the sixth diode D6 is used to prevent voltage backflow, the switching transistor T is used to control the on and off of the circuit, and the third clock signal source CLK is composed of a pulse width modulation circuit to control the on and off of the switching transistor.

[0126] Based on this, at a certain moment, after the switching transistor T is closed, the inductor L converts electrical energy into magnetic field energy and stores it. When the switching transistor T is disconnected, the inductor L converts the stored magnetic field energy into electric field energy, and the converted electric field energy is superimposed on the input power supply voltage and provided to the load Vout through the sixth diode D6.

[0127] As shown in Figure 11, when the passive device 71 of the voltage conversion circuit 70 provided in the embodiment of the present application includes an inductor, the voltage conversion circuit 70 can have a higher power conversion efficiency, which is beneficial to improving the power supply efficiency and driving capability of the memory 100 and reducing the operating power consumption of the memory 100.

[0128] In the memory 100 provided in the embodiment of the present application, the passive components 71 of the voltage conversion circuit 70 are located on at least one of the side of the first substrate 10 facing away from the memory array 20 or the side of the second substrate 40 facing away from the peripheral circuit layer 50. In other words, the inductor is located on at least one of the side of the first substrate 10 facing away from the memory array 20 or the side of the second substrate 40 facing away from the peripheral circuit layer 50. This prevents the inductor from occupying space in the peripheral circuit layer, leaving more space in the peripheral circuit layer for driver devices. This helps reduce the size of the memory blocks in the memory, reduces the load of the memory's read and write operations, and improves the memory's read and write performance.

[0129] It can be understood that when the passive device 71 includes an inductor (or when the voltage conversion circuit is an inductor-based boost converter), the circuit structure of the voltage conversion circuit 70 provided in the embodiment of the present application is not limited to the circuit structure shown in Figure 11.

[0130] In some embodiments, the passive device 71 includes an inductor, which may be a thin film inductor. In this case, the size of the passive device 71 can be smaller, and the space occupied by the passive device 71 can be smaller, thereby further reducing the size of the memory 100.

[0131] In some examples, the material of the inductor may include a ferromagnetic material. For example, the material of the inductor may include iron, cobalt, nickel, and alloys thereof.

[0132] In some examples, the inductor may be a wound inductor, a stacked coil inductor, or a spiral inductor. FIG1 , FIG3 , FIG6 , and FIG8 all illustrate the inductor as a spiral inductor.

[0133] 4 and 5 , in some embodiments, the memory 100 further includes an embedded power rail 80, which is located in the peripheral circuit layer 50 and coupled to the transistors 51 in the peripheral circuit layer 50. The embedded power rail 80 can be used to provide voltage signals to the plurality of transistors 51 in the peripheral circuit layer 50.

[0134] In some examples, the embedded power rail 80 may be fabricated by a front-end process.

[0135] In some examples, in a direction perpendicular to the second substrate 40 , the buried power rail 80 is closer to the second substrate 40 than the transistor 51 in the peripheral circuit layer 50 .

[0136] For example, the material of the embedded power rail 80 may include metal, such as copper.

[0137] In the embodiment of the present application, an embedded power rail 80 is provided in the memory 100. The embedded power rail 80 is coupled to the multiple transistors 51 in the peripheral circuit layer 50 to provide voltage signals to the multiple transistors 51. As a result, there is no need to provide wiring in the second interconnect layer 60 to provide voltage signals to the transistors. This effectively simplifies the layout design of the wiring in the second interconnect layer 60, frees up layout resources in the second interconnect layer 60, and makes it possible to further reduce the size of the memory 100.

[0138] In some examples, as shown in FIG12 , the passive device 71 is disposed on a side of the first substrate 10 facing away from the memory array 20. That is, the passive device 71 is located on the side of the first substrate 10 facing away from the memory array 20. The memory 100 further includes a third connection structure 13, a fourth connection structure 14, and a first pad M1. The third connection structure 13 connects the embedded power rail 80 to the second interconnect layer 60. The fourth connection structure 14 extends through the memory array 20 and the first substrate 10. The first pad M1 is located on the side of the first substrate 10 facing away from the memory array 20. The first pad M1 is electrically connected to the embedded power rail 80 via the third connection structure 13, the fourth connection structure 14, the first interconnect layer 30, and the second interconnect layer 60.

[0139] The third connection structure 13 and the fourth connection structure 14 may be made of the same material. For example, the third connection structure 13 and the fourth connection structure 14 may be made of metal.

[0140] Exemplarily, the material of the first pad M1 may also include metal.

[0141] In the embodiment of the present application, there is no limitation on the number, distribution position and size of the third connection structure 13 , the fourth connection structure 14 and the first pad M1 , and they can be designed according to actual needs.

[0142] In the memory 100 provided in the embodiment of the present application, the first solder pad M1 and the passive device 71 are both located on the side of the first substrate 10 facing away from the memory array 20. In this way, when preparing the first solder pad M1 and the passive device 71, only the first substrate 10 can be thinned, which is beneficial to simplify the preparation process of the memory 100, improve the preparation efficiency of the memory 100, and reduce the preparation cost of the memory 100.

[0143] In other examples, as shown in FIG4 , the passive device 71 is disposed on a side of the second substrate 40 facing away from the peripheral circuit layer 50. That is, the passive device 71 is located on a side of the second substrate 40 facing away from the peripheral circuit layer 50. The memory 100 further includes a fifth connection structure 15 and a second pad M2. The fifth connection structure 15 penetrates the second substrate 40 and is in electrical contact with the embedded power rail 80. The second pad M2 is located on a side of the second substrate 40 facing away from the peripheral circuit layer 50 and is electrically connected to the embedded power rail 80 via the fifth connection structure 15.

[0144] For example, the material of the fifth connection structure 15 may include metal, and the material of the second pad M2 may also include metal.

[0145] In the embodiment of the present application, there is no limitation on the number, distribution position and size of the fifth connection structure 15 and the second pad M2, and they can be designed according to actual needs.

[0146] In the memory device 100 provided in the embodiment of the present application, the second pads M2 and the passive device 71 are both located on the side of the second substrate 40 facing away from the peripheral circuit layer 50. Thus, when manufacturing the second pads M2 and the passive device 71, only the second substrate 40 needs to be thinned, thereby simplifying the manufacturing process of the memory device 100, improving the manufacturing efficiency of the memory device 100, and reducing the manufacturing cost of the memory device 100.

[0147] When the passive device 71 is located on the side of the second substrate 40 facing away from the peripheral circuit layer 50, the memory may further include a backside power delivery network (BSPDN). The backside power delivery network may be located on the side of the second substrate 40 facing away from the peripheral circuit layer 50. The backside power delivery network, in conjunction with the embedded power rail, can effectively shorten the power supply line and reduce the resistance and capacitance delays on the power supply line, thereby helping to reduce the power consumption of the memory.

[0148] It can be understood that, referring to Figure 2, in the embodiment of the present application, in addition to including the first pad M1 or the second pad M2 electrically connected to the embedded power rail 80, the memory 100 may also include a third pad M3 for providing a control signal to the peripheral circuit layer 50, and a sixth connection structure 16 connecting the third pad M3 and the peripheral circuit layer 50.

[0149] In order to simplify the preparation process of the memory 100 and improve the preparation efficiency of the memory 100, the third pad M3 can be formed using the same process steps as the first pad M1 or the second pad M2 in the above embodiment, and the sixth connection structure 16 can be formed using the same process steps as the fourth connection structure 14 or the fifth connection structure 15.

[0150] 2 , 4 and 5 , the memory 100 may further include a passivation layer 90 , which covers the passive components 71 of the voltage conversion circuit 70 . The passivation layer 90 may be used to protect the passive components 71 .

[0151] For example, the material of the passivation layer 90 may include insulating materials such as silicon oxide or nitride.

[0152] It is understood that, when the passive device 71 is located on the side of the first substrate 10 facing away from the memory array 20, the passivation layer 90 can also be located on the side of the first substrate 10 facing away from the memory array 20. When the passive device 71 is located on the side of the second substrate 40 facing away from the peripheral circuit layer 50, the passivation layer 90 can also be located on the side of the second substrate 40 facing away from the peripheral circuit layer 50.

[0153] In some examples, referring to FIG. 2 , FIG. 4 , and FIG. 12 , the passivation layer 90 may include a plurality of openings 91 , and the plurality of openings 91 may expose the first pad M1 , the second pad M2 , and the third pad M3 .

[0154] An embodiment of the present application provides a method for manufacturing a memory 100 , as shown in FIG13 . The method includes steps S100 to S600 .

[0155] S100 , as shown in FIG. 14 , a memory array 20 is formed on a first substrate 10 .

[0156] The first substrate 10 may be a silicon wafer.

[0157] For example, the memory array 20 may be formed on the first substrate 10 by using a front-end process.

[0158] In some examples, as shown in FIG. 14 , the memory array 20 may include multiple gate layers 21 and multiple dielectric layers 22 that are alternately stacked, and a plurality of gate contacts 23 .

[0159] For example, the gate layer 21 can be formed by a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process. The dielectric layer 22 can be formed by a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a high-density plasma chemical vapor deposition process, an atomic layer deposition process, or a sputtering process.

[0160] S200, as shown in FIG15, a first interconnection layer 30 is formed on a side of the memory array 20 facing away from the first substrate 10. The first interconnection layer 30 is prepared by a back-end process.

[0161] S300, as shown in FIG16, forming a peripheral circuit layer 50 on the second substrate 40. The second substrate 40 may be a silicon wafer.

[0162] For example, the peripheral circuit layer 50 may be formed on the second substrate 40 by using a front-end process.

[0163] S400, as shown in Figure 17, a second interconnection layer 60 is formed on the side of the peripheral circuit layer 50 facing away from the second substrate 40. The second interconnection layer 60 is prepared by a back-end process.

[0164] S500 , as shown in FIG18 , bonding the first interconnection layer 30 and the second interconnection layer 60 .

[0165] S600, referring to FIG. 2 , FIG. 4 and FIG. 5 , a passive device 71 of the voltage conversion circuit 70 is formed, and the passive device 71 is disposed at at least one of the side of the first substrate 10 facing away from the memory array 20 or the side of the second substrate 40 facing away from the peripheral circuit layer 50 .

[0166] As shown in FIG2 , the “passive component 71 forming the voltage conversion circuit 70” may be a passive component 71 forming the voltage conversion circuit 70 on the side of the first substrate 10 facing away from the memory array 20. Alternatively, as shown in FIG4 , the “passive component 71 forming the voltage conversion circuit 70” may be a passive component 71 forming the voltage conversion circuit 70 on the side of the second substrate 40 facing away from the peripheral circuit layer 50. Alternatively, the “passive component 71 forming the voltage conversion circuit 70” may be a passive component 71 forming the voltage conversion circuit 70 on both the side of the first substrate 10 facing away from the memory array 20 and the side of the second substrate 40 facing away from the peripheral circuit layer 50.

[0167] For example, the passive device 71 of the voltage conversion circuit 70 may be formed by using a deposition process and an etching process.

[0168] In the memory fabricated using the fabrication method provided in the embodiments of the present application, the passive components 71 in the voltage conversion circuit 70 are disposed on the side of the first substrate 10 facing away from the memory array 20, or on the side of the second substrate 40 facing away from the peripheral circuit layer 50, effectively utilizing the space on the side of the first substrate 10 facing away from the memory array 20 or the space on the side of the second substrate 40 facing away from the peripheral circuit layer 50. Compared to the related art solution of integrating the voltage conversion circuit into the peripheral circuit layer, the embodiments of the present application do not require space to be reserved in the peripheral circuit layer 50 for the passive components 71 of the voltage conversion circuit 70, allowing for more drive devices to be disposed in the peripheral circuit layer 50. This facilitates reducing the size of the memory blocks in the memory 100, reducing the load of read and write operations on the memory array 20, and improving the read and write performance of the memory 100.

[0169] It can be understood that the voltage conversion circuit 70 provided in the embodiment of the present application further includes an active device 72 .

[0170] At this time, referring to FIG. 19 , in some examples, the preparation method further includes: forming an active device 72 during the process of forming the peripheral circuit layer 50 on the second substrate 40 .

[0171] The active device 72 and the peripheral circuit layer 50 can both be fabricated using a front-end process. During the fabrication of the memory 100 , no additional process steps are required to fabricate the active device 72 , which simplifies the fabrication process of the memory 100 and improves the fabrication efficiency of the memory 100 .

[0172] 1 , in some other examples, the preparation method further includes: forming an active device 72 on a side of the first substrate 10 facing away from the memory array 20 .

[0173] When both the passive components 71 and the active components 72 are located on the side of the first substrate 10 facing away from the memory array 20, the present embodiment does not restrict the order in which the passive components 71 and the active components 72 are formed. That is, in the present embodiment, the passive components 71 of the voltage conversion circuit 70 can be formed first on the side of the first substrate 10 facing away from the memory array 20, and then the active components 72 of the voltage conversion circuit 70 can be formed on the side of the first substrate 10 facing away from the memory array 20. Alternatively, the active components 72 of the voltage conversion circuit 70 can be formed first on the side of the first substrate 10 facing away from the memory array 20, and then the passive components 71 of the voltage conversion circuit 70 can be formed on the side of the first substrate 10 facing away from the memory array 20.

[0174] In the embodiment of the present application, the active device 72 is formed on the side of the first substrate 10 away from the memory array 20, so that a larger space can be reserved in the peripheral circuit layer 50, and more driving devices can be set in the peripheral circuit layer 50, which is conducive to further reducing the size of multiple storage blocks in the memory 100, reducing the load of the storage array read and write operations, and improving the read and write operation performance of the memory 100.

[0175] 3 and 4 , in some other examples, the preparation method further includes: forming an active device 72 on a side of the second substrate 40 facing away from the peripheral circuit layer 50 .

[0176] When the passive devices 71 and the active devices 72 are both located on the side of the second substrate 40 away from the peripheral circuit layer 50 , the embodiment of the present application does not limit the order of forming the passive devices 71 and the active devices 72 .

[0177] In the embodiment of the present application, the active device 72 is formed on the side of the second substrate 40 away from the peripheral circuit layer 50, which can also reserve a larger space in the peripheral circuit layer 50, so that more driving devices can be set up in the peripheral circuit layer 50, thereby further reducing the size of the storage block in the memory 100, reducing the load of the read and write operations of the storage array 20, and improving the read and write operation performance of the memory 100.

[0178] As shown in FIG. 20 , in some embodiments, the preparation method further includes steps S101 to S105 .

[0179] S101 , referring to FIG16 , during the process of forming the peripheral circuit layer 50 on the second substrate 40 , an embedded power rail 80 is formed. The embedded power rail 80 is coupled to the transistor 51 in the peripheral circuit layer 50 .

[0180] S102 , referring to FIG. 12 , a third connection structure 13 is formed, and the embedded power rail 80 is electrically connected to the second interconnection layer 60 via the third connection structure 13 .

[0181] S103 , as shown in FIG21 , thinning the first substrate 10 .

[0182] S104 , referring to FIG22 , forming a fourth connection structure 14 penetrating the first substrate 10 and the memory array 20 . The fourth connection structure 14 is electrically connected to the first interconnection layer 30 .

[0183] S105 , referring to FIG. 22 , a first pad M1 is formed on the side of the first substrate 10 away from the memory array 20 , and the first pad M1 is electrically connected to the embedded power rail 80 through the third connection structure 13 , the fourth connection structure 14 , the first interconnection layer 30 and the second interconnection layer 60 .

[0184] 12 , after forming the first pad M1 on the side of the first substrate 10 away from the memory array 20 , the passive components 71 of the voltage conversion circuit 70 are formed on the side of the first substrate 10 away from the memory array 20 .

[0185] In other embodiments, as shown in FIG. 23 , the preparation method may further include steps S201 to S204 .

[0186] S201 , referring to FIG16 , during the process of forming the peripheral circuit layer 50 on the second substrate 40 , an embedded power rail 80 is formed. The embedded power rail 80 is coupled to the transistor 51 in the peripheral circuit layer 50 .

[0187] S202 , as shown in FIG. 24 , thinning the second substrate 40 .

[0188] S203 , referring to FIG. 25 , a fifth connection structure 15 penetrating the second substrate 40 is formed, and the fifth connection structure 15 is electrically connected to the embedded power rail 80 .

[0189] S204 , referring to FIG. 25 , a second pad M2 is formed on a side of the second substrate 40 away from the peripheral circuit layer 50 . The second pad M2 is electrically connected to the embedded power rail 80 through the fifth connection structure 15 .

[0190] 4 , after forming the second pad M2 on the side of the second substrate 40 away from the peripheral circuit layer 50 , the passive component 71 of the voltage conversion circuit 70 is formed on the side of the second substrate 40 away from the peripheral circuit layer 50 .

[0191] In some embodiments, as shown in FIG26 , the preparation method further comprises:

[0192] S700 , referring to FIG. 2 , FIG. 4 and FIG. 5 , a passivation layer 90 is formed, and the passivation layer 90 covers the passive device 71 .

[0193] As shown in FIG. 27 , an embodiment of the present application provides a storage system 200 , which includes a controller 210 and the memory 100 described in any of the above embodiments, and the controller 210 is electrically connected to the memory 100 .

[0194] In some examples, the controller 210 can be configured to manage data stored in the memory 100 and communicate with an external device (e.g., a circuit board). In other examples, the controller 210 can also be configured to control operations of the memory 100, such as read, erase, and program operations. In yet other examples, the controller 210 can also be configured to manage various functions regarding data stored or to be stored in the memory 100, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In yet other examples, the controller 210 can also be configured to process error correction codes for data read from or written to the memory 100.

[0195] Of course, the controller 210 may also perform any other suitable functions, such as formatting the memory 100. For another example, the controller 210 may also communicate with an external device (eg, a circuit board) via at least one of various interface protocols.

[0196] In the embodiment of the present application, there is no limit on the number of memories 100 in the storage system 200, that is, the storage system 200 provided in the embodiment of the present application may include one memory 100 or multiple memories 100. FIG27 illustrates an example in which the storage system 200 includes four memories 100.

[0197] The storage system 200 provided in the embodiment of the present application can be integrated into various types of storage devices, for example, solid state drives (SSDs), universal flash storage (UFS), network cards or redundant array of independent disks (RAID) cards, embedded multimedia cards (eMMCs) or embedded multi-chip packages (eMCPs), or any one of USB flash drives.

[0198] It can be understood that the technical effect that can be achieved by the storage system 200 provided in the embodiment of the present application is the same as the technical effect that can be achieved by the memory 100 provided in any of the above embodiments of the present application.

[0199] The present application also provides an electronic device, which may include a mobile phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, an in-vehicle device, a wearable device, augmented reality (AR) glasses, an AR helmet, virtual reality (VR) glasses, or a VR helmet, or other devices that need to store data, or a consumer-grade or enterprise-grade solid-state drive. The present application does not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0200] For ease of explanation, the following description uses the mobile phone shown in Figure 28 as an example. Figure 28 is a schematic diagram of the disassembled structure of an electronic device 300 provided in some embodiments of the present application. As shown in Figure 28, the electronic device 300 includes a display 310, a middle frame 320, a housing (also known as a battery cover or rear housing) 330, a cover plate 340, and a circuit board 350 fixed to the middle frame 320.

[0201] The electronic device 300 provided in the embodiment of the present application may further include the storage system 200 provided in any of the above embodiments of the present application. The storage system 200 is electrically connected to the circuit board 350.

[0202] Exemplarily, the storage system 200 may be disposed on a circuit board 350 and electrically connected to the circuit board 350 .

[0203] Exemplarily, the circuit board 350 may be a printed circuit board (PCB).

[0204] It can also be understood that the technical effect that can be achieved by the electronic device 300 provided in the embodiment of the present application is the same as the technical effect that can be achieved by the memory 100 provided in any of the above embodiments of the present application.

[0205] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0206] The above is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: include: a first substrate, A storage array and a first interconnection layer are located on the first substrate, and the first interconnection layer is located on a side of the storage array away from the first substrate; the second substrate, The peripheral circuit layer and the second interconnection layer are located on the second substrate, and the second interconnection layer is located on the side of the peripheral circuit layer away from the second substrate; the first interconnection layer and the second interconnection layer are both prepared by a back-end process; the first interconnection layer is bonded to the second interconnection layer; The voltage conversion circuit includes a passive device, wherein the passive device is disposed at at least one of a side of the first substrate facing away from the storage array or a side of the second substrate facing away from the peripheral circuit layer.

2. The memory according to claim 1, characterized in that: The voltage conversion circuit also includes an active device; the active device is electrically connected to the passive device, and the setting position of the active device includes any one of the side of the first substrate away from the storage array in the peripheral circuit layer and the side of the second substrate away from the peripheral circuit layer.

3. The memory according to claim 2, characterized in that: The passive device is set at a side of the first substrate away from the storage array, and the active device is set in the peripheral circuit layer. The memory also includes a first connection structure, which runs through the first substrate and the storage array; the passive device is electrically connected to the active device through the first connection structure, the first interconnection layer and the second interconnection layer.

4. The memory according to claim 2, characterized in that: The passive device is disposed at a side of the second substrate away from the peripheral circuit layer, the active device is disposed in the peripheral circuit layer, the memory further includes a second connection structure, the second connection structure passes through the second substrate, and the passive device is electrically connected to the active device through the second connection structure.

5. The memory according to any one of claims 1 to 4, characterized in that: Passive components include capacitors or inductors.

6. The memory according to any one of claims 2 to 4, characterized in that: The passive device includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, and the active device includes: a first diode, wherein an input end of the first diode is connected to a voltage source, and an output end of the first diode is connected to a first electrode of the first capacitor; a second diode, wherein an input end of the second diode is connected to the first electrode of the first capacitor, and an output end of the second diode is connected to the first electrode of the second capacitor; a third diode, wherein an input end of the third diode is connected to the first electrode of the second capacitor, and an output end of the third diode is connected to the first electrode of the third capacitor; a fourth diode, wherein an input end of the fourth diode is connected to the first electrode of the third capacitor, and an output end of the fourth diode is connected to the first electrode of the fourth capacitor; a fifth diode, wherein an input end of the fifth diode is connected to the first electrode of the fourth capacitor, and an output end of the fifth diode is connected to a load; Among them, the second electrode of the first capacitor and the second electrode of the third capacitor are both coupled to the first clock signal source, the second electrode of the second capacitor and the second electrode of the fourth capacitor are both coupled to the second clock signal source, and the signal output by the first clock signal source is inverted with the signal output by the second clock signal source.

7. The memory according to any one of claims 2 to 4, characterized in that: The passive device comprises an inductor, the input end of the inductor is connected to a voltage source, and the active device comprises: a switch transistor, comprising a first electrode, a second electrode and a gate, wherein the first electrode of the switch transistor is coupled to the output end of the inductor, the second electrode of the switch transistor is grounded, and the gate of the switch transistor is coupled to a third clock signal source; A sixth diode, wherein an input end of the sixth diode is coupled to the output end of the inductor, and an output end of the sixth diode is coupled to a load.

8. The memory according to any one of claims 1 to 5, characterized in that: The passive component includes an inductor, and the inductor is a thin film inductor.

9. The memory according to any one of claims 1 to 8, characterized in that: The memory also includes: The buried power rail is located in the peripheral circuit layer and coupled to the transistors in the peripheral circuit layer.

10. The memory according to claim 9, characterized in that: The passive device is set at a side of the first substrate away from the storage array. The memory also includes a third connection structure, a fourth connection structure and a first pad. The third connection structure connects the embedded power rail and the second interconnection layer. The fourth connection structure runs through the storage array and the first substrate. The first pad is located on a side of the first substrate away from the storage array. The first pad is electrically connected to the embedded power rail through the third connection structure, the fourth connection structure, the first interconnection layer and the second interconnection layer.

11. The memory according to claim 9, characterized in that: The setting position of the passive device includes a side of the second substrate away from the peripheral circuit layer. The memory also includes a fifth connection structure and a second pad. The fifth connection structure passes through the second substrate and is electrically in contact with the embedded power rail. The second pad is located on the side of the second substrate away from the peripheral circuit layer. The second pad is electrically connected to the embedded power rail through the fifth connection structure.

12. The memory according to any one of claims 1 to 11, characterized in that: The storage array includes multiple layers of gate layers and multiple layers of dielectric layers that are alternately stacked, and the projection of the passive device on the first substrate at least partially overlaps with the projection of the gate layer on the first substrate; the peripheral circuit layer includes multiple transistors, and the projection of the passive device on the second substrate partially overlaps with the projection of the multiple transistors on the second substrate.

13. The memory according to any one of claims 1 to 12, characterized in that: Also includes: A passivation layer covers the passive device.

14. A method for preparing a memory, characterized in that: include: forming a memory array on the first substrate; forming a first interconnect layer on a side of the storage array away from the first substrate; The first interconnect layer is prepared by a back-end process; forming a peripheral circuit layer on the second substrate; forming a second interconnection layer on a side of the peripheral circuit layer away from the second substrate; the second interconnection layer is prepared by a back-end process; bonding the first interconnect layer and the second interconnect layer; A passive device for forming a voltage conversion circuit is disposed at a position including at least one of a side of the first substrate facing away from the storage array or a side of the second substrate facing away from the peripheral circuit layer.

15. The preparation method according to claim 14, characterized in that: The voltage conversion circuit further includes an active device, and the active device is electrically connected to the passive device; the preparation method further includes: In the process of forming the peripheral circuit layer on the second substrate, the active device is formed; or, The active device is formed on a side of the first substrate away from the memory array; or, The active device is formed on a side of the second substrate away from the peripheral circuit layer.

16. The preparation method according to claim 14 or 15, characterized in that: Also includes: forming a buried power rail during forming a peripheral circuit layer on the second substrate; The buried power rail is coupled to transistors in the peripheral circuit layer; forming a third connection structure, the embedded power rail and the second interconnect layer being electrically connected via the third connection structure; thinning the first substrate; forming a fourth connection structure penetrating the first substrate and the memory array; the fourth connection structure is electrically connected to the first interconnection layer; forming a first pad on a side of the first substrate away from the memory array, wherein the first pad is electrically connected to the embedded power rail through the third connection structure, the fourth connection structure, the first interconnection layer, and the second interconnection layer; After the first pad is formed on the side of the first substrate away from the memory array, the passive components of the voltage conversion circuit are formed on the side of the first substrate away from the memory array.

17. The preparation method according to claim 14 or 15, characterized in that: Also includes: forming a buried power rail during forming a peripheral circuit layer on the second substrate; The buried power rail is coupled to transistors in the peripheral circuit layer; thinning the second substrate; forming a fifth connection structure penetrating the second substrate, the fifth connection structure being electrically connected to the embedded power rail; forming a second pad on a side of the second substrate away from the peripheral circuit layer, wherein the second pad is electrically connected to the embedded power rail through the fifth connection structure; After forming the second pad on the side of the second substrate away from the peripheral circuit layer, the passive components of the voltage conversion circuit are formed on the side of the second substrate away from the peripheral circuit layer.

18. The preparation method according to any one of claims 14 to 17, characterized in that: Also includes: A passivation layer is formed, wherein the passivation layer covers the passive device.

19. A storage system, characterized in that: include: Controller, The memory according to any one of claims 1 to 13, wherein the controller is electrically connected to the memory.

20. An electronic device, characterized in that: include: Circuit Boards, The storage system of claim 19, wherein the storage system is electrically connected to the circuit board.

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