Array substrate and manufacturing method therefor, and display panel and display apparatus

Abstract

Provided in the embodiments of the present disclosure are an array substrate and a manufacturing method therefor, and a display panel and a display apparatus. The array substrate comprises a first base substrate, a driving circuit layer, a transmission electrode layer and a reflection electrode layer which are sequentially stacked, wherein a plurality of gate lines and a plurality of data lines in the driving circuit layer extend in a first direction and a second direction, respectively, the gate lines and the data lines intersect and define a plurality of pixel regions, and each pixel region comprises a transmission region and a reflection region. In each pixel region, the transmission region comprises at least one first region and at least one second region which are connected to each other, wherein the first region and the second region are located between two adjacent reflection regions in the first direction and the second direction, respectively, and the length directions of the first region and the second region are the second direction and the first direction, respectively. The reflection electrode layer comprises reflection electrodes which are in one-to-one correspondence with the reflection regions and cover the corresponding reflection regions. The transmission electrode layer comprises transmission electrodes which are in one-to-one correspondence with the transmission regions and at least cover the corresponding transmission regions. The embodiments of the present disclosure can improve the aperture ratio of a display panel.

Description

Array substrate and manufacturing method thereof, display panel and display device Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] A transflective liquid crystal display device has both a reflective and a transmissive display mode. In bright light environments, the reflective display mode maintains display contrast and reduces power consumption. In low-light conditions, the transmissive display mode uses a backlight to provide supplemental display. The display panel of a transflective liquid crystal display device includes a first substrate and a second substrate positioned opposite each other, and a liquid crystal layer located between the first and second substrates.

[0003] In the related art, a first substrate includes a base substrate and a drive circuit layer, a transmissive electrode layer, and a reflective electrode layer sequentially stacked on the base substrate. The drive circuit layer includes multiple gate lines and multiple data lines, wherein the multiple gate lines extend along a first direction and the multiple data lines extend along a second direction. The multiple gate lines intersect with the multiple data lines and define multiple pixel regions. The transmissive electrode layer includes multiple transmissive electrodes, each of which is located in a corresponding pixel region. The reflective electrode layer includes multiple reflective electrodes, each of which is located in a corresponding pixel region.

[0004] However, in order to prevent adjacent reflective electrodes from growing and overlapping in the air and causing a short circuit, a large distance must be left between two adjacent reflective electrodes, resulting in a large distance between two adjacent pixel areas and a small pixel aperture ratio.

[0005] Summary of the Invention

[0006] The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a display device, which can improve the problem of a large distance between two adjacent pixel areas in a first direction and a small pixel aperture ratio.

[0007] In one aspect, an array substrate is provided, comprising a first base substrate and a driving circuit layer, a transmissive electrode layer, and a reflective electrode layer sequentially stacked on the first base substrate; the driving circuit layer comprising a plurality of gate lines and a plurality of data lines, the plurality of gate lines extending along a first direction, the plurality of data lines extending along a second direction, the plurality of gate lines intersecting with the plurality of data lines and defining a plurality of pixel regions; each of the pixel regions comprising a transmissive region and a reflective region, and in at least one of the pixel regions, the transmissive region comprising at least one first region and at least one second region connected to each other, the first region being located between two adjacent reflective regions in the first direction and the length direction of the first region being consistent with the second direction, and the second region being located between two adjacent reflective regions in the second direction and the length direction of the second region being consistent with the first direction; the reflective electrode layer comprising a plurality of reflective electrodes, the plurality of reflective electrodes corresponding one-to-one to the plurality of reflective regions and respectively covering the corresponding reflective regions; the transmissive electrode layer comprising a plurality of transmissive electrodes, the plurality of transmissive electrodes corresponding one-to-one to the plurality of transmissive regions, each of the transmissive electrodes covering at least the corresponding transmissive region.

[0008] Optionally, in at least one of the pixel regions, the transmission area includes one first region and one second region.

[0009] Optionally, the multiple pixel areas include a first pixel area and a second pixel area adjacent to each other in the first direction, the reflective electrode in the first pixel area is a first reflective electrode, the reflective electrode in the second pixel area is a second reflective electrode, and the transmissive electrode in the first pixel area is a first transmissive electrode; the orthographic projection of the first transmissive electrode on the supporting surface of the first base substrate overlaps with the orthographic projections of the first reflective electrode and the second reflective electrode on the supporting surface of the first base substrate.

[0010] Optionally, the multiple pixel areas include a third pixel area and a fourth pixel area adjacent to each other in the second direction, the reflective electrode in the third pixel area is a third reflective electrode, the reflective electrode in the fourth pixel area is a fourth reflective electrode, and the transmissive electrode in the third pixel area is a second transmissive electrode; the orthographic projection of the second transmissive electrode on the supporting surface of the first base substrate overlaps with the orthographic projections of the third reflective electrode and the fourth reflective electrode on the supporting surface of the first base substrate.

[0011] Optionally, in the first direction, the spacing between the reflective regions of two adjacent pixel regions is greater than or equal to 6 μm; in the second direction, the spacing between the reflective regions of two adjacent pixel regions is greater than or equal to 6 μm.

[0012] Optionally, the driving circuit layer further includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits correspond one-to-one to the plurality of pixel areas; the plurality of pixel driving circuits are respectively located in the reflective areas of the corresponding pixel areas.

[0013] Optionally, the array substrate further includes a passivation layer, which is located between the driving circuit layer and the transmissive electrode layer; the passivation layer has a plurality of vias, each of the pixel driving circuits is electrically connected to the corresponding transmissive electrode through at least one of the vias, and the vias are located in the reflective area of ​​the corresponding pixel area.

[0014] Optionally, the array substrate further includes a planarization layer, and the planarization layer is located between the reflective electrode layer and the transmissive electrode layer.

[0015] Optionally, the planarization layer includes a plurality of isolation blocks, the plurality of isolation blocks correspond one-to-one to the plurality of pixel areas, and the isolation blocks are respectively located in the corresponding pixel areas; in the same pixel area, the reflective electrode is located on the top surface of the isolation block and at least one side wall of the plurality of side walls, and the side of the reflective electrode located on the side wall away from the top surface of the isolation block is connected to the transmissive electrode.

[0016] Optionally, an orthographic projection of the data line on the supporting surface of the first base substrate at least partially overlaps with an orthographic projection of the reflective electrode on the supporting surface of the first base substrate.

[0017] Optionally, the reflective electrode layer is made of silver or aluminum.

[0018] On the other hand, an embodiment of the present disclosure provides an array substrate, comprising a first base substrate and a driving circuit layer, a transmissive electrode layer, and a reflective electrode layer sequentially stacked on the first base substrate, the driving circuit layer comprising a plurality of gate lines and a plurality of data lines, the plurality of gate lines extending along a first direction, the plurality of data lines extending along a second direction, the plurality of gate lines intersecting with the plurality of data lines and defining a plurality of pixel regions; the reflective electrode layer comprising a plurality of reflective electrodes arranged in an array, each of the reflective electrodes being located in a corresponding pixel region; the transmissive electrode layer comprising a plurality of transmissive electrodes arranged in an array, each of the transmissive electrodes being located in a corresponding pixel region; a first reflective electrode among the plurality of reflective electrodes and a first transmissive electrode among the plurality of transmissive electrodes being insulated from each other, and an orthographic projection of the first reflective electrode on the first base substrate partially overlapping with an orthographic projection of the first transmissive electrode on the first base substrate, the first reflective electrode being located in a first pixel region, the first transmissive electrode being located in a second pixel region, and the first pixel region and the second pixel region being two adjacent pixel regions in the first direction or the second direction.

[0019] In another aspect, a method for manufacturing an array substrate is provided, the method comprising:

[0020] A first base substrate is provided; a driving circuit layer, a transmissive electrode layer, and a reflective electrode layer are sequentially stacked on one side of the first base substrate; wherein the driving circuit layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines extending along a first direction, the plurality of data lines extending along a second direction, the plurality of gate lines intersecting with the plurality of data lines and defining a plurality of pixel regions; each of the pixel regions includes a transmissive area and a reflective area, and in at least one of the pixel regions, the transmissive area includes a first area and a second area connected to each other, the first area being located between two adjacent reflective areas in the first direction and the length direction of the first area being consistent with the second direction, and the second area being located between two adjacent reflective areas in the second direction and the length direction of the second area being consistent with the first direction; the reflective electrode layer includes a plurality of reflective electrodes, the plurality of reflective electrodes corresponding one-to-one to the plurality of reflective areas and respectively covering the corresponding reflective areas, and the transmissive electrode layer includes a plurality of transmissive electrodes, the plurality of transmissive electrodes corresponding one-to-one to the plurality of transmissive areas, and each transmissive electrode covering at least the corresponding transmissive area.

[0021] On the other hand, a display panel is provided, comprising a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is any one of the aforementioned array substrates.

[0022] Optionally, the second substrate includes a transparent substrate; or, the second substrate includes a second base substrate and a shading layer and a color filter layer stacked on the second base substrate, the color filter layer includes a plurality of color-resistance blocks arranged in an array along the first direction and the second direction, the plurality of color-resistance blocks correspond one-to-one to the plurality of pixel areas, the colors of two adjacent color-resistance blocks in the second direction are the same, and the colors of two adjacent color-resistance blocks in the first direction are different, the shading layer includes a plurality of shading strips, the plurality of shading strips are located between the plurality of color-resistance blocks, and the plurality of shading strips are arranged in parallel and spaced apart and extend along the second direction.

[0023] On the other hand, a display device is provided, comprising any one of the aforementioned display panels and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

[0024] The technical solution provided by this disclosure provides at least the following beneficial effects: the distance between two adjacent reflective regions must be greater than or equal to a limit distance to prevent overlapping short circuits between adjacent reflective electrodes due to their proximity. By providing a transmissive region between two adjacent reflective regions in both the first and second directions, the area between two adjacent reflective electrodes in both the first and second directions can be fully utilized. This improves the aperture ratio of the display panel while maintaining the same area ratio of the transmissive region to the reflective region as in related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] FIG1 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0027] FIG2 is a schematic diagram of a top view of a display panel in the related art;

[0028] FIG3 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0029] FIG4 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0030] FIG5 is a schematic top view of the structure of an array substrate provided in an embodiment of the present disclosure;

[0031] FIG6 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0032] 7 is a schematic diagram of projections of a transmissive electrode and a reflective electrode in a pixel region on the supporting surface of a first base substrate provided by an embodiment of the present disclosure;

[0033] FIG8 is a schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure;

[0034] FIG9 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure;

[0035] FIG10 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure;

[0036] FIG11 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure.

[0037] Legend: x, first direction y, second direction m, transmissive area n, reflective area m1, first area m2 of the transmissive area, second area 1 of the transmissive area, array substrate / first substrate 11, first base substrate 12, driving circuit layer 120, pixel driving circuit 121, gate line 122, data line 123, gate layer 124, gate insulating layer 125, active layer 126, source and drain layer 13, transmissive electrode layer 130, transmissive electrode 14, reflective electrode layer 140, reflective electrode 15, passivation layer 150, via 16, planarization layer 160, isolation block 2, second substrate 21, second base substrate 22, light shielding layer 221, light shielding strip 23, color filter layer 3, liquid crystal layer DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the ordinary meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "a" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The directional terms mentioned in the present disclosure, such as "top", "bottom", "up", "down", "left" or "right", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present disclosure, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0040] Figure 1 is a schematic cross-sectional view of a display panel in the related art. As shown in Figure 1, the display panel in the related art includes a first substrate 1x and a second substrate 2x disposed opposite each other, and a liquid crystal layer 3x positioned between the first and second substrates 1x and 2x. The first substrate 1x includes a first base substrate 11x, and a drive circuit layer 12x, a transmissive electrode layer 13x, and a reflective electrode layer 14x sequentially stacked on the first base substrate 11x.

[0041] FIG2 is a schematic top view of the display panel in FIG1 , and FIG1 is a cross-sectional view of FIG2 along line AA. As shown in FIG2 , the drive circuit layer 12x includes a plurality of gate lines 121x and a plurality of data lines 122x. The plurality of gate lines 121x extend along a first direction x, and the plurality of data lines 122x extend along a second direction y. The plurality of gate lines 121x and the plurality of data lines 122x intersect and define a plurality of pixel regions p. The plurality of pixel regions p corresponds to one pixel. Each pixel region p includes a transmissive region m and a reflective region n.

[0042] Figure 3 is a cross-sectional view taken along line BB in Figure 2 . Referring to Figures 1, 2, and 3 , the reflective electrode layer 14x includes a plurality of reflective electrodes 140x. Each of the reflective electrodes 140x corresponds one-to-one with each of the reflective regions n, with each reflective electrode 140x covering a corresponding reflective region n. Referring to Figures 1 and 2 , the transmissive electrode layer 13x includes a plurality of transmissive electrodes 130x. Each of the transmissive electrodes 130x corresponds one-to-one with each of the transmissive regions m, with each transmissive electrode 130x covering a corresponding transmissive region m. Within a pixel region, the transmissive region m is located to one side of the reflective region n in the second direction y.

[0043] The spacing between two adjacent reflective electrodes 140x must not be less than a limited distance; otherwise, the reflective electrodes 140x may grow in the air, leading to overlapping and short-circuiting between the two adjacent reflective electrodes 140x. In the related art, the distance between two adjacent reflective regions in the first direction x and the second direction y is greater than or equal to the limited distance to prevent the adjacent reflective electrodes 140x from growing in the air due to being too close together, leading to overlapping and short-circuiting. In the related art, for a design in which a transmissive region m in a pixel region p is located to one side of a reflective region n in the second direction y, the area between the two adjacent reflective regions n in the second direction y is utilized. However, in the first direction x, there is no transmissive region m between the two adjacent reflective regions n. This means that the area between the two adjacent reflective regions n is not fully utilized, thus limiting the aperture ratio.

[0044] For a transflective liquid crystal display panel, in the transmissive display mode, that is, when using a backlight for supplementary display, in order to prevent the backlight from leaking through the gap between two adjacent pixel areas, a light shielding layer needs to be provided in the second substrate 2x to block light.

[0045] As shown in Figures 1 to 3, the second substrate 2x includes a second base substrate 21x and a light shielding layer 22x and a color filter layer 23x sequentially stacked on the second base substrate 21x. The color filter layer 23x includes a plurality of color resist blocks distributed in an array. The light shielding layer 22x includes a black matrix structure and the black matrix structure is located between two adjacent color resist blocks. In the first direction x, the width of the black matrix is ​​determined by the limiting distance and the process fluctuation control capability. In the first direction x, the width of the black matrix is ​​at least equal to the sum of the limiting distance S3 and twice the process alignment fluctuation value S2 of the first substrate and the second substrate, that is, S3+2*S2. In the second direction y, the width of the black matrix is ​​at least equal to the sum of S1 and twice the process alignment fluctuation value S2 of the first substrate and the second substrate, that is, S1+2*S2, where S1 is the size of the spacing between the two pixel areas determined according to the process alignment requirements. Typically, S1 is smaller than S3.

[0046] As can be seen, in the related art, the spacing between two adjacent pixel regions in the first direction x is limited by a limited distance, and the pixel aperture ratio is also limited by the limited distance. To this end, the embodiments of the present disclosure provide an array substrate that can reduce the spacing between two adjacent pixel regions and increase the pixel aperture ratio.

[0047] Figure 4 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in Figure 4 , the array substrate 1 includes a first base substrate 11 and a driving circuit layer 12 , a transmissive electrode layer 13 , and a reflective electrode layer 14 sequentially stacked on the first base substrate 11 .

[0048] Figure 5 is a schematic top view of an array substrate provided in an embodiment of the present disclosure, and Figure 4 is a cross-sectional view taken along the CC section line in Figure 5. As shown in Figure 5, the driving circuit layer 12 includes a plurality of gate lines 121 and a plurality of data lines 122. The plurality of gate lines 121 extend along a first direction x, and the plurality of data lines 122 extend along a second direction y. The plurality of gate lines 121 and the plurality of data lines 122 intersect and define a plurality of pixel regions.

[0049] Each pixel region includes a transmissive region m and a reflective region n. The transmissive region m in each pixel region includes a first region m1 and a second region m2. In a first direction x, the first region m1 is located between two adjacent reflective regions n, and the length of the first region m1 aligns with a second direction y. In a second direction y, the second region m2 is located between two adjacent reflective regions n, and the length of the second region m2 aligns with the first direction x. The reflective electrode layer 14 includes a plurality of reflective electrodes 140. The plurality of reflective electrodes 140 correspond one-to-one with the plurality of reflective regions n and cover the corresponding reflective regions n. The transmissive electrode layer 13 includes a plurality of transmissive electrodes 130. The plurality of transmissive electrodes 130 correspond one-to-one with the plurality of transmissive regions m, and each transmissive electrode 130 covers at least the corresponding transmissive region m.

[0050] In the embodiment of the present disclosure, "each reflective electrode 140 covers the corresponding reflective region n" means that the reflective electrode 140 completely fills the reflective region n, or in other words, the reflective region n and the reflective electrode 140 have the same coverage area. "each transmissive electrode 130 at least covers the corresponding transmissive region m" means that the transmissive electrode 130 at least fills the transmissive region m and may extend beyond the transmissive region m.

[0051] In the disclosed embodiment, a portion of the transmissive electrode 130 exists between two adjacent reflective electrodes 140, requiring a certain amount of space. When the dimension of this space in the direction in which the two reflective electrodes 140 are arranged is greater than the limiting distance, the spacing between the two adjacent pixel regions, defined as S1, only needs to be considered based on the process alignment requirements. When the process alignment accuracy is sufficiently high, the distance between the two adjacent pixel regions can theoretically be infinitely small. However, when the dimension of this space in the direction in which the two reflective electrodes 140 are arranged is less than the limiting distance, the spacing between the two adjacent pixel regions is limited by the difference between the limiting distance and the dimension of this space in the direction in which the two reflective electrodes 140 are arranged. Providing a transmissive region m between two adjacent reflective regions n in both the first direction x and the second direction y fully utilizes the area between two adjacent reflective electrodes 140 in both the first direction x and the second direction y that requires a spacing greater than or equal to the limiting distance. While maintaining the same transmissive area to reflective area ratio as in the related art, the display panel provided by the disclosed embodiment can achieve a higher aperture ratio.

[0052] In other possible embodiments, each pixel region includes a transmissive region m and a reflective region n. In at least one pixel region, the transmissive region m includes two connected first regions m1 and two connected second regions m2. In the first direction x, the two first regions m1 are located between two adjacent reflective regions n and on both sides of the reflective region n of the pixel region. The length direction of the first region m1 is consistent with the second direction y. In the second direction y, the two second regions m2 are located between two adjacent reflective regions n and on both sides of the reflective region n of the pixel region. The length direction of the second regions m2 is consistent with the first direction x.

[0053] In other possible embodiments, each pixel area includes a transmission area m and a reflection area n, wherein the transmission area m of a part of the pixel areas includes the aforementioned connected first area m1 and second area m2, and the transmission area m of another part of the pixel areas includes only the first area m1 or only the second area m2.

[0054] In the embodiment of the present disclosure, there are at least two adjacent pixel areas, the reflective electrode in one pixel area and the transmissive electrode in the other pixel area are insulated from each other, and the orthographic projection of the reflective electrode in one pixel area on the first base substrate 11 partially overlaps with the orthographic projection of the transmissive electrode in the other pixel area on the first base substrate.

[0055] Optionally, the two adjacent pixel regions may be two pixel regions adjacent to each other in the first direction x, or may be two pixel regions adjacent to each other in the second direction y.

[0056] The positional relationship between the reflective electrodes 140 and the transmissive electrodes 130 will be described below, taking the reflective electrodes 140 in any two adjacent pixel regions and the transmissive electrode 130 between the two reflective electrodes 140 as an example. As shown in Figures 4 and 6 , regardless of whether in the first direction x or the second direction y, the transmissive electrode 130 not only covers the first region m1 or the second region m2 in the corresponding transmissive region m, but also partially covers the two adjacent reflective regions n. Therefore, the gap between the two adjacent pixel regions is seamlessly filled by the two reflective electrodes and the transmissive electrode, thereby preventing backlight leakage from the display panel in transmissive display mode.

[0057] Figure 6 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure, and is an interface diagram along the cross-sectional line DD in Figure 5 . As shown in Figure 6 , the plurality of pixel regions include a first pixel region p1 and a second pixel region p2 adjacent to each other in a first direction x. The reflective electrode 140 in the first pixel region p1 is a first reflective electrode 140a, the reflective electrode 140 in the second pixel region p2 is a second reflective electrode 140b, and the transmissive electrode 130 in the first pixel region p1 is a first transmissive electrode 130a. The orthographic projection of the first transmissive electrode 130a on the supporting surface of the first base substrate 11 overlaps with the orthographic projections of the first reflective electrode 140a and the second reflective electrode 140b on the supporting surface of the first base substrate 11.

[0058] Optionally, the sub-pixels corresponding to the first pixel region p1 and the second pixel region p2 may belong to one pixel, or may respectively belong to one pixel.

[0059] In the first direction x, the first transmissive electrode 130a not only covers the corresponding transmissive area, but also partially covers the two adjacent reflective areas. Therefore, the first pixel area p1 and the second pixel area p2 adjacent to each other are seamlessly filled with the first reflective electrode 140a, the second reflective electrode 140b, and the first transmissive electrode 130a. The spacing between adjacent pixel areas is small, or even zero, which can further improve the pixel aperture ratio.

[0060] Optionally, the width of the overlapping portion between the orthographic projection of the first transmissive electrode 130a on the supporting surface of the first base substrate 11 and the orthographic projection of the first reflective electrode 140a on the supporting surface of the first base substrate 11 is D1. The width of the overlapping portion between the orthographic projection of the first transmissive electrode 130a on the supporting surface of the first base substrate 11 and the orthographic projection of the second reflective electrode 140b on the supporting surface of the first base substrate 11 is D2. The sum of D1, D2, and the alignment process fluctuation is less than the size of a pixel area in the first direction x, so that two adjacent reflective electrodes 140 in the first direction x do not contact each other.

[0061] In the embodiment of the present disclosure, referring again to FIG. 4 , the plurality of pixel regions include a third pixel region and a fourth pixel region adjacent to each other in the second direction y. The reflective electrode 140 in the third pixel region is a third reflective electrode 140c, the reflective electrode 140 in the fourth pixel region is a fourth reflective electrode 140d, and the transmissive electrode 130 in the third pixel region is a second transmissive electrode 130b. The orthographic projection of the second transmissive electrode 130b on the supporting surface of the first base substrate 11 overlaps with the orthographic projections of the third reflective electrode 140c and the fourth reflective electrode 140d on the supporting surface of the first base substrate 11.

[0062] In the second direction y, the second transmissive electrode 130b not only covers the corresponding transmissive area, but also partially covers the two adjacent reflective areas. Therefore, the space between the adjacent third pixel area p3 and fourth pixel area p4 is seamlessly filled by the third reflective electrode 140c, the fourth reflective electrode 140d, and the second transmissive electrode 130b, thereby preventing backlight leakage from the display panel.

[0063] Optionally, the width of the overlapping portion between the orthographic projection of the second transmissive electrode 130b on the supporting surface of the first base substrate 11 and the orthographic projection of the third reflective electrode 140c on the supporting surface of the first base substrate 11 is D3. The width of the overlapping portion between the orthographic projection of the second transmissive electrode 130b on the supporting surface of the first base substrate 11 and the orthographic projection of the fourth reflective electrode 140d on the supporting surface of the first base substrate 11 is D4. The sum of D3, D4, and the alignment process fluctuation is less than the size of a pixel area in the second direction y, so that two adjacent reflective electrodes 140 in the second direction y do not contact each other.

[0064] In other possible embodiments, in the first direction x, the first transmissive electrode 130a only covers the corresponding transmissive region. Therefore, between adjacent first and second pixel regions, the orthographic projection of the first transmissive electrode 130a on the supporting surface of the first base substrate 11 seamlessly connects with the orthographic projections of the first and second reflective electrodes 140a and 140b on the supporting surface of the first base substrate 11. In the second direction y, the second transmissive electrode 130b only covers the second transmissive region. The orthographic projection of the second transmissive electrode 130b on the supporting surface of the first base substrate 11 seamlessly connects with the orthographic projections of the third and fourth reflective electrodes 140c and 140d on the supporting surface of the first base substrate 11.

[0065] Exemplarily, the reflective electrode layer 14 is made of a metal material, such as silver or aluminum. Both silver and aluminum have high reflectivity and are suitable for forming the reflective electrode layer 14. Silver has a higher reflectivity, but silver-based reflective electrodes react with sulfur, sulfides, oxygen, and other substances in the air to form silver sulfide or silver oxide particles, which gradually grow larger. If two adjacent silver-based reflective electrodes are too close together, the silver sulfide or silver oxide particles generated by the silver-based reflective electrodes can gradually grow to cover the adjacent reflective electrodes, leading to overlapping short circuits. Therefore, the embodiments of the present disclosure are particularly suitable for silver-based reflective electrode layers.

[0066] For example, in the first direction x, the spacing between the reflective areas n of two adjacent pixel areas is greater than or equal to 6μm. In the second direction y, the spacing between the reflective areas n of two adjacent pixel areas is greater than or equal to 6μm. The spacing between two adjacent silver reflective electrodes 140 needs to be greater than or equal to 6μm, otherwise they may grow in the air and cause overlapping short circuit problems. Therefore, the spacing between two adjacent reflective areas n needs to be greater than or equal to 6μm. Optionally, the spacing between the reflective areas n of two adjacent pixel areas in the first direction x is smaller than the size of the pixel area in the first direction x; the spacing between the reflective areas n of two adjacent pixel areas in the second direction y is smaller than the size of the pixel area in the second direction y. The specific size needs to be determined based on the transmission area required by the product.

[0067] For example, as shown in Figures 4 and 5 , the driver circuit layer 12 further includes a plurality of pixel driver circuits 120, each corresponding one-to-one to a plurality of pixel regions. That is, each pixel region is provided with a pixel driver circuit 120. Each pixel driver circuit 120 is located in the reflective region n of the corresponding pixel region. The plurality of pixel driver circuits 120 are respectively located in the reflective region n of the corresponding pixel region, i.e., below the corresponding reflective electrode 140 and shielded by the reflective electrode 140. This eliminates the need for other structures to shield the pixel driver circuits 120, thereby improving the aperture ratio.

[0068] For example, as shown in Figures 5 and 6, the orthographic projection of the data line 122 on the supporting surface of the first base substrate 11 at least partially overlaps with the orthographic projection of the reflective electrode 140 on the supporting surface of the first base substrate 11. Since the reflective electrode 140 can block the data line 122 below, arranging the data line 122 below the reflective electrode 140 helps to improve the aperture ratio.

[0069] For example, as shown in FIG4 , the array substrate 1 further includes a passivation layer 15, which is located between the driving circuit layer 12 and the transmissive electrode layer 13. The passivation layer 15 has a plurality of vias 150, and each pixel driving circuit 120 is electrically connected to the corresponding transmissive electrode 130 through at least one via 150. The vias 150 are located in the reflective region of the corresponding pixel area.

[0070] In order to connect the transmissive electrode 130 with the driving circuit layer 12 , a via hole connecting the transmissive electrode 130 and the driving circuit layer 12 needs to be formed in the film layer between the transmissive electrode layer 130 and the first base substrate 11 .

[0071] In the related art, as shown in Figure 1 , in reflective region n, the reflective electrode layer 14x is electrically connected to the drive circuit layer 12x via vias in the passivation layer 15x and other film layers. Because the film layer between the reflective electrode layer 14x and the drive circuit layer 12x is relatively thick, the vias can cause an uneven reflective surface in the reflective region n closest to the light-emitting side, reducing the effective reflectivity of the reflective region n. In contrast, in the disclosed embodiment, the transmissive electrode layer 13 is connected to the source / drain electrode layer 126 of the drive circuit layer 12 via vias 150 in the passivation layer 15. Because the passivation layer 15 in the disclosed embodiment is thinner than the passivation layer 15x and other film layers in the related art, the depression at the via 150 in the passivation layer 15 is shallower. Therefore, the via 150 in the disclosed embodiment has a lesser impact on the flatness of the reflective electrode 140, thereby improving the effective reflectivity of the reflective region n.

[0072] Optionally, the embodiment of the present disclosure does not limit the shape of the via hole 150 , which may be cylindrical, truncated cone, prism-shaped, or prismatic.

[0073] For example, as shown in FIG4 , the array substrate further includes a planarization layer 16, which is located between the reflective electrode layer 14 and the transmissive electrode layer 13. Providing a thicker planarization layer 16 can reduce the potential interaction between the reflective electrode 140 in one pixel region and the transmissive electrode 130 in the other pixel region in two adjacent pixel regions. The thickness of the liquid crystal layer in the transmissive region m can also be adjusted by removing the planarization layer 16 from the transmissive region m. Combined with adjusting the refractive index of the liquid crystal, an optimal cell thickness design for the transmissive region can be achieved. Optionally, the cell thickness of the liquid crystal in the transmissive region m is approximately twice that of the reflective region n.

[0074] For example, as shown in FIG4 , the planarization layer 16 includes a plurality of isolation blocks 160, each corresponding to a plurality of pixel regions. Within the same pixel region, a reflective electrode 140 is located on the top surface of the isolation block 160 and at least one of the plurality of sidewalls. The side of the reflective electrode 140 located on the sidewall, away from the top surface of the isolation block 160, is connected to the transmissive electrode 130. The reflective electrode 140 is connected to the transmissive electrode 130, allowing the reflective electrode 140 to be electrically connected to the underlying drive circuit layer 12 through the transmissive electrode 130. This arrangement avoids the need for vias in the reflective region n connecting the reflective layer 14 and the drive circuit layer 12, which would otherwise affect the reflective effect of the reflective electrode 140. Optionally, a portion of the reflective electrode 140 extends to the side of the transmissive electrode 130 away from the first base substrate 11.

[0075] Exemplarily, the connection line between the reflective electrode 140 and the transmissive electrode 130 is the boundary between the reflective and transmissive regions in the pixel region. As shown in Figures 4 and 5, the reflective electrode 140 and the transmissive electrode 130 in the cross-sectional view of Figure 4 intersect at a point. This intersection, when extended in the first direction x, forms the actual connection line between the reflective electrode 140 and the portion of the transmissive electrode 130 adjacent in the first direction. This connection line also forms the boundary between the second region m2 of the transmissive region and the reflective region n in Figure 5. As shown in Figures 5 and 6, the reflective electrode 140 and the transmissive electrode 130 in the cross-sectional view of Figure 6 intersect at a point. This intersection, when extended in the second direction y, forms the actual connection line between the reflective electrode 140 and the portion of the transmissive electrode 130 adjacent in the second direction. This connection line also forms the boundary between the first region m1 of the transmissive region and the reflective region n in Figure 5.

[0076] Optionally, as shown in FIG5 , in a pixel region, the transmissive region m is L-shaped and the reflective region n is rectangular. In other possible embodiments, the transmissive region m may also be an “O”-shaped ring that fully surrounds the reflective region n, or a semi-enclosed ring with one side open.

[0077] FIG7 is a schematic diagram of projections of a transmissive electrode and a reflective electrode on the supporting surface of a first substrate in a pixel region provided by an embodiment of the present disclosure, as shown in FIG7 :

[0078] Alternatively, as shown in FIG7a , in a pixel region, the reflective region n is rectangular, and the orthographic projection of the reflective electrode 140 on the supporting surface of the first base substrate 11 is rectangular; the transmissive region m is L-shaped, and the orthographic projection of the transmissive electrode 130 on the supporting surface of the first base substrate 11 extends from one side of the L-shape toward the reflective region n. The transmissive electrode 130 corresponding to the extra projection compared to the L-shape is used to connect to the driving circuit layer 12. The actual reflective electrode 140 may have a planar structure located on the top surface of the isolation block 160, and a structure that is adjacent to two side edges of the planar structure and extends toward the transmissive electrode 130 located in the transmissive region n, i.e., the reflective electrode 140 is located on the top surface and two side walls of the isolation block 160. Alternatively, the actual reflective electrode 140 may have a planar structure located on the top surface of the isolation block 160, and a structure that is adjacent to one of the two side edges of the planar structure near the transmissive region n and extends toward the transmissive electrode 130 located in the transmissive region n, i.e., the reflective electrode 140 is located on the top surface and one side wall of the isolation block 160.

[0079] Alternatively, as shown in FIG7b , the transmissive region m is annular and has a square shape. Within a pixel region, the reflective region n is rectangular. The orthographic projection of the reflective electrode 140 on the supporting surface of the first base substrate 11 is rectangular. The orthographic projection of the transmissive electrode 130 on the supporting surface of the first base substrate 11 can be, based on the square shape, extended from any side of the square shape toward the reflective region n. The transmissive electrode 130 corresponding to this portion of the projection is used to connect to the driving circuit layer 12. The actual reflective electrode 140 can have a planar structure located on the top surface of the isolation block 160, and can be in contact with at least some of the multiple side edges of the planar structure and extend toward the transmissive electrode 130 located in the transmissive region n. That is, the reflective electrode 140 is located on the top surface and at least one sidewall of the isolation block 160.

[0080] Alternatively, as shown in FIG7c , the transmissive region m is in the shape of a semi-enclosed ring with one side open, and within a pixel region, the reflective region n is in the shape of a rectangle. The orthographic projection of the reflective electrode 140 on the supporting surface of the first base substrate 11 is rectangular. The orthographic projection of the transmissive electrode 130 on the supporting surface of the first base substrate 11, based on the open semi-enclosed ring shape, can extend from a portion of the semi-enclosed ring toward the reflective region n. The transmissive electrode 130 corresponding to this portion of the projection is used to connect to the driving circuit layer 12. The actual reflective electrode 140 can have a planar structure located on the top surface of the isolation block 160, and can be in contact with at least some of the multiple side edges of the planar structure and extend toward the transmissive electrode 130 located in the transmissive region n. That is, the reflective electrode 140 is located on the top surface and at least one sidewall of the isolation block 160.

[0081] In the embodiments shown in FIG. 7 a , FIG. 7 b and FIG. 7 c , since the transmissive electrode 130 and the reflective electrode 140 in FIG. 7 a have fewer intersections, the light effect in the embodiment of FIG. 7 a is less affected by the step difference at the intersection between the transmissive electrode 130 and the reflective electrode 140 . Therefore, the display effect of the embodiment shown in FIG. 7 a is better in comparison.

[0082] In one possible embodiment, as shown in FIG4 , the driving circuit layer 12 includes a gate layer 123, a gate insulating layer 124, an active layer 125, and a source-drain electrode layer 126 stacked sequentially on the first base substrate 11. In a pixel region, a pixel driving circuit 120 includes at least one thin film transistor (TFT), each of which includes a gate in the gate layer 123 and a source and drain in the source-drain electrode layer 126.

[0083] In other possible implementations, the driving circuit layer includes an active layer, a gate insulating layer, a gate layer, an insulating layer, and a source / drain electrode layer stacked in sequence on the supporting surface of the first base substrate.

[0084] Exemplarily, the gate layer 123 is made of a metal material, such as one or more of molybdenum, copper, and aluminum.

[0085] Exemplarily, the gate insulating layer 124 and the insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0086] Exemplarily, the active layer 125 is made of low-temperature polysilicon material or metal oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide).

[0087] Exemplarily, the source-drain electrode layer 126 may be a single-layer metal film such as aluminum, molybdenum, copper, or titanium, or a multi-layer metal film such as a molybdenum layer, an aluminum layer, and a molybdenum layer stacked in sequence, or a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0088] Exemplarily, the passivation layer 15 may be made of a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer.

[0089] Exemplarily, the planarization layer 16 is made of an organic insulating material, such as resin.

[0090] FIG8 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure. As shown in FIG8 , the method includes:

[0091] In step S1, providing a first substrate substrate.

[0092] In step S2, a driving circuit layer, a transmission electrode layer and a reflection electrode layer are sequentially stacked on a first base substrate.

[0093] The driving circuit layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel areas; each pixel area includes a transmission area and a reflection area, and in at least one pixel area, the transmission area includes a first area and a second area that are connected, the first area is located between two adjacent reflection areas in the first direction and the length direction of the first area is consistent with the second direction, and the second area is located between two adjacent reflection areas in the second direction and the length direction of the second area is consistent with the first direction; the reflective electrode layer includes a plurality of reflective electrodes, the plurality of reflective electrodes correspond to the plurality of reflection areas one-to-one and respectively cover the corresponding reflection areas, and the transmittance electrode layer includes a plurality of transmittance electrodes, the plurality of transmittance electrodes correspond to the plurality of transmission areas one-to-one, and each transmittance electrode covers at least the corresponding transmittance area.

[0094] Exemplarily, step S2 may include:

[0095] In the first step, an initial gate layer is formed on the first substrate by, for example, deposition, and then a photoresist structure is obtained on the initial gate layer by processes such as photoresist coating, exposure, and development. The initial gate layer is then etched using the photoresist structure as a mask to form a gate layer.

[0096] The second step is to form a gate insulating layer on the gate layer by, for example, deposition. An active layer is then formed on the gate insulating layer. For example, an initial active layer can be deposited on the gate insulating layer, and then a photoresist structure can be obtained by processes such as photoresist coating, exposure, and development. The initial active layer can then be etched using the photoresist structure as a mask to form the active layer.

[0097] In the third step, a source and drain layer is formed on the active layer by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping.

[0098] Step 4: Form an initial passivation layer on the second source and drain electrode pattern layer, for example, by deposition. A series of processes, including photoresist coating, exposure, etching, and stripping, are used to form multiple vias exposing the source and drain electrode layers, thereby forming a passivation layer. An initial transmissive electrode layer is formed on the passivation layer, for example, by deposition. A photoresist structure is formed on the initial transmissive electrode layer through processes including photoresist coating, exposure, and development. The initial transmissive electrode layer is then etched using this photoresist structure as a mask to form a transmissive electrode layer. The transmissive electrode layer is electrically connected to the source and drain electrode layers through the vias in the passivation layer.

[0099] Step 5: Form an initial planarization layer on the transmissive electrode layer, for example, by deposition. The planarization layer is formed through a series of processes, including photoresist coating, exposure, etching, and stripping. An initial reflective electrode layer is formed on the planarization layer, for example, by deposition. A photoresist structure is formed on the initial reflective electrode layer through processes including photoresist coating, exposure, and development. The initial reflective electrode layer is then etched using this photoresist structure as a mask to form the reflective electrode layer.

[0100] The materials of each layer are as described in the above embodiments and will not be described again here.

[0101] Figure 9 is a schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure. As shown in Figure 8 , the display panel includes a first substrate 1 and a second substrate 2 disposed opposite each other, and a liquid crystal layer 3 positioned between the first substrate 1 and the second substrate 2. The first substrate 1 is the aforementioned array substrate 1. This display panel has the same effects as the aforementioned array substrate 1 and will not be further described here.

[0102] FIG10 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, and FIG11 is a schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG9 and FIG11, the second substrate 2 includes a second base substrate 21 and a light-shielding layer 22 and a color filter layer 23 stacked on the second base substrate 21. The color filter layer 23 includes a plurality of color blocks arranged in an array along a first direction x and a second direction y. The plurality of color blocks correspond one-to-one to a plurality of pixel areas, and a color block is provided in each pixel area. The colors of the two adjacent color blocks in the second direction y are the same. For example, as shown in FIG9, the plurality of color blocks arranged along the second direction y can be an integrated structure. As shown in FIG11, the colors of the two adjacent color blocks in the first direction x are different.

[0103] 10 and 11 , the light shielding layer 22 includes a plurality of light shielding strips 221. The plurality of light shielding strips 221 are positioned between the plurality of color resist blocks. The plurality of light shielding strips 221 are arranged in parallel and spaced apart, extending along the second direction y. As previously described, because the orthographic projection of the data line 122 on the first base substrate partially overlaps with the orthographic projection of the reflective electrode 140 on the first base substrate, and the data line 122 is positioned between the first base substrate and the reflective electrode 140, the data line 122 can be shielded by the reflective electrode 140, eliminating the need for light shielding strips 221 to shield the data line 122. The light shielding strips 221 and the data line 122 are arranged parallel to each other in the second direction y.

[0104] For color display panels, since adjacent pixel regions in the second direction y correspond to the same color and there is no risk of cross-coloring, it is possible to omit the light-shielding strips extending along the first direction x and only provide light-shielding strips extending along the second direction y. The width of the light-shielding strips only needs to consider process alignment deviation and is not limited by the limiting distance, thereby improving the aperture ratio. Here, process alignment deviation refers to the dimensional deviation between the first substrate 1 and the second substrate 2 in directions parallel to the first direction x and the second direction y when they are relatively connected. Optionally, the process alignment deviation is 2μm.

[0105] Optionally, a dimension of the light shielding strip 221 in the first direction x is greater than or equal to 4 μm.

[0106] Optionally, a size of the light shielding strip 221 in the first direction x is smaller than a size of the pixel area in the first direction x.

[0107] Table 1: Improvement ratio of aperture ratio of different PPI products in the embodiment of the present disclosure

[0108] Table 1 shows the aperture ratio improvement achieved by different PPI (Pixels Per Inch) products in the disclosed embodiments. As can be seen from Table 1, compared to related technologies, the aperture ratios of products with PPIs of 150, 200, 250, and 300 in the disclosed embodiments all increased by 17.2%, 24.5%, 32.9%, and 43.1%, respectively. The improvement in aperture ratio was more pronounced for products with higher PPIs.

[0109] Exemplarily, the display panel can adopt a normally white mode, that is, when a voltage is applied, the liquid crystal is opaque and in a dark state, and when no voltage is applied, the liquid crystal is translucent and in a bright state. Because in the normally white mode, the liquid crystal state in the dark state is controlled by the electric field, and the orientation of the liquid crystal molecules is uniformly controlled by the electric field at the step difference position where the transmissive electrode and the reflective electrode overlap, a better contrast can be achieved. In contrast, in the normally black mode, that is, when a voltage is applied, the liquid crystal is translucent and in a bright state, and when no voltage is applied, the liquid crystal is opaque and in a dark state. The brightness of the dark state depends on the initial alignment of the liquid crystal molecules. Alignment unevenness is likely to occur at the step difference position where the transmissive electrode and the reflective electrode overlap, resulting in a certain amount of black state light leakage. The normally black mode is commonly seen in vertical alignment (VA) or electronically controlled birefringence (ECB) display panels, wherein the polarizer of the former is usually a polarizing layer, a 1 / 2 wave plate and a 1 / 4 wave plate, and the polarizer of the latter is usually a polarizing layer and a 1 / 2 wave plate. Normally white mode is commonly seen in twisted nematic (TN) or electrically controlled birefringence display panels, the polarizers of which usually consist of a polarizing layer, a half-wave plate, and a quarter-wave plate.

[0110] In another possible embodiment, if the display panel is a monochrome display (e.g., a black and white display), the second substrate 2 may comprise only a transparent substrate. Since there is no risk of cross-color in the first direction x and the second direction y, a light shielding structure is not required, and the aperture ratio of the monochrome display panel can be close to 100%.

[0111] An embodiment of the present disclosure provides a display device, which includes any one of the aforementioned display panels and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

[0112] For example, the display device provided in the embodiments of the present disclosure is any product or component with a display function, such as an outdoor electronic billboard, an outdoor charging station, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Due to its advantages such as high reliability, excellent outdoor image quality, and low power consumption, the display device is particularly widely used in scenarios such as outdoor electronic billboards and outdoor charging stations.

[0113] The display device has the same effects as the aforementioned display panel, which will not be described in detail here.

[0114] The above are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. An array substrate, characterized in that: The array substrate (1) comprises a first base substrate (11), and a driving circuit layer (12), a transmission electrode layer (13) and a reflection electrode layer (14) sequentially stacked on the first base substrate (11); The driving circuit layer (12) comprises a plurality of gate lines (121) and a plurality of data lines (122), the plurality of gate lines (121) extending along a first direction, the plurality of data lines (122) extending along a second direction, the plurality of gate lines (121) intersecting with the plurality of data lines (122) and defining a plurality of pixel areas; Each of the pixel regions comprises a transmission region and a reflection region, and in at least one of the pixel regions, the transmission region comprises at least one first region and at least one second region connected to each other, the first region is located between two adjacent reflection regions in the first direction and the length direction of the first region is consistent with the second direction, and the second region is located between two adjacent reflection regions in the second direction and the length direction of the second region is consistent with the first direction; The reflective electrode layer (14) comprises a plurality of reflective electrodes (140), the plurality of reflective electrodes (140) correspond one-to-one to the plurality of reflective regions and respectively cover the corresponding reflective regions; the transmissive electrode layer (13) comprises a plurality of transmissive electrodes (130), the plurality of transmissive electrodes (130) correspond one-to-one to the plurality of transmissive regions, and each of the transmissive electrodes (130) at least covers the corresponding transmissive region.

2. The array substrate according to claim 1, characterized in that: In at least one of the pixel regions, the transmission area includes a first region and a second region.

3. The array substrate according to claim 1, characterized in that: The plurality of pixel regions include a first pixel region and a second pixel region adjacent to each other in the first direction, the reflective electrode (140) in the first pixel region is a first reflective electrode, the reflective electrode (140) in the second pixel region is a second reflective electrode, and the transmissive electrode (130) in the first pixel region is a first transmissive electrode; The orthographic projection of the first transmissive electrode on the bearing surface of the first base substrate (11) overlaps with the orthographic projections of the first reflective electrode and the second reflective electrode on the bearing surface of the first base substrate (11).

4. The array substrate according to claim 1, characterized in that: The plurality of pixel regions include a third pixel region and a fourth pixel region adjacent to each other in the second direction, the reflective electrode (140) in the third pixel region is a third reflective electrode, the reflective electrode (140) in the fourth pixel region is a fourth reflective electrode, and the transmissive electrode (130) in the third pixel region is a second transmissive electrode; The orthographic projection of the second transmissive electrode on the bearing surface of the first base substrate (11) overlaps with the orthographic projections of the third reflective electrode and the fourth reflective electrode on the bearing surface of the first base substrate (11).

5. The array substrate according to claim 1, characterized in that: In the first direction, a distance between the reflective areas of two adjacent pixel regions is greater than or equal to 6 μm; In the second direction, a distance between the reflective regions of two adjacent pixel regions is greater than or equal to 6 μm.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The driving circuit layer (12) further comprises a plurality of pixel driving circuits (120), wherein the plurality of pixel driving circuits (120) correspond one-to-one to the plurality of pixel areas; The plurality of pixel driving circuits (120) are respectively located in the reflection areas of the corresponding pixel areas.

7. The array substrate according to claim 6, characterized in that: The array substrate (1) further comprises a passivation layer (15), wherein the passivation layer (15) is located between the driving circuit layer and the transmission electrode layer (13); The passivation layer (15) has a plurality of via holes (150), each of the pixel driving circuits (120) is electrically connected to the corresponding transmission electrode (130) via at least one of the via holes (150), and the via holes (150) are located in the reflection area of ​​the corresponding pixel area.

8. The array substrate according to claim 7, characterized in that: The array substrate (1) further comprises a planarization layer (16), wherein the planarization layer (16) is located between the reflective electrode layer (14) and the transmissive electrode layer (13).

9. The array substrate according to claim 8, characterized in that: The planarization layer (16) comprises a plurality of isolation blocks (160), the plurality of isolation blocks (160) correspond one-to-one to the plurality of pixel regions, and the isolation blocks (160) are respectively located in the corresponding pixel regions; In the same pixel area, the reflective electrode (140) is located on the top surface and the bottom surface of the isolation block (160). At least one of the plurality of side walls, and a side edge of the reflective electrode (140) located on the side wall away from the top surface of the isolation block (160) is connected to the transmission electrode (130).

10. The array substrate according to any one of claims 1 to 5 and claims 7 to 9, characterized in that: The orthographic projection of the data line (122) on the bearing surface of the first base substrate (11) at least partially overlaps with the orthographic projection of the reflective electrode (140) on the bearing surface of the first base substrate (11).

11. The array substrate according to any one of claims 1 to 5 and claims 7 to 9, characterized in that: The reflective electrode layer (14) is made of silver or aluminum.

12. An array substrate, characterized in that: The array substrate comprises a first base substrate (11), and a driving circuit layer (12), a transmission electrode layer (13), and a reflection electrode layer (14) sequentially stacked on the first base substrate (11); the driving circuit layer comprises a plurality of gate lines (121) and a plurality of data lines (122); the plurality of gate lines (121) extend along a first direction; the plurality of data lines (122) extend along a second direction; the plurality of gate lines (121) intersect with the plurality of data lines (122) and define a plurality of pixel areas; The reflective electrode layer (14) comprises a plurality of reflective electrodes (140) arranged in an array, each of the reflective electrodes (140) being located in a corresponding pixel region; The transmission electrode layer (13) comprises a plurality of transmission electrodes (130) arranged in an array, each of the transmission electrodes (130) being located in a corresponding pixel region; A first reflective electrode among the plurality of reflective electrodes (140) and a first transmissive electrode among the plurality of transmissive electrodes (130) are insulated from each other, and an orthographic projection of the first reflective electrode on the first base substrate (11) partially overlaps with an orthographic projection of the first transmissive electrode on the first base substrate (11), the first reflective electrode is located in a first pixel region, the first transmissive electrode is located in a second pixel region, and the first pixel region and the second pixel region are two pixel regions adjacent to each other in the first direction or the second direction.

13. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a first substrate; A driving circuit layer, a transmission electrode layer and a reflection electrode layer are sequentially stacked on one side of the first base substrate; Wherein, the driving circuit layer comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel areas; Each of the pixel regions comprises a transmission region and a reflection region, and in at least one of the pixel regions, the transmission region comprises at least one first region and at least one second region connected to each other, the first region is located between two adjacent reflection regions in the first direction and the length direction of the first region is consistent with the second direction, and the second region is located between two adjacent reflection regions in the second direction and the length direction of the second region is consistent with the first direction; The reflective electrode layer includes a plurality of reflective electrodes, the plurality of reflective electrodes correspond to the plurality of reflective regions one by one and respectively cover the corresponding reflective regions, and the transmissive electrode layer includes a plurality of transmissive electrodes, the plurality of transmissive electrodes correspond to the plurality of transmissive regions one by one, and each of the transmissive electrodes at least covers the corresponding transmissive region.

14. A display panel, characterized in that: The display panel comprises a first substrate (1) and a second substrate (2) arranged opposite to each other, and a liquid crystal layer (3) located between the first substrate (1) and the second substrate, wherein the first substrate (1) is an array substrate (1) according to any one of claims 1 to 12.

15. The display panel according to claim 14, characterized in that: The second substrate includes a transparent substrate; or, The second substrate (2) comprises a second base substrate (21) and a light shielding layer (22) and a color filter layer (23) stacked on the second base substrate (21); the color filter layer (23) comprises a plurality of color blocks arranged in an array along the first direction and the second direction; the plurality of color blocks correspond to the plurality of pixel areas one by one; two color blocks adjacent to each other in the second direction have the same color; and two color blocks adjacent to each other in the first direction have different colors; the light shielding layer (22) comprises a plurality of light shielding strips (221); the plurality of light shielding strips (221) are located between the plurality of color shielding blocks, and the plurality of light shielding strips (221) are arranged in parallel and spaced apart and extend along the second direction.

16. A display device, characterized in that: The display device comprises the display panel as claimed in claim 14 or 15 and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

Images