Coding method, decoding method, and communication apparatus

Abstract

Provided in the embodiments of the present application are a coding method, a decoding method, and a communication apparatus, which can implement high-efficiency coding and decoding. The coding method comprises: performing coding processing on data on the basis of a base matrix, so as to obtain coded data, and sending the coded data, wherein the base matrix has a first sequence which is used for low-bit-rate expansion and has a length of M, a core area matrix of the base matrix has a column grouping feature, there is an association feature between one row and another row, and M is an integer greater than 1.

Description

Coding and decoding method and communication device Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular to encoding and decoding methods and communication devices. Background Art

[0002] Low-density parity check code (LDPC) is a linear block code with a sparse parity check matrix. It not only boasts excellent performance approaching the Shannon limit, but also offers low decoding complexity and a flexible structure. It has been selected by the 3rd Generation Partnership Project (3GPP) as the fifth-generation (5G) data channel coding scheme. The mainstream LDPC codes are all quasi-cyclic (QC) parity check matrices, known as QC-LDPC codes. By setting a shift for each block, they avoid short loops and other loop structures, thereby increasing the code distance.

[0003] The lifting factor supported by 5G ranges from 2 to 384, meaning that encoding / decoding chips are designed based on the maximum supported lifting factor. The LDPC codes supported by enhanced mobile broadband (eMBB) channels have a wide range of code lengths. Therefore, considering chip area, resource idleness, and resource waste, and considering the complexity and large area of ​​row-parallel decoding, the mainstream decoding architecture is block-parallel decoding. However, existing new radio (NR) LDPC codes have random edge relationships between check nodes and variable nodes. When computing resources exceed twice the current lifting factor, adopting block-parallel decoding results in significant computational resource waste. Although the degree of parallelism and computing resources double, throughput still fails to double. Regarding row-parallel decoding, existing NR LDPC codes only have a row-orthogonal structure in the low-rate portion, while the high-rate portion only supports QC block parallelism and cannot support full-row parallel decoding. This results in inconsistent computational units between high and low code rates, resulting in wasted computing resources and sub-optimal throughput.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a coding and decoding method and a communication device, which can achieve high-efficiency coding and decoding through a matrix with a column grouping structure.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, a coding method is provided. The method can be executed by a transmitting device, or by a component of the transmitting device, such as a processor, chip, or chip system of the transmitting device, or by a logic module or software that can realize all or part of the functions of the transmitting device. The method includes: encoding data according to a base matrix to obtain coded data. The core area matrix in the base matrix is ​​divided into S column grouping matrices according to the column number, and the columns of the core area matrix include the information column and the core check column of the base matrix. The base matrix corresponds to a first sequence of length M, and the mth sequence value θ in the first sequence is θ. m Used to indicate the mth row and the θth row of the basis matrix during low bit rate expansion m Elimination is performed on the row; in θ m >0, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s ]; in θ m ≤0, there is a sequence value θ corresponding to the nth row in the basis matrix n ≤0, and the mth row is orthogonal to the nth row; where M is equal to the number of rows of the basis matrix, k s is the number of columns of the s-th column grouping matrix, M, S, k s is an integer greater than 1, 1≤m≤M, θ m <m, 1≤s≤S, 1≤t s ≤k s , m, s, t s ,θ m Integer. Send encoded data.

[0008] Based on this encoding method, the transmitting device utilizes a base matrix having a first sequence for low-code rate expansion, a core area matrix having column grouping characteristics, and a correlation characteristic between rows, to achieve data encoding processing at different code rates, and based on this base matrix, a decoding matrix suitable for a block-parallel decoding architecture and a row-parallel decoding architecture can be generated to achieve high-efficiency decoding.

[0009] In an embodiment of the present application, the sending device that executes the method can be a terminal device or a network device, or a chip (system) or other parts or components that can be set in the terminal device or network device, or an apparatus that includes a terminal device or a network device, without limitation.

[0010] In a possible design, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrix m The number of 1 elements in the row is equal to t s, then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s ], including: if the θth of the sth column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s -1]. Based on this design, the θth order of the grouping matrix in the same column is associated by the sequence value. m The number of elements in a row that are 1 is always greater than the number of elements in the mth row that are 1. Based on this feature, the base matrix can be transformed to obtain a decoding matrix including a first submatrix with both row weight and column weight of 1, so as to improve decoding efficiency.

[0011] In a possible design, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s ], including: if the θth of the sth column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is t s Or 0. Based on this design, the number of elements in the mth row that are 1 in the same column grouping matrix connected by sequence values ​​is equal to the θth row. m The number of elements in a row that are 1 or 0 can be transformed to obtain a base matrix based on this feature, including a decoding matrix having a column grouping structure and each column group including a first submatrix with a column weight equal to 1 and a row weight greater than 1, so as to improve decoding efficiency.

[0012] In one possible design, the S column grouping matrices may have the same number of columns. Based on this design, the number of columns in each of the S column grouping matrices may be different, or some of the column grouping matrices may have the same number of columns while others may have different numbers of columns. This is not a limitation.

[0013] In one possible design, the kth column grouping matrix s The column numbers can be discrete or continuous. Based on this design, the k columns in each column grouping matrix s The column numbers can be continuous or discrete, or some column numbers can be continuous and some column numbers can be discrete, or the column numbers of some column grouping matrices can be discrete and some column grouping matrices can be continuous. There is no limitation on this.

[0014] In one possible design, m>0, the column number of each column grouping matrix in the S column grouping matrices is a column grouping, the row number of the mth row in the base matrix is ​​associated with the grouping number of one or more first column groups, and the grouping number of one or more first column groups is used to determine the column number of the element 1 in the mth row. Based on this design, the transmitting end device can store θ m The column group number of the column group associated with the row with a value greater than 0 represents the position of the element with a value of 1 in the mth row. m For rows ≤0, the sending device stores θ m The column number of the element that is 1 in the row with value ≤ 0.

[0015] In one possible design, when the θ m Sequence value of the row The column with 1 in the mth row is one or more first column groups. Each first column group includes the same column number as the θth column. m The intersection of the column numbers whose elements in the row are 1. That is, when the θth m Sequence value of the row Which columns in the mth row have 1 elements can be determined by the group number associated with the mth row and the θth row. m The column number of the element in the row that is 1 is determined.

[0016] In one possible design, when the θ m Sequence value of the row One or more first columns are grouped into the θth m The subset of columns grouped corresponding to the rows. That is, in the θth m When the row sequence value is greater than 0, the θth m The column grouping associated with a row includes the column grouping associated with the mth row.

[0017] In one possible design, the translation value of the first element is the same as the translation value of the second element, or there is a translation difference between the translation value of the first element and the translation value of the second element, the first element and the second element are elements with a value of 1 located in the same column of the basis matrix, the first element is located in the mth row, and the second element is located in the θth row. m That is, the mth row and the θth row m There is also a corresponding relationship between the row elements and the corresponding translation values.

[0018] In one possible design, when 1<j0≤j≤M, there is at most one sequence value of 0 from the first sequence value to the jth sequence value in the first sequence, and the number of rows associated with the row corresponding to the sequence value of 0 is not a power of 2, and j0 is the first segment position of the sequence value in the first sequence. Based on this design, it is possible to avoid the situation where the number of rows obtained by splitting a row with a sequence value less than or equal to 0 in the core area matrix is ​​not a power of 2 after multiple consecutive splits, thereby reducing the complexity of the decoding architecture. For example, θ m = 0, in the process of splitting the m-th row twice in a row, only one of the two rows generated by the first split is split during the second split, and the other row is not split, so the number of rows obtained by splitting the m-th row is 3, which makes the splitting structure complex and causes additional hardware overhead.

[0019] In a possible design, j0 can satisfy the following relationship: Wherein, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R0 is the first coding rate threshold of the base matrix.

[0020] In one possible design, R0 = 1 / 2, 2 / 3, or 1 / 3.

[0021] In one possible design, where 1≤j≤j1≤M, there is at most one sequence value of 0 among the first through jth sequence values ​​in the first sequence, and the number of rows associated with the row corresponding to the sequence value of 0 is not a power of 2. j1 is the second segment position of the sequence value in the first sequence. This design avoids the situation where rows with sequence values ​​less than or equal to 0 in the core region matrix are split multiple times consecutively, resulting in the number of rows not being a power of 2, thereby reducing the complexity of the decoding architecture.

[0022] In a possible design, j1 can satisfy the following relationship: Wherein, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R1 is the second coding rate threshold of the base matrix.

[0023] In one possible design, R1 = 1 / 2, 2 / 3, or 3 / 4.

[0024] In one possible design, k s =2, 3, or 4.

[0025] In a second aspect, a decoding method is provided. The method can be executed by a receiving device, or by a component of the receiving device, such as a processor, chip, or chip system of the receiving device, or by a logic module or software that can realize all or part of the functions of the receiving device. The method includes: generating a decoding matrix. The decoding matrix is ​​divided into S column grouping matrices according to the column number, and the s-th column grouping matrix in the S column grouping matrices includes multiple first sub-matrices with a column weight less than or equal to 1, and the first sub-matrix is ​​q×k s The matrix, k s is equal to the number of columns of the sth column grouping matrix, s and q are integers greater than 0, S and k s is an integer greater than 1, 1≤s≤S. ​​The coded data is decoded according to the decoding matrix.

[0026] Based on this decoding method, a receiving device can generate a decoding matrix having a column grouping structure, wherein each column group includes a first submatrix with a column weight less than or equal to 1. The fixed grouping structure ensures a fixed degree of parallelism, thereby ensuring consistency of hardware resources and reducing waste of parallelism resources and computing resources. At the same time, the number of elements in the first submatrix with a column weight equal to 1 that are 1 is at least 2, so that at least two elements can be read, calculated, and stored in parallel during decoding, the operation time slots are completely consistent, the decoding complexity is reduced, and the decoding efficiency can be improved. The first submatrix can be applied to row-parallel decoding and block-parallel decoding architectures.

[0027] In an embodiment of the present application, the receiving device that executes the method can be a terminal device or a network device, or a chip (system) or other parts or components that can be set in the terminal device or network device, or an apparatus that includes a terminal device or a network device, without limitation.

[0028] In one possible design, when q=k s In the case of , the number of 1 elements in each row of the first submatrix is ​​1 or 0. Based on this design, the first submatrix can be a matrix with both column and row weights of 1, or a zero matrix with both column and row weights of 0. During decoding, at least two check nodes (the number of rows of the first submatrix) and at least two variable nodes (the number of columns of the first submatrix) can be processed simultaneously, which can improve decoding efficiency.

[0029] In one possible design, when q=1, the number of k in each row of the first submatrix is s The elements are all 1 or 0. Based on this design, the first sub-matrix can be a matrix with column weight 1 and row weight k s The matrix can also be a zero matrix with both column weight and row weight being 0. During decoding, at least two variable nodes (the number of columns of the first submatrix) can be processed simultaneously, which can improve decoding efficiency.

[0030] In a possible design scheme, the decoding matrix can be determined according to the base matrix. The core area matrix in the base matrix is ​​divided into S column grouping matrices according to the column number. The columns of the core area matrix include the information column and the core check column of the base matrix. The base matrix corresponds to a first sequence of length M. The mth sequence value in the first sequence is θ m Used to indicate the mth row and the θth row of the basis matrix during low bit rate expansion m Elimination is performed on the row; in θ m >0, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is [0, t s ]; in θ m ≤0, there is a sequence value θ corresponding to the nth row in the basis matrix n ≤0, and the mth row is orthogonal to the nth row; wherein M is equal to the number of rows of the basis matrix, and the number of columns of the sth column grouping matrix of the core region matrix is ​​equal to k s , M is an integer greater than 1, 1≤m≤M, 1≤n≤M, m≠n, θ m <m, 1≤t s ≤k s , m, n, t s ,θ m is an integer. Based on this design, the decoding matrix can be generated based on a base matrix having a first sequence for low-code rate expansion, a core area matrix having column grouping characteristics, and a correlation feature between rows. The decoding matrix generated by low-code rate expansion according to the first sequence has a highly parallel feature in the expanded rows. Under the row-parallel decoding architecture, high hardware utilization and low-complexity decoding can be achieved; under the block-parallel decoding architecture, the number of equivalent QC blocks for decoding is small (one submatrix corresponds to one QC block), that is, the equivalent QC block density is small, which can improve hardware utilization and achieve low-complexity decoding.

[0031] In a possible design, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is [0, t s ], including: if the sth column grouping matrix of the core region matrix is ​​θth m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is [0, t s -1].

[0032] In a possible design, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is [0, t s ], including: if the sth column grouping matrix of the core region matrix is ​​θth m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is t s or 0.

[0033] In a possible design, the S column grouping matrices of the core region matrix may have the same number of columns.

[0034] In one possible design, the kth column of the core region matrix is ​​grouped by s The column numbers can be discrete or continuous.

[0035] In one possible design, m >0, the column number of each column grouping matrix in the S column grouping matrices of the core region matrix is ​​a column grouping, the row number of the m-th row in the base matrix is ​​associated with the grouping number of one or more first column groups, and the grouping number of one or more first column groups is used to determine the column number of the element 1 in the m-th row.

[0036] In one possible design, when the θ m Sequence value of the row The column with 1 in the mth row is one or more first column groups. Each first column group includes the same column number as the θth column. m The intersection of the column numbers where the elements in the rows are 1.

[0037] In one possible design, when the θ m Sequence value of the row One or more first columns are grouped into the θth m The rows correspond to a subset of the column groupings.

[0038] In one possible design, the translation value of the first element is the same as the translation value of the second element, or there is a translation difference between the translation value of the first element and the translation value of the second element, the first element and the second element are elements with a value of 1 located in the same column of the basis matrix, the first element is located in the mth row, and the second element is located in the θth row. m OK.

[0039] In one possible design scheme, when 1<j0≤j≤M, there is at most one sequence value with a value of 0 among the 1st sequence value to the jth sequence value in the first sequence, and the number of rows associated with the row corresponding to the sequence value with a value of 0 is not a power of 2, and j0 is the first segment position of the sequence value in the first sequence.

[0040] In a possible design, j0 can satisfy the following relationship: Wherein, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R0 is the first coding rate threshold of the base matrix.

[0041] In one possible design, R0 = 1 / 2, 2 / 3, or 1 / 3.

[0042] In one possible design scheme, when 1≤j≤j1≤M, there is at most one sequence value with a value of 0 from the 1st sequence value to the jth sequence value in the first sequence, and the number of rows associated with the row corresponding to the sequence value with a value of 0 is not a power of 2, and j1 is the second segment position of the sequence value in the first sequence.

[0043] In a possible design, j1 can satisfy the following relationship: Wherein, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R1 is the second coding rate threshold of the base matrix.

[0044] In one possible design, R1 = 1 / 2, 2 / 3, or 3 / 4.

[0045] In one possible design, k s =2, 3, or 4.

[0046] In a third aspect, a communication device is provided. The communication device includes: a module, unit, or means for executing the method described in the first aspect or the second aspect, and the module, unit, or means can be implemented by hardware, software, or by executing the corresponding software implementation through hardware. The hardware or software includes one or more modules or units corresponding to the above functions, such as a transceiver module and a processing module. For example, the transceiver module is used to indicate the transceiver function of the communication device, and the processing module is used to perform functions of the communication device other than the transceiver function.

[0047] In one possible design solution, the transceiver module may include a receiving module and a sending module, wherein the sending module is used to implement the sending function of the communication device described in the third aspect, and the receiving module is used to implement the receiving function of the communication device described in the third aspect.

[0048] In one possible design, the communication device described in the third aspect may further include a storage module that stores a program or instruction. When the processing module executes the program or instruction, the communication device described in the third aspect may execute the method described in the first aspect or the second aspect.

[0049] Among them, the communication device described in the third aspect can be a terminal device or a network device, or it can be a chip (system) or other parts or components that can be set in the terminal device or network device, or it can be a device that includes a terminal device or a network device. This application does not limit this.

[0050] In a fourth aspect, a communication device is provided, comprising: a processor and a communication interface; the communication interface is used to communicate with a module outside the communication device; the processor is used to execute a computer program or instruction so that the communication device executes the method described in the first or second aspect above.

[0051] In a fifth aspect, a communication device (for example, the communication device may be a chip or a chip system) is provided, which includes a processor for implementing the functions involved in the first or second aspect above.

[0052] In some possible designs, the communication device includes a memory for storing necessary program instructions and / or data.

[0053] In one possible design, the processor can be integrated with the memory.

[0054] In some possible designs, when the communication device is a chip system, it can be composed of a chip, or it can include a chip and other discrete devices.

[0055] In a sixth aspect, a communication device is provided, comprising: a transceiver and a processor, wherein the transceiver is used to exchange information between the communication device and other communication devices, and the processor executes program instructions to perform the method described in the first or second aspect.

[0056] In one possible design, the communication device described in aspect 6 may further include a memory. The memory may be integrated with the processor or provided separately. The memory may be used to store the computer program and / or data involved in the method described in aspect 1 or aspect 2 above.

[0057] It should be understood that the fourth to sixth aspects above include modules, units, or means corresponding to the methods described in the first or second aspects above, and the modules, units, or means may be implemented by hardware, software, or by hardware executing the corresponding software implementation. The hardware or software includes one or more modules or units for performing the functions involved in the above methods.

[0058] It can be understood that when the communication device provided in any one of the fourth to sixth aspects is a chip, the above-mentioned sending action / function can be understood as output, and the above-mentioned receiving action / function can be understood as input.

[0059] In a seventh aspect, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer-readable storage medium is run on a communication device, the communication device can execute the method described in the first or second aspect above.

[0060] In an eighth aspect, a computer program product comprising instructions is provided, which, when executed on a communication device, enables the communication device to execute the method described in the first or second aspect above.

[0061] In a ninth aspect, a communication system is provided, comprising a transmitting device for executing the method described in the first aspect and a receiving device for executing the method described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic diagram of the structure of a base matrix corresponding to a NR LDPC code check matrix;

[0063] Figure 2 is a Tanner graph corresponding to a NR LDPC code check matrix;

[0064] FIG3 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0065] FIG4 is a schematic diagram of the structure of an encoding-decoding architecture provided in an embodiment of the present application;

[0066] FIG5 is a flow chart of a coding method according to an embodiment of the present application;

[0067] FIG6 is a schematic structural diagram of a core region matrix of a base matrix provided in an embodiment of the present application;

[0068] FIG7 is a schematic structural diagram of a core region matrix of another base matrix provided in an embodiment of the present application;

[0069] FIG8 is a schematic diagram of a splitting process during low bit rate expansion provided by an embodiment of the present application;

[0070] FIG9 is a schematic diagram of the structure of a decoding matrix provided in an embodiment of the present application;

[0071] FIG10 is a schematic diagram of the structure of another decoding matrix provided in an embodiment of the present application;

[0072] FIG11 is a schematic structural diagram of a decoding matrix obtained based on base matrix transformation according to an embodiment of the present application;

[0073] FIG12 is a diagram showing simulation results of the corresponding relationship between the number of equivalent QC blocks and the encoding bit rate based on the decoding matrix and NR LDPC BG decoding according to an embodiment of the present application;

[0074] FIG13 is a simulation result diagram showing the correspondence between the number of equivalent decoding rows and the encoding bit rate based on the decoding matrix and NR LDPC BG decoding under a row-parallel decoding architecture provided by an embodiment of the present application;

[0075] FIG14 is a simulation result diagram showing the corresponding relationship between the SNR and the coding rate required for the block error rate to reach 0.01 based on the decoding matrix and NR LDPC BG decoding according to an embodiment of the present application;

[0076] FIG15 is a simulation result diagram showing the corresponding relationship between the SNR and the information length required for achieving a block error rate of 0.01 based on the decoding matrix and NR LDPC BG decoding under different code rates provided by an embodiment of the present application;

[0077] FIG16 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0078] FIG17 is a schematic structural diagram of another communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to better understand the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0080] First, in the embodiments of the present application, "used to indicate" can include being used for direct indication and being used for indirect indication. When describing a certain "indication information" as being used to indicate A, it can include the indication information directly indicating A or indirectly indicating A, and does not necessarily mean that the indication information carries A.

[0081] The information indicated by the indication information is called the information to be indicated. In the specific implementation process, there are many ways to indicate the information to be indicated, such as but not limited to, directly indicating the information to be indicated, such as the information to be indicated itself or the index of the information to be indicated. The information to be indicated can also be indirectly indicated by indicating other information, wherein there is an association between the other information and the information to be indicated. It is also possible to indicate only a part of the information to be indicated, while the other parts of the information to be indicated are known or agreed in advance. For example, it is also possible to use the arrangement order of each piece of information agreed in advance (such as specified in the protocol) to achieve the indication of specific information, thereby reducing the indication overhead to a certain extent. At the same time, it is also possible to identify the common parts of each piece of information and indicate them uniformly to reduce the indication overhead caused by indicating the same information separately.

[0082] In addition, the specific indication method can also be various existing indication methods, such as but not limited to the above-mentioned indication methods and various combinations thereof. The specific details of the various indication methods can be referred to the prior art and will not be repeated herein. As can be seen from the above, for example, when it is necessary to indicate multiple information of the same type, there may be a situation where the indication methods for different information are different. In the specific implementation process, the required indication method can be selected according to specific needs. The embodiment of the present application does not limit the selected indication method. In this way, the indication method involved in the embodiment of the present application should be understood to cover various methods that can enable the party to be indicated to obtain the information to be indicated.

[0083] Second, in the embodiments of the present application, the first, second, and various numerical numbers are merely distinctions made for ease of description and are not intended to limit the scope of the embodiments of the present application. For example, different indication information is used to distinguish one from another. For another example, the first indication information and the second indication information are merely used to distinguish different areas and do not limit their order of precedence. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and order of execution, and words such as "first" and "second" do not necessarily limit them to be different.

[0084] Third, in the embodiments of the present application, descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device (such as a terminal device or a network device) will make corresponding processing under certain objective circumstances. It does not limit the time, and does not require the device (such as a terminal device or a network device) to perform a judgment action when implementing it, nor does it mean that there are other limitations.

[0085] At the same time, in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0086] Fourth, the technical solutions of the embodiments of the present application can be applied to various communication systems, such as wireless fidelity (Wi-Fi) systems, vehicle to everything (V2X) communication systems, device-to-device (D2D) communication systems, Internet of Vehicles communication systems, 4th generation (4G) mobile communication systems, such as long term evolution (LTE) systems, world-wide interoperability for microwave access (WiMAX) communication systems, 5G mobile communication systems, such as NR systems, and future communication systems, such as 6th generation (6G) mobile communication systems.

[0087] In particular, this application will present various aspects, embodiments, or features around systems that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. Furthermore, combinations of these aspects may also be used.

[0088] Finally, the network architecture and business scenarios described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0089] The following describes the related technologies involved in the embodiments of this application.

[0090] 1. LDPC code check matrix

[0091] LDPC code is a linear block code, which is determined by a sparse matrix H with M rows and N columns. H consists of elements 0 and 1. Since most elements in the matrix are 0 except for a few 1s, it is called a sparse matrix. The sparse matrix H can also be called the LDPC code check matrix. H meets the following conditions: the ratio of the matrix row weight (the number of 1s in each row) and column weight (the number of 1s in each column) to the code length is much less than 1; any two rows (columns) have at most one 1 in the same position; and the number of any linearly independent columns is as large as possible.

[0092] QC-LDPC code is a subclass of LDPC code, and its check matrix H has a cyclic property. The check matrix H of a QC-LDPC code can usually be expressed as the following array:

[0093] Among them, each matrix A i,j Both are circulant matrices of size Z×Z. If the number of rows and columns of the parity check matrix H is denoted by M = ρZ and N = cZ, respectively, the length of the information sequence packet to be transmitted is K = NM. The transmitter needs to use the parity check matrix to encode the information sequence packet to be transmitted, and the receiver also needs to decode it based on the parity check matrix. The design process of QC-LDPC codes involves three key concepts: the circular permutation matrix (CPM), the base graph (BG), and the base matrix.

[0094] There are many ways to construct a check matrix for a QC-LDPC code. One possible method for constructing a check matrix for a quasi-cyclic LDPC code is to first construct a basis matrix B of size ρ×c, for example:

[0095] The fundamental mode graph of a QC-LDPC code is a matrix of the same size as the base matrix, with elements that are either 0 or 1: a "1" indicates that the shifting value (also called translation value) at the corresponding position in the base matrix is ​​not equal to -1; a "0" indicates that the shifting value at the corresponding position in the base matrix is ​​-1. For example, the fundamental mode graph of the base matrix in the above example is:

[0096] Then, each non-"-1" element in the basis matrix B is expanded into a circulant permutation matrix of size Z×Z, and the "-1" element is expanded into a full-zero matrix of size Z×Z. Assume that P is used i represents a Z×Z circulant permutation matrix, also called a subcirculant matrix of the basis matrix, and i is called P i For example:

[0097] Take Z=8 as an example:

[0098] It can be seen that P 0 is the identity matrix, each cyclic permutation matrix P i In fact, it is obtained by cyclically shifting the unit matrix right by i positions. Moreover, for a given Z, there are Z P i , that is, i∈{0,1,2,…,Z-1}. Each P i (0≤i<Z) is used to expand the elements with value i in the basis matrix B.

[0099] In this way, different parts of the base matrix B can be intercepted and expanded into corresponding check matrices according to different code rates, where a maximum check matrix of (ρZ)×(cZ) can be obtained; thus, the information sequence to be transmitted can be encoded and decoded at different code rates based on the different check matrices obtained.

[0100] For example, Figure 1 is a schematic structural diagram of a base matrix corresponding to an NR LDPC code check matrix provided in an embodiment of the present application. As shown in (a) in Figure 1, the base matrix is ​​divided into a high rate region, an incremental redundancy region, a 0 matrix region, and an extended / expanded node region (raptor-like region). In practical applications, the first X rows and Y columns of the base matrix can be intercepted. As X and Y gradually increase, the code rate decreases from high to low, so that the area where the matrix is ​​used gradually expands. Thus, the intercepted matrix part can be expanded to a check matrix.

[0101] Furthermore, (b) in Figure 1 is a possible structure of the base matrix. As shown in (b) in Figure 1, A and B together constitute the core matrix of the high code rate, A corresponds to the information bits to be encoded, B is a square matrix, and the B matrix has a dual diagonal structure, corresponding to the check bits of the high code rate. C is an all-zero matrix. E is a unit matrix, corresponding to the check bits of the low extended code rate. D and E together constitute a single parity check relationship. As of now, the 3GPP radio access network (RAN)1 stipulates that two base matrices with a length x width of 46×68 and 42x52 respectively are used in the eMBB scenario to support large code length and high code rate and medium and low code length and low code rate coding, respectively.

[0102] Since NR LDPC codes support shortening (shortening by zero padding) and puncturing operations during the encoding process, the base matrix of some NR LDPC codes may also include the number of information bit puncturing bits, the number of information bit shortening bits, and the number of parity bit puncturing bits.

[0103] In the embodiment of the present application, the information bits are information bits encoded for LDPC codes, which can be information bits to be sent, or information bits to be sent after including CRC check bits, and there is no limitation on this.

[0104] 2. Tanner graph

[0105] The LDPC code check matrix can be defined by the Tanner graph corresponding to the LDPC code check matrix. For example, an example of an LDPC code check matrix and its corresponding check equation is:

[0106] Here, "+" represents modulo 2 addition. The Tanner graph corresponding to this check matrix can be represented as shown in Figure 2. Each circular node in Figure 2 (such as v0 to v9) is a variable node, representing a column in the check matrix H, and each square node is a check node (such as c0 to c4), representing a row in the check matrix H. Each edge connecting a check node and a variable node in Figure 2 (i.e., a connecting edge) represents the presence of a non-zero element at the intersection of the row and column corresponding to these two nodes.

[0107] NR LDPC codes support a lifting value / lifting factor / expansion factor (Lifting Size) range of 2-384. This means that chips are designed for the maximum supported Lifting Size. If the current Lifting Size is less than 384 during actual decoding, the excess storage and computing resources are wasted. Currently, eMBB channels support a wide range of LDPC code lengths. Therefore, considering chip area and resource idleness or waste, the mainstream decoding architecture is block-parallel decoding, in which all non-zero elements in the parity check matrix are decoded together. In high-throughput, low-latency scenarios requiring high-speed parallel decoding, a row-parallel decoding architecture is used, in which multiple orthogonal rows in the parity check matrix are decoded together.

[0108] For the block-parallel decoding architecture, the throughput calculation method for decoding based on the existing NR LDPC code is:

[0109] Among them, N ldpc is the code length, N frame is the number of packets decoded simultaneously, f clk is the clock number, f clk is the operating frequency, N iteration is the number of decoding iterations, N Zc is the number of QC blocks using the decoding matrix, C layer is the number of decoding clocks for the decoding line. The part that mainly affects the throughput is N Zc, which is the number of non-zero values ​​in the decoding matrix during a decoding iteration. Under the block-parallel decoding architecture, the existing NR LDPC code parity check matrix has highly random edge relationships. If computing resources exceed twice the current Lifting Size or in high-throughput scenarios (to achieve decoding with minimal latency), multi-block parallel decoding is employed, wasting significant computing resources. Although the degree of parallelism and computing resources are doubled, the actual throughput does not double.

[0110] For the row-parallel decoding architecture, the throughput calculation method for decoding based on the NR LDPC code check matrix is:

[0111] Among them, N layer =Equivalent number of decoding rows. Existing NR LDPC codes have significant limitations on decoding architecture. The high-rate portion (core portion) can only support parallel decoding of QC blocks, not full-row parallel decoding. While the low-rate portion (orthogonal (RO) portion) supports two-row parallel decoding, the computational units cannot be kept constant for high and low rates, resulting in significant area waste. Peak throughput cannot reach 100 gigabits per second (Gbps), leading to significant decoding latency.

[0112] To address the problem that existing NR LDPC codes cannot achieve efficient decoding for both block-parallel and row-parallel decoding, the embodiments of the present application provide an encoding method and a decoding method for LDPC codes based on column grouping, which can achieve high hardware utilization and low-complexity decoding under both block-parallel decoding architectures and row-parallel decoding architectures.

[0113] For example, Figure 3 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application. As shown in Figure 3, the communication system includes a network device and a terminal device. The network device and the terminal device can communicate directly with each other or forward the communication through other devices. It should be noted that Figure 3 exemplarily shows one network device and one terminal device, and the embodiment of the present application does not limit the number of network devices and terminal devices.

[0114] In the embodiment of the present application, the network device may also be referred to as a RAN node, an access network device, a RAN entity or an access node, etc., which is located on the network side of the above-mentioned communication system to help the terminal device achieve wireless access, and has a device with wireless transceiver function or a chip or chip system that can be set in the device. The network device includes but is not limited to: a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a next-generation base station in a 6G mobile communication system, a base station in a future mobile communication system, or an access node in a Wi-Fi system, etc. The network device may be a macro base station, a micro base station or an indoor station, a relay node or a donor node, or a wireless controller in a centralized radio access network (CRAN) scenario. Optionally, the RAN node may also be a server, a wearable device, a vehicle or an on-board device, etc. For example, the access network device in the V2X technology may be a road side unit (RSU). All or part of the functions of the network device in this application may also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (such as a cloud platform). The network device in this application may also be a logical node, logical module, or software that can implement all or part of the network device functions.

[0115] In another possible scenario, multiple RAN nodes collaborate to assist terminal devices in achieving wireless access, and different RAN nodes respectively implement part of the functions of the base station. For example, the RAN node can be a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU can be set separately, or they can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0116] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in an open (open, O)RAN system, CU may also be called O-CU (open CU), DU may also be called O-DU, CU-CP may also be called O-CU-CP, CU-UP may also be called O-CU-UP, and RU may also be called O-RU. For the convenience of description, this application uses CU, CU-CP, CU-UP, DU and RU as examples for description. Any unit of CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0117] In the embodiment of the present application, the terminal device is a terminal that accesses the above-mentioned communication system and has a wireless transceiver function or a chip or chip system that can be set in the terminal. The terminal device can also be called a user device, an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent or a user device. The terminal device in the embodiment of the present application can be a mobile phone, a tablet computer, a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical care, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a vehicle-mounted terminal, an RSU with terminal function, etc. The terminal device of the present application can also be a vehicle-mounted module, vehicle-mounted module, vehicle-mounted component, vehicle-mounted chip or vehicle-mounted unit that is built into the vehicle as one or more components or units. The vehicle can implement the method provided by the present application through the built-in vehicle-mounted module, vehicle-mounted module, vehicle-mounted component, vehicle-mounted chip or vehicle-mounted unit.

[0118] It should be noted that the solutions in the embodiments of the present application can also be applied to other communication systems, and the corresponding names can also be replaced by the names of corresponding functions in other communication systems.

[0119] For example, FIG4 is a schematic diagram of the structure of a coding-decoding architecture provided in an embodiment of the present application. As shown in FIG4 , the transmitting device performs source coding, channel coding, and modulation processing on the source data to obtain coded data, and sends the coded data to the receiving device through a wireless channel. Accordingly, the receiving device can demodulate, channel decode, and recover the source of the received coded data to obtain the source data. The transmitting device can be the network device shown in FIG3 , and the receiving device can be the terminal device shown in FIG4 ; or, the transmitting device can be the terminal device shown in FIG3 , and the receiving device can be the network device shown in FIG4 .

[0120] It should be understood that Figure 4 is only a simple example. In a specific implementation, other possible steps can be added on the basis of Figure 4, such as radio network temporary identity (RNTI) scrambling, rate matching, descrambling, rate dematching, etc., without specific limitation.

[0121] In the embodiment of the present application, the coding and modulation process or the decoding and demodulation process can be implemented by an application specific integrated circuit (ASIC) chip or a field programmable gate array (FPGA) chip, or by software (program code in a memory).

[0122] The encoding method and decoding method provided in the embodiments of the present application will be described in detail below with reference to Figures 5-15.

[0123] For example, Figure 5 is a flowchart of a coding method provided by an embodiment of the present application. The coding method can be executed by a transmitting device or a chip provided in the transmitting device, and the transmitting device can be the network device or terminal device shown in Figure 3.

[0124] As shown in FIG5 , the encoding and decoding method includes the following steps:

[0125] S501: A transmitting end device encodes data according to a basis matrix to obtain encoded data.

[0126] In the embodiment of the present application, both the transmitting and receiving devices locally store a base matrix. For the transmitting device, the base matrix can be used for data encoding, and for the receiving device, the base matrix can be used for data decoding. The base matrix can be the base matrix corresponding to the check matrix used for encoding or decoding, or the base matrix can be the base matrix corresponding to the check matrix used for encoding or decoding obtained after transformation processing (such as elimination, puncturing, or merging, etc.). The base matrix is ​​lifted / expanded to obtain the check matrix, which is not limited. The following takes the size of the base matrix as M×N as an example, where M is the number of rows of the base matrix, N is the number of columns of the base matrix, and M and N are integers greater than 1. In the embodiment of the present application, the base matrix is ​​a matrix of size M×N composed of 0 and 1.

[0127] Among them, the core area matrix of the base matrix is ​​divided into S column grouping matrices according to the column number, where S is an integer greater than 1. The columns of the core area matrix include information columns and core check columns of the base matrix. The number of information columns corresponds to the number of information bits to be encoded, such as the number of columns corresponding to area A in (b) of Figure 1, and the number of core check columns corresponds to the number of check bits in the non-raptor-like area, such as the number of columns corresponding to area B in (b) of Figure 1. In other words, the core area matrix of the base matrix in the embodiment of the present application has a column grouping feature.

[0128] For example, the size of the core region matrix is ​​M×(K+L), where K is the number of information columns of the base matrix, L is the number of core check columns of the base matrix, and K and L are integers greater than or equal to 1. The core region matrix includes a high code rate region, such as the A+B+D region in (b) of FIG1 .

[0129] For any column grouping matrix among the S column grouping matrices, such as the s-th column grouping matrix, its matrix size is M×k s , where k s is the number of columns of the s-th column grouping matrix, 1≤s≤S, s is an integer, k s is an integer greater than 1. For example, k s The value can be 2, 3, or 4.

[0130] Correspondingly, the column number of each column grouping matrix in the S column grouping matrices is a column grouping. In other words, the column numbers of the core region matrix in the base matrix are divided into S column groups, where a column grouping includes the column numbers of the columns included in a column grouping matrix in the base matrix, and the s-th column grouping includes the column numbers of the columns included in the s-th column grouping matrix in the base matrix.

[0131] In one possible design, the number of columns in each of the S column grouping matrices may be the same. In other words, the S column grouping matrices may be evenly divided by the number of columns. For example, the number of columns in each of the S column grouping matrices is k, i.e., ks =k, k×S=K+L<N, k is an integer greater than or equal to 1.

[0132] In this design, the k columns in each column grouping matrix can be continuous or discrete, or some column numbers can be continuous and some column numbers can be discrete, or some column grouping matrices can have discrete column numbers and some column grouping matrices continuous column numbers, without limitation. For example, the core region matrix has K + L = 12 columns, with column numbers 0 to 11 or 1 to 12. For example, with column numbers 1 to 12 and k = 3, S = 4. If the k column numbers in each column grouping matrix are continuous, the column numbers corresponding to the first column grouping matrix (such as S1) are 1 to 3, forming column group 1 {1, 2, 3}, the column numbers corresponding to the second column grouping matrix (such as S2) are 4 to 6, forming column group 2 {4, 5, 6}, the column numbers corresponding to the third column grouping matrix (such as S3) are 7 to 9, forming column group 3 {7, 8, 9}, and the column numbers corresponding to the fourth column grouping matrix (such as S4) are 10 to 12, forming column group 4 {10, 11, 12}. If the k column numbers in each column grouping matrix are discrete, for example, the first column grouping matrix (such as S1) corresponds to column numbers 1, 7, and 9, constituting column group 1 {1, 7, 9}, the second column grouping matrix (such as S2) corresponds to column numbers 2, 5, and 10, constituting column group 2 {2, 5, 10}, the third column grouping matrix (such as S3) corresponds to column numbers 3, 6, and 11, constituting column group 3 {3, 6, 11}, and the fourth column grouping matrix (such as S4) corresponds to column numbers 4, 8, and 12, constituting column group 4 {4, 8, 12}. If the k column numbers in each column grouping matrix are partially continuous and partially discrete, for example, the column numbers corresponding to the first column grouping matrix (such as S1) are 1, 2, and 9, forming column grouping 1 {1, 2, 9}, the column numbers corresponding to the second column grouping matrix (such as S2) are 3, 4, and 10, forming column grouping 2 {3, 4, 10}, the column numbers corresponding to the third column grouping matrix (such as S3) are 5, 6, and 11, forming column grouping 3 {5, 6, 11}, and the column numbers corresponding to the fourth column grouping matrix (such as S4) are 7, 8, and 12, forming column grouping 4 {7, 8, 12}.

[0133] In another possible design, at least two of the S column grouping matrices can have different numbers of columns. In other words, the number of columns in each of the S column grouping matrices can be different, or some column grouping matrices can have the same number of columns while others can have different numbers of columns. For example, S = 4, the number of columns in the core region matrix K + L = 12, and the number of columns in the four column grouping matrices (k1-k4) is 2, 2, 4, and 4, respectively.

[0134] In this design, the column numbers in each column grouping matrix can be continuous or discrete, or some column numbers can be continuous and some column numbers can be discrete, or some column grouping matrices can have discrete column numbers and some column grouping matrices can have continuous column numbers. This is not limited to any particular embodiment. For details, please refer to the relevant description in the above design and will not be repeated here.

[0135] The base matrix (or core region matrix) corresponds to a first sequence of length M. The mth sequence value θ in the first sequence is m Used to indicate the mth row and the θth row of the basis matrix during low bit rate expansion m Eliminate the variables in the row, where 1≤m≤M, θ m <m,θ m is an integer. That is, each row of the basis matrix corresponds to a sequence value θ m , there are M sequence values ​​in total, i.e., the length of the first sequence is M, and the size of the sequence value corresponding to the mth row is the row number of the row that undergoes elimination with the mth row. It should be understood that in this embodiment of the application, the mth row of the basis matrix is ​​also the mth row of the core region matrix.

[0136] Exemplarily, the first sequence corresponding to the base matrix is ​​as shown in Table 1 below. Each sequence value in the first sequence corresponds to an identifier (identify, ID) (or serial number), which is used to indicate the row number corresponding to the sequence value. For example, if ID=4 and θ4=1, it means that when the base matrix is ​​expanded at a low bit rate, the 4th row and the 1st row are eliminated.

[0137] Table 1

[0138] In the embodiment of the present application, the first sequence is used to perform low-rate transformation processing on the base matrix. The base matrix is ​​transformed according to the first sequence to obtain a matrix that meets the code rate requirements. m Elements in the same column of a row are added modulo 2 (i.e., XORed).

[0139] In the sequence value θ m > 0, it means that there is a row in the basis matrix that is eliminated with the mth row, and the row number of the row that is eliminated with the mth row is one of [1, m-1], that is, θ m ∈[1, m-1], it can be considered that the mth row and the θth row m The rows are related.

[0140] As shown in FIG6 (a), the number of rows of the base matrix M = 8, the number of columns of the core region matrix in the base matrix K + L = 6, the number of column grouping matrices S = 3, and the number of columns of each column grouping matrix in the S column grouping matrices is the same, that is, k s=2, and the column numbers of each column grouping matrix are continuous. For example, the first sequence corresponding to the basis matrix is ​​{0, 0, 0, 1, 2, 3, 0, 4}. The sequence value θ4 corresponding to the 4th row (ID = 4) in the basis matrix is ​​1. That is, when the basis matrix is ​​subjected to low bit rate expansion, the 4th row and the 1st row are eliminated. That is, the elements 1, 1, 1, 1, 1 in the 1st row are eliminated with the elements 1, 0, 1, 0, 0, 1 in the 4th row. The structure of the basis matrix after elimination is shown in (b) of FIG6 . The elements in the 1st row become 0, 1, 0, 1, 1, 0, and the elements in the 4th row remain unchanged.

[0141] It can be seen that the element in the column where the element that is 1 in the 4th row after elimination is located has an element at the corresponding position in the 1st row that is 0, and the union of the column number where the element that is 1 in the 1st row after elimination is located and the column number where the element that is 1 in the 4th row is located is the column number where the element that is 1 in the 1st row before elimination is located. Therefore, the 1st row and the 4th row after elimination (the 1st row and the 4th row in (b) in Figure 6) can be considered to be obtained by splitting the elements in the 1st row before elimination (the 1st row in (a) in Figure 6), and the split result is obtained by elimination. It should be understood that in the embodiment of the present application, the θth element in the core area matrix in the base matrix m When the element in the zth column of the row is 0, the element in the zth column of the mth row cannot usually be 1. If elimination is performed based on this, it will result in the θth m The element in the zth column of the row is 1. This situation does not satisfy the splitting property. z is an integer, 1≤z≤K+L.

[0142] It should be noted that the examples involved in the embodiments of the present application are shown in Figure 6, as well as the following Figures 7 and 11, which are all based on the elimination process of the core area of ​​the basis matrix (such as the A+B+D area shown in (b) of Figure 1). In the process of complete elimination of the basis matrix, if the basis matrix is ​​the structure of A+B+D+C+E shown in (b) of Figure 1, in θ m > 0, the θth m The same elimination process as the core area is also performed on the row and the mth row. If the element in the pth column (p is an integer greater than K+L) of the mth row in the expanded part is 1, after elimination, the 1 element will also appear in the θth column after elimination. m row and the pth column of the mth row.

[0143] In the embodiment of the present application, the θth m The elimination process of the mth row and the mth row can also be called the θth m After intercepting some rows and columns of the basis matrix, we can split the θth m The row is split and expanded to obtain a new row (i.e., the mth row), and the θth row of the basis matrixm The row can be called the θth row of the matrix obtained after splitting. m The parent node (or root node) of the row and the mth row, the θth matrix obtained after splitting m The row and the mth row can be called the θth row of the basis matrix m In this case, if the θth row of the sth column grouping matrix in the S column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s ], 1≤t s ≤k s , t s is an integer. That is, for any of the S column grouping matrices, the number of elements in its mth row that are 1 is the same as the number of elements in its associated θth row. m The number of elements in the row that are 1 is related, and the number of elements in the mth row of the column grouping matrix that are 1 is at most equal to the θth row. m The number of elements in the row that are 1 (i.e., t s ), the minimum is 0. As shown in (a) of FIG6 , the number of elements in the first row of the column grouping matrix 1 that are 1 is 2, and the number of elements in the fourth row associated with the first row that are 1 is 1.

[0144] In one possible design, if the θth column of the sth column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is [0, t s -1] is one of them. In this case, the number of elements in the mth row of the sth column grouping matrix that are 1 is at most greater than the number of elements in the θth row associated with the mth row. m The number of elements that are 1 in the row is 1 less, and the number of elements that are 1 in the mth row can be at least 0.

[0145] As shown in (a) of FIG6 , θ4=1>0, that is, the 4th row and the 1st row of the base matrix are eliminated when the low bit rate is extended. Taking the column grouping matrix 1 as an example, the other column grouping matrices are similar to the column grouping matrix 1. The number of elements in the first row of the column grouping matrix 1 that are 1 is 2 (t s =k s =2), the number of elements in the 4th row associated with the 1st row that are 1 is 1; θ8=4>0, that is, when the base matrix is ​​extended at a low bit rate, the 8th row and the 4th row are eliminated, and the number of elements in the 4th row of the column grouping matrix 1 that are 1 is 1 (t s =1), the number of 1 elements in the 8th row associated with the 4th row is 0.

[0146] Under this design, the sth column grouping matrix can be further divided into multiple ks ×k s The second sub-matrix of . That is, each M×k s The column grouping matrix can be divided into A second submatrix with the same number of rows and columns, where is a positive integer greater than 1. As shown in (a) of Figure 6, k s =2, that is, the number of rows and columns of the second submatrix are both 2.

[0147] It should be understood that in some possible situations, Cannot be divided exactly. At this time, each M×k s The column grouping matrix may have a row greater than or equal to 1 and less than k s The number of columns is k s The second sub-matrix of .

[0148] In another possible design, if the θth column of the sth column grouping matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is t s Or 0. In this case, the number of elements in the mth row of the sth column grouping matrix that are 1 is 0, or the number of elements in the θth row of the sth column grouping matrix that are 1 is 0. m The number of elements in each row that are 1 is equal.

[0149] The structure of the column grouping matrix divided by the core area matrix of the base matrix shown in (a) of FIG7 is the same as the matrix shown in (a) of FIG6, and the first sequence is also the same. The difference is that, as shown in (a) of FIG7, θ4=1>0, that is, in the low code rate extension, the 4th row and the 1st row are eliminated, and the number of elements in the 1st row of the column grouping matrix 1 that are 1 is 2 (t s =k s =2), the number of 1 elements in the 4th row associated with the 1st row is 2; θ8 = 4 > 0, that is, in the low bit rate extension, the 8th row and the 4th row are eliminated, the number of 1 elements in the 4th row of the column grouping matrix 1 is 2, and the number of 1 elements in the 8th row associated with the 4th row is 2. The core region matrix of the basis matrix after the 4th row and the 1st row are eliminated is shown in Figure 7 (b).

[0150] Under this design, the sth column grouping matrix can be further divided into multiple 1×k s The second sub-matrix of . That is, each M×k s The column grouping matrix can be divided into M rows with 1 and k columns s As shown in (a) of Figure 7, k s =2, that is, the number of rows of the second submatrix is ​​1 and the number of columns is 2.

[0151] In θ m ≤0(or θ m (is a special character), it means that there is no row in the basis matrix that is eliminated with the mth row. In low-rate extension, it can be considered that the mth row is obtained by normal extension. In this case, there is a sequence value θ corresponding to the nth row in the basis matrix. n ≤0, and the mth row and the nth row are mutually orthogonal, 1≤m≤M, where m is an integer. In other words, there is an orthogonal relationship between two rows in the basis matrix whose sequence values ​​are less than or equal to 0.

[0152] In the case where the sth column grouping matrix can be further divided into multiple second sub-matrices, if the size of the second sub-matrix is ​​k s ×k s , then the number of elements in the mth row of the sth column grouping matrix that are 1 is at most k s -1, for example, k s =2, then the number of 1 elements in the mth row of the sth column grouping matrix is ​​at most 1. If the size of the second submatrix is ​​1×k s , then the number of elements that are 1 in the mth row of the sth column grouping matrix is ​​k s or 0.

[0153] In the embodiment of the present application, the rows of the base matrix are numbered starting from 1, that is, the rows of the base matrix are numbered from 1 to M. It should be understood that the rows of the base matrix can also be numbered starting from 0, that is, the rows of the base matrix are numbered from 0 to M-1, and the corresponding sequence values ​​in the first sequence include θ m ≥0 and θ m <0(or θ m is a special character), when θ m ≥0, there is a row that can be eliminated with the mth row; when θ m <0(or θ m is a special character), there is no row to be eliminated with the mth row.

[0154] For the basis matrix that satisfies the above column grouping structure characteristics, for the sequence value θ m For rows ≤0, the sending device stores θ m ≤0 in the row whose element is 1. Specifically, the sending device stores θ m The correspondence between the row numbers of the rows with a value ≤ 0 and the column numbers of the elements in the rows whose values ​​are 1 can be expressed in a table.

[0155] For example, k b +k c =27, S=9, the number of columns in each of the S column grouping matrices is the same, that is, k s= 3, and the column numbers of each column grouping matrix are consecutive. The S column groupings corresponding to the S column grouping matrices are shown in Table 2 below, and each column grouping has a corresponding column grouping number. Based on this grouping structure of the base matrix, the sequence value corresponding to the first row is θ1 = 0, and the columns with 1 elements in the first row are 1, 2, 3, 4, 5, 13, 14, 15, 17, and 18. The storage content of the first row of the base matrix can be shown in Table 3-1 below.

[0156] Table 2

[0157] Table 3-1

[0158] For the sequence value θ m >0, the sending device stores θ m Specifically, the transmitting device stores one or more column grouping numbers of the first column groupings associated with the row number of the mth row in the base matrix. The column grouping numbers of the one or more first column groupings are used to determine the column number of the element 1 in the mth row. That is, for θ m >0, when storing, only the column grouping number of the column grouping associated with the row (the first column grouping) can be stored, and the column numbers included in the column grouping corresponding to the column grouping number include the column numbers of the elements in the m-th row being 1. Continuing to refer to the column grouping shown in Table 2 above, the sequence value corresponding to the 3rd row of the base matrix is ​​θ3=1>0, and the storage content of the 3rd row of the base matrix can be shown in Table 3-2 below. The column grouping numbers of the column grouping associated with the 3rd row are S1 and S2. For the column grouping number stored in the m-th row, its associated row (i.e., the θ-th row) indicated by the sequence value corresponding to the m-th row is m The storage content of the row is related.

[0159] Table 3-2

[0160] In one possible design, when the θ m Sequence value of the row The column whose element is 1 in the mth row can be one or more first column groups, and the column number of each first column group is the same as the column number of the θth row. m The intersection of the column numbers whose elements in the row are 1. That is, if the mth row is associated with the θth m If the sequence value of the row is less than or equal to 0, then the θth m The storage content of the row includes the θth m The column number of the row where all elements are 1, thus, the transmitting end device can determine the column number of one or more first column groups according to the stored column group number, and thus compare the column number of each first column group in the one or more first column groups with the stored θth column number. mThe column numbers of all elements in the row that are 1 intersect, and then we can determine which columns in the mth row have elements that are 1.

[0161] Continuing with the above example, m=3, θ m =1, the storage content of the first row of the basis matrix is ​​as shown in Table 3-1 above, and the storage content of the third row can be as shown in Table 3-2 above. The column numbers included in S1 and S2 are {1,2,3,4,5,6}. Therefore, the column numbers of the elements in the third row with element 1 are the intersection of {1,2,3,4,5,13,14,15,17,18} and {1,2,3,4,5,6} {1,2,3,4,5}.

[0162] In one possible design, when the θ m Sequence value of the row One or more first column groups can be the θth m The subset of the column grouping corresponding to the row. That is, the sequence value θ corresponding to the mth row m The indicated θ m The sequence value corresponding to the row If is also greater than 0, then the θ m The storage content of the row is also the column group number described in the above design scheme. At this time, the column group number associated with the mth row is the θth m The subset of column grouping numbers to which the row is associated.

[0163] Continuing to refer to the column grouping shown in Table 2 above, m = 4, θ4 = 2, and θ2 = 1> 0, the storage content of the second row of the base matrix is ​​shown in Table 4-1 below, that is, the column grouping numbers of the column groupings associated with the second row are S2, S7, S8, and S9. The storage content of the fourth row of the base matrix is ​​shown in Table 4-2 below, that is, the column grouping numbers of the column groupings associated with the fourth row are S7 and S8. It can be seen that since the sequence value corresponding to the fourth row indicates that the sequence value corresponding to the second row is greater than 0, the storage content of the second row is also the column grouping number associated with the second row. At this time, the column grouping number stored in the fourth row is a subset of the column grouping number stored in the second row. Furthermore, which columns in the second row have elements that are 1 can be determined based on the storage content of the θ2=1th row indicated by the sequence value corresponding to the second row. For example, the storage content of the first row is shown in Table 4-3 below. The column numbers in the second row with elements that are 1 are the intersection of the column numbers stored in the first row (i.e., the column numbers with elements that are 1) and the column numbers of the column group corresponding to the column group number stored in the second row. That is, the column numbers in the second row with elements that are 1 are {1,2,4,5,6,7,8,19,20,21,23,24,26,27} and {4,5,6,1 The intersection of {7,8,19,20,21,23,24,22,23,24} is {7,8,19,20,21,23,24,26,27}. Similarly, the column number whose element is 1 in the 4th row is the intersection of the column number whose element is 1 in the determined 2nd row and the column number of the column group corresponding to the column group number stored in the 4th row, that is, the intersection of {7,8,19,20,21,23,24,26,27} and {19,20,21,22,23,24} is {19,20,21,23,24}.

[0164] Table 4-1

[0165] Table 4-2

[0166] Table 4-3

[0167] In the embodiment of the present application, in addition to the storage of the base matrix, the storage of the translation value of each element in each row of the base matrix is ​​also included. The translation value is used to indicate the shift value when the element is expanded and promoted. For details, please refer to the description in the existing design scheme, which will not be repeated here. m ≤0, then the translation values ​​corresponding to all elements with values ​​1 in the mth row are stored; if the sequence value θ m > 0, then the translation value of the element in the mth row is 1 and the θth m There is an association between the translation values ​​corresponding to the elements with a value of 1 in the row. For example, the first element and the second element are elements with a value of 1 in the same column of the basis matrix, the first element is in the mth row, and the second element is in the θth row. mThe translation value of the first element is the same as the translation value of the second element, or there is a translation difference between the translation value of the first element and the translation value of the second element. That is, in θ m > 0, the translation value of the element with a value of 1 in the mth row and the i-th column is the θth m The translation value of the element with the value of 1 in the i-th column of the row, or the translation value of the element with the value of 1 in the i-th column of the m-th row is m Add or subtract a translation difference from the translation value of the element whose value in the i-th column in the row is 1.

[0168] In the embodiment of the present application, in order to ensure that when the base matrix is ​​extended at a low bit rate, for rows whose sequence values ​​of the base matrix are less than or equal to 0, after 1 round of splitting, 2 rounds of splitting, ..., Q rounds of splitting (Q is a positive integer), the number of rows obtained by splitting is a power of 2, that is, the number of child nodes is a power of 2. For the first sequence of the base matrix, the following characteristics exist:

[0169] In one possible design, when 1<j0≤j≤M, there is at most one sequence value less than or equal to 0 among the first to jth sequence values ​​in the first sequence, and the number of rows associated with the row corresponding to the sequence value less than or equal to 0 is not a power of 2, and j0 is the first segment position of the sequence value in the first sequence. The number of rows associated with the row with a sequence value less than or equal to 0 can be considered as the number of rows obtained by splitting the row with a sequence value less than or equal to 0, that is, the number of child nodes. This can avoid the situation where the grouping structure of the decoding matrix does not meet the conditions when the decoding matrix is ​​obtained based on the splitting of the base matrix, such as not meeting the decoding structure shown in the following column grouping structure 1 or column grouping structure 2.

[0170] For example, the first sequence of the base matrix is ​​{0,0,0,0,2,4,3,1,4,6,8,1,3,7,2,5}, where the sequence values ​​of rows 1 to 4 are 0, and the number of child nodes (associated rows) obtained by splitting rows with sequence values ​​0 is expressed as |X s |, s is the row number in the base matrix with a sequence value of 0. When the base matrix is ​​expanded (split expansion) at a low code rate according to the first sequence, as shown in FIG8:

[0171] When intercepting rows 1 to 4, since the sequence values ​​of rows 1 to 4 are all 0, it is considered that rows 1 to 4 are obtained by normal expansion and no splitting is required. This can be called the 0th round of splitting of rows 1 to 4. At this time, the number of child nodes in each row of rows 1 to 4 of the basis matrix is ​​1 and is itself, expressed as |X s |=1=2 0 , s=1,2,3,4.

[0172] In the first round of splitting of the 1st to 4th rows of the basis matrix, it can be seen from the first sequence that the 2nd row, 4th row, 3rd row and 1st row are split in turn. Taking the splitting of the 2nd row of the basis matrix as an example, the 5th row of the basis matrix is ​​eliminated from the 2nd row to obtain the 2nd and 5th rows after elimination. The 5-row matrix obtained by splitting is called matrix 1-1. The 2nd and 5th rows in matrix 1-1 are obtained by splitting the 2nd row of the basis matrix, that is, the number of rows obtained by splitting the 2nd row of the basis matrix is ​​2 (the number of child nodes is 2). s |=2=2 1 . Similarly, the 6-row matrix obtained after the 4th row of the basis matrix is ​​split is called matrix 1-2, and the 4th and 6th rows in matrix 1-2 are obtained by splitting the 4th row of the basis matrix; the 7-row matrix obtained after the 3rd row of the basis matrix is ​​split is called matrix 1-3, and the 3rd and 7th rows in matrix 1-3 are obtained by splitting the 3rd row of the basis matrix; the 8-row matrix obtained after the 1st row of the basis matrix is ​​split is called matrix 1-4, and the 1st and 8th rows in matrix 1-4 are obtained by splitting the 1st row of the basis matrix. Therefore, after the first round of splitting processing is completed for the 1st to 4th rows of the basis matrix with a sequence value of 0, the number of rows obtained by splitting each row is 2, that is, |X s |=2=2 1 , s=1,2,3,4.

[0173] During the second round of splitting of the 1st to 4th rows of the basis matrix, that is, during the further splitting of the rows obtained from the first round of splitting of the 1st to 4th rows of the basis matrix, it can be seen from the first sequence that the 4th row of matrix 1-4 is first split, that is, the 9th row of matrix 1-4 is eliminated using the 9th row of the basis matrix to obtain the 4th and 9th rows after elimination. At this time, the 9-row matrix obtained by expanding matrix 1-4 is called matrix 2-1. The 4th row (obtained by the second round of splitting), the 9th row (obtained by the second round of splitting), and the 6th row (obtained by the first round of splitting) of matrix 2-1 are obtained by splitting the 4th row of the basis matrix. Currently, |X4| = 3, that is, the number of child nodes is not a power of 2. Because the 1st to 3rd rows of the basis matrix have only completed the first round of splitting and the second round of splitting has not yet begun, |X1| = |X2| = |X3| = 2. It should be understood that except for the 4th and 9th rows in matrix 2-1, which are different from matrix 1-4, the contents of other rows are the same, and the changes of other related matrices in the embodiment of the present application (such as matrices 1-1 to 1-3) are similar.

[0174] Therefore, in order to ensure that the number of rows obtained by splitting the 4th row of the base matrix after the second round of splitting is a power of 2, after the 4th row of matrix 1-4 is split to obtain matrix 2-1, the next split row must be the 6th row of matrix 2-1 (that is, obtained by splitting the 4th row of the base matrix in the first round), that is, the sequence values ​​4 and 6 in the first sequence are adjacent, and the row number of the newly added row after the 6th row of matrix 2-1 is split must be continuous with the row number of the newly added row after the 4th row of matrix 1-4 is split. For example, if the 4th row of matrix 1-4 is split to obtain the 4th and 9th rows of matrix 2-1, then the 6th row of matrix 2-1 must be split to obtain the 6th and 10th rows of the 10-row matrix (matrix 2-2), so that |X4|=4=2 2 , that is, after the second round of splitting, the 4th row of the basis matrix is ​​split into a power of 2 (the number of child nodes is 4). Similarly, to ensure that the 1st, 3rd, and 2nd rows of the basis matrix are split into a power of 2 after the second round of splitting, in the first sequence, sequence values ​​8 and 1 are adjacent, sequence values ​​3 and 7 are adjacent, and sequence values ​​2 and 5 are adjacent.

[0175] In the first sequence of length M designed based on the above features, there is a sequence position j0 (which can be considered as a serial number), and the first sequence is divided into two segments 1~j0 and j0~M, and the basis matrix is ​​divided into a high code rate area and a low code rate area. When j0≤j≤M, there is at most one sequence value less than or equal to 0 from the 1st sequence value to the jth sequence value, and the row corresponding to the sequence value less than or equal to 0 is not associated with a number of rows that is a power of 2 during low code rate expansion. Referring to the above example, the first sequence is {0,0,0,0,2,4,3,1,4,6,8,1,3,7,2,5}, j0=7 (that is, the position of the sequence value corresponding to the 7th row of the basis matrix), j=9 (that is, the position of the sequence value corresponding to the 9th row of the basis matrix). Between the 1st sequence value and the 9th sequence value, that is, {0,0,0,0,2,4,3,1,4}, there is only the 4th row (sequence value is 0), and the number of rows obtained by splitting is 3, that is, the number of child nodes is not a power of 2.

[0176] For sequence positions greater than j, there is at least one sequence position with a sequence value greater than 0, such as there is a sequence position j<j2≤M, and The number of rows associated with all rows whose sequence values ​​in the first sequence are less than or equal to 0 is a power of 2. Continuing with the above example, j = 9, then the 10th, 12th, 14th, and 16th sequence values ​​in the first sequence {0, 0, 0, 0, 2, 4, 3, 1, 4, 6, 8, 1, 3, 7, 2, 5} can all make the number of rows associated with all rows whose sequence values ​​in the first sequence are less than or equal to 0 be a power of 2, that is, j2 = 10, 12, 14, or 16.

[0177] When 1≤j<j0, corresponding to the high code rate area, there may be multiple rows corresponding to sequence values ​​less than or equal to 0 in the first sequence value to the jth sequence value, and the number of associated rows during low code rate expansion is not a power of 2.

[0178] Since j0 is related to the coding rate of the base matrix, in one possible design, j0 can satisfy the following relationship: Where K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R0 is the first coding rate threshold of the base matrix. R0 can be used to divide the high-rate and low-rate regions in the base matrix. For example, R0 can be 1 / 2, 2 / 3, or 1 / 3.

[0179] In another possible design scheme, when 1≤j≤j1≤M, among the 1st sequence value to the jth sequence value in the first sequence, there is at most one sequence value whose value is less than or equal to 0, and the number of rows associated with the row corresponding to the sequence value whose value is less than or equal to 0 is not a power of 2, and j1 is the second segment position of the sequence value in the first sequence.

[0180] This design differs from the previous one in that, when j1 ≠ M, the first sequence can be divided into two segments, 1 to j1 and j1 to M; when j1 = M, the first sequence is not divided into two segments. This design still satisfies the requirement that at most one sequence value from the first to the jth sequence value is less than or equal to 0, and that the number of rows associated with the row corresponding to this sequence value less than or equal to 0 during low-rate scaling is not a power of 2.

[0181] Among them, j1 can satisfy the following relationship: Wherein, R1 is the second coding rate threshold of the base matrix. For example, R1 can be 1 / 2, 2 / 3, or 3 / 4. It should be understood that R1 ≥ R0, and correspondingly, j1 ≤ j0.

[0182] That is to say, based on the first sequence of the above-mentioned features, it is possible to avoid the situation in which, during the process of splitting the row with a sequence value less than or equal to 0 in the core area matrix twice in a row, only one of the two rows generated by the first split is split during the second split, and the other row is not split, so that the number of rows obtained by splitting the row with a sequence value less than or equal to 0 is 3.

[0183] The column grouping structure and first sequence basis matrix with the above-mentioned specific characteristics are described below using a 46×48 basis matrix as an example. The first sequence of the basis matrix is ​​shown in Table 5-1 below. The core region matrix of the basis matrix has columns numbers 1 to 26. The core region matrix is ​​divided into two column grouping matrices with consecutive column numbers as shown in (a) of Figure 6 , and each column grouping matrix includes a 2×2 first submatrix, i.e., column numbers 1 and 2 form a column grouping, column numbers 3 and 4 form a column grouping, and so on. Furthermore, the column numbers of the elements with a value of 1 in the third row are shown in Table 5-2 below. During low-rate expansion, the rows that are eliminated from the third row are the 9th and 15th rows, the column numbers of the elements with a value of 1 in the 9th row are shown in Table 5-3 below, the column numbers of the elements with a value of 1 in the 15th row are shown in Table 5-4 below, the row that is eliminated from the 9th row is the 16th row, and the column numbers of the elements with a value of 1 in the 16th row are shown in Table 5-5 below.

[0184] Table 5-1

[0185] Table 5-2

[0186] Table 5-3

[0187] Table 5-4

[0188] Table 5-5

[0189] From Tables 5-1 to 5-5 above, we can see that in most column grouping matrices, there are 2 or 0 elements in the 3rd row that are 1, and in a few column grouping matrices, there is 1 element in the 3rd row that is 1. In each column grouping matrix, at most one element in the 9th and 15th rows that are eliminated from the 3rd row is 1. Similarly, in each column grouping matrix, at most one element in the 16th row that is eliminated from the 9th row is 1. m >0, when q=k s When the θth column in the sth column grouping matrix m The number of elements in the row that are 1 is t s When , the number of elements in the mth row of the sth column grouping matrix that are 1 is [0,t s -1] is one of the "features".

[0190] Moreover, in the case of low bit rate expansion, after the first round of splitting, the 3rd row of the basis matrix is ​​split into the 3rd and 9th rows. After the second round of splitting, the 3rd and 9th rows obtained from the first round of splitting are split again. After the 3rd row obtained from the first round of splitting is split again, the 3rd and 15th rows are obtained. After the 9th row obtained from the first round of splitting is split again, the 9th and 16th rows are obtained. At this time, the number of rows (the number of child nodes) obtained by splitting the 3rd row of the basis matrix is ​​2. 2 =4.

[0191] For example, θ 19 = 0, the column numbers of the elements that are 1 in the 19th row are shown in Table 5-6 below, and there is a row with a sequence value of 0 that is orthogonal to the 19th row (such as the 25th row) in the core area matrix of the basis matrix, the column numbers of the elements that are 1 in the 25th row are shown in Table 5-7 below, and in each column grouping matrix, the number of elements that are 1 in the 19th row and the 25th row with a sequence value of 0 is 1 or 0.

[0192] Table 5-6

[0193] Table 5-7

[0194] S502: The transmitting device sends the coded data to the receiving device. Correspondingly, the receiving device receives the coded data from the transmitting device.

[0195] In the embodiments of the present application, a transmitting device may perform encoding processing on the data to be encoded based on the base matrix to obtain the encoded data, and transmit the encoded data to the receiving device. It should be understood that when using the base matrix for encoding processing, the base matrix may be subjected to processing such as truncation, puncturing, lifting and expansion, and then the encoded data may be encoded using the matrix obtained by the processing. The specific implementation process can be found in the relevant description of the existing implementation method and will not be repeated here.

[0196] Furthermore, the transmitting device can also send coding information to the receiving device. Accordingly, the receiving device receives the coding information from the transmitting device. The coding information includes the code length and coding rate of the coded data, etc., to facilitate decoding processing by the receiving device.

[0197] As can be seen from the above, the base matrix in the embodiments of the present application has a column grouping structure and a first sequence with specific characteristics, allowing the encoding end device to perform encoding processing based on the base matrix with these characteristics. Accordingly, after receiving the encoded data, the receiving end device can transform the base matrix based on the base matrix with the specific column grouping structure and the first sequence described in S501 above to obtain a decoding matrix that meets the requirements, thereby improving the decoding rate. For details, please refer to the description of S503-S504 below.

[0198] It should be understood that there is a difference between the encoded data received by the receiving device and the encoded data sent by the transmitting device. The encoded data is affected by the channel during the transmission process and there will be noise. The receiving device can perform denoising and other processing on the received data before decoding, or it can complete denoising during the decoding process. There is no limitation on this.

[0199] S503: The receiving device generates a decoding matrix.

[0200] In the embodiment of the present application, the decoding matrix is ​​divided into S column grouping matrices according to the column number, and the number of columns of the s-th column grouping matrix in the S column grouping matrices is k s , and the sth column grouping matrix includes multiple first sub-matrices with column weights less than or equal to 1, and the first sub-matrix is ​​q×k s Matrix, s, q are integers greater than 0, S, k s is an integer greater than 1, 1≤s≤S. ​​For example, k s The value of can be 2, 3, or 4. During decoding, a first sub-matrix is ​​a QC block.

[0201] The number of columns in each of the S column grouping matrices can be the same or different, and some of the column grouping matrices can have the same number of columns while others can have different numbers of columns, without limitation. Furthermore, the column numbers in each column grouping matrix can be continuous or discrete, or some of the column numbers can be continuous while others can be discrete, or some of the column grouping matrices can have discrete column numbers while others can have continuous column numbers, without limitation. For details, please refer to the description of the division of the column grouping matrix in S501 above, which will not be repeated here.

[0202] The first submatrix is ​​a matrix with a column weight less than or equal to 1, that is, each column in the first submatrix has at most one element that is 1. A column grouping matrix may include a first submatrix with a column weight of 0 (i.e., a zero matrix) and a first submatrix with a column weight of 1.

[0203] In one possible design, q = k s , the number of elements in each row of the first submatrix that are 1 is 1 or 0. That is, the size of the first submatrix is ​​k s ×k s For any column grouping matrix, such as the s-th column grouping matrix, the multiple first sub-matrices it contains may include matrices with both column weight and row weight being 1, or zero matrices with both column weight and row weight being 0. For example, the decoding matrix includes 13 column grouping matrices, i.e., S=13, and the number of columns of each column grouping matrix in the S column grouping matrices is the same, i.e., k s=2, the column numbers of each column grouping matrix are continuous, and the size of the first submatrix is ​​2×2, that is, q=k s = 2. The structure of the decoding matrix is ​​shown in Figure 9. The number of elements in each row of each column grouping matrix is ​​at most 1, and each column grouping matrix includes a first submatrix that is a zero matrix and a first submatrix with both row and column weights of 1. During decoding, for the first submatrix with both row and column weights of 1, two variable nodes and two check nodes are involved. The decoding matrix structure under this design scheme can be referred to as column grouping structure 1.

[0204] In another possible design, q=1, and k in each row of the first submatrix s elements are all 1 or 0. That is, the size of the first submatrix is ​​1×k s For any column grouping matrix, such as the s-th column grouping matrix, the multiple first sub-matrices it contains can have a column weight of 1 and a row weight of k s There may also be a zero matrix with both column weight and row weight being 0. For example, the decoding matrix includes 13 column grouping matrices, ie S=13, and the number of columns of each column grouping matrix in the S column grouping matrices is the same, ie k s =2, the column numbers of each column grouping matrix are continuous, and the size of the first submatrix is ​​1×2, that is, q=1, k s =2. The structure of the decoding matrix is ​​shown in Figure 10. The elements in each row of each column grouping matrix are all 1 or all 0. That is, each column grouping matrix includes a first submatrix that is a zero matrix and a first submatrix with a row weight of 2 and a column weight of 1. During decoding, for the first submatrix with a row weight of 2 and a column weight of 1, two variable nodes and one check node are involved. The decoding matrix structure under this design scheme can be called column grouping structure 2.

[0205] In the embodiment of the present application, the decoding matrix can be determined based on the base matrix, and the base matrix has the relevant features described in S501 above. For a specific description, please refer to the relevant description in S501 above, which will not be repeated here. Specifically, the receiving end device can intercept a portion of the matrix in the base matrix based on the received coding information (such as the coding rate and code length) and expand it according to the first sequence (split transformation). After multiple splitting and row transformation processes, a decoding matrix with a structure as shown in Figure 9 or Figure 10 can be obtained.

[0206] For example, taking the generation of a decoding matrix with column grouping structure 1 as an example, as shown in FIG11 , the core area matrix of the base matrix is ​​divided into three column grouping matrices, i.e., S=3, and the number of columns of each column grouping matrix in the S column grouping matrices is the same, i.e., k s =2, the column numbers of each column grouping matrix are continuous, and the size of the first submatrix is ​​2×2, that is, q=k s=2, and the first sequence is {0,0,0,1,2,3}. The receiving device can truncate rows 1 to 3 of the basis matrix for low-rate expansion. For example, when the truncated 3-row matrix is ​​expanded to a 4-row matrix (matrix 1), the 4th row of the basis matrix is ​​used to eliminate the 1st row. That is, the 1st and 4th rows of matrix 1 are obtained by splitting the 1st row of the basis matrix. When matrix 1 is further expanded from 4 rows to 5 rows (matrix 2), the 5th row of the basis matrix is ​​used to eliminate the 2nd row. That is, the 2nd and 5th rows of matrix 2 are obtained by splitting the 2nd row of the basis matrix (or matrix 1). When matrix 3 is further expanded to 6 rows (matrix 3), the 6th row of the basis matrix is ​​used to eliminate the 3rd row. That is, the 3rd and 6th rows of matrix 3 are obtained by splitting the 2nd row of the basis matrix (or matrix 2). At this time, the number of 1 elements in each row of each column grouping matrix of matrix 3 is 1. Then, matrix 3 is subjected to row transformation processing to obtain a decoding matrix with a structure similar to that of FIG. 9 . Similarly, after the core area matrix of the base matrix shown in (a) of FIG7 is split and transformed according to the first sequence, a decoding matrix with a structure similar to that of FIG10 can be obtained, which will not be described in detail.

[0207] S504: The receiving end device decodes the encoded data according to the decoding matrix.

[0208] In the embodiment of the present application, the receiving device may generate a decoding matrix of the column grouping structure 1 or the column grouping structure 2 type to perform decoding processing on the received encoded data.

[0209] In the case of a decoding matrix with a column grouping structure of 1, as shown in Figure 9, a 2×2 first submatrix is ​​a QC block. The elements of a QC block can be decoded in parallel. For a first submatrix with both row and column weights of 1, the decoding parallelism is 2Zc, where Zc is the boost value. Two variable nodes and two check nodes can be processed at a time, and the number of quasi-cyclic LDPC shift networks (QSNs) is 2. Within a single iteration, check node processing is faster. Check nodes are stored in row groups, with each group occupying the same memory area.

[0210] When the decoding matrix is ​​a matrix with column grouping structure 2, as shown in Figure 10, a 1×2 first sub-matrix is ​​a QC block. The elements of a QC block can be decoded in parallel, and high, medium, and low bit rates can share the same decoding architecture. This is a decoding method that is more compatible with extended nodes, and the calculation area of ​​the minimum calculation at the check node is smaller.

[0211] The two decoding matrix structures shown in Figures 9 and 10 can process two variable nodes at a time under the Layered-MS decoding algorithm hardware architecture, performing read, calculation, and storage of the two variable nodes in parallel. The operations are time-consistent, eliminating the need to wait for other nodes in the same group to complete processing before proceeding. Therefore, processing two variable nodes is consistent with processing a single variable node from a latency perspective. Furthermore, the column grouping structure facilitates hardware implementation. The evenly divided column groups (each group has a fixed structure, i.e., the first submatrix) only require hardware support for an architecture with k columns and q rows. The degree of parallelism is also fixed (at most k), facilitating hardware resource consistency. This further simplifies the hardware architecture and eliminates waste of parallelism and computational resources.

[0212] In addition, variable nodes can be stored in column groups, that is, variable nodes in the same column group are stored in the same memory location, and the nodes in the group are read into the computing unit at the same time, and the calculations are completed in the computing unit at the same time.

[0213] Based on the encoding and decoding method shown in Figure 5, both the transmitting and receiving devices store a base matrix, which has a first sequence with specific characteristics for low code rate expansion, a core area with column grouping characteristics, and correlation characteristics between rows in the core area. For the transmitting device, it can use the base matrix to encode data; for the receiving device, it can use the base matrix to generate a decoding matrix with a specific column grouping structure. Therefore, on the one hand, under a multi-block parallel decoding architecture, very high hardware utilization can be achieved, and the performance is better under the same complexity and decoding delay conditions; on the other hand, low code rate expansion is performed according to the first sequence, and the expanded rows have a highly parallel feature. Under a row-parallel decoding architecture, high hardware utilization and low complexity decoding can be achieved. The solution provided in the embodiment of the present application is applicable to block parallel decoding and row parallel decoding architectures, which can improve decoding efficiency.

[0214] The following describes the beneficial effects of the base matrix structure provided in the embodiments of the present application in conjunction with specific simulation results.

[0215] For example, FIG12 is a simulation result diagram of the correspondence between the number of equivalent QC blocks and the coding rate when decoding based on the decoding matrix and the NR LDPC BG (as shown in FIG1 ) provided in an embodiment of the present application. Curve 1 is the correspondence between the number of equivalent QC blocks and the coding rate when decoded by the NR LDPC BG when the block parallel number is 1, curve 2 is the correspondence between the number of equivalent QC blocks and the coding rate when decoded by the NR LDPC BG when the block parallel number is 2, curve 3 is the correspondence between the number of equivalent QC blocks and the coding rate when decoded by the decoding matrix with a column grouping structure provided in an embodiment of the present application when the block parallel number is 1, and curve 4 is the correspondence between the number of equivalent QC blocks and the coding rate when decoded by the decoding matrix with a column grouping structure provided in an embodiment of the present application when the block parallel number is 2. As shown in Figure 12, regardless of whether the block parallel number is 1 or 2, under the same bit rate, such as curve 1 compared with curve 3, and curve 2 compared with curve 4, the equivalent number of QC blocks decoded using the decoding matrix is ​​reduced by 40% (comprehensive benefit 40%) compared with the equivalent number of QC blocks decoded using NR LDPC BG, thereby lowering the decoding complexity, shortening the decoding delay, and improving the decoding efficiency.

[0216] For example, FIG13 is a simulation result diagram of the correspondence between the equivalent number of decoding rows and the encoding rate based on the decoding matrix and NR LDPC BG decoding under the row-parallel decoding architecture provided by the embodiment of the present application. Among them, Curve 1 is the correspondence between the equivalent number of decoding rows and the encoding rate when the NR LDPC BG is decoded with a row parallel number of 1, Curve 2 is the correspondence between the equivalent number of decoding rows and the encoding rate when the NR LDPC BG is decoded with a row parallel number of 2, and Curve 3 is the correspondence between the equivalent number of decoding rows and the encoding rate when the decoding matrix with a column grouping structure is decoded according to the embodiment of the present application. As shown in Figure 13, under the row-parallel decoding architecture, at the same bit rate, the number of equivalent decoding rows using decoding matrix decoding is less than the equivalent decoding rows using NR LDPC BG decoding, which can reduce the equivalent decoding rows by up to 60% (the maximum benefit is about 60%), and the overall equivalent decoding rows can be reduced by 50% (the overall benefit is 50%), which reduces the decoding complexity, shortens the decoding delay, and improves the decoding efficiency.

[0217] Therefore, Figures 12 and 13 above show that when decoding using the decoding matrix structure provided by the embodiments of the present application, decoding is superior to NR LDPC BG under both the block-parallel decoding architecture and the row-parallel decoding architecture. Specifically, under the block-parallel decoding architecture, the number of equivalent QC blocks is smaller than when decoding using NR LDPC BG, and under the row-parallel decoding architecture, the number of equivalent decoding rows is smaller than when decoding using NR LDPC BG, both of which improve decoding efficiency.

[0218] For example, FIG14 is a simulation result diagram of the correspondence between the signal-to-noise ratio (SNR) and the coding rate required for the block error rate to reach 0.01 based on the decoding matrix and NR LDPC BG decoding, respectively, provided in an embodiment of the present application. Among them, the decoding matrix is ​​a matrix with a column grouping structure 2. As shown in FIG14, as the coding rate increases, the SNR required for the block error rate to reach 0.01 based on the decoding matrix and NR LDPC BG decoding gradually increases. At the same code rate, the SNR required for the block error rate to reach 0.01 based on the decoding matrix decoding is basically the same as the SNR required for the block error rate to reach 0.01 based on the NR LDPC BG decoding, that is, at each code rate, decoding based on the decoding matrix does not lose the extreme performance (such as 20 rounds of iterations), and the decoding complexity is reduced.

[0219] For example, Figure 15 is a simulation result diagram of the correspondence between the SNR and information length required for the block error rate to reach 0.01 based on the decoding matrix and NR LDPC BG decoding under different code rates provided by the embodiment of the present application. As shown in Figure 15, the solid line is the correspondence between the SNR and information length required for the block error rate to reach 0.01 based on NR LDPC BG decoding, and the dotted line is the correspondence between the SNR and information length required for the block error rate to reach 0.01 based on the decoding matrix decoding. The coding rates from top to bottom are 5 / 6, 2 / 3, 1 / 2, and 1 / 3. Among them, the information length is the length of the information to be encoded.

[0220] As can be seen from Figure 15, when the decoding delay (complexity) of the decoding matrix and the NR LDPC BG decoding is aligned, the NR LDPC BG decoding is iterated 20 times. Except for the high code rate case, at the same code rate and the same information length, the SNR required for the block error rate of 0.01 for decoding based on the decoding matrix is ​​smaller than the SNR required for the block error rate of 0.01 for decoding based on the NR LDPC BG, and the performance gain is 0.1 decibel (dB).

[0221] It can be understood that in each of the above embodiments, the methods and / or steps implemented by the sending device can also be implemented by components that can be used for the sending device (such as a processor, chip, chip system, circuit, logic module, or software); the methods and / or steps implemented by the receiving device can also be implemented by components that can be used for the receiving device (such as a processor, chip, chip system, circuit, logic module, or software).

[0222] The above mainly introduces the solution provided by this application. Accordingly, this application also provides a communication device, which is used to implement the various methods in the above method embodiments. The communication device can be the transmitting device in the above method embodiments, or a device including a transmitting device, or a component that can be used for the transmitting device, such as a chip or chip system. Alternatively, the communication device can be the receiving device in the above method embodiments, or a device including a receiving device, or a component that can be used for the receiving device, such as a chip or chip system.

[0223] It is understandable that, in order to realize the above functions, the communication device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0224] The embodiment of the present application can divide the functional modules of the communication device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.

[0225] Taking the communication device as the transmitting or receiving device in the above method embodiment as an example, Figure 16 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. As shown in Figure 16, communication device 1600 includes a processing module 1601 and a transceiver module 1602. Processing module 1601 is configured to perform the processing functions of the transmitting or receiving device in the above method embodiment. Transceiver module 1602 is configured to perform the transceiver functions of the transmitting or receiving device in the above method embodiment.

[0226] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0227] Since the communication device 1600 provided in this embodiment can execute the above method, the technical effects that can be obtained can refer to the above method embodiments and will not be repeated here.

[0228] In one possible design solution, in the embodiment of the present application, the transceiver module 1602 may include a receiving module and a sending module (not shown in FIG16 ). The transceiver module is used to implement the sending function and the receiving function of the communication device 1600 .

[0229] In one possible design, communication device 1600 may further include a storage module (not shown in FIG16 ) storing a program or instruction. When processing module 1601 executes the program or instruction, communication device 1600 may perform the functions of the transmitting end device or the receiving end device in the method shown in FIG5 .

[0230] It should be understood that the processing module 1601 involved in the communication device 1600 can be implemented by a processor or a processor-related circuit component, which can be a processor or a processing unit; the transceiver module 1602 can be implemented by a transceiver or a transceiver-related circuit component, which can be a transceiver or a transceiver unit.

[0231] For example, FIG17 is a schematic diagram of the structure of another communication device provided in an embodiment of the present application. The communication device may be a transmitting device or a receiving device, or a chip (system) or other component or assembly that can be provided in the transmitting device or the receiving device. As shown in FIG17 , the communication device 1700 may include a processor 1701. In one possible design scheme, the communication device 1700 may further include a memory 1702 and / or a transceiver 1703. The processor 1701 is coupled to the memory 1702 and the transceiver 1703, such as by a communication bus.

[0232] The following is a detailed introduction to the various components of the communication device 1700 with reference to FIG17 :

[0233] The processor 1701 is the control center of the communication device 1700 and can be a single processor or a collective term for multiple processing elements. For example, the processor 1701 can be one or more central processing units (CPUs), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application, such as one or more digital signal processors (DSPs) or one or more field programmable gate arrays (FPGAs).

[0234] In one possible design, the processor 1701 may execute various functions of the communication device 1700 by running or executing software programs stored in the memory 1702 and calling data stored in the memory 1702 .

[0235] In a specific implementation, as an embodiment, the processor 1701 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG17 .

[0236] In a specific implementation, as an embodiment, the communication device 1700 may also include multiple processors, such as the processor 1701 and the processor 1704 shown in FIG17 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0237] Among them, the memory 1702 is used to store the software program for executing the solution of this application, and the execution is controlled by the processor 1701. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0238] In one possible design, the memory 1702 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1702 may be integrated with the processor 1701 or exist independently and be coupled to the processor 1701 via an interface circuit (not shown in FIG. 17 ) of the communication device 1700, which is not specifically limited in this embodiment of the present application.

[0239] Transceiver 1703 is used for communication with other communication devices. For example, if communication device 1700 is a terminal device, transceiver 1703 can be used to communicate with an access network device or another terminal device. For another example, if communication device 1700 is a network device, transceiver 1703 can be used to communicate with a terminal device or another network device.

[0240] In one possible design, transceiver 1703 may include a receiver and a transmitter (not shown separately in FIG17 ), wherein the receiver is configured to implement a receiving function, and the transmitter is configured to implement a transmitting function.

[0241] In one possible design scheme, the transceiver 1703 can be integrated with the processor 1701, or it can exist independently and be coupled to the processor 1701 through the interface circuit of the communication device 1700 (not shown in Figure 17). This embodiment of the present application does not specifically limit this.

[0242] It should be noted that the structure of the communication device 1700 shown in FIG17 does not constitute a limitation on the communication device. The actual communication device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0243] In addition, the technical effects of the communication device 1700 can refer to the technical effects of the methods described in the above method embodiments, and will not be repeated here.

[0244] An embodiment of the present application further provides a computer-readable storage medium on which a computer program or instruction is stored. When the computer program or instruction is executed by a computer, the functions of the above-mentioned method embodiment are realized.

[0245] The embodiments of the present application also provide a computer program product, which implements the functions of the above method embodiments when executed by a computer.

[0246] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0247] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0248] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0249] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0250] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0251] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0252] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0253] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0254] Although the present application has been described with reference to specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely illustrative of the present application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, the present application is intended to include such modifications and variations as fall within the scope of the claims of the present application and their equivalents.

Claims

1. A coding method, characterized in that: The method comprises: The data is encoded according to the base matrix to obtain the encoded data, wherein the core area matrix in the base matrix is ​​divided into S column grouping matrices according to the column number, the columns of the core area matrix include the information column and the core check column of the base matrix, the base matrix corresponds to a first sequence with a length of M, and the mth sequence value θ in the first sequence m Used to indicate the mth row and the θth row of the base matrix in low bit rate expansion m Perform elimination on the row; In θ m >0, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements with 1 in the mth row of the sth column grouping matrix of the core region matrix is ​​[0, t s ]one of the; In θ m ≤0, there is a sequence value θ corresponding to the nth row in the basis matrix n ≤0, and the mth row is orthogonal to the nth row; wherein M is equal to the number of rows of the base matrix, and the number of columns of the sth column grouping matrix of the core region matrix is ​​equal to k s , M, S, k s is an integer greater than 1, 1≤m≤M, 1≤n≤M, m≠n, θ m <m, 1≤s≤S, 1≤t s ≤k s , m, n, s, t s ,θ m is an integer; The encoded data is transmitted.

2. A decoding method, characterized in that: The method comprises: Generate a decoding matrix, wherein the decoding matrix is ​​divided into S column grouping matrices according to the column number, the sth column grouping matrix of the S column grouping matrices includes a plurality of first sub-matrices with a column weight less than or equal to 1, and the first sub-matrix is ​​q×k s The matrix, k s is equal to the number of columns of the sth column grouping matrix, s and q are integers greater than 0, S and k s is an integer greater than 1, 1≤s≤S; The coded data is decoded according to the decoding matrix.

3. The method according to claim 2, characterized in that When q=k s In the case of , the number of elements that are 1 in each row of the first submatrix is ​​1 or 0.

4. The method according to claim 2, characterized in that: When q=1, the k in each row of the first submatrix s Each element is either 1 or 0.

5. The method according to any one of claims 2 to 4, characterized in that: The decoding matrix is ​​determined according to the base matrix. The core area matrix in the base matrix is ​​divided into S column grouping matrices according to the column number. The columns of the core area matrix include the information column and the core check column of the base matrix. The base matrix corresponds to a first sequence with a length of M. The mth sequence value θ in the first sequence m Used to indicate the mth row and the θth row of the base matrix in low bit rate expansion m Perform elimination on the row; In θ m >0, if the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements with 1 in the mth row of the sth column grouping matrix of the core region matrix is ​​[0, t s ]one of the; In θ m ≤0, there is a sequence value θ corresponding to the nth row in the basis matrix n ≤0, and the mth row is orthogonal to the nth row; wherein M is equal to the number of rows of the base matrix, and the number of columns of the sth column grouping matrix of the core region matrix is ​​equal to k s , M is an integer greater than 1, 1≤m≤M, 1≤n≤M, m≠n, θ m <m, 1≤t s ≤k s , m, n, t s ,θ m is an integer.

6. The method according to claim 1 or 5, characterized in that: If the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements with 1 in the mth row of the sth column grouping matrix of the core region matrix is ​​[0, t s ], including: If the θth column grouping matrix of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements with 1 in the mth row of the sth column grouping matrix of the core region matrix is ​​[0, t s -1].

7. The method according to claim 1 or 5, characterized in that: If the θth column grouping matrix of the sth column grouping matrix in the S column grouping matrices of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements with 1 in the mth row of the sth column grouping matrix of the core region matrix is ​​[0, t s ], including: If the θth column grouping matrix of the core region matrix m The number of 1 elements in the row is equal to t s , then the number of elements in the mth row of the sth column grouping matrix of the core region matrix that are 1 is t s or 0.

8. The method according to any one of claims 1 or 5-7, characterized in that: The S column grouping matrices of the core region matrix have the same number of columns.

9. The method according to any one of claims 1 or 6-8, characterized in that: The kth column of the core region matrix is ​​grouped into s The column numbers are either discrete or continuous.

10. The method according to any one of claims 1 or 6-9, characterized in that: In θ m >0, the column number of each column grouping matrix in the S column grouping matrices of the core area matrix is ​​a column grouping, and the row number of the m-th row in the base matrix is ​​associated with the grouping number of one or more first column groupings, and the grouping number of the one or more first column groupings is used to determine the column number of the element 1 in the m-th row.

11. The method according to claim 10, characterized in that When the θ m The sequence value of the row The column whose element in the mth row is 1 is the column number of each first column group in the one or more first column groups and the column number of the θth row. m The intersection of the column numbers where the elements in the rows are 1.

12. The method according to claim 10, characterized in that When the θ m The sequence value of the row The one or more first columns are grouped into the θth m The rows correspond to a subset of the column groupings.

13. The method according to any one of claims 10 to 12, characterized in that: The translation value of the first element is the same as the translation value of the second element, or there is a translation difference between the translation value of the first element and the translation value of the second element, the first element and the second element are elements with a value of 1 located in the same column of the basis matrix, the first element is located in the mth row, and the second element is located in the θth row. m OK.

14. The method according to any one of claims 1 or 5-13, characterized in that: When j0≤j≤M, there is at most one sequence value whose value is 0 among the first sequence value to the jth sequence value in the first sequence, and the number of rows associated with the row corresponding to the sequence value whose value is 0 is not a power of 2, and j0 is the first segment position of the sequence value in the first sequence.

15. The method according to claim 14, characterized in that The j0 satisfies the following relationship: Wherein, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R0 is the first coding rate threshold of the base matrix.

16. The method according to claim 15, characterized in that R0=1 / 2, 2 / 3, or 1 / 3.

17. The method according to any one of claims 1 or 5-13, characterized in that: When 1≤j≤j1≤M, there is at most one sequence value whose value is 0 among the first sequence value to the jth sequence value in the first sequence, and the number of rows associated with the row corresponding to the sequence value whose value is 0 is not a power of 2, and j1 is the second segment position of the sequence value in the first sequence.

18. The method according to claim 17, characterized in that The j1 satisfies the following relationship: Among them, K is the number of information columns in the base matrix, P is the number of punctured columns in the base matrix, and R1 is the second coding rate threshold of the base matrix.

19. The method according to claim 18, characterized in that R1=1 / 2, 2 / 3, or 3 / 4.

20. The method according to any one of claims 1 to 19, characterized in that k s =2, 3, or 4.

21. A communication device, characterized in that: include: Processing module and transceiver module; wherein, The processing module is used to perform the processing function of the method according to any one of claims 1 to 20; The transceiver module is used to perform the transceiver function of the method as described in any one of claims 1-20.

22. A communication device, characterized in that: include: A processor, wherein the processor is configured to execute a computer program so that the communication device executes the method according to any one of claims 1 to 20.

23. A communication chip, characterized in that: Instructions are stored therein, and when the chip runs on a communication device, the method according to any one of claims 1 to 20 is implemented.

24. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction. When the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 20 is implemented.

25. A computer program product, characterized in that The device comprises a computer program code, and when the computer program code is executed on a communication device, the communication device implements the method according to any one of claims 1 to 20.

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