Display panel and display apparatus

Abstract

Provided in the embodiments of the present application are a display panel and a display apparatus. The display panel comprises a plurality of pixel units, and a plurality of data lines and scanning lines, the data lines comprising a first data line and a second data line, wherein the first data line and the second data line are provided between two adjacent pixel units, two adjacent sub-pixels have different voltage polarities, and each scanning line is electrically connected to both of the two different sub-pixels. Therefore, the problem of pixels being prone to the coupling of different scanning lines is effectively solved, and the comprehensive performance of the pixels is improved.

Description

Display panel and display device Technical Field

[0001] The present application relates to the technical field of display panel design, and in particular to a display panel and a display device. Background Art

[0002] With the development of display panel manufacturing technology, people have put forward higher requirements on the display effects and comprehensive performance of display panels and display devices.

[0003] Liquid crystal display panels are gradually developing towards superior features such as wide viewing angles, low energy consumption, and high charging rates. Although LCDs have a higher charging rate than other displays, with their increasing popularity, most consumers prefer larger and brighter displays, driving the rapid development of the display industry. To improve the display performance and effects of these LCD panels, conventional technologies often employ tri-gate transistor (Tri-gate) technology to horizontally arrange multiple pixel units. In this common Tri-gate technology, each pixel consists of three gate scan lines and one data line, along with other control signal lines. This effectively reduces the number of data lines and lowers the production cost of LCD panels. However, as the demand for larger and higher-resolution display panels continues to increase, the Tri-gate architecture shortens the charging time of each stage of the gate driver on array (GOA), making pixels susceptible to coupling between scan line signals at different stages. This, in turn, results in short charging times and insufficient charging rates for each pixel within a plane, hindering further improvement in the overall performance of the display panel.

[0004] Therefore, it is necessary to propose solutions to the problems in the prior art. SUMMARY OF THE INVENTION

[0005] To sum up, in the process of preparing and forming a display panel in the existing technology, there is usually a steep inclination angle at the packaging layer inside the panel. When metal wiring is further set and etched at this inclination angle, metal residue will exist, which will cause a short circuit problem inside the panel, thereby reducing the reliability and overall performance of the display panel.

[0006] To solve the above problems, embodiments of the present application provide a display panel and a display device to effectively improve the pixel unit and wiring structure in the existing display panel, enhance the charging effect of the pixels, and improve the overall performance of the display panel.

[0007] To solve the above technical problems, a first aspect of an embodiment of the present application provides a display panel, wherein a plurality of pixel units are arrayed in rows and columns, and each of the pixel units is provided with a plurality of sub-pixels;

[0008] a plurality of data lines arranged along a first direction and electrically connected to each of the sub-pixels, with one group of the data lines being arranged between two adjacent pixel units; and

[0009] a plurality of scanning lines arranged along the second direction and electrically connected to the sub-pixels; and

[0010] Common electrode lines, wherein the common electrode lines and the scanning lines are alternately arranged between two different sub-pixels;

[0011] The data lines include a first data line and a second data line that are adjacent to each other, the first data line and the second data line are both disposed between two adjacent pixel units, and the polarities of the voltages on the two adjacent sub-pixels are different;

[0012] Two sub-pixels are disposed between two adjacent scan lines, and in the second direction, each scan line controls two different sub-pixels.

[0013] According to an embodiment of the present application, the scan line is electrically connected to the sub-pixels on both sides of the scan line at the same time.

[0014] According to an embodiment of the present application, each of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially arranged along the first direction;

[0015] The scan line is disposed between the first sub-pixel and the second sub-pixel, and the scan line is electrically connected to both the first sub-pixel and the second sub-pixel.

[0016] According to an embodiment of the present application, the scan line is electrically connected to two different sub-pixels on the same side of the scan line.

[0017] According to an embodiment of the present application, each of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially arranged along the first direction;

[0018] The scan line is disposed at a corresponding position below the third sub-pixel, and the scan line is electrically connected to the first sub-pixel and the second sub-pixel at the same time.

[0019] According to an embodiment of the present application, the data voltage on the first data line is different from the data voltage on the second data line.

[0020] According to one embodiment of the present application, the display panel also includes a chip-on-chip film and a driving circuit. The chip-on-chip film is arranged on the first side or the second side of the display panel, and the first side and the second side are the sides corresponding to the column direction of the display panel. The driving circuit is arranged on the third side of the display panel, and the third side is the side corresponding to the row direction of the display panel.

[0021] According to an embodiment of the present application, the first direction is the same as a row direction of the display panel, and the first data line and the second data line are disposed between two adjacent pixel units.

[0022] According to a second aspect of an embodiment of the present application, a display panel is provided, wherein a plurality of pixel units are arrayed in rows and columns, and a plurality of sub-pixels are disposed in each pixel unit;

[0023] a plurality of data lines arranged along a first direction and electrically connected to each of the sub-pixels, with one group of the data lines being arranged between two adjacent pixel units; and

[0024] a plurality of scanning lines arranged along the second direction and electrically connected to the sub-pixels;

[0025] The data lines include a first data line and a second data line that are adjacent to each other, the first data line and the second data line are both disposed between two adjacent pixel units, and the polarities of the voltages on the two adjacent sub-pixels are different;

[0026] Two sub-pixels are disposed between two adjacent scan lines, and in the second direction, each scan line controls two different sub-pixels.

[0027] According to an embodiment of the present application, the scan line is electrically connected to the sub-pixels on both sides of the scan line at the same time.

[0028] According to an embodiment of the present application, each of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially arranged along the first direction;

[0029] The scan line is disposed between the first sub-pixel and the second sub-pixel, and the scan line is electrically connected to both the first sub-pixel and the second sub-pixel.

[0030] According to an embodiment of the present application, the scan line is electrically connected to two different sub-pixels on the same side of the scan line.

[0031] According to an embodiment of the present application, each of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially arranged along the first direction;

[0032] The scan line is disposed at a corresponding position below the third sub-pixel, and the scan line is electrically connected to the first sub-pixel and the second sub-pixel at the same time.

[0033] According to an embodiment of the present application, the data voltage on the first data line is different from the data voltage on the second data line.

[0034] According to one embodiment of the present application, the display panel also includes a chip-on-chip film and a driving circuit. The chip-on-chip film is arranged on the first side or the second side of the display panel, and the first side and the second side are the sides corresponding to the column direction of the display panel. The driving circuit is arranged on the third side of the display panel, and the third side is the side corresponding to the row direction of the display panel.

[0035] According to an embodiment of the present application, the first direction is the same as a row direction of the display panel, and the first data line and the second data line are disposed between two adjacent pixel units.

[0036] According to an embodiment of the present application, the display panel further includes common electrode lines. The common electrode lines are arranged in the same direction as the scan lines, and the common electrode lines and the scan lines are alternately arranged between different sub-pixels.

[0037] According to a third aspect of the embodiments of the present application, a display device is further provided, comprising the display panel provided in the embodiments of the present application.

[0038] According to an embodiment of the present application, the scan line is electrically connected to two sub-pixels located on both sides of the scan line.

[0039] According to an embodiment of the present application, the scan line is electrically connected to two different sub-pixels located on the same side of the scan line. Beneficial effects

[0040] In summary, the beneficial effects of the embodiments of the present application are:

[0041] The embodiment of the present application provides a display panel and a display device. The display panel includes a plurality of pixel units arranged in an array along a first direction and a second direction, a plurality of sub-pixels are arranged in each pixel unit, a plurality of data lines arranged along the first direction, and a scan line arranged along the second direction. The data line includes a first data line and a second data line arranged adjacent to each other, the first data line and the second data line are arranged between two adjacent pixel units, and the voltage polarities on the two adjacent sub-pixels are different, and two sub-pixels are arranged between two adjacent scan lines. In the second direction, each scan line is electrically connected to two different sub-pixels at the same time. In the embodiment of the present application, by improving the layout of the above-mentioned scan lines and data lines and the connection structure and method between the corresponding sub-pixels, the susceptibility of pixels to the coupling of different scan lines can be effectively improved, the charging efficiency of the pixels can be improved, and the overall performance of the display panel can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of a pixel structure of a display panel provided in the prior art;

[0043] FIG2A is a schematic diagram illustrating an arrangement of a pixel structure of a display panel provided in an embodiment of the present application;

[0044] FIG2B is a simplified schematic diagram of the pixel unit corresponding to FIG2A ;

[0045] FIG2C is a schematic diagram showing connections between sub-pixels, data lines, and scan lines in a corresponding pixel unit in FIG2A ;

[0046] FIG3 is a schematic diagram of the arrangement of another pixel structure provided in an embodiment of the present application;

[0047] FIG4 is a schematic diagram of a display panel provided in an embodiment of the present application;

[0048] FIG5 is a schematic diagram of the vertically arranged pixel structure provided in an embodiment of the present application;

[0049] FIG6 is a layout structure diagram corresponding to the vertically arranged pixel structure;

[0050] 7-8 are schematic diagrams of another structure of vertical arrangement of sub-pixels provided in an embodiment of the present application. Best Mode for Carrying Out the Invention

[0051] The following descriptions of the embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present disclosure may be implemented.

[0052] As shown in Figure 1, a schematic diagram of the pixel structure of a display panel provided in the prior art is shown. In the prior art, when configuring the pixel structure within a display panel, the display panel includes m data lines D1'-Dm' (data lines) and n scan lines G1'-Gn' (gate lines). The data lines extend vertically, while the scan lines extend horizontally, intersecting to form different pixel units and corresponding sub-pixels within the pixel units. When charging different sub-pixels, one data line charges two adjacent columns of sub-pixels separately in an interleaved manner, achieving column flipping and point flipping connections. However, in the conventional wiring and pixel layout architecture described above, as the size and resolution of the display panel increase, the charging time of each level of scan lines decreases, resulting in short charging times and insufficient charging rates for the sub-pixels within the panel. Therefore, it is necessary to develop a pixel structure with a high charging rate that supports the Tri-gate architecture and improves its resolution, refresh rate, and overall display panel performance.

[0053] A display panel and a display device are provided in the embodiments of the present application to improve the pixel structure arrangement and routing inside the existing display panel, and effectively improve the charging efficiency of the pixels and the overall performance of the panel.

[0054] As shown in FIG2A , FIG2A is a schematic diagram of the arrangement of a pixel structure of a display panel provided in an embodiment of the present application. The arrangement of the pixel structure in FIG2A is illustrated using the structure within a portion of an area as an example. During the arrangement, the pixel structure is repeatedly arranged according to this structure, and ultimately pixels are formed within the entire area of ​​the display panel, thereby achieving luminous display of the display panel.

[0055] Specifically, the display panel includes a plurality of pixel units 100 arranged in a first direction Y and a second direction X. The pixel units 100 are arranged in an array in the first direction and the second direction. Optionally, the first direction Y is a vertical direction and the second direction X is a horizontal direction. FIG2A only illustrates one column.

[0056] At this time, a plurality of pixel units 100 are arranged in an array within the display area of ​​the display panel and form a pixel area in the embodiment of the present application. Wherein, for each pixel unit 100, it also includes a plurality of sub-pixels. In the following embodiments, the sub-pixels are described by taking the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 as an example. The first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged in sequence in the first direction Y. Optionally, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel.

[0057] Furthermore, the display panel is also provided with a plurality of data lines 40. In one embodiment, the plurality of data lines are arranged along a first direction and are electrically connected to each sub-pixel, thereby providing data signals to the corresponding sub-pixels and controlling the operation of each sub-pixel. Specifically, when the first direction is a vertical direction, the data lines 40 are arranged along the vertical direction, and when the first direction is a horizontal direction, the data lines 40 are arranged along the horizontal direction. No further details are given here. In the embodiment of the present application, when the data lines 40 are arranged, a group of data lines are arranged in the blank area between the pixel units 100. Specifically, each group of data lines includes a first data line 401 and a second data line 402. The first data line 401 and the second data line 402 are arranged adjacent to each other. At the same time, the polarity of the corresponding voltages on the first data line 401 and the second data line 402 are different, and the polarity of the data voltages corresponding to the two adjacent sub-pixels is different.

[0058] Furthermore, the display panel includes a plurality of scan lines 30. In the embodiment of the present application, when the plurality of scan lines 30 are arranged, the scan lines 30 are arranged along the second direction, and the first direction and the second direction form an angle, such as the first direction and the second direction are perpendicular to each other. At the same time, the scan lines are electrically connected to the corresponding sub-pixels and provide scan signals to ensure the normal operation of each sub-pixel.

[0059] In the embodiment of the present application, when setting the scan lines 30, two sub-pixels are set between two adjacent scan lines, and a scan line 30 is set every two sub-pixels. As shown in FIG2A , the scan lines 30 are taken as an example of a first scan line 301, a second scan line 302, and a third scan line 303. In this column, the first scan line 301 is set between the first sub-pixel 101 and the second sub-pixel 102, and the second scan line 302 is set between the third sub-pixel 103 and the first sub-pixel 101 in another pixel unit 100. In this way, the first scan line 301 and the second scan line 302 are separated by two sub-pixels.

[0060] As shown in FIG2A , when the data line 40 and scan line 30 are configured, the two sub-pixels electrically connected to the scan line 30 are located on either side of the scan line. Specifically, the second scan line 302 is used as an example for illustration. The second scan line 302 is electrically connected to the second sub-pixel 102 above it and to the second sub-pixel 102 in another pixel unit 100 below it. In other words, the second scan line 302 is electrically connected to both the second sub-pixel 102 in the first pixel unit 100 and the second sub-pixel 102 in the second pixel unit 100.

[0061] In this way, the same scan line can simultaneously control two sub-pixels and provide control signals to two different sub-pixels at the same time. In the embodiment of the present application, in the above-mentioned 3G2D pixel architecture, each level of scan line simultaneously controls two sub-pixels, and the two sub-pixels are provided with data signals by two data lines respectively. In this way, by reducing the total number of scan lines, the corresponding impedance on the scan lines is effectively reduced, and the charging time of the pixels is increased, thereby improving the charging efficiency of the sub-pixels and ensuring the overall performance of the display panel.

[0062] Furthermore, in the embodiment of the present application, when the second scan line 302 is electrically connected to two different sub-pixels, it can be electrically connected to sub-pixels at different locations through a provided via hole and in combination with a corresponding connection electrode 71. Specifically, the connection electrode 71 can pass through the first sub-pixel 101 through the via hole and be electrically connected to the second sub-pixel 102.

[0063] As shown in FIG2B , FIG2B is a simplified schematic diagram of the pixel unit corresponding to FIG2A . When electrically connecting different sub-pixels to corresponding scan lines 30, the connections are made through vias 68 provided in the corresponding regions of each sub-pixel to form an electrical connection relationship. Simultaneously, in each column, the first data line 401 can be electrically connected to the first sub-pixel 101 on the left and provide it with a positive voltage, while the second data line 402 can be electrically connected to the first sub-pixel 101 on the right and provide it with a negative voltage. This allows the sub-pixels to have voltages of different polarities and ensures that the charging rate of each sub-pixel is maintained at a high level.

[0064] As shown in FIG2C , FIG2C is a schematic diagram of the connection between the sub-pixels and the data lines and scan lines in a corresponding pixel unit in FIG2A . In combination with the structures in FIG2A and FIG2B , in the embodiment of the present application, within the pixel unit 100, the first sub-pixel 101 and the first sub-pixel 101 in another pixel unit are electrically connected to the first scan line 301 at the same time, and the first sub-pixel 101 is electrically connected to the corresponding data line, and the two sub-pixels connected to the first scan line 301 are respectively located on the upper and lower sides of the first scan line 301. Similarly, the second sub-pixel 102, the third sub-pixel 103 and the corresponding second scan line 302 and third scan line 303 are all connected in accordance with the above-mentioned connection method between the first scan line and the first sub-pixel, and form the arrangement and connection structure in the embodiment of the present application. No further details will be given here.

[0065] FIG3 is a schematic diagram illustrating another pixel structure arrangement according to an embodiment of the present application. Referring to the pixel structure in FIG2 , the second scan line 302 is still used as an example for illustration. In this case, the two sub-pixels electrically connected to the second scan line 302 are located on the same side of the second scan line 302, such as at corresponding positions above the second scan line 302.

[0066] At this time, the second scan line 302 is positioned below the corresponding position of the third sub-pixel 103, and the second scan line 302 is electrically connected to both the first sub-pixel 101 and the second sub-pixel 102 within the pixel unit 100. Thus, the second scan line 302 simultaneously controls two different sub-pixels on the same side. Furthermore, during the control process, the effects of coupling between upper and lower level signals on the pixel voltage can be effectively avoided. Furthermore, by placing the pixels on the same side of the scan line, the pixel signal can be immediately charged and refreshed after receiving the signal from the upper level scan line, thereby minimizing the problem of display quality degradation caused by coupling between different signals.

[0067] Specifically, when the second scan line 302 is electrically connected to the first sub-pixel 101 and the second sub-pixel 102 , the first connection area 65 on the left is connected to the second connection area 64 on the right through corresponding connection electrodes, thereby controlling two different sub-pixels at the same time.

[0068] Furthermore, in an embodiment of the present application, in combination with the structures in FIG. 2 and FIG. 3 , in an embodiment of the present application, the display panel further includes a common electrode line. The common electrode line is correspondingly arranged between two adjacent sub-pixels, and the arrangement direction of the common electrode line is the same as the arrangement direction of the scan line. At the same time, the common electrode line and the scan line are alternately arranged between two different sub-pixels. For example, the first common electrode line 201, the second common electrode line 202, and the third common electrode line 203. There are two sub-pixels arranged between the first common electrode line 201 and the second common electrode line 202, and the second scan line 302 is correspondingly arranged between the first common electrode line 201 and the second common electrode line 202.

[0069] As shown in Figure 4, Figure 4 is a schematic diagram of the display panel provided in an embodiment of the present application. In combination with the structures in Figures 2-3, when setting the above-mentioned data lines and scan lines, the first direction is the vertical direction and the second direction is the horizontal direction, so that the pixel units are arranged horizontally. In Figure 4, the architecture of the above-mentioned pixel structure can also be set to a vertical arrangement. At this time, when arranged vertically, the long side of each sub-pixel is set along the vertical direction, that is, the long side of each sub-pixel is the same as the first direction Y, which is equivalent to the first direction being the same as the direction of the row of the display panel. And the setting direction of the data line is set along the direction of the row of the display panel. The scan line is set along the direction of the column of the display panel, thereby forming a plurality of vertically arranged sub-pixels.

[0070] In the embodiment of the present application, the display panel 111 further includes a chip-on-film (COF) 521 and a driver circuit 522. Specifically, the COF 521 is disposed on a first side or a second side of the display panel, while the driver circuit 522 is correspondingly disposed on a third side. The first side is opposite the second side, and is the left and right side of the display panel. The third side is the bottom side of the display panel, i.e., the third side is the side of the display panel in the row direction.

[0071] As shown in Figures 5 and 6, Figure 5 is a schematic diagram of the vertically arranged pixel structure provided in an embodiment of the present application, and Figure 6 is a layout structure diagram corresponding to the vertically arranged pixel structure. In combination with the above-mentioned horizontally arranged structure, in an embodiment of the present application, the first data line 401 and the second data line 402 are arranged along the horizontal direction of the display panel. At the same time, the first scan line 301, the second scan line 302, and the third scan line 303 are arranged along the vertical direction of the display panel. In this way, the first data line 401 and the second data line 402 intersect with different scan lines and form a plurality of sub-pixels. At this time, the pixel unit 100 is still arranged in an array within the display area of ​​the display panel. See the array arrangement structure in Figure 5 for details, which will not be repeated here.

[0072] In the embodiment of the present application, when a vertical arrangement structure is set, the polarities of the data voltages corresponding to the first data line 401 and the second data line 402 are different, and data voltages are provided to different sub-pixels respectively, and the above-mentioned common electrode lines and scanning lines are alternately arranged in sequence, so that two different sub-pixels are set between every two adjacent scanning lines.

[0073] Specifically, the first scan line 301 is vertically arranged between the first sub-pixel 101 and the second sub-pixel 102, the first common electrode line 201 is vertically arranged between the second sub-pixel 102 and the third sub-pixel 103, and the second scan line 302 is arranged between the third sub-pixel 103 and the first sub-pixel 101 of another pixel unit 100. Different scan lines and common electrode lines are arranged in sequence according to this distribution rule, and finally the arrangement structure shown in Figure 5 is formed.

[0074] Each scan line controls two different sub-pixels simultaneously. As shown in FIG5 , since the voltage polarities of the first data line 401 and the second data line 402 are opposite, while the voltage polarities on the same scan line are the same, adjacent sub-pixels have opposite polarities. This reduces the number of scan line levels and mitigates the coupling effect between scan lines of different levels.

[0075] At the same time, in the vertical arrangement structure of sub-pixels, the data line and the cover chip film 521 are placed on the left or right side of the display panel, and the driving circuit 522 is integrated at the bottom of the display panel. The 3G2D pixel structure design is used to realize the vertical arrangement display of pixels, thereby effectively improving the display viewing angle compared to the horizontal arrangement.

[0076] Furthermore, different vertical pixel arrangements can implement either a flip architecture or a stripe architecture within the display panel. As shown in Figure 5, when the scan lines and common electrode lines are fixed in the same column and do not switch, the voltage polarities of adjacent row and column sub-pixels are opposite, indicating flip dot inversion.

[0077] Furthermore, as shown in Figures 7 and 8, another schematic diagram of a vertical subpixel arrangement according to an embodiment of the present application is provided. In conjunction with the pixel structure of Figures 5 and 6, as detailed in Figure 7, when the pixel unit 100 is configured, it is configured as a stripe architecture. In this case, the voltages corresponding to the first data line 401 and the second data line 402 have opposite polarities and are electrically connected to the corresponding subpixels. At the same time, the different scan lines and different common electrode lines are alternately arranged, and the same scan line simultaneously controls two different subpixels. Compared to the flip architecture of Figure 6, in this embodiment of the present application, the voltages corresponding to two adjacent subpixels in the same column have the same polarity, while the voltages corresponding to two adjacent subpixels in the same row have different polarities. For example, in the first row, the first subpixel 101 and the third subpixel 103 have negative voltages, while the second subpixel 102, located between the first and third subpixels 101 and 103, has a positive voltage. Meanwhile, in the second row, the corresponding first sub-pixel 101 and third sub-pixel 103 are also set to the same negative voltage, while the second sub-pixel 102 is set to a positive voltage, so that sub-pixels at different positions have different polarities.

[0078] That is, when the scan lines and common electrode lines periodically switch in the vertical direction, the voltage polarity of adjacent row sub-pixels is the same, while the voltage polarity of adjacent column sub-pixels is opposite. In this case, the display drive mode of the display panel is stripe column inversion. Optionally, for the 3G2D pixel structure design, in addition to the above two display drive modes, other arrangement methods and display drive modes are also applicable and will not be detailed here.

[0079] In an embodiment of the present application, by resetting the different data lines and the corresponding scan lines and pixel units in the display panel and changing the electrical connection relationship between them, the signal coupling effect between different signal lines is effectively reduced, and the charging rate of the pixels is effectively improved, thereby ensuring the comprehensive performance of the display panel.

[0080] Furthermore, an embodiment of the present application also provides a display device, which includes the display panel in the embodiment of the present application. When preparing the display panel in the embodiment of the present application, the pixel structure provided above is used to arrange different signal lines and pixel units, thereby effectively improving the charging rate of the pixels and ensuring the overall performance of the panel.

[0081] To sum up, the above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present application. Although the present application is disclosed as above with preferred embodiments, the above preferred embodiments are not used to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A display panel, wherein a plurality of pixel units are arranged in an array in a first direction and a second direction, and a plurality of sub-pixels are arranged in each of the pixel units; a plurality of data lines arranged along the first direction and electrically connected to each of the sub-pixels, and a group of the data lines is arranged between two adjacent pixel units; and, a plurality of scanning lines arranged along the second direction and electrically connected to the sub-pixels; and, A common electrode line, wherein the common electrode line and the scanning line are alternately arranged between two different sub-pixels; in, Each group of data lines includes a first data line and a second data line that are adjacently arranged, and the polarities of the voltages on the first data line and the second data line are different; Two sub-pixels are disposed between two adjacent scan lines, and in the second direction, each scan line is electrically connected to two different sub-pixels. 2 . The display panel according to claim 1 , wherein the scan line is electrically connected to two sub-pixels located on two sides of the scan line respectively.

3. The display panel according to claim 2, wherein each of the pixel units comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel are sequentially arranged along the first direction; in, The scan line is disposed between the first sub-pixel and the third sub-pixel, and the scan line is electrically connected to the second sub-pixel in the first pixel unit and the second sub-pixel in the second pixel unit at the same time. 4 . The display panel according to claim 1 , wherein the scan line is electrically connected to two different sub-pixels located on the same side of the scan line.

5. The display panel according to claim 4, characterized in that: Each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel are sequentially arranged along the first direction; The scan line is disposed at a corresponding position below the third sub-pixel, and the scan line is electrically connected to the first sub-pixel and the second sub-pixel at the same time. 6 . The display panel according to claim 1 , wherein in the first direction, polarities of voltages on two adjacent sub-pixels are different.

7. The display panel according to claim 1, wherein the display panel further comprises a chip-on-chip film and a driving circuit, the chip-on-chip film is arranged on a first side or a second side of the display panel, the first side and the second side are corresponding sides in the column direction of the display panel, and the driving circuit is arranged on a third side of the display panel, and the third side is a corresponding side in the row direction of the display panel.

8. The display panel according to claim 7, wherein the first direction is the same as a row direction of the display panel, and the first data line and the second data line are disposed between two adjacent pixel units; in, In the same row direction, the voltage polarities of two adjacent sub-pixels are different.

9. A display panel, wherein a plurality of pixel units are arranged in an array in a first direction and a second direction, and a plurality of sub-pixels are arranged in each of the pixel units; a plurality of data lines arranged along the first direction and electrically connected to each of the sub-pixels, and a group of the data lines is arranged between two adjacent pixel units; and, a plurality of scanning lines arranged along the second direction and electrically connected to the sub-pixels; in, Each group of data lines includes a first data line and a second data line that are adjacently arranged, and the polarities of the voltages on the first data line and the second data line are different; Two sub-pixels are disposed between two adjacent scan lines, and in the second direction, each scan line is electrically connected to two different sub-pixels. 10 . The display panel according to claim 9 , wherein the scan line is electrically connected to two sub-pixels located on two sides of the scan line respectively.

11. The display panel according to claim 10, wherein each of the pixel units comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel are sequentially arranged along the first direction; in, The scan line is disposed between the first sub-pixel and the third sub-pixel, and the scan line is electrically connected to the second sub-pixel in the first pixel unit and the second sub-pixel in the second pixel unit at the same time. 12 . The display panel according to claim 9 , wherein the scan line is electrically connected to two different sub-pixels located on the same side of the scan line.

13. The display panel according to claim 12, wherein each of the pixel units comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel are sequentially arranged along the first direction; in, The scan line is disposed at a corresponding position below the third sub-pixel, and the scan line is electrically connected to the first sub-pixel and the second sub-pixel at the same time. 14 . The display panel according to claim 9 , wherein in the first direction, polarities of voltages on two adjacent sub-pixels are different.

15. The display panel according to claim 9, wherein the display panel further comprises a chip-on-chip film and a driving circuit, the chip-on-chip film is arranged on a first side or a second side of the display panel, the first side and the second side are corresponding sides in the column direction of the display panel, and the driving circuit is arranged on a third side of the display panel, and the third side is a corresponding side in the row direction of the display panel.

16. The display panel according to claim 15, wherein the first direction is the same as a row direction of the display panel, and the first data line and the second data line are disposed between two adjacent pixel units; in, In the same row direction, the voltage polarities of two adjacent sub-pixels are different.

17. The display panel according to claim 9, wherein the display panel further comprises common electrode lines, the arrangement direction of the common electrode lines is the same as the arrangement direction of the scan lines, and the common electrode lines and the scan lines are alternately arranged between different sub-pixels in sequence.

18. A display device, comprising a display panel, the display panel comprising: A plurality of pixel units are arrayed in the first direction and the second direction, and a plurality of sub-pixels are arranged in each of the pixel units; a plurality of data lines arranged along the first direction and electrically connected to each of the sub-pixels, and a group of the data lines is arranged between two adjacent pixel units; and, a plurality of scanning lines arranged along the second direction and electrically connected to the sub-pixels; Each group of data lines includes a first data line and a second data line that are adjacently arranged, and the polarities of the voltages on the first data line and the second data line are different; Two sub-pixels are disposed between two adjacent scan lines, and in the second direction, each scan line is electrically connected to two different sub-pixels. 19 . The display device according to claim 18 , wherein the scan line is electrically connected to two sub-pixels located on two sides of the scan line respectively. 20 . The display device according to claim 18 , wherein the scan line is electrically connected to two different sub-pixels located on the same side of the scan line.

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