Open-drain output circuit and chip

Abstract

Disclosed in the present invention are an open-drain output circuit and a chip. The circuit comprises: a first pull-down unit, a pull-up resistor, and a second pull-down unit and / or a third pull-down unit, wherein the first pull-down unit comprises a first inverting unit, a first MOS transistor and a first resistor, a control end of the first MOS transistor being connected to the first inverting unit, the first MOS transistor being connected to the pull-up resistor and an output end of the output circuit, and the first resistor being connected to the first MOS transistor; the second pull-down unit pulls down the voltage of the output end when a first power supply voltage is relatively low; and the third pull-down unit pulls down the voltage of the output end in the descending process of the first power supply voltage. In the open-drain output circuit and the chip of the present invention, by means of the first pull-down unit, the voltage of the output end is pulled down so as to output a low level when the first power supply voltage is low; by means of the second pull-down unit, the output end is prevented from output overshoot during the rapid power-down process of the first power supply voltage, thus solving the abnormal situation where an output driver chip is reenabled during the power-down process.

Description

Open-drain output circuit and chip

[0001] This invention claims priority to Chinese patent application number 202311115528.9 filed with the Patent Office of China on August 31, 2023, entitled “Open-drain output circuit and chip”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of integrated circuits, and in particular to an open-drain output circuit and a chip. Background Art

[0003] Figure 1 shows a typical open-drain output structure, where high-level drive capability is provided by an external pull-up resistor, RPU_ext. Because the output voltage is determined by the second power supply voltage, VS_ext, this structure is well-suited for applications requiring level shifting. However, if the output terminal OUT of the open-drain output structure is to be set to a low level by default, the chip's internal first power supply voltage, VS_in, is equal to 0. The open-drain MOS transistor, M1, has no pull-down capability, and the voltage at the output terminal OUT equals the second power supply voltage, VS_ext, resulting in a high level.

[0004] The open-drain structure shown in Figure 2 connects the drain and gate terminals of an open-drain MOS transistor M1 via resistor R1. When the first power supply voltage VS_in is zero and the second power supply voltage VS_ext is present, the open-drain MOS transistor M1 has a certain pull-down capability, causing the output terminal OUT to output a low level by default. At this time, current flows from the second power supply voltage VS_ext through the pull-up resistor RPU_ext and resistor R1. The connection between the substrate and the drain terminal of the MOS transistor M4 in Figure 2 prevents current from flowing back from the second power supply voltage VS_ext to the first power supply voltage VS_in.

[0005] The open-drain structure shown in Figure 2 already achieves a default pull-down at the output terminal OUT and prevents backflow between ports. As the first power supply voltage VS_in gradually increases, the gate voltage of the open-drain MOS transistor M1 increases, and the pull-down capability of the open-drain MOS transistor M1 gradually increases. At this time, due to the presence of MOS transistor M4, the voltage difference between the gate voltage of MOS transistor M1 and the first power supply voltage VS_in is Vdsat (the voltage between the source and drain terminals of MOS transistor M2) + Vgs (the voltage between the source and gate terminals of MOS transistor M4). As a result, the first power supply voltage VS_in must be sufficiently high to drive the MOS transistor M1 to pull down. Ultimately, when the first power supply voltage VS_in is low, the pull-down capability of MOS transistor M1 is limited, and the voltage at the output terminal OUT is not low enough.

[0006] At the same time, the open-drain structure shown in Figure 2 also suffers from the problem of power-down overshoot. When the second power supply voltage VS_ext is active and the first power supply voltage VS_in is rapidly powered down, when the first power supply voltage VS_in drops to a point where it cannot pull the MOS transistor M1 down, the voltage at the output terminal OUT stops dropping and is applied to the gate of the MOS transistor M1 through resistor R1, providing pull-down capability for the MOS transistor M1. It is known that to reduce leakage at the output terminal OUT when the MOS transistor M1 is turned off, the resistance of resistor R1 must be at least in the MΩ range. To achieve better pull-down capability, the W / L (width-to-length ratio) of the MOS transistor M1 must be sufficiently large. Consequently, the parasitic capacitance from the gate of the MOS transistor M1 to ground is also very large. Therefore, a large RC exists between the voltage at the output terminal OUT and the gate of the MOS transistor M1. As a result, when the first power supply voltage VS_in drops to a critical point where it cannot pull the MOS transistor M1 down, the gate voltage of the MOS transistor M1 cannot continue to drop, causing the voltage at the output terminal OUT to overshoot, eventually leading to the two voltages becoming consistent.

[0007] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art.

[0008] Summary of the Invention

[0009] The object of the present invention is to provide an open-drain output circuit and chip, which can improve the pull-down of the MOS tube when the first power supply voltage is low, and prevent the voltage at the output end of the open-drain output circuit from overshooting when the first power supply voltage is quickly powered off.

[0010] To achieve the above objectives, an embodiment of the present invention provides an open-drain output circuit, comprising: a first pull-down unit and a pull-up resistor, and a second pull-down unit and / or a third pull-down unit.

[0011] The first pull-down unit includes a first inverting unit, a first MOS transistor, and a first resistor. The first inverting unit is connected between a first power supply voltage and a ground voltage. The first inverting unit has a first input terminal and a first output terminal. The control terminal of the first MOS transistor is connected to the first output terminal of the first inverting unit. The first terminal of the first MOS transistor is connected to the first terminal of the pull-up resistor and the output terminal of the open-drain output circuit. The second terminal of the first MOS transistor is connected to the ground voltage. The second terminal of the pull-up resistor is connected to the second power supply voltage. The first terminal of the first resistor is connected to the first terminal of the first MOS transistor. The second terminal of the first resistor is connected to the control terminal of the first MOS transistor.

[0012] The second pull-down unit is used to pull down the voltage of the output end of the open-drain output circuit when the first power supply voltage is lower than the first power supply voltage, and the third pull-down unit is used to pull down the voltage of the output end of the open-drain output circuit when the first power supply voltage is powered off;

[0013] The second pull-down unit includes a second inverting unit and a seventh MOS transistor, the second inverting unit is connected between the first power supply voltage and the ground voltage, the second inverting unit has a second input end and a second output end, the control end of the seventh MOS transistor is connected to the second output end of the second inverting unit, the first end of the seventh MOS transistor is connected to the output end of the open-drain output circuit, and the second end of the seventh MOS transistor is connected to the ground voltage;

[0014] The third pull-down unit includes a third inverting unit and an eleventh MOS transistor. The third inverting unit is connected between the first power supply voltage and the ground voltage. The third inverting unit has a third input terminal and a third output terminal. The control terminal of the eleventh MOS transistor is connected to the third output terminal of the third inverting unit. The first terminal of the eleventh MOS transistor is connected to the output terminal of the open-drain output circuit. The second terminal of the eleventh MOS transistor is connected to the ground voltage.

[0015] In one or more embodiments of the present invention, the first inverting unit includes a second MOS transistor, a first backflow prevention unit and a third MOS transistor; the control end of the second MOS transistor is connected to the control end of the third MOS transistor to form the first input end of the first inverting unit, the second end of the second MOS transistor is connected to the first power supply voltage, the first end of the second MOS transistor is connected to the second end of the first backflow prevention unit, and the first end of the third MOS transistor is connected to the first end of the first backflow prevention unit to form the first output end of the first inverting unit.

[0016] In one or more embodiments of the present invention, the first backflow prevention unit includes a fourth MOS transistor or a first diode, the second end of the fourth MOS transistor is connected to the first end of the second MOS transistor, the control end of the fourth MOS transistor is connected to the first end of the fourth MOS transistor, the first end of the fourth MOS transistor is connected to the first end of the third MOS transistor, the anode of the first diode is connected to the first end of the second MOS transistor, and the cathode of the first diode is connected to the first end of the third MOS transistor.

[0017] In one or more embodiments of the present invention, the second inverting unit includes a fifth MOS transistor and a sixth MOS transistor. The first end of the fifth MOS transistor and the first end of the sixth MOS transistor are connected to form the second output end of the second inverting unit. The control end of the fifth MOS transistor and the control end of the sixth MOS transistor are connected to form the second input end of the second inverting unit. The second end of the fifth MOS transistor is connected to the first power supply voltage, and the second end of the sixth MOS transistor is connected to the ground voltage.

[0018] In one or more embodiments of the present invention, the third inverting unit includes an eighth MOS transistor, a second backflow prevention unit, and a tenth MOS transistor. The control end of the eighth MOS transistor is connected to the control end of the tenth MOS transistor to form a third input end of the third inverting unit. The first end of the eighth MOS transistor is connected to the second end of the second backflow prevention unit. The first end of the second backflow prevention unit is connected to the first end of the tenth MOS transistor to form a third output end of the third inverting unit.

[0019] In one or more embodiments of the present invention, the second backflow prevention unit includes a ninth MOS transistor or a second diode, the first end of the ninth MOS transistor is connected to the control end of the ninth MOS transistor and to the first end of the tenth MOS transistor, the second end of the ninth MOS transistor is connected to the first end of the eighth MOS transistor, the anode of the second diode is connected to the first end of the eighth MOS transistor, and the cathode of the second diode is connected to the first end of the tenth MOS transistor.

[0020] In one or more embodiments of the present invention, the width-to-length ratio of the first MOS transistor and the seventh MOS transistor is 4:3.

[0021] In one or more embodiments of the present invention, the width-to-length ratio of the first MOS transistor and the eleventh MOS transistor is 4:1.

[0022] In one or more embodiments of the present invention, the width-to-length ratio of the first MOS transistor, the seventh MOS transistor, and the eleventh MOS transistor is 4:3:1.

[0023] The invention also discloses a chip comprising the open-drain output circuit.

[0024] Compared with the prior art, according to the open-drain output circuit and chip of the embodiments of the present invention, the open-drain output circuit, through the second pull-down unit composed of the second inverting unit and the seventh MOS transistor, can pull down and control the output end of the open-drain output circuit to output a low level under a low first power supply voltage; through the third pull-down unit composed of the third inverting unit and the eleventh MOS transistor, when the first MOS transistor connected in a diode manner is used to pull down the output end of the default open-drain output circuit, the output end of the open-drain output circuit is prevented from generating an output overshoot during a rapid power-off process of the first power supply voltage, thereby solving the abnormal situation of the output-driven chip being re-enabled during the power-off process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a circuit diagram of an open-drain output circuit according to a prior art.

[0026] FIG2 is a circuit schematic diagram of an open-drain output circuit according to another prior art.

[0027] FIG3 is a circuit diagram of an open-drain output circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0029] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0030] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0031] Example 1

[0032] As shown in FIG3 , an open-drain output circuit includes a pull-up resistor Rp, a first pull-down unit, a second pull-down unit, and a third pull-down unit.

[0033] The first pull-down unit includes: a first inverting unit 10, a first MOS transistor M1 and a first resistor R1.

[0034] The first inverting unit 10 is connected between a first power supply voltage VS_in and a ground voltage GND. The first inverting unit 10 has a first input terminal IN and a first output terminal. The control terminal of the first MOS transistor M1 is connected to the first output terminal of the first inverting unit 10 to form a node G1. The first terminal of the first MOS transistor M1 is connected to the first terminal of the pull-up resistor Rp and the output terminal OUT of the open-drain output circuit. The second terminal of the first MOS transistor M1 is connected to the ground voltage GND. The second terminal of the pull-up resistor Rp is connected to the second power supply voltage VS_ext. The first terminal of the first resistor R1 is connected to the first terminal of the first MOS transistor M1, and the second terminal of the first resistor R1 is connected to the control terminal of the first MOS transistor M1. In one embodiment, the first power supply voltage VS_in is an on-chip power supply, and the second power supply voltage VS_ext is an off-chip power supply. In other embodiments, the first power supply voltage VS_in and the second power supply voltage VS_ext can be the same on-chip power supply or an off-chip power supply.

[0035] In one embodiment, the first MOS transistor M1 is an N-channel MOS transistor, the control end of the first MOS transistor M1 is a gate, the first end of the first MOS transistor M1 is a drain, and the second end of the first MOS transistor M1 is a source.

[0036] The first inverting unit 10 includes a second MOS transistor M2, a first backflow prevention unit, and a third MOS transistor M3. The control terminal of the second MOS transistor M2 is connected to the control terminal of the third MOS transistor M3 to form a first input terminal IN of the first inverting unit 10. The second terminal of the second MOS transistor M2 is connected to the first power supply voltage VS_in. The first terminal of the second MOS transistor M2 is connected to the second terminal of the first backflow prevention unit. The first terminal of the third MOS transistor M3 is connected to the first terminal of the first backflow prevention unit to form a first output terminal of the first inverting unit 10.

[0037] In one embodiment, the first backflow prevention unit includes a fourth MOS transistor M4. The second end of the fourth MOS transistor M4 is connected to the first end of the second MOS transistor M2, the control end of the fourth MOS transistor M4 is connected to the first end of the fourth MOS transistor M4, and the first end of the fourth MOS transistor M4 is connected to the first end of the third MOS transistor M3, i.e., the fourth MOS transistor M4 is connected in a diode configuration. In other embodiments, the first backflow prevention unit includes a first diode, the anode of the first diode being connected to the first end of the second MOS transistor M2, and the cathode of the first diode being connected to the first end of the third MOS transistor M3.

[0038] In one embodiment, the second MOS transistor M2 and the fourth MOS transistor M4 are P-channel MOS transistors, the third MOS transistor M3 is an N-channel MOS transistor, the control terminals of the second MOS transistor M2, the fourth MOS transistor M4, and the third MOS transistor M3 are all gates, the first terminals of the second MOS transistor M2, the fourth MOS transistor M4, and the third MOS transistor M3 are all drains, and the second terminals of the second MOS transistor M2, the fourth MOS transistor M4, and the third MOS transistor M3 are all sources.

[0039] The second pull-down unit is configured to pull down the voltage of the output terminal OUT of the open-drain output circuit when the first power supply voltage VS_in is low. The third pull-down unit is configured to pull down the voltage of the output terminal OUT of the open-drain output circuit when the first power supply voltage VS_in is powered down. In one embodiment, the low first power supply voltage VS_in is generally 1.2±0.3V.

[0040] As shown in Figure 3, the second pull-down unit includes a second inverting unit 20 and a seventh MOS transistor M7. The second inverting unit 20 is connected between the first power supply voltage VS_in and the ground voltage GND. The second inverting unit 20 has a second input terminal and a second output terminal. The second input terminal of the second inverting unit 20 is connected to the first input terminal IN of the first inverting unit 10. The control terminal of the seventh MOS transistor M7 is connected to the second output terminal of the second inverting unit 20 to form a node G2. The first terminal of the seventh MOS transistor M7 is connected to the output terminal OUT of the open-drain output circuit, and the second terminal of the seventh MOS transistor M7 is connected to the ground voltage GND.

[0041] In one embodiment, the seventh MOS transistor M7 is an N-channel MOS transistor, the control end of the seventh MOS transistor M7 is a gate, the first end of the seventh MOS transistor M7 is a drain, and the second end of the seventh MOS transistor M7 is a source.

[0042] The second inverting unit 20 includes a fifth MOS transistor M5 and a sixth MOS transistor M6. A first end of the fifth MOS transistor M5 and a first end of the sixth MOS transistor M6 are connected to form a second output end of the second inverting unit 20. A control end of the fifth MOS transistor M5 and a control end of the sixth MOS transistor M6 are connected to form a second input end of the second inverting unit 20. A second end of the fifth MOS transistor M5 is connected to a first power supply voltage VS_in, and a second end of the sixth MOS transistor M6 is connected to a ground voltage GND.

[0043] In one embodiment, the fifth MOS transistor M5 is a P-channel MOS transistor, the sixth MOS transistor M6 is an N-channel MOS transistor, the control terminals of the fifth MOS transistor M5 and the sixth MOS transistor M6 are both gates, the first terminals of the fifth MOS transistor M5 and the sixth MOS transistor M6 are both drains, and the second terminals of the fifth MOS transistor M5 and the sixth MOS transistor M6 are both sources.

[0044] The third pull-down unit includes a third inverting unit 30 and an eleventh MOS transistor M11. The third inverting unit 30 is connected between the first power supply voltage VS_in and the ground voltage GND. The third inverting unit 30 has a third input terminal and a third output terminal. The third input terminal of the third inverting unit 30 is connected to the first input terminal IN of the first inverting unit 10. The control terminal of the eleventh MOS transistor M11 is connected to the third output terminal of the third inverting unit 30 to form a node G3. The first terminal of the eleventh MOS transistor M11 is connected to the output terminal OUT of the open-drain output circuit, and the second terminal of the eleventh MOS transistor M11 is connected to the ground voltage GND.

[0045] The third inverting unit 30 includes an eighth MOS transistor M8, a second backflow prevention unit, and a tenth MOS transistor M10. The control terminal of the eighth MOS transistor M8 is connected to the control terminal of the tenth MOS transistor M10 to form a third input terminal of the third inverting unit 30. The first terminal of the eighth MOS transistor M8 is connected to the second terminal of the second backflow prevention unit. The first terminal of the second backflow prevention unit is connected to the first terminal of the tenth MOS transistor M10 to form a third output terminal of the third inverting unit 30.

[0046] The second backflow prevention unit includes a ninth MOS transistor M9, a first end of which is connected to the control end of the ninth MOS transistor M9 and to the first end of the tenth MOS transistor M10. The second backflow prevention unit includes a second end of the ninth MOS transistor M9 connected to the first end of the eighth MOS transistor M8. In other embodiments, a second diode is provided, wherein the anode of the second diode is connected to the first end of the eighth MOS transistor M8, and the cathode of the second diode is connected to the first end of the tenth MOS transistor M10.

[0047] In one embodiment, the eighth MOS transistor M8 and the ninth MOS transistor M9 are P-channel MOS transistors, the tenth MOS transistor M10 is an N-channel MOS transistor, the control terminals of the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all gates, the first terminals of the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all drains, and the second terminals of the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all sources.

[0048] In one embodiment, the width-to-length ratio of the first MOS transistor M1, the seventh MOS transistor M7, and the eleventh MOS transistor M11 is 4:3:1. While minimizing chip area, the required pull-down capability is achieved by selecting MOS transistors with appropriate width-to-length ratios. The larger areas of the first MOS transistor M1, the seventh MOS transistor M7, and the eleventh MOS transistor M11 can be reused as MOS transistors for electrostatic discharge (ESD) in the ESD circuit. In other embodiments, the width-to-length ratio of the first MOS transistor M1, the seventh MOS transistor M7, and the eleventh MOS transistor M11 can also be other ratios.

[0049] As shown in FIG1 , because the seventh MOS transistor M7 does not connect its control terminal and first terminal to each other but instead forms a diode, current backflow does not occur, and a backflow prevention MOS transistor is not required at the first terminal of the fifth MOS transistor M5. The voltage Vdsat5 between the second terminal and the first terminal of the fifth MOS transistor M5 is significantly lower than the sum of the voltage Vdsat2 between the second terminal and the first terminal of the second MOS transistor M2 and the voltage Vgs4 between the control terminal and the second terminal of the fourth MOS transistor M4. When the difference between the first power supply voltage VS_in and the voltage Vdsat5 between the second terminal and the first terminal of the fifth MOS transistor M5 is greater than the voltage Vth7 between the control terminal and the second terminal of the seventh MOS transistor M7, the seventh MOS transistor M7 is turned on and has the ability to pull down the output terminal OUT. This ensures that, even at low first power supply voltage VS_in, the seventh MOS transistor M7 has a stronger pull-down capability for the output terminal OUT than the first MOS transistor M1.

[0050] During power-off of the first power supply voltage VS_in, the current at node G1 flows to the output terminal OUT and then flows from the first MOS transistor M1 to the ground voltage GND. Therefore, the voltage at node G1 decreases as the first power supply voltage VS_in decreases. The current at node G2 flows to the first power supply voltage VS_in, and the voltage at node G2 decreases as the first power supply voltage VS_in decreases. Node G3 has no current path to the output terminal OUT, and the addition of the ninth MOS transistor M9, whose substrate is connected to the first terminal, prevents current from flowing from node G3 to the first power supply voltage VS_in. Therefore, node G3 does not decrease as the first power supply voltage VS_in decreases during power-off of the first power supply voltage VS_in. That is, during a rapid decrease of the first power supply voltage VS_in (especially near the end of power-off), the eleventh MOS transistor M11 maintains a pull-down capability, and the voltage overshoot at the output terminal OUT disappears.

[0051] In one embodiment, when the first power supply voltage VS_in is less than the sum of Vdsat5 of the fifth MOS transistor M5 and Vth7 of the seventh MOS transistor M7 , the first MOS transistor M1 is turned on to provide a pull-down capability for the output terminal OUT.

[0052] When the first power supply voltage VS_in is less than the sum of the voltage Vdsat2 between the second terminal and the first terminal of the second MOS transistor M2, the voltage Vgs4 between the second terminal and the control terminal of the fourth MOS transistor M4, and the voltage Vth1 between the control terminal and the second terminal of the first MOS transistor M1, but is greater than the sum of the voltage Vdsat5 between the second terminal and the first terminal of the fifth MOS transistor M5 and the voltage Vth7 between the control terminal and the second terminal of the seventh MOS transistor M7, the seventh MOS transistor M7 is turned on to provide a pull-down capability for the output terminal OUT.

[0053] When the first power supply voltage VS_in is greater than the sum of Vdsat2 of the second MOS transistor M2, Vgs4 of the fourth MOS transistor M4, and the voltage Vth1 between the control terminal and the second terminal of the first MOS transistor, the first MOS transistor M1 and the seventh MOS transistor M7 are turned on to simultaneously provide pull-down capability for the output terminal OUT.

[0054] When the first power supply voltage VS_in is in a fast power-down state, especially when it is powered down to close to 0V or 0V, the eleventh MOS transistor M11 is always turned on to pull down, thereby eliminating overshoot; when the first power supply voltage VS_in is in a slow power-down state, the turn-on and turn-off conditions of the first MOS transistor M1 and the eleventh MOS transistor M11 are the same.

[0055] Example 2

[0056] In one embodiment, only the first pull-down unit, the pull-up resistor Rp, and the second pull-down unit are provided. The connection relationship of each component is the same as that described in Embodiment 1 and will not be repeated here. The width-to-length ratio of the first MOS transistor M1 and the seventh MOS transistor M7 is 4:3.

[0057] Example 3

[0058] In one embodiment, only the first pull-down unit, the pull-up resistor Rp and the third pull-down unit are provided. The connection relationship of each component is the same as that described in Embodiment 1 and will not be repeated here. The width-to-length ratio of the first MOS transistor M1 and the eleventh MOS transistor M11 is 4:1.

[0059] The present invention also discloses a chip, comprising the open-drain output circuit of embodiment 1, embodiment 2 or embodiment 3.

[0060] The foregoing descriptions of specific exemplary embodiments of the present invention are for the purpose of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings, and the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different options and changes without departing from the scope and spirit of the present invention. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. An open-drain output circuit, characterized in that: include: A first pull-down unit and a pull-up resistor; The first pull-down unit includes a first inverting unit, a first MOS transistor and a first resistor, the first inverting unit is connected between a first power supply voltage and a ground voltage, the first inverting unit has a first input end and a first output end, the control end of the first MOS transistor is connected to the first output end of the first inverting unit, the first end of the first MOS transistor is connected to the first end of the pull-up resistor and the output end of the open-drain output circuit, the second end of the first MOS transistor is connected to the ground voltage, the second end of the pull-up resistor is connected to the second power supply voltage, the first end of the first resistor is connected to the first end of the first MOS transistor, and the second end of the first resistor is connected to the control end of the first MOS transistor; The open-drain output circuit further comprises a second pull-down unit and / or a third pull-down unit, wherein the second pull-down unit is used to pull down the voltage at the output end of the open-drain output circuit when the first power supply voltage is lower than the first power supply voltage, and the third pull-down unit is used to pull down the voltage at the output end of the open-drain output circuit when the first power supply voltage is powered off; The second pull-down unit includes a second inverting unit and a seventh MOS transistor, the second inverting unit is connected between the first power supply voltage and the ground voltage, the second inverting unit has a second input end and a second output end, the control end of the seventh MOS transistor is connected to the second output end of the second inverting unit, the first end of the seventh MOS transistor is connected to the output end of the open-drain output circuit, and the second end of the seventh MOS transistor is connected to the ground voltage; The third pull-down unit includes a third inverting unit and an eleventh MOS transistor, the third inverting unit is connected between the first power supply voltage and the ground voltage, the third inverting unit has a third input end and a third output end, the control end of the eleventh MOS transistor is connected to the third output end of the third inverting unit, the first end of the eleventh MOS transistor is connected to the output end of the open-drain output circuit, and the second end of the eleventh MOS transistor is connected to the ground voltage.

2. The capacitive operational amplifier according to claim 1, wherein: The first inverting unit includes a second MOS tube, a first backflow prevention unit and a third MOS tube; the control end of the second MOS tube is connected to the control end of the third MOS tube to form a first input end of the first inverting unit, the second end of the second MOS tube is connected to a first power supply voltage, the first end of the second MOS tube is connected to the second end of the first backflow prevention unit, and the first end of the third MOS tube is connected to the first end of the first backflow prevention unit to form a first output end of the first inverting unit.

3. The open-drain output circuit according to claim 2, characterized in that: The first anti-backflow unit includes a fourth MOS tube or a first diode, the second end of the fourth MOS tube is connected to the first end of the second MOS tube, the control end of the fourth MOS tube is connected to the first end of the fourth MOS tube, the first end of the fourth MOS tube is connected to the first end of the third MOS tube, the anode of the first diode is connected to the first end of the second MOS tube, and the cathode of the first diode is connected to the first end of the third MOS tube.

4. The open-drain output circuit according to claim 1, wherein: The second inverting unit includes a fifth MOS tube and a sixth MOS tube, a first end of the fifth MOS tube and a first end of the sixth MOS tube are connected to form a second output end of the second inverting unit, a control end of the fifth MOS tube and a control end of the sixth MOS tube are connected to form a second input end of the second inverting unit, a second end of the fifth MOS tube is connected to a first power supply voltage, and a second end of the sixth MOS tube is connected to a ground voltage.

5. The open-drain output circuit according to claim 1, wherein: The third inverting unit includes an eighth MOS tube, a second backflow prevention unit and a tenth MOS tube, the control end of the eighth MOS tube is connected to the control end of the tenth MOS tube to form a third input end of the third inverting unit, the first end of the eighth MOS tube is connected to the second end of the second backflow prevention unit, and the first end of the second backflow prevention unit is connected to the first end of the tenth MOS tube to form a third output end of the third inverting unit.

6. The open-drain output circuit according to claim 5, characterized in that: The second backflow prevention unit includes a ninth MOS tube or a second diode, the first end of the ninth MOS tube is connected to the control end of the ninth MOS tube and to the first end of the tenth MOS tube, the second end of the ninth MOS tube is connected to the first end of the eighth MOS tube, the anode of the second diode is connected to the first end of the eighth MOS tube, and the cathode of the second diode is connected to the first end of the tenth MOS tube.

7. The open-drain output circuit according to claim 1, wherein: The ratio of the width to length of the first MOS tube to that of the seventh MOS tube is 4:

3.

8. The open-drain output circuit according to claim 1, wherein: The ratio of the width to length of the first MOS tube to that of the eleventh MOS tube is 4:

1.

9. The open-drain output circuit according to claim 1, wherein: The ratio of the width to length of the first MOS tube, the seventh MOS tube and the eleventh MOS tube is 4:3:

1.

10. A chip, characterized in that: It comprises the open-drain output circuit as claimed in any one of claims 1 to 9.

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