Processor, computing chip and computing device

Abstract

The present disclosure relates to a processor, a computing chip and a computing device. Disclosed is a processor. The processor comprises: N registers; an arithmetic logic unit, which comprises a plurality of arithmetic logic sub-units, wherein each arithmetic logic sub-unit executes an operation, and an input of each arithmetic logic sub-unit is coupled to outputs of the N registers; and N multiplexers, wherein an input of each multiplexer is coupled to an output of each arithmetic logic sub-unit, and each multiplexer selects an output of a corresponding arithmetic logic sub-unit on the basis of a control signal. Each arithmetic logic sub-unit comprises: a selection module, which is coupled to the outputs of the N registers, and selects an output of a corresponding register on the basis of a control signal and transmits the output to an operation module, or does not select the output of any register and transmits a predetermined value to an operation module; and the operation module, which performs an operation on the output of the register transmitted by the selection module, wherein N is an integer greater than or equal to 2 and less than or equal to the number of arithmetic logic sub-units.

Description

Processors, computing chips, and computing devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority to the Chinese patent application with Chinese application number 202311077779.2 and application date August 25, 2023. The disclosed content of the Chinese patent application is hereby introduced as a whole into this application. Technical Field

[0003] The present disclosure relates to the field of computers. Specifically, the present disclosure relates to a processor, a computing chip including the processor, and a computing device, which are particularly suitable for computing related to neural networks. Background Art

[0004] Neural network applications often require processors to perform a large number of computations. The processor's computational efficiency, power consumption, and area are crucial to the efficiency and cost of the entire computing device.

[0005] Summary of the Invention

[0006] One of the objects of the present disclosure is to provide an improved processor.

[0007] According to one aspect of the present disclosure, a processor is provided, which includes: N registers; an arithmetic logic unit (ALU) including multiple ALUs, each ALU being configured to perform an operation, and an input of each ALU being coupled to outputs of the N registers; and N multiplexers, each multiplexer having an input coupled to an output of each ALU of the ALU, and each multiplexer selecting an output of a corresponding ALU according to a control signal of the multiplexer, wherein each ALU includes: a selection module coupled to the outputs of the N registers, configured to select the output of a corresponding register and pass it to an operation module according to the control signal of the ALU, or not select the output of any register and pass a predetermined value indicating that the output of any register is not selected to the operation module; and an operation module configured to perform an operation on the output of the register passed by the selection module, wherein N is an integer greater than or equal to 2 and less than or equal to the number of ALUs.

[0008] According to another aspect of the present disclosure, a computing chip is provided, which includes one or more of the above-mentioned processors.

[0009] According to another aspect of the present disclosure, a computing device is provided, which includes one or more computing chips as described above.

[0010] Other characteristic features and advantages of the present disclosure will become apparent from the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The included drawings are for illustrative purposes only and are intended only to provide examples of possible structures and arrangements of the inventive apparatus and methods of applying the same to computing devices disclosed herein. These drawings in no way limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood by the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals represent similar structural elements.

[0012] FIG. 1 shows a schematic diagram of a processor in the related art.

[0013] FIG2 shows a schematic diagram of a processor according to an embodiment of the present disclosure.

[0014] FIG3 is a schematic diagram showing a connection method of an arithmetic logic subunit in a processor according to an embodiment of the present disclosure.

[0015] FIG4 shows a schematic diagram of a processor according to another embodiment of the present disclosure.

[0016] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0017] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0018] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0019] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or use. That is, the hash engines described herein are presented in an exemplary manner to illustrate various embodiments of the circuitry of the present disclosure and are not intended to be limiting. Those skilled in the art will appreciate that these are merely exemplary, not exhaustive, ways to implement the present disclosure.

[0020] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0021] 1 shows a schematic diagram of a related art processor 100. The processor 100 can be used to implement various arithmetic and logical calculations.

[0022] The processor 100 includes a register 110 , an arithmetic logic unit 120 , and a multiplexer 130 .

[0023] Register 110 is used to store data, and its output is coupled to an arithmetic logic unit 120. ALU 120 may include multiple arithmetic logic subunits AH, each of which is used to perform a specific operation. The input of each arithmetic logic subunit AH is coupled to the output of register 110. The input of multiplexer 130 is coupled to the output of each arithmetic logic subunit AH of arithmetic logic unit 120, and the output of a corresponding arithmetic logic subunit is selected based on a control signal (not shown) of the multiplexer.

[0024] When the processor 100 of the related art is running, data from register 110 is transferred to each arithmetic logic sub-unit AH of the arithmetic logic unit 120 for operation. The operation result of each arithmetic logic sub-unit AH is then output to multiplexer 130. Multiplexer 130 then selects the operation result of the corresponding arithmetic logic sub-unit as its output based on its control signal. For example, multiplexer 130 may select the operation result of arithmetic logic sub-unit A as its output based on its control signal being 0.

[0025] However, the processor 100 of the related art has several problems. First, the processor 100 can only perform one arithmetic logic operation within a cycle. Therefore, the processor 100 has limited computing performance and low operational efficiency. Second, when the processor 100 is running, each arithmetic logic subunit AH performs an operation, but only one of the results is selected and output. In other words, the processor 100 performs a large number of ineffective operations, resulting in high power consumption. It is desirable to implement a high-efficiency, low-power processor to improve computing efficiency and reduce production and operating costs.

[0026] The present disclosure aims to address at least part of the above-mentioned problems.

[0027] 2 shows a schematic diagram of a processor 200 according to an embodiment of the present disclosure. The processor 200 can be used to implement various arithmetic and logical calculations, such as addition, subtraction, multiplication, division, shift, truncation, reciprocal, and modulo.

[0028] The processor 200 includes N registers 211 , 212 , 213 , 214 , an arithmetic logic unit 220 including a plurality of arithmetic logic subunits 220A- 220H, and N multiplexers 231 , 232 , 233 , 234 .

[0029] Wherein, N is an integer greater than or equal to 2 and less than or equal to the number of arithmetic logic subunits. In the embodiment shown in FIG2 , N is 4 and the number of arithmetic logic subunits is 8. In other embodiments, both N and N may be appropriately selected to different values ​​based on actual application requirements. For example, N may be 2.

[0030] The registers 211, 212, 213, and 214 are used to store data, and their outputs are coupled to the arithmetic logic unit 220. Specifically, the output of each register 211, 212, 213, and 214 is coupled to the input of each arithmetic logic sub-unit 220A-220H of the arithmetic logic unit 220. For the sake of clarity, FIG2 does not depict all connections between the output of each register 211, 212, 213, and 214 and the input of each arithmetic logic sub-unit 220A-220H.

[0031] The arithmetic logic unit 220 may include multiple arithmetic logic subunits 220A-220H, each of which is configured to perform an operation. In one embodiment, each arithmetic logic subunit is configured to perform one of the following operations: addition, subtraction, multiplication, division, shift, truncation, reciprocal, and modulo. As described above, the inputs of each arithmetic logic subunit 220A-220H are coupled to the outputs of the N registers 211, 212, 213, and 214. Each arithmetic logic subunit 220A-220H includes a selection module 221A-221H and an operation module AH.

[0032] Each selection module 221A-221H is coupled to the outputs of the N registers 211, 212, 213, and 214 and is configured to select the output of a corresponding register and pass it to the calculation module based on the control signal of the arithmetic logic subunit, or to select none of the outputs of the registers and pass a predetermined value indicating that none of the outputs of the registers are selected to the calculation module. The predetermined value can be any suitable pre-specified value indicating that none of the outputs of the registers are selected. In a preferred embodiment, the predetermined value can be zero, thereby further reducing the power consumption of the processor.

[0033] In a preferred embodiment, the control signal of each ALU 220A-220H can include N values, corresponding to N registers. For example, the selection module 221A can select the output of register 211 and pass it to the operation module A based on the control signal 280A of the ALU 220A being "1000." Alternatively, the selection module 221A can select no register output and pass a predetermined value to the operation module A based on the control signal 280A of the ALU 220A being "0000." For clarity, the control signals of the other ALUs 220B-220H are not shown in FIG. However, those skilled in the art will appreciate that the control signals of the other ALUs 220B-220H can operate similarly to the control signal 280A of the ALU 220A.

[0034] The operation module AH is configured to perform operations on the register outputs passed by the selection modules 221A-221H. In particular, in a preferred embodiment, the predetermined value may be zero, and when the value passed by the selection modules 221A-221H is zero, the operation module AH does not need to perform any operations. This significantly reduces the overall power consumption of the processor 200. In one embodiment, the operation modules AH can each be configured to perform one of the following operations: addition, subtraction, multiplication, division, shift, truncation, reciprocal, and modulo.

[0035] The inputs of each multiplexer 231, 232, 233, and 234 are coupled to the outputs of each arithmetic logic sub-unit 220A-220H of the arithmetic logic unit 220, and each multiplexer 231, 232, 233, and 234 selects the output of a corresponding arithmetic logic sub-unit as the operation result based on the control signals 291, 292, 293, and 294 of the multiplexer. For clarity, FIG2 does not depict all connections between the outputs of each arithmetic logic sub-unit 220A-220H and the inputs of each multiplexer 231, 232, 233, and 234. Each multiplexer 231, 232, 233, and 234 can be implemented by logic gate devices.

[0036] The output of each multiplexer 231, 232, 233, 234 can be coupled to the input of the corresponding register 211, 212, 213, 214, so that the operation result is transferred to the corresponding register 211, 212, 213, 214. In addition, the output of each multiplexer 231, 232, 233, 234 can be coupled to the output of the processor 200, so that the operation result is output at the end of the operation cycle.

[0037] At the beginning of an operation cycle, the N registers 211, 212, 213, and 214 can each receive input from the outside as input to the processor 100. During the operation cycle, the N multiplexers 231, 232, 233, and 234 can each feed back the operation results of the current cycle to the corresponding registers 211, 212, 213, and 214, thereby cyclically performing further operations. At the end of the operation cycle, the N multiplexers 231, 232, 233, and 234 can each output the operation results.

[0038] In a preferred embodiment, as shown in FIG. 2 , the outputs of the 1st to Nth multiplexers 231 , 232 , 233 , and 234 may be coupled to the inputs of the 1st to Nth registers 211 , 212 , 213 , and 214 , respectively, and also coupled to the output of the processor 200 .

[0039] In a further preferred embodiment, the processor 200 shown in FIG2 can process N different operations in parallel. That is, in each cycle, the processor 200 can process N mutually different operations. Thus, the control signals 291, 292, 293, 294 of the first to N multiplexers 231, 232, 233, 234 can respectively select the outputs of the arithmetic logic subunits corresponding to the first to N registers 211, 212, 213, 214, and feed them back to the first to N registers 211, 212, 213, 214, respectively. In other words, the processor 200 shown in FIG2 can execute N different operations in parallel on the data stored in the N registers 211, 212, 213, 214.

[0040] For example, in the current cycle, four operations, A, B, C, and D, can be performed on the values ​​of registers 1 through 4, respectively. Then, the selection module 221A of the arithmetic logic subunit 220A can select the output of register 211, which is then operated by operation module A. The control signal 291 of the multiplexer 231 can select the output of the arithmetic logic subunit 220A corresponding to register 211 and feed that output back to register 211. For example, the control signal 291 can be 0 to select the output of the arithmetic logic subunit 220A. Similarly, the selection module 221B of the arithmetic logic subunit 220B can select the output of register 212, which is then operated by operation module B. The control signal 292 of the multiplexer 232 can select the output of the arithmetic logic subunit 220B corresponding to register 212 and feed that output back to register 212. For example, the control signal 292 can be 1 to select the output of the arithmetic logic subunit 220B. The selection module 221C of the arithmetic logic subunit 220C can select the output of the register 213 for operation by the operation module C, while the control signal 293 of the multiplexer 233 selects the output of the arithmetic logic subunit 220C corresponding to the register 213 and feeds this output back to the register 213. For example, the control signal 293 can be 2 to select the output of the arithmetic logic subunit 220C. The selection module 221D of the arithmetic logic subunit 220D can select the output of the register 214 for operation by the operation module D, while the control signal 294 of the multiplexer 234 can select the output of the arithmetic logic subunit 220D corresponding to the register 214 and feed this output back to the register 214. For example, the control signal 294 can be 3 to select the output of the arithmetic logic subunit 220D.

[0041] Therefore, when the processor 200 is running, the processor 200 can process N different operations in parallel, which makes the computing efficiency of the processor 200 N times that of the processor 100 in the related art, significantly improving the computing performance of the processor.

[0042] Furthermore, in a preferred embodiment, the predetermined value indicating that no register is selected can be zero. Thus, when the processor 200 is running, under the control of the selection modules 221A-221H in the arithmetic logic subunits 220A-220H, only the operation modules in the arithmetic logic subunits that are intended to perform operations receive the corresponding values ​​and perform the operations. The operation modules in the other arithmetic logic subunits receive the value zero and therefore do not perform the operations. This eliminates a large number of ineffective operations in the processor 200, significantly reducing its power consumption.

[0043] Note that when the processor 200 is running, it can process N unrelated operations in parallel, or it can perform a series of identical operations on N sets of data in parallel, as long as the N operations performed simultaneously in the same cycle are different from each other. If an operation conflict occurs (i.e., at least some of the N operations performed simultaneously in the same cycle are identical), the control signals of the corresponding arithmetic logic subunits can be adjusted so that at least one set of operations waits for one or more cycles, thereby staggering them.

[0044] For example, if it is desired to sequentially execute operations A, B, C, D, etc. on the data in N registers 211, 212, 213, and 214 (i.e., to execute a series of identical operations in parallel on N sets of data), the control signals of the various arithmetic logic subunits can be adjusted to perform the following operations: in the first cycle, the arithmetic logic subunit 220A selects the output of the register 211 and performs operation A on it, while the control signal 291 of the multiplexer 231 selects the output of the arithmetic logic subunit 220A corresponding to the register 211 and feeds the output back to the register 211; in the second cycle, the arithmetic logic subunit 220A selects the output of the register 211 and performs operation A on it; The arithmetic logic subunit 220A selects the output of register 212 and performs operation A on it, and the arithmetic logic subunit 220B selects the output of register 211 and performs operation B on it. The control signals 291 and 292 of the multiplexers 231 and 232 respectively select the outputs of the arithmetic logic subunits 220B and 220A corresponding to the registers 211 and 212 and feed the outputs back to the registers 211 and 212 respectively. In the third cycle, the arithmetic logic subunit 220A selects the output of register 213 and performs operation A on it, and the arithmetic logic subunit 220B selects the output of register 212. And perform B operation on it, and make the arithmetic logic subunit 220C select the output of register 211 and perform C operation on it, while the control signals 291, 292, 293 of the multiplexers 231, 232, 233 respectively select the outputs of the arithmetic logic subunits 220C, 220B, 220A corresponding to the registers 211, 212, 213 and feed the outputs back to the registers 211, 212, 213 respectively; in the fourth cycle, make the arithmetic logic subunit 220A select the output of register 214 and perform A operation on it, make the arithmetic logic subunit 220B select the output of register 213 The output of register 211 is selected and operation B is performed on it. The arithmetic logic subunit 220C selects the output of register 212 and performs operation C on it. The arithmetic logic subunit 220D selects the output of register 211 and performs operation D on it. The control signals 291, 292, 293, and 294 of multiplexers 231, 232, 233, and 234 respectively select the outputs of arithmetic logic subunits 220D, 220C, 220B, and 220A corresponding to registers 211, 212, 213, and 214, and feed these outputs back to registers 211, 212, 213, and 214, respectively. And so on. In this way, the operation timing can be flexibly adjusted, and the problem of operation conflict can be solved at the cost of a certain delay.

[0045] FIG3 is a schematic diagram showing a connection method of an arithmetic logic subunit 220A in a processor 200 according to an embodiment of the present disclosure.

[0046] The arithmetic logic subunit 220A includes a selection module 221A and an operation module A. The selection module 221A is coupled to the outputs of the N registers 211, 212, 213, and 214, and is configured to select the output of a corresponding register and pass it to the operation module A based on a control signal 280A from the arithmetic logic subunit 220A, or not select the output of any register and pass a predetermined value indicating that the output of any register is not selected to the operation module A.

[0047] In a preferred embodiment, the control signal 280A may include N values, each corresponding to N registers. In a preferred embodiment, as shown in FIG3 , the selection module 221A may be composed of N AND gates and an OR gate having N input terminals. The first terminal of each AND gate may be coupled to the output of a corresponding register 211, 212, 213, or 214, and the second terminal may be coupled to one of the N values ​​of the control signal 280A of the arithmetic logic subunit 220A corresponding to the register 211, 212, 213, or 214 coupled to the first terminal. Each input terminal of the OR gate may be coupled to the output terminals of the N AND gates, and the output terminal of the OR gate may be coupled to the operation module A of the arithmetic logic subunit 220A.

[0048] For example, when it is desired to perform Operation A on the value of register 211, control signal 280A can be "1000," causing the values ​​"1," "0," "0," and "0" to be sequentially input to one input terminal of four AND gates. The outputs of the four registers 211, 212, 213, and 214 are then coupled to the other input terminals of the four AND gates. Thus, the output of the first AND gate is the value of register 211, while the outputs of the second through fourth AND gates are predetermined values ​​indicating that none of the registers are selected. The value of register 211 is then output to operation module A via an OR gate. Operation module A receives the value of register 211 and performs Operation A on it.

[0049] In another example, when operation A is not desired, control signal 280A can be "0000," causing the values ​​"0," "0," "0," and "0" to be sequentially input to one input terminal of the four AND gates, while the outputs of the four registers 211, 212, 213, and 214 are sequentially coupled to the other input terminals of the four AND gates. In this way, the outputs of the four AND gates and the output of the OR gate are all predetermined values ​​indicating that no register output is selected. In a preferred embodiment, this predetermined value can be zero. Consequently, operation module A receives a zero value and does not perform the operation. This eliminates invalid operations, significantly reducing the overall power consumption of processor 200.

[0050] In a preferred embodiment, the selection module 221A may be composed of N NAND gates and a NOR gate having N input terminals. The first terminal of each NAND gate may be coupled to the output of a corresponding register 211, 212, 213, or 214, and the second terminal may be coupled to one of the N values ​​of the control signal 280A of the arithmetic logic subunit 220A corresponding to the register 211, 212, 213, or 214 coupled to the first terminal. Each input terminal of the NOR gate may be coupled to the output terminal of the N NAND gates, and the output terminal of the NOR gate may be coupled to the operation module A of the arithmetic logic subunit 220A. In this embodiment, the NAND and NOR gates operate similarly to the AND and OR gates in the previous embodiments and will not be described in detail here.

[0051] Figure 4 shows a schematic diagram of a processor 400 according to another embodiment of the present disclosure. In neural network-related computations, it is often necessary to perform a series of identical operations on large amounts of data. The processor 400 in the embodiment shown in Figure 4 can implement a pipelined operation mode, making it particularly suitable for such application scenarios.

[0052] Processor 400 includes N registers 411, 412, 413, and 414, an arithmetic logic unit (ALU) 420 including a plurality of ALUs 420A-420H, and N multiplexers 431, 432, 433, and 434. Each ALU 420A-420H includes a selection module 421A-421H and an operation module AH. The output of each register 411, 412, 413, and 414 is coupled to the input of each ALU 420A-420H, while the input of each multiplexer 431, 432, 433, and 434 is coupled to the output of each ALU 420A-420H. For clarity, FIG. 4 does not depict all connections between the registers, ALUs, and multiplexers described above.

[0053] The structure of the processor 400 is substantially similar to that of the processor 200 shown in FIG. 2 , and thus details thereof are omitted for brevity.

[0054] In processor 400, each selection module 421A-421H is coupled to the outputs of N registers 411, 412, 413, and 414, and is configured to select the output of a corresponding register and pass it to the operation module based on a control signal of the arithmetic logic subunit, or to select no output of any register and pass a predetermined value indicating no output of any register to the operation module. For clarity, FIG4 illustrates only the control signal 480A of the arithmetic logic subunit 220A.

[0055] In the embodiment shown in Figure 4, the outputs of the 1st to N-1st multiplexers 431, 432, and 433 can be coupled to the inputs of the 2nd to Nth registers 412, 413, and 414, respectively, and the output of the Nth multiplexer 434 can be coupled to the output of the processor 400 for outputting the operation result at the end of the operation cycle.

[0056] In each cycle, the first register 411 can receive input from the outside as an input to the processor 400, and the value is passed to the operation module of the corresponding arithmetic logic subunit to perform the corresponding operation. The multiplexer 431 selects the operation result of the corresponding operation and outputs it to the register 412 to wait for the next operation. At the same time, the values ​​stored in the 2nd to N-1st registers 412 and 413 (i.e., the previous operation results) are passed to the operation module of the corresponding arithmetic logic subunit to perform the corresponding operation, and the multiplexers 432 and 433 respectively select the operation results of the corresponding operation and output them to the registers 413 and 414 respectively to wait for the next operation. At the same time, the value stored in the Nth register 414 is passed to the operation module of the corresponding arithmetic logic subunit to perform the corresponding operation, and the multiplexer 434 selects the operation result of the corresponding operation and outputs it.

[0057] In this way, the processor 400 can continuously perform a series of identical operations on different data in a pipeline operation manner.

[0058] Note that in this embodiment, during a series of operations, the registers corresponding to each arithmetic logic subunit 420A-420H in processor 400 remain the same. For example, if operations A, B, C, and D are to be performed sequentially, then arithmetic logic subunits 420A, 420B, 420C, and 420D will always receive data from registers 411, 412, 413, and 414, respectively. Therefore, during the operation, the control signals of each arithmetic logic subunit do not need to change, further reducing the power consumption caused by switching the control signals. As a result, the power consumption of processor 400 is further reduced compared to processor 200 shown in FIG. 2 .

[0059] In a further preferred embodiment, a pipeline operation mode similar to that of the processor 400 shown in FIG. 4 may be implemented in the connection mode of the processor 200 shown in FIG. 2 .

[0060] As shown in FIG2 , in the processor 200, the outputs of the 1st to Nth multiplexers 231, 232, 233, and 234 can be coupled to the inputs of the 1st to Nth registers 211, 212, 213, and 214, respectively, and also to the output of the processor 200. In this preferred embodiment, the control signals of the 2nd to Nth multiplexers 232, 233, and 234 can respectively select the outputs of the arithmetic logic subunits corresponding to the 1st to N-1st registers 211, 212, and 213, and the control signal of the 1st multiplexer 231 can select the output of the arithmetic logic subunit corresponding to the Nth register 214.

[0061] In this way, the control signals of each arithmetic logic subunit can be adjusted to achieve a pipeline operation mode. For example, if it is desired to execute operations A, B, C, and D sequentially in a pipeline manner, then in each cycle: the first register 211 can receive input from the outside as an input to the processor 200, and the value is passed to the operation module of the corresponding arithmetic logic subunit (i.e., arithmetic logic subunit 420A) to perform the corresponding operation; the second multiplexer 232 can select the output of the arithmetic logic subunit (i.e., arithmetic logic subunit 420A) corresponding to the first register 211 and output it to the second register 212 to wait for the next operation. At the same time, the values ​​stored in the second to N-1 registers 212 and 213 are passed to the operation modules of the corresponding ALUs (i.e., ALUs 420B and 420C) for corresponding operations. The third to N multiplexers 433 and 434 respectively select the outputs of the ALUs corresponding to the second to N-1 registers 212 and 213 (i.e., ALUs 420B and 420C) and output them to the third to N registers 213 and 214, respectively, to await the next operation. At the same time, the value stored in the Nth register 214 is passed to the operation module of the corresponding ALU (i.e., ALU 420D) for corresponding operations. The first multiplexer 231 selects the output of the ALU corresponding to the Nth register 214 (i.e., ALU 420D) and outputs it as the operation result of the processor 400.

[0062] Therefore, based on the control signals of the N multiplexers described above, the processor 200 can continuously perform a series of identical operations on different data in a pipeline form.

[0063] Furthermore, as previously mentioned, the processor 200 can also operate in parallel. In a preferred embodiment, the connection mode of the processor 200 can be implemented in hardware, and the operating mode of the processor 200 (i.e., parallel mode or pipeline mode) can be changed by changing the control signals of the N multiplexers. This allows for more flexible selection of the processor's operating mode without requiring additional hardware costs.

[0064] In one implementation, a computing chip may include one or more of the aforementioned processors. In one implementation, a computing device may include one or more computing chips. Multiple computing chips may execute computing tasks in parallel.

[0065] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0066] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0067] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are intended to be illustrative only and not to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A processor, comprising: N registers; an arithmetic logic unit, comprising a plurality of arithmetic logic subunits, each arithmetic logic subunit being used to perform an operation, and an input of each arithmetic logic subunit being coupled to outputs of the N registers; as well as N multiplexers, each multiplexer having an input coupled to an output of each arithmetic logic sub-unit of the arithmetic logic unit, and each multiplexer selecting an output of a corresponding arithmetic logic sub-unit according to a control signal of the multiplexer, Each arithmetic logic subunit includes: a selection module, coupled to the outputs of the N registers, for selecting the output of a corresponding register according to the control signal of the arithmetic logic subunit and transferring it to the operation module, or not selecting the output of any register and transferring a predetermined value indicating that the output of any register is not selected to the operation module; and The operation module is used to perform operations on the output of the register passed by the selection module. Wherein, N is an integer greater than or equal to 2 and less than or equal to the number of arithmetic logic subunits.

2. The processor of claim 1, wherein outputs of the first to N multiplexers are coupled to inputs of the first to N registers, respectively, and are also coupled to an output of the processor. 3 . The processor of claim 2 , wherein control signals of the first to N multiplexers select outputs of the arithmetic logic subunits corresponding to the first to N registers, respectively.

4. The processor of claim 1, wherein outputs of the 1st to N-1st multiplexers are coupled to inputs of the 2nd to Nth registers, respectively, and an output of the Nth multiplexer is coupled to an output of the processor. 5 . The processor of claim 4 , wherein control signals of the first to N multiplexers select outputs of the arithmetic logic subunits corresponding to the first to N registers, respectively.

6. The processor of claim 2, wherein control signals of the 2nd to Nth multiplexers respectively select outputs of the arithmetic logic subunits corresponding to the 1st to N-1st registers, and the control signal of the 1st multiplexer selects the output of the arithmetic logic subunit corresponding to the Nth register.

7. The processor of any one of claims 1 to 6, wherein the predetermined value indicating that the output of any register is not selected is zero.

8. The processor according to any one of claims 1 to 6, wherein the control signal of each arithmetic logic subunit comprises N values, respectively corresponding to N registers.

9. The processor of claim 8, wherein the selection module of each ALU comprises: N AND gates, each AND gate having a first terminal coupled to an output of a corresponding register, and a second terminal coupled to a value of the control signal of the arithmetic logic subunit corresponding to the register coupled to the first terminal; as well as An OR gate includes N input terminals, each input terminal of the OR gate is respectively coupled to the output terminals of the N AND gates, and the output terminal of the OR gate is coupled to the operation module of the arithmetic logic subunit.

10. The processor of claim 8, wherein the selection module of each ALU comprises: N NAND gates, each NAND gate having a first terminal coupled to an output of a corresponding register, and a second terminal coupled to a value of the control signal of the arithmetic logic subunit corresponding to the register coupled to the first terminal; as well as A NOR gate includes N input terminals, each input terminal of the NOR gate is coupled to the output terminals of the NAND gates respectively, and the output terminal of the NOR gate is coupled to the operation module of the arithmetic logic subunit.

11. The processor of any one of claims 1-6, wherein each multiplexer is implemented by a logic gate device.

12. The processor of any one of claims 1-6, wherein N is 4.

13. The processor according to any one of claims 1 to 6, wherein each of the plurality of ALUs is configured to perform one of the following operations: addition, subtraction, multiplication, division, shift, truncation, reciprocal, and modulo.

14. A computing chip comprising one or more processors according to any one of claims 1-13.

15. A computing device comprising one or more computing chips according to claim 14.

Images