Sequence processing method, apparatus and system

Abstract

A sequence processing method, apparatus and system, relating to the technical field of communications. The method comprises: on the basis of an initial bit sequence, obtaining a plurality of intermediate bit sequences, wherein the initial bit sequence comprises a plurality of bit sub-sequences, and at least one intermediate bit sequence among the plurality of intermediate bit sequences is related to at least two bit sub-sequences among the plurality of bit sub-sequences; then, respectively performing distributed matching processing on the plurality of intermediate bit sequences to obtain a plurality of target bit sequences in one-to-one correspondence to the plurality of intermediate bit sequences; and combining the obtained target bit sequences. The present application solves the problem that the method for a sending node to process bit sequences is relatively single, and the present application is used for processing bit sequences.

Description

Sequence processing method, device and system

[0001] This application claims priority to a Chinese patent application filed on August 28, 2023, with application number 202311097721.4 and application name “SEQUENCE PROCESSING METHOD, DEVICE AND SYSTEM”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a sequence processing method, device and system. Background Art

[0003] In a communication system, a sending node and a receiving node can communicate with each other.

[0004] In related technologies, a sending node processes a bit sequence to be transmitted, modulates symbols based on the processed sequence, processes the modulated symbols again, and transmits them to a receiving node via a channel. The receiving node then performs the inverse of the processing performed by the sending node on the received symbols to recover the bit sequence.

[0005] However, in the related art, the sending node processes the bit sequence in a relatively simple manner.

[0006] Summary of the Invention

[0007] This application provides a sequence processing method, device, and system to solve the problem in related technologies that the sending node only processes bit sequences in a single way. The technical solution is as follows:

[0008] In a first aspect, the present application provides a sequence processing method, the method comprising: obtaining multiple intermediate bit sequences based on an initial bit sequence; the initial bit sequence comprises multiple bit subsequences, and at least one of the multiple intermediate bit sequences is correlated with at least two bit subsequences of the multiple bit subsequences.

[0009] Optionally, the sequence processing method further includes: performing distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences corresponding one-to-one to the multiple intermediate bit sequences, and then merging the obtained target bit sequences.

[0010] In summary, the sequence processing method provided in the embodiments of the present application first obtains multiple intermediate bit sequences based on an initial bit sequence. These multiple intermediate bit sequences are then individually distributed and matched to obtain multiple target bit sequences that correspond one-to-one with the multiple intermediate bit sequences. Finally, the resulting target bit sequences are combined. Furthermore, at least one of the multiple intermediate bit sequences is correlated with at least two bit subsequences of the initial bit sequence. This sequence processing method differs from sequence processing methods in related arts and, therefore, enriches the range of sequence processing options.

[0011] In addition, since at least one of the multiple intermediate bit sequences is related to at least two bit subsequences of the initial bit sequence, the value of the at least one intermediate bit sequence depends on the values ​​of the at least two bit subsequences. When any bit subsequence in the at least two bit subsequences changes, the value of the at least one intermediate bit sequence changes. It can be seen that the present application will combine the values ​​of the at least two bit subsequences for global consideration to determine the value of the at least one intermediate bit sequence, so that the value of the at least one intermediate bit sequence is more conducive to improving the transmission effect of the signal.

[0012] It is understood that the at least two intermediate bit sequences may be the multiple intermediate bit sequences or some of the multiple intermediate bit sequences; and the at least two bit subsequences may be the multiple bit subsequences or some of the multiple bit subsequences, which is not limited in this embodiment of the present application. When the at least two intermediate bit sequences include multiple intermediate bit sequences, and the at least two bit subsequences include multiple bit subsequences, each intermediate bit sequence in the multiple intermediate bit sequences is correlated with all bit subsequences in the multiple bit subsequences.

[0013] Optionally, the bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be consecutive bits containing the most significant bit in the intermediate bit sequence. The at least two bit subsequences include: a first bit subsequence and a second bit subsequence, the value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the at least one intermediate bit sequence includes: a first intermediate bit sequence and a second intermediate bit sequence, the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value.

[0014] In this application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understood that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the following three conditions is met: the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values, or none of these three conditions are met.

[0015] Assume that the value of the sequence obtained by padded with 0 bits after the most significant bit (one bit higher than the most significant bit) of the first bit subsequence is the fifth value, and the value of the sequence obtained by padded with 0 bits after the most significant bit of the second bit subsequence is the sixth value. Then, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; if the third value is greater than the first and second values, and the fourth value is less than the first and second values, the absolute value of the difference between the fifth and sixth values ​​is less than the absolute value of the difference between the third and fourth values; and if the third value is greater than the fifth and sixth values, and the fourth value is less than the fifth and sixth values.

[0016] Take the example that 0 bits will be mapped to higher amplitude bits and 1 bits will be mapped to lower amplitude bits. Assume that the above distribution matching process is implemented by a lookup table, and the table searched in the lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, and the number of 0 bits in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. Then, the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the first bit subsequence is the first number, and the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the second bit subsequence is the second number; the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the first intermediate bit sequence is the third number, and the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the fourth intermediate bit sequence is the fourth number; the sum of the third number and the fourth number is less than the sum of the first number and the second number. In this way, after merging the two target bit sequences, a bit sequence with fewer 0 bits can be obtained, which is conducive to improving the transmission effect of the signal.

[0017] Optionally, the method satisfies at least one of the following conditions: the first type of bit segment includes one bit or two bits, and the second type of bit segment includes at least three bits; the multiple bit subsequences are two bit subsequences, and the multiple intermediate bit sequences are two intermediate bit sequences. Of course, the method may not satisfy this at least one condition. For example, the number of bit subsequences may be greater than 2, such as 2, 3, 4, 5, etc.; the number of intermediate bit sequences may be greater than 2, such as 3, 4, 5, etc.

[0018] Optionally, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 10, and the number of bits in the intermediate bit sequence is 11.

[0019] Furthermore, the bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; there is a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups, wherein the first bit sequence includes: the first type of bit segments in the multiple bit subsequences, and the bit sequence group includes the second type of bit segments in the multiple intermediate bit sequences.

[0020] When obtaining multiple intermediate bit sequences based on an initial bit sequence, the multiple intermediate bit sequences can be obtained based on the initial bit sequence and a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups. The target first bit sequence in the multiple first bit sequences includes: a first-category bit segment in the multiple bit subsequences; the bit sequence group includes multiple second-category bit segments, the multiple second-category bit segments in the target bit sequence group correspond one-to-one with the multiple intermediate bit sequences, and the target bit sequence group is the bit sequence group in the multiple bit sequence groups corresponding to the target first bit sequence; the second-category bit segment of the intermediate bit sequence includes the second-category bit segment corresponding to the intermediate bit sequence, and the second-category bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. Optionally, the multiple intermediate bit sequences can be obtained without the initial bit sequence and the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups. For example, an algorithm can be used to operate on the initial bit sequence to obtain the multiple intermediate bit sequences.

[0021] Optionally, in the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, the value of at least one second-category bit segment in at least one bit sequence group is greater than the value of each first-category bit segment in the multiple first bit sequences.

[0022] For example, the bit sequence group includes two second-category bit segments, and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes:

[0023] The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0024] The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0025] The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0026] The correspondence between the first bit sequence (0, 0, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0027] The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0028] The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1);

[0029] The correspondence between the first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0030] The correspondence between the first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1);

[0031] The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0032] The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0033] The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0034] The correspondence between the first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0035] The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0036] The correspondence between the first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0037] The correspondence between the first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0038] The correspondence between the first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0039] The bits in the bit sequence are arranged from left to right in order from low to high bit position.

[0040] Optionally, the bit subsequences further include a third type of bit segment (also called a to-be-reallocated bit segment) in addition to the first type of bit segment; and the intermediate bit sequences further include a fourth type of bit segment (also called a reallocated bit segment) in addition to the second type of bit segment. The fourth type of bit segment in the plurality of intermediate bit sequences includes bits in the third type of bit segment in the plurality of bit subsequences.

[0041] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0042] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include the third-category bit segments. In other words, a third-category bit segment may serve as a whole as all or part of a fourth-category bit segment in an intermediate bit sequence, or the bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0043] Optionally, the sum of the number of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence. The sum of the number of bits in the multiple target bit sequences may also be greater than the number of bits in the initial bit sequence.

[0044] Optionally, the present application may further divide the initial bit sequence into multiple bit subsequences from the bit sequence to be processed. The bit sequence to be processed may belong to a bit stream received by an apparatus for performing the method, and the apparatus may select, from the received bit stream, a number of bits in the bit sequence to be processed as the bits to be processed, based on the number of bits in the bit sequence to be processed.

[0045] Optionally, there may be multiple initial bit sequences. When multiple initial bit sequences are obtained by dividing the bit sequence to be processed, the bit sequence to be processed may be divided into multiple initial bit sequences, or the bit sequence to be processed may be divided into multiple bit subsequences within the multiple initial bit sequences. Furthermore, the multiple initial bit sequences may be continuous or discontinuous within the bit sequence to be processed. In this application, the example of the multiple initial bit sequences being continuous within the bit sequence to be processed is used.

[0046] Optionally, in the present application, the number of bits in the to-be-processed bit sequence is 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained after merging is 64 or 128. It is understandable that the number of bits in the to-be-processed bit sequence may not be 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained after merging may not be 64 or 128, and this application does not impose any limitation on this.

[0047] For example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64.

[0048] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0049] For example, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10;

[0050] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0051] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; and in yet another portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0052] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72; the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is respectively: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0053] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 116, and the numbers of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0054] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0055] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0056] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0057] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 8 bits; in another portion of bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0058] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 8 bits.

[0059] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; wherein, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

[0060] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits of the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, and 11 respectively; 4 intermediate bit sequences with a number of 10 bits are obtained based on 4 bit subsequences with a number of 9 bits, and 4 intermediate bit sequences with a number of 11 bits are obtained based on 4 bit subsequences with a number of 10 bits.

[0061] Alternatively, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences is 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10.

[0062] Optionally, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r ≥ 1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the 6 initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s ≥ 1;

[0063] Optionally, the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively;

[0064] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0065] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0066] Alternatively, the number of bits in the to-be-processed bit sequence is 72; the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0067] Alternatively, the number of bits in the to-be-processed bit sequence is 116, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0068] Alternatively, the number of bits in the to-be-processed bit sequence is 106, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0069] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively;

[0070] Alternatively, the number of bits in the to-be-processed bit sequence is 72, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6, and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0071] Alternatively, the number of bits in the to-be-processed bit sequence is 96, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0072] Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequence obtained according to the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, and 11, respectively.

[0073] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 6 initial bit sequences, the bits in the initial bit sequences are continuous in the bit sequence to be processed, and the sth initial bit sequence and the s+1th initial bit sequence in the 6 initial bit sequences are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth initial bit sequences in the 6 initial bit sequences are 18, 18, 20, 20, 20, and 20, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the 6 initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0074] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, r≥1; in the 12 bit subsequences, every four consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 In the three initial bit sequences composed of bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the 1st to 3rd initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0075] As another example, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 6 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 6 bit subsequences, every two continuous bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 6 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth bit subsequences in the 6 bit subsequences are 9, 9, 10, 10, 10 and 10, respectively; the number of bits in the intermediate bit sequence obtained according to the first to third initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0076] Optionally, the number of bits in the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, distribution matching processing can be performed on any intermediate bit sequence in the multiple intermediate bit sequences in various ways.

[0077] For example, when the first method is used to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, the first result bit sequence corresponding to the first index bit sequence among the multiple index bit sequences can be used as the target bit sequence corresponding to the intermediate bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence.

[0078] For example, when the second method is used to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, when the t-th bit of the intermediate bit sequence is a target class bit, according to the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, the first result bit sequence corresponding to the first index bit sequence in the multiple index bit sequences is used as the target bit sequence corresponding to the intermediate bit sequence; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence; the target class bit is 0 bit or 1 bit; when the t-th bit is not the target class bit, the valid bit segment is inverted (the inversion processing is used to update the 0 bit to 1 bit, and update the 1 bit to 0 bit); then, according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, a second result bit sequence corresponding to the second index bit sequence in the multiple index bit sequences is obtained (the second index bit sequence includes: the valid bit segment after the inversion processing), and the second result bit sequence is inverted to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0079] In the second distributed matching process, in the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, fewer index bit sequences can be used. Therefore, the index bit sequences and their corresponding result bit sequences that are not used in the correspondence can be deleted from the correspondence. In this way, the number of index bit sequences and the number of result bit sequences in the correspondence can be smaller.

[0080] For example, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be less than the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method. Furthermore, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be greater than or equal to half the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method.

[0081] The number of index bit sequences X ≥ 2 (u-t-1) .

[0082] In a second aspect, the present application provides a sequence processing method, the method comprising: obtaining an initial bit sequence based on multiple intermediate bit sequences; the initial bit sequence comprises multiple bit subsequences, and each intermediate bit sequence in at least two intermediate bit sequences in the multiple intermediate bit sequences is correlated with at least two bit subsequences in the multiple bit subsequences.

[0083] Optionally, the method further includes: splitting a plurality of target bit sequences from a bit sequence; and performing an inverse process of the distribution matching process on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences corresponding one to one to the plurality of target bit sequences.

[0084] The sequence processing method provided in the second aspect is the inverse of the sequence processing method provided in the first aspect. The sequence processing method provided in the second aspect is used to process the bit sequence obtained by the sequence processing method provided in the first aspect to restore the bit sequence before processing by the sequence processing method provided in the first aspect.

[0085] It is understood that the at least two intermediate bit sequences may be the multiple intermediate bit sequences or some of the multiple intermediate bit sequences; and the at least two bit subsequences may be the multiple bit subsequences or some of the multiple bit subsequences, which is not limited in this embodiment of the present application. When the at least two intermediate bit sequences include multiple intermediate bit sequences, and the at least two bit subsequences include multiple bit subsequences, each intermediate bit sequence in the multiple intermediate bit sequences is correlated with all bit subsequences in the multiple bit subsequences.

[0086] Optionally, the bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be consecutive bits containing the most significant bit in the intermediate bit sequence. The at least two bit subsequences include: a first bit subsequence and a second bit subsequence, the value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the at least one intermediate bit sequence includes: a first intermediate bit sequence and a second intermediate bit sequence, the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value.

[0087] In this application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understood that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the following three conditions is met: the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values, or none of these three conditions are met.

[0088] Optionally, the method satisfies at least one of the following conditions: the first type of bit segment includes one bit or two bits, and the second type of bit segment includes at least three bits; the multiple bit subsequences are two bit subsequences, and the multiple intermediate bit sequences are two intermediate bit sequences. Of course, the method may not satisfy this at least one condition. For example, the number of bit subsequences may be greater than 2, such as 2, 3, 4, 5, etc.; the number of intermediate bit sequences may be greater than 2, such as 3, 4, 5, etc.

[0089] Optionally, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 10, and the number of bits in the intermediate bit sequence is 11.

[0090] Furthermore, when obtaining an initial bit sequence based on multiple intermediate bit sequences, the multiple intermediate bit sequences can be obtained based on the initial bit sequence and a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups. The target first bit sequence in the multiple first bit sequences includes: a first-category bit segment in the multiple bit subsequences; the bit sequence group includes multiple second-category bit segments, the multiple second-category bit segments in the target bit sequence group correspond one-to-one with the multiple intermediate bit sequences, and the target bit sequence group is the bit sequence group in the multiple bit sequence groups corresponding to the target first bit sequence; the second-category bit segment of the intermediate bit sequence includes the second-category bit segment corresponding to the intermediate bit sequence, and the second-category bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. Optionally, the multiple intermediate bit sequences can be obtained without the initial bit sequence and a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups. For example, an algorithm can be used to operate on multiple intermediate bit sequences to obtain the initial bit sequence.

[0091] Optionally, in the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, the value of at least one second-category bit segment in at least one bit sequence group is greater than the value of each first-category bit segment in the multiple first bit sequences.

[0092] For example, the bit sequence group includes two second-category bit segments, and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes:

[0093] The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0094] The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0095] The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0096] The correspondence between the first bit sequence (0, 0, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0097] The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0098] The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1);

[0099] The correspondence between the first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0100] The correspondence between the first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1);

[0101] The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0102] The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0103] The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0104] The correspondence between the first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0105] The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0106] The correspondence between the first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0107] The correspondence between the first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0108] The correspondence between the first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0109] The bits in the bit sequence are arranged from left to right in order from low to high bit position.

[0110] Optionally, the bit subsequences further include a third type of bit segment (also called a to-be-reallocated bit segment) in addition to the first type of bit segment; and the intermediate bit sequences further include a fourth type of bit segment (also called a reallocated bit segment) in addition to the second type of bit segment. The fourth type of bit segment in the plurality of intermediate bit sequences includes bits in the third type of bit segment in the plurality of bit subsequences.

[0111] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0112] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include the third-category bit segments. In other words, a third-category bit segment may serve as a whole as all or part of a fourth-category bit segment in an intermediate bit sequence, or the bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0113] Optionally, the sum of the number of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence. The sum of the number of bits in the multiple target bit sequences may also be greater than the number of bits in the initial bit sequence.

[0114] Optionally, there may be multiple initial bit sequences. The sequence processing method provided in the present application may further include: merging the obtained multiple initial bit sequences into a bit sequence to be processed.

[0115] Optionally, in the present application, the number of bits in the to-be-processed bit sequence is 58, 72, 73, 96, 106, or 116, and the number of bits in the aforementioned bit sequence is 64 or 128. It is understandable that the number of bits in the to-be-processed bit sequence may not be 58, 72, 73, 96, 106, or 116, and the number of bits in the aforementioned bit sequence may not be 64 or 128, and this application does not limit this.

[0116] For example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64.

[0117] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0118] For example, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained based on two bit subsequences with a number of 9 bits; two intermediate bit sequences with a number of 11 bits are obtained based on two bit subsequences with a number of 10 bits;

[0119] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0120] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; and in yet another portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0121] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72; the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is respectively: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0122] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 116, and the numbers of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0123] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0124] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0125] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0126] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 8 bits; in another portion of bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0127] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 8 bits.

[0128] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; wherein, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

[0129] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits of the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, and 11 respectively; 4 intermediate bit sequences with a number of 10 bits are obtained based on 4 bit subsequences with a number of 9 bits, and 4 intermediate bit sequences with a number of 11 bits are obtained based on 4 bit subsequences with a number of 10 bits.

[0130] Alternatively, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences is 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10.

[0131] By way of example, the number of bits in the above-mentioned bit sequence is 128, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, where r ≥ 1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, where s ≥ 1;

[0132] The number of bits in the to-be-processed bit sequence is 116, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively;

[0133] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0134] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0135] Alternatively, the number of bits in the to-be-processed bit sequence is 72; the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0136] Alternatively, the number of bits in the to-be-processed bit sequence is 116, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0137] Alternatively, the number of bits in the to-be-processed bit sequence is 106, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0138] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively;

[0139] Alternatively, the number of bits in the to-be-processed bit sequence is 72, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6, and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0140] Alternatively, the number of bits in the to-be-processed bit sequence is 96, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0141] Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequence obtained according to the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, and 11, respectively.

[0142] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the above-mentioned bit sequence is 128; the bit sequence to be processed is divided into 6 initial bit sequences, the bits in the initial bit sequences are continuous in the bit sequence to be processed, and the sth initial bit sequence and the s+1th initial bit sequence in the 6 initial bit sequences are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth initial bit sequences in the 6 initial bit sequences are 18, 18, 20, 20, 20, and 20, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the 6 initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0143] As another example, the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the above-mentioned one bit sequence is 128; the to-be-processed bit sequence is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the to-be-processed bit sequence, and the r-th bit subsequence and the r+1-th bit subsequence in the 12 bit subsequences are continuous in the to-be-processed bit sequence, and r≥1; in the 12 bit subsequences, every four consecutive bit subsequences in the to-be-processed bit sequence constitute an initial bit sequence, and the 12 bit subsequences are continuous. Among the three initial bit sequences composed of the special subsequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the 1st to 3rd initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0144] As another example, the number of bits in the bit sequence to be processed is 58, and the number of bits in the above-mentioned bit sequence is 64; the bit sequence to be processed is divided into 6 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 6 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 6 bit subsequences, every two continuous bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 6 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth bit subsequences in the 6 bit subsequences are 9, 9, 10, 10, 10, and 10, respectively; and the number of bits in the intermediate bit sequences obtained from the first to third initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0145] Optionally, the number of bits in each of the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, various methods can be used to perform an inverse process of the distribution matching process on any target bit sequence in the multiple target bit sequences.

[0146] For example, if the number of bits in the intermediate bit sequence is equal to the number of bits in the index bit sequence, the first method can be used to perform the inverse distribution matching processing on the target bit sequence; if the number of bits in the intermediate bit sequence is less than the number of bits in the result bit sequence, the second method can be used to perform the inverse distribution matching processing on the target bit sequence.

[0147] When the first method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the first index bit sequence corresponding to the first result bit sequence in the multiple result bit sequences can be used as the intermediate bit sequence corresponding to the target bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first result bit sequence includes: the target bit sequence.

[0148] For example, when the second method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the above-mentioned first index bit sequence can be inverted, and then the target class bit (or the target class bit and at least one fixed bit in sequence) can be added after the highest bit to obtain the intermediate bit sequence corresponding to the target bit sequence.

[0149] In a third aspect, the present application provides a sequence processing apparatus, comprising: a first processing module, configured to obtain a plurality of intermediate bit sequences based on an initial bit sequence; the initial bit sequence comprising a plurality of bit subsequences, at least one of the plurality of intermediate bit sequences being correlated with at least two of the plurality of bit subsequences;

[0150] Optionally, the sequence processing device further includes: a second processing module, used to perform distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences corresponding one-to-one to the multiple intermediate bit sequences; and a merging module, used to merge the obtained target bit sequences.

[0151] In summary, the method implemented by the sequence processing device provided in the embodiments of the present application first obtains multiple intermediate bit sequences based on an initial bit sequence, then performs distribution matching processing on each of the multiple intermediate bit sequences to obtain multiple target bit sequences that correspond one-to-one with the multiple intermediate bit sequences, and finally combines the obtained target bit sequences. Furthermore, at least one of the multiple intermediate bit sequences is correlated with at least two bit subsequences of the initial bit sequence. This sequence processing method differs from sequence processing methods in related arts and, therefore, enriches the methods for sequence processing.

[0152] In addition, since at least one of the multiple intermediate bit sequences is related to at least two bit subsequences of the initial bit sequence, the value of the at least one intermediate bit sequence depends on the values ​​of the at least two bit subsequences. When any bit subsequence in the at least two bit subsequences changes, the value of the at least one intermediate bit sequence changes. It can be seen that the present application will combine the values ​​of the at least two bit subsequences for global consideration to determine the value of the at least one intermediate bit sequence, so that the value of the at least one intermediate bit sequence is more conducive to improving the transmission effect of the signal.

[0153] It is understood that the at least two intermediate bit sequences may be the multiple intermediate bit sequences or some of the multiple intermediate bit sequences; and the at least two bit subsequences may be the multiple bit subsequences or some of the multiple bit subsequences, which is not limited in this embodiment of the present application. When the at least two intermediate bit sequences include multiple intermediate bit sequences, and the at least two bit subsequences include multiple bit subsequences, each intermediate bit sequence in the multiple intermediate bit sequences is correlated with all bit subsequences in the multiple bit subsequences.

[0154] Optionally, the bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be consecutive bits containing the most significant bit in the intermediate bit sequence. The at least two bit subsequences include: a first bit subsequence and a second bit subsequence, the value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the at least one intermediate bit sequence includes: a first intermediate bit sequence and a second intermediate bit sequence, the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value.

[0155] In this application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understood that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the following three conditions is met: the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values, or none of these three conditions are met.

[0156] Assume that the value of the sequence obtained by padded with 0 bits after the most significant bit (one bit higher than the most significant bit) of the first bit subsequence is the fifth value, and the value of the sequence obtained by padded with 0 bits after the most significant bit of the second bit subsequence is the sixth value. Then, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; if the third value is greater than the first and second values, and the fourth value is less than the first and second values, the absolute value of the difference between the fifth and sixth values ​​is less than the absolute value of the difference between the third and fourth values; and if the third value is greater than the fifth and sixth values, and the fourth value is less than the fifth and sixth values.

[0157] Take the example that 0 bits will be mapped to higher amplitude bits and 1 bits will be mapped to lower amplitude bits. Assume that the above distribution matching process is implemented by a lookup table, and the table searched in the lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, and the number of 0 bits in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. Then, the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the first bit subsequence is the first number, and the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the second bit subsequence is the second number; the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the first intermediate bit sequence is the third number, and the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the fourth intermediate bit sequence is the fourth number; the sum of the third number and the fourth number is less than the sum of the first number and the second number. In this way, after merging the two target bit sequences, a bit sequence with fewer 0 bits can be obtained, which is conducive to improving the transmission effect of the signal.

[0158] Optionally, the method satisfies at least one of the following conditions: the first type of bit segment includes one bit or two bits, and the second type of bit segment includes at least three bits; the multiple bit subsequences are two bit subsequences, and the multiple intermediate bit sequences are two intermediate bit sequences. Of course, the method may not satisfy this at least one condition. For example, the number of bit subsequences may be greater than 2, such as 2, 3, 4, 5, etc.; the number of intermediate bit sequences may be greater than 2, such as 3, 4, 5, etc.

[0159] Optionally, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 10, and the number of bits in the intermediate bit sequence is 11.

[0160] Furthermore, when the first processing module obtains multiple intermediate bit sequences based on the initial bit sequence, the multiple intermediate bit sequences can be obtained based on the initial bit sequence and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups. The target first bit sequence in the multiple first bit sequences includes: the first type of bit segments in the multiple bit subsequences; the bit sequence group includes multiple second type of bit segments, the multiple second type of bit segments in the target bit sequence group correspond one-to-one with the multiple intermediate bit sequences, and the target bit sequence group is the bit sequence group in the multiple bit sequence groups corresponding to the target first bit sequence; the second type of bit segment of the intermediate bit sequence includes the second type of bit segment corresponding to the intermediate bit sequence, and the second type of bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. Optionally, the multiple intermediate bit sequences can be obtained without the initial bit sequence and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups. For example, an algorithm can be used to operate on the initial bit sequence to obtain the multiple intermediate bit sequences.

[0161] Optionally, in the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, the value of at least one second-category bit segment in at least one bit sequence group is greater than the value of each first-category bit segment in the multiple first bit sequences.

[0162] For example, the bit sequence group includes two second-category bit segments, and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes:

[0163] The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0164] The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0165] The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0166] The correspondence between the first bit sequence (0, 0, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0167] The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0168] The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1);

[0169] The correspondence between the first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0170] The correspondence between the first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1);

[0171] The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0172] The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0173] The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0174] The correspondence between the first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0175] The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0176] The correspondence between the first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0177] The correspondence between the first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0178] The correspondence between the first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0179] The bits in the bit sequence are arranged from left to right in order from low to high bit position.

[0180] Optionally, the bit subsequences further include a third type of bit segment (also called a to-be-reallocated bit segment) in addition to the first type of bit segment; and the intermediate bit sequences further include a fourth type of bit segment (also called a reallocated bit segment) in addition to the second type of bit segment. The fourth type of bit segment in the plurality of intermediate bit sequences includes bits in the third type of bit segment in the plurality of bit subsequences.

[0181] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0182] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include the third-category bit segments. In other words, a third-category bit segment may serve as a whole as all or part of a fourth-category bit segment in an intermediate bit sequence, or the bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0183] Optionally, the sum of the number of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence. The sum of the number of bits in the multiple target bit sequences may also be greater than the number of bits in the initial bit sequence.

[0184] Optionally, the present application may further divide the initial bit sequence into multiple bit subsequences from the bit sequence to be processed. The bit sequence to be processed may belong to a bit stream received by the sequence processing device, and the sequence processing device may select the number of bits in the received bit stream as the bits to be processed based on the number of bits in the bit sequence to be processed.

[0185] Optionally, there may be multiple initial bit sequences. When multiple initial bit sequences are obtained by dividing the bit sequence to be processed, the bit sequence to be processed may be divided into multiple initial bit sequences, or the bit sequence to be processed may be divided into multiple bit subsequences within the multiple initial bit sequences. In addition, the bits in the initial bit sequence may be continuous or discontinuous in the bit sequence to be processed, and the multiple initial bit sequences may be continuous or discontinuous in the bit sequence to be processed. In this application, the example in which the bits in the initial bit sequence are continuous in the bit sequence to be processed and the multiple initial bit sequences are continuous in the bit sequence to be processed is taken as an example.

[0186] Optionally, in the present application, the number of bits in the to-be-processed bit sequence is 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained after merging is 64 or 128. It is understandable that the number of bits in the to-be-processed bit sequence may not be 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained after merging may not be 64 or 128, and this application does not impose any limitation on this.

[0187] For example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64.

[0188] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0189] For example, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10;

[0190] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0191] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; and in yet another portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0192] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72; the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is respectively: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0193] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 116, and the numbers of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0194] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0195] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0196] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0197] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 8 bits; in another portion of bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0198] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 8 bits.

[0199] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; wherein, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

[0200] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits of the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, and 11 respectively; 4 intermediate bit sequences with a number of 10 bits are obtained based on 4 bit subsequences with a number of 9 bits, and 4 intermediate bit sequences with a number of 11 bits are obtained based on 4 bit subsequences with a number of 10 bits.

[0201] Alternatively, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences is 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10.

[0202] For example, the number of bits in the bit sequence obtained after merging is 128, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r ≥ 1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the 6 initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s ≥ 1;

[0203] The number of bits in the to-be-processed bit sequence is 116, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively;

[0204] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0205] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0206] Alternatively, the number of bits in the to-be-processed bit sequence is 72; the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0207] Alternatively, the number of bits in the to-be-processed bit sequence is 116, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0208] Alternatively, the number of bits in the to-be-processed bit sequence is 106, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0209] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively;

[0210] Alternatively, the number of bits in the to-be-processed bit sequence is 72, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6, and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0211] Alternatively, the number of bits in the to-be-processed bit sequence is 96, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0212] Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequence obtained according to the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, and 11, respectively.

[0213] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 6 initial bit sequences, the bits in the initial bit sequences are continuous in the bit sequence to be processed, and the sth initial bit sequence and the s+1th initial bit sequence in the 6 initial bit sequences are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth initial bit sequences in the 6 initial bit sequences are 18, 18, 20, 20, 20, and 20, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the 6 initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0214] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, r≥1; in the 12 bit subsequences, every four consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 In the three initial bit sequences composed of bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the 1st to 3rd initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0215] As another example, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 6 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 6 bit subsequences, every two continuous bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 6 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth bit subsequences in the 6 bit subsequences are 9, 9, 10, 10, 10, and 10, respectively; and the number of bits in the intermediate bit sequences obtained from the first to third initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0216] Optionally, the number of bits in the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, the second processing module can use multiple methods to perform distribution matching processing on any intermediate bit sequence in the multiple intermediate bit sequences.

[0217] For example, when the second processing module adopts the first method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, the second processing module can, based on the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, use the first result bit sequence corresponding to the first index bit sequence among the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence.

[0218] For example, when the second processing module uses the second method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, when the t-th bit of the intermediate bit sequence is a target class bit, the second processing module uses the first result bit sequence corresponding to the first index bit sequence in the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence; the target class bit is 0 bit or 1 bit; when the t-th bit is not the target class bit, the valid bit segment is inverted (the inversion processing is used to update the 0 bit to 1 bit, and update the 1 bit to 0 bit); then, according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, a second result bit sequence corresponding to the second index bit sequence in the multiple index bit sequences is obtained (the second index bit sequence includes: the valid bit segment after the inversion processing), and the second result bit sequence is inverted to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0219] In the second distributed matching process, in the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, fewer index bit sequences can be used. Therefore, the index bit sequences and their corresponding result bit sequences that are not used in the correspondence can be deleted from the correspondence. In this way, the number of index bit sequences and the number of result bit sequences in the correspondence can be smaller.

[0220] For example, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be less than the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method. Furthermore, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be greater than or equal to half the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method.

[0221] The number of index bit sequences X ≥ 2 (u-t-1) .

[0222] In a fourth aspect, the present application provides a sequence processing device, which includes: a fourth processing module, used to obtain an initial bit sequence based on the multiple intermediate bit sequences; the initial bit sequence includes multiple bit subsequences, and each intermediate bit sequence in at least two intermediate bit sequences in the multiple intermediate bit sequences is related to at least two bit subsequences in the multiple bit subsequences.

[0223] Optionally, the sequence processing device further includes: a splitting module for splitting a plurality of target bit sequences from a bit sequence; a third processing module for performing an inverse process of the distribution matching process on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences corresponding one to one to the plurality of target bit sequences;

[0224] The sequence processing method executed by the sequence processing device provided in the fourth aspect is the inverse of the sequence processing method executed by the sequence processing device provided in the third aspect. The sequence processing method executed by the sequence processing device provided in the fourth aspect is used to process the bit sequence obtained by the sequence processing method executed by the sequence processing device provided in the third aspect, so as to restore the bit sequence before processing by the sequence processing device provided in the third aspect.

[0225] It is understood that the at least two intermediate bit sequences may be the multiple intermediate bit sequences or some of the multiple intermediate bit sequences; and the at least two bit subsequences may be the multiple bit subsequences or some of the multiple bit subsequences, which is not limited in this embodiment of the present application. When the at least two intermediate bit sequences include multiple intermediate bit sequences, and the at least two bit subsequences include multiple bit subsequences, each intermediate bit sequence in the multiple intermediate bit sequences is correlated with all bit subsequences in the multiple bit subsequences.

[0226] Optionally, the bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be consecutive bits containing the most significant bit in the intermediate bit sequence. The at least two bit subsequences include: a first bit subsequence and a second bit subsequence, the value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the at least one intermediate bit sequence includes: a first intermediate bit sequence and a second intermediate bit sequence, the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value.

[0227] In this application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understood that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the following three conditions is met: the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values, or none of these three conditions are met.

[0228] Optionally, the method satisfies at least one of the following conditions: the first type of bit segment includes one bit or two bits, and the second type of bit segment includes at least three bits; the multiple bit subsequences are two bit subsequences, and the multiple intermediate bit sequences are two intermediate bit sequences. Of course, the method may not satisfy this at least one condition. For example, the number of bit subsequences may be greater than 2, such as 2, 3, 4, 5, etc.; the number of intermediate bit sequences may be greater than 2, such as 3, 4, 5, etc.

[0229] Optionally, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 10, and the number of bits in the intermediate bit sequence is 11.

[0230] Furthermore, when the fourth processing module obtains the initial bit sequence based on the multiple intermediate bit sequences, it can obtain the multiple intermediate bit sequences based on the initial bit sequence and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups. The target first bit sequence in the multiple first bit sequences includes: the first type of bit segments in the multiple bit subsequences; the bit sequence group includes multiple second type of bit segments, the multiple second type of bit segments in the target bit sequence group correspond one-to-one with the multiple intermediate bit sequences, and the target bit sequence group is the bit sequence group in the multiple bit sequence groups corresponding to the target first bit sequence; the second type of bit segment of the intermediate bit sequence includes the second type of bit segment corresponding to the intermediate bit sequence, and the second type of bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. Optionally, the multiple intermediate bit sequences can be obtained without the initial bit sequence and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups. For example, an algorithm can be used to operate on the multiple intermediate bit sequences to obtain the initial bit sequence.

[0231] Optionally, in the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, the value of at least one second-category bit segment in at least one bit sequence group is greater than the value of each first-category bit segment in the multiple first bit sequences.

[0232] For example, the bit sequence group includes two second-category bit segments, and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes:

[0233] The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0234] The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0235] The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0236] The correspondence between the first bit sequence (0, 0, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0237] The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0238] The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1);

[0239] The correspondence between the first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0240] The correspondence between the first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1);

[0241] The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0242] The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0243] The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0244] The correspondence between the first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0245] The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0246] The correspondence between the first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0247] The correspondence between the first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0248] The correspondence between the first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0249] The bits in the bit sequence are arranged from left to right in order from low to high bit position.

[0250] Optionally, the bit subsequences further include a third type of bit segment (also called a to-be-reallocated bit segment) in addition to the first type of bit segment; and the intermediate bit sequences further include a fourth type of bit segment (also called a reallocated bit segment) in addition to the second type of bit segment. The fourth type of bit segment in the plurality of intermediate bit sequences includes bits in the third type of bit segment in the plurality of bit subsequences.

[0251] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0252] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include the third-category bit segments. In other words, a third-category bit segment may serve as a whole as all or part of a fourth-category bit segment in an intermediate bit sequence, or the bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0253] Optionally, the sum of the number of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence. The sum of the number of bits in the multiple target bit sequences may also be greater than the number of bits in the initial bit sequence.

[0254] Optionally, there may be multiple initial bit sequences. The sequence processing apparatus provided in the present application may further include: a module for merging the obtained multiple initial bit sequences into a bit sequence to be processed.

[0255] Optionally, in the present application, the number of bits in the to-be-processed bit sequence is 58, 72, 73, 96, 106, or 116, and the number of bits in the aforementioned bit sequence is 64 or 128. It is understandable that the number of bits in the to-be-processed bit sequence may not be 58, 72, 73, 96, 106, or 116, and the number of bits in the aforementioned bit sequence may not be 64 or 128, and this application does not limit this.

[0256] For example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64.

[0257] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0258] For example, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10;

[0259] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0260] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; and in yet another portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0261] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72; the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; and in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits.

[0262] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 116, and the numbers of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0263] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0264] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0265] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0266] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 8 bits; in another portion of bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0267] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 8 bits.

[0268] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; wherein, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

[0269] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits of the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, and 11 respectively; 4 intermediate bit sequences with a number of 10 bits are obtained based on 4 bit subsequences with a number of 9 bits, and 4 intermediate bit sequences with a number of 11 bits are obtained based on 4 bit subsequences with a number of 10 bits.

[0270] Alternatively, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences are 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10.

[0271] By way of example, the number of bits in the above-mentioned bit sequence is 128, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, where r ≥ 1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, where s ≥ 1;

[0272] The number of bits in the to-be-processed bit sequence is 116, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively;

[0273] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0274] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively;

[0275] Alternatively, the number of bits in the to-be-processed bit sequence is 72; the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0276] Alternatively, the number of bits in the to-be-processed bit sequence is 116, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0277] Alternatively, the number of bits in the to-be-processed bit sequence is 106, and the numbers of bits in the first to twelfth bit subsequences in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; and the numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, 11, respectively;

[0278] Alternatively, the number of bits in the to-be-processed bit sequence is 73, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively;

[0279] Alternatively, the number of bits in the to-be-processed bit sequence is 72, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6, and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0280] Alternatively, the number of bits in the to-be-processed bit sequence is 96, the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 10, 10, 11, 11, 11, and 11, respectively.

[0281] Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequence obtained according to the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, and 11, respectively.

[0282] As another example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the above-mentioned bit sequence is 128; the bit sequence to be processed is divided into 6 initial bit sequences, the bits in the initial bit sequences are continuous in the bit sequence to be processed, and the sth initial bit sequence and the s+1th initial bit sequence in the 6 initial bit sequences are continuous in the bit sequence to be processed, and s ≥ 1; the number of bits in the first to sixth initial bit sequences in the 6 initial bit sequences are 18, 18, 20, 20, 20 and 20 respectively; the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the 6 initial bit sequences are 10, 10, 11, 11, 11, and 11 respectively.

[0283] As another example, the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the above-mentioned one bit sequence is 128; the to-be-processed bit sequence is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the to-be-processed bit sequence, and the r-th bit subsequence and the r+1-th bit subsequence in the 12 bit subsequences are continuous in the to-be-processed bit sequence, and r≥1; in the 12 bit subsequences, every four consecutive bit subsequences in the to-be-processed bit sequence constitute an initial bit sequence, and the 12 bit subsequences are continuous. Among the three initial bit sequences composed of the special subsequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; and the numbers of bits in the intermediate bit sequences obtained from the 1st to 3rd initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0284] As another example, the number of bits in the bit sequence to be processed is 58, and the number of bits in the above-mentioned bit sequence is 64; the bit sequence to be processed is divided into 6 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 6 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 6 bit subsequences, every two continuous bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 6 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to sixth bit subsequences in the 6 bit subsequences are 9, 9, 10, 10, 10, and 10, respectively; and the number of bits in the intermediate bit sequences obtained from the first to third initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively.

[0285] Optionally, the number of bits in each of the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, the third processing module can use various methods to perform the inverse of the distribution matching process on any target bit sequence in the multiple target bit sequences.

[0286] For example, if the number of bits in the intermediate bit sequence is equal to the number of bits in the index bit sequence, the third processing module can use the first method to perform the inverse processing of the distribution matching processing on the target bit sequence; if the number of bits in the intermediate bit sequence is less than the number of bits in the result bit sequence, the third processing module can use the second method to perform the inverse processing of the distribution matching processing on the target bit sequence.

[0287] When the first method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the third processing module can use the first index bit sequence corresponding to the first result bit sequence in the multiple result bit sequences as the intermediate bit sequence corresponding to the target bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first result bit sequence includes: the target bit sequence.

[0288] For example, when the second method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the third processing module can invert the above-mentioned first index bit sequence, and then add the target class bit (or the target class bit and at least one fixed bit in sequence) after the highest bit to obtain the intermediate bit sequence corresponding to the target bit sequence.

[0289] In a fifth aspect, the present application provides a chip, which includes a programmable logic circuit and / or program instructions, and when the chip is running, it is used to implement the sequence processing method described in any design of the first aspect or the second aspect.

[0290] In a sixth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a computer, the computer executes the sequence processing method as described in any one of the designs in the first aspect or the second aspect.

[0291] In the seventh aspect, a sequence processing device is provided, wherein the communication device includes: a processor and a memory, wherein the memory stores a program, and the processor is used to execute the program stored in the memory to implement the sequence processing method described in any design in the first aspect.

[0292] In an eighth aspect, a sequence processing device is provided, wherein the communication device includes: a processor and a memory, wherein the memory stores a program, and the processor is used to execute the program stored in the memory to implement the sequence processing method described in any design in the second aspect.

[0293] In the ninth aspect, the present application provides a communication system, comprising: a sending node and a receiving node, the sending node comprising the sequence processing device described in any design of the third aspect, and the receiving node comprising the sequence processing device described in any design of the fourth aspect; or, the sending node comprising the sequence processing device described in any design of the seventh aspect, and the receiving node comprising the sequence processing device described in any design of the eighth aspect.

[0294] In a tenth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the sequence processing method described in any one of the designs of the first aspect or the second aspect.

[0295] The effects of the second to tenth aspects mentioned above can refer to the effects of the corresponding designs in the first aspect, and this application will not elaborate on them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0296] FIG1 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0297] FIG2 is a schematic structural diagram of a first sequence processing module provided in an embodiment of the present application;

[0298] FIG3 is a flow chart of a sequence processing method provided in an embodiment of the present application;

[0299] FIG4 is a schematic diagram of an initial bit sequence provided in an embodiment of the present application;

[0300] FIG5 is a schematic diagram of another initial bit sequence provided in an embodiment of the present application;

[0301] FIG6 is a schematic diagram of another initial bit sequence provided in an embodiment of the present application;

[0302] FIG7 is a schematic diagram of a processing process of an initial bit sequence provided in an embodiment of the present application;

[0303] FIG8 is a schematic diagram of a bit subsequence and an intermediate bit subsequence provided in an embodiment of the present application;

[0304] FIG9 is a schematic diagram of a processing process of a bit sequence to be processed provided by an embodiment of the present application;

[0305] FIG10 is a schematic diagram of a processing process of another bit sequence to be processed provided by an embodiment of the present application;

[0306] FIG11 is a schematic diagram showing the relationship between a bit subsequence, an initial bit sequence, and a bit sequence to be processed provided in an embodiment of the present application;

[0307] FIG12 is a schematic diagram of a processing process of multiple initial bit sequences provided in an embodiment of the present application;

[0308] FIG13 is a schematic diagram of Example 1 provided in an embodiment of the present application;

[0309] FIG14 is a schematic diagram of Example 2 provided in an embodiment of the present application;

[0310] FIG15 is a schematic diagram of Example 3 provided in an embodiment of the present application;

[0311] FIG16 is a schematic diagram of Example 4 provided in an embodiment of the present application;

[0312] FIG17 is a schematic diagram of Example 5 provided in an embodiment of the present application;

[0313] FIG18 is a schematic diagram of Example 6 provided in an embodiment of the present application;

[0314] FIG19 is a schematic diagram of Example 7 provided in an embodiment of the present application;

[0315] FIG20 is a schematic diagram of Example 8 provided in an embodiment of the present application;

[0316] FIG21 is a schematic diagram of Example 9 provided in an embodiment of the present application;

[0317] FIG22 is a schematic diagram of Example 10 provided in an embodiment of the present application;

[0318] FIG23 is a schematic diagram of Example 11 provided in an embodiment of the present application;

[0319] FIG24 is a schematic diagram of Example 12 provided in an embodiment of the present application;

[0320] FIG25 is a schematic diagram of Example 13 provided in an embodiment of the present application;

[0321] FIG26 is a schematic structural diagram of a sequence processing device provided in an embodiment of the present application;

[0322] FIG27 is a schematic structural diagram of another sequence processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0323] In order to make the principles and technical solutions of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0324] The present application provides a communication system, which can be an optical communication system such as a metropolitan area telecommunications transmission system or a metropolitan area data center interconnection (DCI) system. As shown in Figure 1, the communication system includes a transmitting node 01 and a receiving node 02, with a communication connection established between the transmitting node 01 and the receiving node 02 via a channel 03.

[0325] Both the sending node 01 and the receiving node 02 can be communication devices (such as optical line terminals (OLT), optical network devices (ONT), etc.), or they can be part of a communication device (such as an optical module in a communication device (which can be a pluggable optical module or a non-pluggable optical module), etc.). At the same time, the sending node 01 can also have the function of the receiving node 02, so the sending node 01 can also serve as a receiving node; the receiving node 02 can also have the function of the sending node 01, so the receiving node 02 can also serve as a sending node, and this application does not limit this. Channel 03 can be a wired channel, such as an optical fiber.

[0326] Transmitting node 01 can send signals to receiving node 02 via channel 03, enabling communication between the two nodes. For example, transmitting node 01 can perform transmission processing on a bit sequence to obtain a data frame, which it then transmits to channel 03. Receiving node 02 can receive the data frame sent by transmitting node 01 on channel 03 and perform reception processing on the data frame to obtain a bit sequence. This reception process is the inverse of the transmission process.

[0327] Continuing with reference to FIG1 , the sending node 01 includes: an information source 011, a first sequence processing module 012, and a first signal processing module 013. The information source 011, the first sequence processing module 012, the first signal processing module 013, and the channel 03 are connected in sequence. The information source 011 is used to provide a bit sequence to the first sequence processing module 012. The bit sequence includes multiple bits, each of which can be a 0 bit or a 1 bit. The values ​​of different bits in the bit sequence can be the same or different. The first sequence processing module 012 can perform sequence processing (including encoding, modulation, etc.) on the bit sequence to obtain multiple symbols, and transmit the multiple symbols to the first signal processing module 013. The first signal processing module 013 can perform framing processing on the multiple symbols to obtain data frames, and transmit the data frames to the receiving node 02 via the channel 03.

[0328] Receiving node 02 includes: a destination 021, a second sequence processing module 022, and a second signal processing module 023. Destination 021, second sequence processing module 022, second signal processing module 023, and channel 03 are sequentially connected. Second signal processing module 023 is capable of receiving data frames transmitted by transmitting node 01 via channel 03, performing operations such as dispersion compensation, synchronization, and phase recovery on the data frames, and then performing inverse framing processing to obtain multiple symbols. These symbols are then transmitted to second sequence processing module 022. Second sequence processing module 022 can perform inverse sequence processing (including decoding and demodulation) on the multiple symbols to obtain a bit sequence, which is then transmitted to destination 021.

[0329] It can be seen that the method for processing the sequence by the sending node in the related art is relatively simple.

[0330] Furthermore, driven by technologies such as the fifth generation mobile communication technology (5G), cloud computing, big data, and artificial intelligence, optical transmission systems are developing towards large capacity, packetization (grouping by transmission rate), and intelligence. Coherent optical communication systems can use the amplitude, phase, polarization, and frequency of light waves to carry information, adapting to the development direction of large capacity, packetization, and intelligence. For example, to improve spectrum efficiency, coherent optical communication systems typically use multi-level quadrature amplitude modulation (QAM), such as 16QAM, 32QAM, 64QAM, and even higher-order QAM.

[0331] Each constellation point symbol (constellation point symbol for short) on the signal constellation diagram corresponding to traditional QAM modulation appears with almost the same probability. However, in common scenarios where the average transmission power is limited, the probability of occurrence of symbols with higher amplitude bits in the signal constellation diagram is negatively correlated with the signal transmission effect. When the probability of occurrence of each symbol is almost the same, the probability of occurrence of symbols with higher amplitude bits is higher, resulting in poor signal transmission effect. Therefore, in order to improve the signal transmission effect, probabilistic constellation shaping (PCS) technology is introduced in the sending node. PCS technology can change the probability of occurrence of constellation point symbols while keeping the position of constellation point symbols on the signal constellation diagram unchanged, so that the probability of occurrence of each constellation point symbol is non-uniformly distributed, thereby reducing the probability of occurrence of symbols with higher amplitude bits, improving the signal transmission effect, improving the transmission performance of the communication system, and achieving a higher baud rate or a longer transmission distance.

[0332] PCS technology has been widely studied due to its advantages, such as approaching the Shannon limit and being flexible and adaptable. A sending node can perform PCS processing on a bit sequence, transforming a k-bit sequence into an N-bit sequence, where 1 < k < N. Statistics on multiple groups of bit sequences (each group includes the bit sequence before and after PCS processing, and the bit sequences before PCS processing vary between groups) reveal that while the bit sequence before PCS processing is an equiprobable bit sequence (the probability of each bit in the bit sequence being 0 or 1 is roughly equal), the bit sequence after PCS processing is an unequal-probability bit sequence (the probability of each bit in the bit sequence being 0 or 1 is unequal).

[0333] For example, when the transmission processing performed by the transmitting node includes PCS processing, the structure of the first sequence processing module in the transmitting node can be as shown in Figure 2. Referring to Figure 2, the first sequence processing module 012 includes a PCS processing module 0121, a forward error correction (FEC) encoding module 0122, and a symbol mapping module 0123. The PCS processing module 0121 is capable of performing PCS processing on a bit sequence comprising k bits in a bit sequence provided by a signal source, thereby obtaining a bit sequence comprising N bits. The FEC encoding module 0122 is capable of performing FEC encoding on the bit sequence comprising N bits output by the PCS processing module 0121, as well as on the remaining bit sequence in the bit sequence provided by the signal source, excluding the bit sequence processed by the PCS processing module 0121, and transmits the bit sequence obtained by the FEC encoding to the symbol mapping module 0123. The symbol mapping module 0123 is capable of modulating symbols based on the bit sequence obtained by the FEC encoding and outputting the modulated symbols. The bits in the bit sequence obtained by the PCS processing are mapped to the amplitude bits of the symbol by the symbol mapping module 0123. For example, in the present application, it is taken that a 0 bit in a bit sequence will be mapped to a higher amplitude bit by the symbol mapping module 0123, and a 1 bit in a bit sequence will be mapped to a lower amplitude bit by the symbol mapping module 0123. Alternatively, it is also possible that a 1 bit in a bit sequence will be mapped to a higher amplitude bit, and a 0 bit in a bit sequence will be mapped to a lower amplitude bit. In general, the first type of bit is used to map to a first amplitude bit, and the second type of bit is used to map to a second amplitude bit, the first amplitude bit is higher than the second amplitude bit, the first type of bit is a 0 bit and the second type of bit is a 1 bit, or the first type of bit is a 1 bit and the second type of bit is a 0 bit.

[0334] It is understood that because the receiving processing performed by the receiving node and the sending processing performed by the sending node are inverse processes of each other, when the sending processing performed by the sending node includes PCS processing, the receiving processing performed by the receiving node includes the inverse process of the PCS processing. For example, the second sequence processing module in the receiving node is configured to perform processing including the inverse process of the PCS processing.

[0335] Assume that the 0 bit in the bit sequence will be mapped to a higher amplitude bit, and the 1 bit in the bit sequence will be mapped to a lower amplitude bit. In the related art, when the sending node performs PCS processing, it processes the bit sequence by means of a look-up table (LUT). The sending node searches the table for the corresponding bit sequence comprising N bits based on the bit sequence comprising k bits. The table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, and the number of 0 bits in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. The bit in the bit sequence can be a 0 bit or a 1 bit, and the value of the bit sequence refers to: the value of the binary number represented by the bit sequence.

[0336] The 0 bits in the result bit sequence are used to map to a higher amplitude bit (amplitude bit of the symbol). If the number of 0 bits in the result bit sequence is larger, the more symbols with higher amplitude bits are obtained by modulating the result bit sequence, and the worse the signal transmission effect is. Therefore, in the related art, before searching for the sequence in the table, 0 bits are added to the end of the bit sequence to lock the bit sequence in the index bit sequence with fewer 0 bits in the corresponding result bit sequence among multiple index bit sequences. Therefore, the number of 0 bits in the result bit sequence found in the table according to the bit sequence after the 0 bits are added is smaller, which is conducive to improving the transmission effect of the signal.

[0337] However, a transmitting node typically performs PCS processing on multiple bit sequences in parallel, then combines the multiple bit sequences obtained after PCS processing and outputs them. When a transmitting node performs PCS processing on multiple bit sequences in parallel, in some cases, the total number of 0 bits in the combined bit sequence is still relatively high.

[0338] For example, assume that the maximum number of 0 bits contained in each of the multiple index bit sequences in the table is 10, and that the number of 0 bits in the resulting bit sequence corresponding to the index bit sequence whose most significant bit is 1 is 10, and the number of 0 bits in the resulting bit sequence corresponding to the index bit sequence whose most significant bit is 0 is 5. If the transmitting node performs PCS processing on two bit sequences in parallel, and after the two bit sequences are padded with 0 bits, the table is searched, the number of 0 bits in the two resulting bit sequences is 5. However, the number of 0 bits in the bit sequence obtained after the two bit sequences are combined is 10. Clearly, the number of 0 bits in the bit sequence obtained after the combination is still large, resulting in poor signal transmission performance.

[0339] In related technologies, the rate loss R loss It is negatively correlated with the signal transmission effect. Therefore, if R loss Reducing it can also improve the signal transmission effect.loss =HR, R = k / N, k is the number of bits in the bit sequence that needs to be processed by PCS, N is the number of bits in the bit sequence obtained by PCS processing, and R can be called the PCS rate. The bits in the bit sequence obtained by PCS processing meet a specific target distribution and are not independent. R is less than H, and H is the entropy rate of the bit sequence that meets the target distribution and is independent. When k and N increase in the same proportion, R remains unchanged, but H changes, and H and R become closer and closer, so R loss Therefore, R can be reduced by increasing k and N. loss , to improve signal transmission performance. However, k and N are positively correlated with the size of the table in the aforementioned lookup table approach. As k and N increase, the storage space required for the table increases exponentially. If optimal signal transmission performance is required, the required storage space for the table becomes very large. Furthermore, a larger storage space increases the complexity and power consumption of PCS processing.

[0340] Based on this, an embodiment of the present application provides a sequence processing method, which can process a bit sequence to obtain an unequal probability bit sequence containing fewer 0 bits. In addition, this method does not need to increase the size of the above-mentioned table. Therefore, this method does not cause the problem of a large storage space required for the table, a large PCS processing complexity, and high power consumption. Therefore, this method can be used for pluggable optical modules with higher power consumption constraints, which is beneficial for the pluggable optical module to achieve a longer transmission distance. In addition, the sequence processing method has a different way of processing bit sequences from the methods provided in the related art. Therefore, it can enrich the way of processing bit sequences.

[0341] The sequence processing method provided in the embodiment of the present application is performed by the sequence processing device in the above-mentioned sending node (referred to as the first sequence processing device) and the sequence processing device in the receiving node (referred to as the second sequence processing device). The first sequence processing device can be the first sequence processing module or other modules such as the PCS processing module in the sending node, and the second sequence processing device can be the second sequence processing module or other modules in the receiving node. For example, Figure 3 is a flowchart of a sequence processing method provided in the embodiment of the present application. As shown in Figure 3, the sequence processing method includes:

[0342] S101: A first sequence processing device obtains multiple intermediate bit sequences based on an initial bit sequence. The initial bit sequence includes multiple bit subsequences; each of at least two intermediate bit sequences in the multiple intermediate bit sequences is correlated with at least two bit subsequences in the multiple bit subsequences.

[0343] The initial bit sequence may consist of the multiple bit subsequences, or the multiple bit subsequences and other bits. The order of bits in the bit subsequence may be consistent with the order of bits in the initial bit sequence. For example, if the bit subsequence includes bit v1 and bit v2, and bits v1 and bit v2 are arranged from left to right, then the initial bit sequence also includes bit v1 and bit v2, and bits v1 and bit v2 are also arranged from left to right. It is understood that in the bit subsequence, bits v1 and bit v2 may be continuous or discontinuous bits, and in the initial bit sequence, bits v1 and bit v2 may also be continuous or discontinuous bits. Multiple bit subsequences may be continuous or discontinuous in the initial bit sequence. When multiple bit subsequences are continuous in the initial bit sequence, the multiple bit subsequences do not overlap; in other words, segmenting the initial bit sequence can produce the multiple continuous bit subsequences. The order of bits in the bit subsequence may also be inconsistent with the order of bits in the initial bit sequence.

[0344] For example, as shown in Figure 4, assuming that the initial bit sequence 1 includes a bit subsequence 1.1 and a bit subsequence 1.2, then the bit subsequence 1.1 and the bit subsequence 1.2 can constitute the initial bit sequence 1, and each bit subsequence in the bit subsequence 1.1 and the bit subsequence 1.2 is a bit segment in the initial bit sequence 1, and the bit subsequence 1.1 and the bit subsequence 1.2 are continuous in the initial bit sequence 1.

[0345] As another example, as shown in FIG5 , assuming that the initial bit sequence 1 includes a bit subsequence 1.1 and a bit subsequence 1.2, then the bit subsequence 1.1 and the bit subsequence 1.2 can constitute the initial bit sequence 1, and each of the bit subsequences 1.1 and 1.2 includes two bit segments in the initial bit sequence 1. For example, the bit subsequence 1.1 includes the bit segment 1 and the bit segment 3 in the initial bit sequence, and the bit subsequence 1.2 includes the bit segment 2 and the bit segment 4 in the initial bit sequence, and the bit segments 1, 2, 3, and 4 are continuous in the initial bit sequence 1.

[0346] As another example, as shown in FIG6 , assuming that the initial bit sequence 1 includes a bit subsequence 1.1 and a bit subsequence 1.2, the bit subsequence 1.1 and the bit subsequence 1.2 can constitute the initial bit sequence 1, and the bit subsequence 1.1 includes the bit segment 1 and the bit segment 3 in the initial bit sequence 1, and the bit subsequence 1.2 includes the bit segment 2 in the initial bit sequence 1. The bit segment 1, the bit segment 2, and the bit segment 3 are continuous in the initial bit sequence 1.

[0347] Optionally, the number of bits in the multiple bit subsequences may be the same or different. When the number of bits in the multiple bit subsequences is the same, the number of bits in these bit subsequences may be a value such as 6, 7, 8, 9, or 10, which is not limited in this embodiment of the present application. In this embodiment of the present application, the number of bits in the bit subsequences in the initial bit sequence can be reasonably set as needed.

[0348] The first sequence processing device obtains multiple intermediate bit sequences based on the initial bit sequence, and each intermediate bit sequence in at least two intermediate bit sequences in the multiple intermediate bit sequences is correlated with at least two bit subsequences of the initial bit sequence. It can be understood that the at least two intermediate bit sequences can be the multiple intermediate bit sequences, or they can be part of the intermediate bit sequences in the multiple intermediate bit sequences; the at least two bit subsequences can be the multiple bit subsequences, or they can be part of the bit subsequences in the multiple bit subsequences, and this embodiment of the present application does not limit this. When the at least two intermediate bit sequences include multiple intermediate bit sequences, and the at least two bit subsequences include multiple bit subsequences, each intermediate bit sequence in the multiple intermediate bit sequences is correlated with all bit subsequences in the multiple bit subsequences.

[0349] Because each of the at least two intermediate bit sequences is associated with at least two bit subsequences, the values ​​of the at least two intermediate bit sequences depend on the values ​​of the at least two bit subsequences. When any of the at least two bit subsequences changes, the values ​​of the at least two intermediate bit sequences also change. Thus, the first sequence processing device globally considers the values ​​of the at least two bit subsequences and determines the values ​​of the at least two intermediate bit sequences.

[0350] Optionally, the number of bits in the multiple intermediate bit sequences may be the same or different. When the number of bits in the multiple intermediate bit sequences is the same, the number of bits in the multiple intermediate bit sequences may be 9, 10, or 11, etc., which is not limited in this embodiment of the present application. Furthermore, the number of intermediate bit sequences in the multiple intermediate bit sequences and the number of bit subsequences in the multiple bit subsequences may be the same or different, which is not limited in this embodiment of the present application.

[0351] For example, the number of bits in the bit subsequence is 6 and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 6 and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 6 and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 7 and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 7 and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8 and the number of bits in the intermediate bit sequence is 9; or, the number of bits in the bit subsequence is 8 and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 8 and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 9 and the number of bits in the intermediate bit sequence is 10; or, the number of bits in the bit subsequence is 9 and the number of bits in the intermediate bit sequence is 11; or, the number of bits in the bit subsequence is 10 and the number of bits in the intermediate bit sequence is 11.

[0352] Optionally, the sum of the numbers of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence.

[0353] S102: The first sequence processing device performs distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences that correspond one to one to the multiple intermediate bit sequences.

[0354] After obtaining multiple intermediate bit sequences, the first sequence processing device may perform distribution matching processing on each of the multiple intermediate bit sequences to obtain a target bit sequence corresponding to each intermediate bit sequence. For example, as shown in FIG7 , after obtaining intermediate bit sequence 1.1 and intermediate bit sequence 1.2 from initial bit sequence 1, the first sequence processing device may perform distribution matching processing on intermediate bit sequence 1.1 to obtain target bit sequence 1.1, and perform distribution matching processing on intermediate bit sequence 1.2 to obtain target bit sequence 1.2.

[0355] Distribution matching (DM) processing is used to convert a bit sequence into a bit sequence with unequal probabilities. The intermediate bit sequence that needs to undergo distribution matching processing can be a bit sequence with equal probability or a bit sequence with unequal probability.

[0356] In the embodiments of this application, the distribution matching process is implemented using the aforementioned lookup table as an example. It is understood that the distribution matching process can also be implemented without using a lookup table, and this embodiment of the application is not limited thereto. When the distribution matching process is implemented using a lookup table, each of the multiple intermediate bit sequences has a corresponding table, which includes a correspondence between multiple index bit sequences and multiple result bit sequences. The first sequence processing device searches the table corresponding to each intermediate bit sequence to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0357] The distribution matching processes performed on different intermediate bit sequences can be the same or different. When the distribution matching processes are all implemented using a lookup table, the tables corresponding to different intermediate bit sequences can be the same or different, which is not limited in this embodiment of the present application.

[0358] Optionally, the sum of the numbers of bits in the multiple target bit sequences is greater than the number of bits in the initial bit sequence.

[0359] In addition, the number of bits in the target bit sequence may be equal to the number of bits in the intermediate bit sequence corresponding to the target bit sequence. Of course, the number of bits in the target bit sequence may also be less than or greater than the number of bits in the intermediate bit sequence corresponding to the target bit sequence.

[0360] S103: The first sequence processing device combines the obtained target bit sequence.

[0361] After obtaining the target bit sequence, the first sequence processing device may combine the target bit sequences obtained in S102.

[0362] The first sequence processing device can merge these target bit sequences in any order. Furthermore, when merging these target bit sequences, the first sequence processing device can combine these target bit sequences in order, or can also scatter the bits in these target bit sequences. The bit order in the target bit sequences and the bit order in the merged bit sequence can be the same or different, and this embodiment of the application does not limit this.

[0363] S104: The first sequence processing device transmits the bit sequence obtained by combining the target bit sequence to the second sequence processing device.

[0364] The bit sequence obtained after the first sequence processing device combines the bits can be transmitted to the second sequence processing device. For example, the bit sequence obtained after the first sequence processing device combines the bits can be transmitted to the second sequence processing device after undergoing FEC encoding, symbol mapping, symbol transmission in the channel, symbol demapping, and FEC decoding.

[0365] S105: The second sequence processing device separates a plurality of target bit sequences from the received bit sequence.

[0366] The second sequence processing device may use the inverse operation of combining the target bit sequences performed by the first sequence processing device in S103 to split the received bit sequence, so as to split the multiple target bit sequences mentioned above from the received bit sequence.

[0367] S106: The second sequence processing device performs an inverse process of the distribution matching process on the multiple target bit sequences to obtain a plurality of intermediate bit sequences corresponding to the multiple target bit sequences in a one-to-one manner.

[0368] After obtaining the multiple target bit sequences, the second sequence processing device may perform inverse processing of the distribution matching processing in S102 on the multiple target bit sequences to restore multiple intermediate bit sequences that correspond one to one to the multiple target bit sequences.

[0369] S107: The second sequence processing device obtains an initial bit sequence according to the multiple intermediate bit sequences.

[0370] After obtaining the multiple intermediate bit sequences, the second sequence processing device may perform the inverse process of the process in S101 to restore the above-mentioned initial bit sequence.

[0371] In this application, it is taken as an example that each of the at least two intermediate bit sequences is correlated with at least two bit subsequences. Of course, it is also possible that at least one intermediate bit sequence is correlated with at least two bit subsequences.

[0372] In summary, the sequence processing method provided in the embodiments of the present application first obtains multiple intermediate bit sequences based on an initial bit sequence. These multiple intermediate bit sequences are then individually distributed and matched to obtain multiple target bit sequences that correspond one-to-one with the multiple intermediate bit sequences. Finally, the resulting target bit sequences are combined. Furthermore, at least one of the multiple intermediate bit sequences is correlated with at least two bit subsequences of the initial bit sequence. This sequence processing method differs from sequence processing methods in related arts and, therefore, enriches the range of sequence processing options.

[0373] In addition, since at least one of the multiple intermediate bit sequences is related to at least two bit subsequences of the initial bit sequence, the value of the at least one intermediate bit sequence depends on the values ​​of the at least two bit subsequences. When any bit subsequence in the at least two bit subsequences changes, the value of the at least one intermediate bit sequence changes. It can be seen that the present application will combine the values ​​of the at least two bit subsequences for global consideration to determine the value of the at least one intermediate bit sequence, so that the value of the at least one intermediate bit sequence is more conducive to improving the transmission effect of the signal.

[0374] For example, the bit subsequence includes a first type of bit segment, and the intermediate bit sequence includes a second type of bit segment. The at least two bit subsequences mentioned above include: a first bit subsequence and a second bit subsequence, each bit subsequence in the multiple bit subsequences includes a first type of bit segment (also called a decision bit segment), and the number of bits in the first type of bit segment is greater than or equal to 1. The first type of bit segment in the bit subsequence may include the most significant bit in the bit subsequence, or may not include the most significant bit, which is not limited in this application. For example, as shown in Figure 8, the first bit subsequence includes a first type of bit segment d1, and the second bit subsequence includes a first type of bit segment d2; the first type of bit segment d1 is a higher bit segment in the first bit subsequence, and the first type of bit segment d1 includes the most significant bit in the first bit subsequence; the first type of bit segment d2 is a higher bit segment in the second bit subsequence, and the first type of bit segment d2 includes the most significant bit in the second bit subsequence. The first type of bit segment in the bit subsequence may be continuous bits or non-continuous bits in the intermediate bit sequence.

[0375] The second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be a continuous bit including the most significant bit in the intermediate bit sequence. The at least one intermediate bit sequence mentioned above includes: a first intermediate bit sequence and a second intermediate bit sequence, each of the plurality of intermediate bit sequences includes a second type of bit segment (also called an extended bit segment), and the second type of bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. The second type of bit segment in the intermediate bit sequence may be a continuous bit including the most significant bit in the intermediate bit sequence. For example, referring to FIG8 , the first intermediate bit sequence includes a second type of bit segment E1, and the second intermediate bit sequence includes a second type of bit segment E2; the second type of bit segment E1 is a higher-order bit segment in the first intermediate bit sequence, and the second type of bit segment E1 includes the most significant bit in the first intermediate bit sequence; the second type of bit segment E2 is a higher-order bit segment in the second intermediate bit sequence, and the second type of bit segment E2 includes the most significant bit in the second intermediate bit sequence.

[0376] The value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value. The absolute value of the difference between the first numerical value and the second numerical value is less than the absolute value of the difference between the third numerical value and the fourth numerical value; the third numerical value is greater than the first numerical value and the second numerical value, and the fourth numerical value is less than the first numerical value and the second numerical value.

[0377] Of course, the first value, the second value, the third value, and the fourth value may not satisfy this relationship, and this is not limited in the embodiments of the present application. For example, the absolute value of the difference between the first value and the second value may be equal to the absolute value of the difference between the third value and the fourth value. The third value may be less than or equal to the first value or the second value, and the fourth value may be greater than or equal to the first value or the second value.

[0378] Assume that the value of the sequence obtained by padded with 0 bits after the most significant bit (one bit higher than the most significant bit) of the first bit subsequence is the fifth value, and the value of the sequence obtained by padded with 0 bits after the most significant bit of the second bit subsequence is the sixth value. Then, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; if the third value is greater than the first and second values, and the fourth value is less than the first and second values, the absolute value of the difference between the fifth and sixth values ​​is less than the absolute value of the difference between the third and fourth values; and if the third value is greater than the fifth and sixth values, and the fourth value is less than the fifth and sixth values.

[0379] Take the example that 0 bits will be mapped to higher amplitude bits and 1 bits will be mapped to lower amplitude bits. Assume that the above distribution matching process is implemented by a lookup table, and the table searched in the lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, and the number of 0 bits in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. Then, the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the first bit subsequence is the first number, and the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the second bit subsequence is the second number; the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the first intermediate bit sequence is the third number, and the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the fourth intermediate bit sequence is the fourth number; the sum of the third number and the fourth number is less than the sum of the first number and the second number. In this way, after merging the two target bit sequences, a bit sequence with fewer 0 bits can be obtained, which is conducive to improving the transmission effect of the signal.

[0380] For example, assuming that the number of 0 bits contained in each of the multiple index bit sequences in the above table is up to 10, and the number of 0 bits in the result bit sequence corresponding to the index bit sequence whose highest bit is 1 bit is 10, and the number of 0 bits in the result bit sequence corresponding to the index bit sequence whose highest bit is 0 bit is 5. If the first number and the second number are both 5, then the sum of the first number and the second number is 10, the number of 0s in the processed bit sequence is large, and the signal transmission effect is poor. In the present application, by setting the third and fourth values, the third number can be 6 or 7, the fourth number can be 0, 1, 2 or 3, and the sum of the third and fourth numbers can be 6, 7, 8 or 9. In this way, the number of 0s in the processed bit sequence (two target bit sequences) can be less than 10, thereby improving the signal transmission effect.

[0381] Taking the example of 1 bit being mapped to a higher amplitude bit and 0 bit being mapped to a lower amplitude bit, the number of 1 bits in the resulting bit sequence obtained by searching the table (distribution matching process) based on the sequence obtained by directly adding 0 bits after the highest bit of the first bit subsequence (one bit higher than the highest bit) is the first number, and the number of 1 bits in the resulting bit sequence obtained by searching the table (distribution matching process) based on the sequence obtained by directly adding 0 bits after the highest bit of the second bit subsequence is the second number; the number of 1 bits in the resulting bit sequence (target bit sequence) obtained by searching the table based on the first intermediate bit sequence is the third number, and the number of 1 bits in the resulting bit sequence (target bit sequence) obtained by searching the table based on the fourth intermediate bit sequence is the fourth number; the sum of the third and fourth numbers is less than the sum of the first and second numbers. In this way, after merging the two target bit sequences, a bit sequence with less than 1 bit can be obtained, which is conducive to improving the transmission effect of the signal.

[0382] In the embodiment of the present application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; the third value is greater than the first and second values, and the fourth value is less than the first and second values. Of course, the first, second, third and fourth values ​​may not satisfy this relationship, and the embodiment of the present application is not limited to this. The absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values. The third value may also be less than or equal to the first or second value, and the fourth value may also be greater than or equal to the first or second value. For example, the first value is equal to the third value, and the second value is equal to the third value. For example, when the first value is 0 and the second value is 4, the third value is 0 and the fourth value is 4; when the first value is 1 and the second value is 4, the third value is 1 and the fourth value is 4.

[0383] In the embodiment of the present application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, and the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understandable that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the three conditions that the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values ​​is satisfied, or none of the three conditions are satisfied.

[0384] Optionally, based on the embodiment of the present application, k and N can also be increased at the same time to reduce R loss , thereby improving the signal transmission effect, which is not limited in this application.

[0385] Furthermore, the bit subsequences further include a third type of bit segments (also called to-be-reallocated bit segments) in addition to the first type of bit segments; and the intermediate bit sequences further include a fourth type of bit segments (also called reallocated bit segments) in addition to the second type of bit segments. The fourth type of bit segments in the plurality of intermediate bit sequences include bits in the third type of bit segments in the plurality of bit subsequences.

[0386] For example, referring to Figure 8 , the first bit subsequence includes, in addition to the first-category bit segment d1, a third-category bit segment f1; the second bit subsequence includes, in addition to the first-category bit segment d2, a third-category bit segment f2; the first intermediate bit sequence includes, in addition to the second-category bit segment E1, a fourth-category bit segment F1; and the second intermediate bit sequence includes, in addition to the second-category bit segment E2, a fourth-category bit segment F2. Furthermore, the fourth-category bit segment F1 and the fourth-category bit segment F2 comprise the bits in the third-category bit segment f1 and the third-category bit segment f2.

[0387] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0388] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include the third-category bit segments. In other words, a third-category bit segment may serve as a whole as all or part of a fourth-category bit segment in an intermediate bit sequence, or the bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0389] Furthermore, when the first sequence processing device obtains multiple intermediate bit sequences according to the initial bit sequence in the above S101, the multiple intermediate bit sequences can be obtained according to the initial bit sequence and a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups.

[0390] In this one-to-one correspondence, a target first bit sequence among the multiple first bit sequences includes: first-category bit segments among the multiple bit subsequences; the bit order in the target first bit sequence may be consistent with or inconsistent with the bit order in the initial bit sequence. A bit sequence group includes multiple second-category bit segments; the target bit sequence group is the bit sequence group among the multiple bit sequence groups that corresponds to the target first bit sequence; the multiple second-category bit segments in the target bit sequence group correspond one-to-one to the multiple intermediate bit sequences; and the second-category bit segment of each intermediate bit sequence among the multiple intermediate bit sequences includes the second-category bit segment corresponding to the intermediate bit sequence.

[0391] For example, the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups can be shown in Table 1 below, which includes: the correspondence between the first bit sequence 1 and a bit sequence group (including the second type of bit segment 2.1, the second type of bit segment 3.1, and the second type of bit segment 4.1); the correspondence between the first bit sequence 2 and a bit sequence group (including the second type of bit segment 2.2, the second type of bit segment 3.2, and the second type of bit segment 4.2); and the correspondence between the first bit sequence 3 and a bit sequence group (including the second type of bit segment 2.3, the second type of bit segment 3.3, and the second type of bit segment 4.3).

[0392] Table 1

[0393] In S101, the first sequence processing device may first obtain a to-be-searched bit sequence based on the first-type bit segments in multiple bit subsequences. The to-be-searched bit sequence includes the first-type bit segments in the multiple bit subsequences. The first sequence processing device then searches for the to-be-searched bit sequence in the multiple first bit sequences until a target first bit sequence identical to the to-be-searched bit sequence is found. The first sequence processing device then further locates a target bit sequence group corresponding to the target first bit sequence and, based on a one-to-one correspondence between multiple second-type bit segments in the bit sequence group and multiple intermediate bit sequences, uses each second-type bit segment in the target bit sequence group as a second-type bit segment in the corresponding intermediate bit sequence. At this point, the first sequence processing device is able to obtain the second-type bit segments in the multiple intermediate bit sequences.

[0394] Furthermore, in the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups, the first bit sequence can also be represented by multiple first-category bit segments in the first bit sequence. Multiple first-category bit segments in the target first bit sequence correspond one-to-one to first-category bit segments in multiple bit subsequences, and the first-category bit segments in the target first bit sequence include the corresponding first-category bit segments. In this case, the correspondence shown in Table 1 can be shown as in Table 2. First bit sequence 1 in Table 1 is represented by first-category bit segments 1.1 and 1.2 in Table 2. First bit sequence 1 consists of first-category bit segments 1.1 and 1.2, and in first bit sequence 1, first-category bit segments 1.1 and 1.2 are consecutive. First bit sequence 2 in Table 1 is represented by first-category bit segments 2.1 and 2.2 in Table 2. First bit sequence 2 consists of first-category bit segments 2.1 and 2.2, and in first bit sequence 2, first-category bit segments 2.1 and 2.2 are consecutive. The first bit sequence 3 in Table 1 is represented by the first type bit segment 3.1 and the first type bit segment 3.2 in Table 2. The first bit sequence 3 is composed of the first type bit segment 3.1 and the first type bit segment 3.2, and in the first bit sequence 3, the first type bit segment 3.1 and the first type bit segment 3.2 are continuous.

[0395] Table 2

[0396] In a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups, there exists at least one first bit sequence that satisfies the following relationship: the absolute value of the difference between the values ​​of two first-category bit segments in the first bit sequence is less than the absolute value of the difference between the values ​​of two second-category bit segments in the bit sequence group corresponding to the first bit sequence, and the value of one second-category bit segment in the bit sequence group is greater than the values ​​of the two first-category bit segments in the first bit sequence, while the value of another second-category bit segment is less than the values ​​of the two first-category bit segments in the first bit sequence. In a one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups, there may also exist at least one first bit sequence that does not satisfy this relationship. For example, the value of one first-category bit segment in the first bit sequence is equal to the value of one second-category bit segment in the bit sequence group corresponding to the first bit sequence, while the value of another first-category bit segment is equal to the value of another second-category bit segment. Furthermore, the bit sequence groups corresponding to the multiple first bit sequences that satisfy this relationship can be interchanged arbitrarily, and the bit sequence groups corresponding to the multiple first bit sequences that do not satisfy this relationship can also be interchanged arbitrarily.

[0397] Optionally, the first type of bit segment includes one bit or two bits; the second type of bit segment includes at least three bits; the multiple bit subsequences are two bit subsequences; and the multiple intermediate bit sequences are two intermediate bit sequences. At least one of these four conditions can be met. In the embodiment of the present application, the simultaneous satisfaction of these four conditions is taken as an example. It is understandable that the number of bits in the first type of bit segment can also be greater than 2, the number of bits in the second type of bit segment can also be greater than or less than 3, the number of bit subsequences in the multiple bit subsequences can also be greater than 2, the number of intermediate bit sequences in the multiple intermediate bit sequences can also be greater than 2, and the number of bit subsequences and the number of intermediate bit sequences can be equal or different.

[0398] Optionally, when the first-type bit segment includes two bits, the second-type bit segment includes at least three bits, the multiple bit subsequences are two bit subsequences, the bit sequence group includes two second-type bit segments, and the multiple intermediate bit sequences are two intermediate bit sequences, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes the following 16 correspondences:

[0399] The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0400] The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0401] The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0402] The correspondence between the first bit sequence (0, 0, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0403] The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0404] The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1);

[0405] The correspondence between the first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0406] The correspondence between the first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1);

[0407] The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0408] The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0);

[0409] The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0410] The correspondence between the first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0);

[0411] The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0412] The correspondence between the first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0413] The correspondence between the first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0);

[0414] The correspondence between the first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0);

[0415] The bits in the bit sequence are arranged from left to right in order from low to high bit position.

[0416] When the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups includes the above 16 correspondences, the one-to-one correspondence can be represented by the following Table 3 or Table 4. Table 3 is represented in the same manner as Table 1, and Table 4 is represented in the same manner as Table 2.

[0417] Table 3

[0418] Table 4

[0419] When the second type bit segment includes only three bits, the second type bit segment is the same as the lowest three bits in the second type bit segment. In this case, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups is the correspondence shown in Table 3 or Table 4.

[0420] When the second-category bit segment includes more than three bits, the bits in the second-category bit segment other than the three lowest bits may be at least one fixed bit. Taking the example of a second-category bit segment including four bits and including one fixed bit (0 bit) in addition to the three lowest bits, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups may be as shown in Table 5 or Table 6. Taking the example of a second-category bit segment including five bits and including two fixed bits (0 bits) in addition to the three lowest bits, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups may be as shown in Table 7 or Table 8. Taking the example of a second-category bit segment including six bits and including three fixed bits (0 bits) in addition to the three lowest bits, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups may be as shown in Table 9 or Table 10. Taking the example of a second-category bit segment consisting of seven bits, and including four fixed bits (0 bits) in addition to the three lowest-order bits, as an example, the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups can be shown in Table 11 or Table 12. Taking the example of a portion of the second-category bit segment consisting of four bits, including one fixed bit (0 bit) in addition to the three lowest-order bits, and another portion of the second-category bit segment consisting of five bits, including two fixed bits (0 bits) in addition to the three lowest-order bits, as an example, the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups can be shown in Table 13 or Table 14. Taking the example of a portion of the second-category bit segment consisting of five bits, including two fixed bits (0 bits) in addition to the three lowest-order bits, and another portion of the second-category bit segment consisting of six bits, including three fixed bits (0 bits) in addition to the three lowest-order bits, as an example, the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups can be shown in Table 15 or Table 16. It can be seen that the number of bits in different second-type bit segments can be the same or different. Correspondingly, the number of bits in the second-type bit segments in different intermediate bit sequences can also be the same or different.

[0421] Table 5

[0422] Table 6

[0423] Table 7

[0424] Table 8

[0425] Table 9

[0426] Table 10

[0427] Table 11

[0428] Table 12

[0429] Table 13

[0430] Table 14

[0431] Table 15

[0432] Table 16

[0433] When the target first bit sequence in each of the first bit sequences in the above-mentioned corresponding relationships is (0, 1, 0, 1), (0, 1, 1, 1), (1, 1, 0, 1), or (1, 1, 1, 1), the absolute value of the difference between the first value and the second value is less than the absolute value of the difference between the third value and the fourth value; the third value is greater than the first value and the second value, and the fourth value is less than the first value and the second value. When the target first bit sequence is (0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 1, 0), (0, 0, 1, 1), (0, 1, 0, 0), (0, 1, 1, 0), (1, 0, 0, 0), (1, 0, 0, 1), (1, 0, 1, 0), (1, 0, 1, 1), (1, 1, 0, 0), or (1, 1, 1, 0), the first value is equal to the third value, and the second value is equal to the fourth value.

[0434] For example, when the target first bit sequence is (0, 1, 1, 1), one first-class bit segment is (0, 1), and another first-class bit segment is (1, 1). The bit sequence group corresponding to the target first bit sequence includes one second-class bit segment (0, 0, 0) and another second-class bit segment (1, 0, 1). The first numerical value is 2 for one first-class bit segment (0, 1), the second numerical value is 3 for another first-class bit segment (1, 1), the fourth numerical value is 0 for one second-class bit segment (0, 0, 0), and the third numerical value is 5 for another second-class bit segment (1, 0, 1). It can be seen that the absolute value of the difference between the first numerical value 2 and the second numerical value 3, which is -1, is smaller than the absolute value of the difference between the third numerical value 5 and the fourth numerical value 0, which is 5; the third numerical value 5 is greater than the first numerical value 2 and the second numerical value 3, and the fourth numerical value 0 is smaller than the first numerical value 2 and the second numerical value 3.

[0435] When the target first bit sequence is (0, 0, 0, 0), one first-class bit segment is (0, 0), and another first-class bit segment is (0, 0). The bit sequence group corresponding to the target first bit sequence includes one second-class bit segment (0, 0, 0) and another second-class bit segment (0, 0, 0). The first numerical value is the value 0 of the first-class bit segment (0, 0), the second numerical value is the value 0 of the other first-class bit segment (0, 0), the fourth numerical value is the value 0 of the second-class bit segment (0, 0, 0), and the third numerical value is the value 5 of the other second-class bit segment (0, 0, 0). It can be seen that the absolute value 0 of the difference between the first numerical value 0 and the second numerical value 0 is equal to the absolute value 0 of the difference between the third numerical value 0 and the fourth numerical value 0.

[0436] Optionally, when the first-category bit segment includes two bits, the second-category bit segment includes at least three bits, the multiple bit subsequences are four bit subsequences, the bit sequence group includes four second-category bit segments, and the multiple intermediate bit sequences are four intermediate bit sequences, in the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, the correspondence between the two first-category bit segments and the two second-category bit segments may also be as shown in Table 4 above, and the correspondence between the other two first-category bit segments and the other two second-category bit segments may also be as shown in Table 4 above. Alternatively, the correspondence between the sequence composed of the two first-category bit segments and the two second-category bit segments may also be as shown in Table 3 above, and the correspondence between the sequence composed of the other two first-category bit segments and the other two second-category bit segments may also be as shown in Table 4 above.

[0437] For example, the correspondence between the sequence composed of the first type of bit segments 1.1 and 1.2 and the second type of bit segments 2.1 and 2.1, and the correspondence between the sequence composed of the first type of bit segments 1.3 and 1.4 and the second type of bit segments 2.3 and 2.4 can be shown in Table 17. The correspondence between the sequence composed of the first type of bit segments 1.1 and 1.2 and the second type of bit segments 2.1 and 2.1, and the correspondence between the sequence composed of the first type of bit segments 1.3 and 1.4 and the second type of bit segments 2.3 and 2.4 can be shown in Table 18.

[0438] It can be seen that the correspondence 1 between the sequence composed of the first-class bit segments 1.1 and 1.2 and the second-class bit segments 2.1 and 2.2 can be any of the correspondences shown in Table 17, and the correspondence 2 between the sequence composed of the first-class bit segments 1.3 and 1.4 and the second-class bit segments 2.3 and 2.4 can also be any of the correspondences shown in Table 17, and the correspondence 1 and the correspondence 2 can be the same or different.

[0439] The correspondence 1 between the first-class bit segments 1.1 and 1.2 and the second-class bit segments 2.1 and 2.2 can be any of the correspondences shown in Table 18, and the correspondence 2 between the first-class bit segments 1.3 and 1.4 and the second-class bit segments 2.3 and 2.4 can also be any of the correspondences shown in Table 18, and the correspondence 1 and the correspondence 2 can be the same or different.

[0440] Table 17

[0441] Table 18

[0442] When the second-type bit segment includes only three bits, the second-type bit segment is identical to the three least significant bits in the second-type bit segment. In this case, the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups is the correspondence shown in Table 3 or Table 4. When the second-type bit segment includes more than three bits, the bits other than the three least significant bits in the second-type bit segment may be at least one fixed bit.

[0443] In addition, in each of the one-to-one correspondences between the plurality of first bit sequences and the plurality of bit sequence groups, the value of at least one second-category bit segment in at least one bit sequence group is greater than the values ​​of each first-category bit segment. For example, in Tables 4 and 18, the second-category bit segments (0, 0, 1), (1, 0, 1), (0, 0, 1), and (1, 0, 1) are all greater than the values ​​of each first-category bit segment (maximum 3).

[0444] Optionally, before S101 above, the first sequence processing device may further divide the bit sequence to be processed into multiple bit subsequences in the initial bit sequence. For example, as shown in FIG9 , based on FIG7 , the first sequence processing device may divide the bit sequence to be processed to obtain multiple bit subsequences (bit subsequence 1.1 and bit subsequence 1.2), and obtain multiple intermediate bit sequences (intermediate bit sequence 1.1) based on the multiple bit subsequences. The bit sequence to be processed may belong to a bit stream received by the first sequence processing device. The first sequence processing device may select, from the received bit stream, a number of bits in the bit sequence to be processed as the bits to be processed, based on the number of bits in the bit sequence to be processed.

[0445] Furthermore, in the above embodiment, a single initial bit sequence is used as an example. Optionally, there may be multiple initial bit sequences. In this case, the first sequence processing device may obtain multiple target bit sequences based on each initial bit sequence in S101 and S102, and merge all target bit sequences obtained from the multiple initial bit sequences in S103.

[0446] The multiple initial bit sequences may be received by the first sequence processing device, or may be obtained by the first sequence processing device dividing the bit sequence to be processed.

[0447] When multiple initial bit sequences are obtained by dividing the bit sequence to be processed, the first sequence processing device may divide the bit sequence to be processed into the multiple initial bit sequences, or the first sequence processing device may divide the bit sequence to be processed into multiple bit subsequences within the multiple initial bit sequences. Furthermore, the multiple initial bit sequences may be continuous or discontinuous within the bit sequence to be processed. In the embodiment of the present application, the multiple initial bit sequences are continuous within the bit sequence to be processed as an example.

[0448] For example, assuming that there are two initial bit sequences, namely initial bit sequence 1 and initial bit sequence 2, as shown in FIG10 , the first sequence processing device may split the bit sequence to be processed into initial bit sequence 1 and initial bit sequence 2.

[0449] The first sequence processing apparatus can obtain an intermediate bit sequence 1.1 and an intermediate bit sequence 1.2 based on the initial bit sequence 1. The intermediate bit sequence 1.1 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2 in the initial bit sequence 1, and the intermediate bit sequence 1.2 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2 in the initial bit sequence 1. The first sequence processing apparatus can also obtain a target bit sequence 1.1 based on the intermediate bit sequence 1.1, and obtain a target bit sequence 1.2 based on the intermediate bit sequence 1.2.

[0450] The first sequence processing apparatus may further obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2. The intermediate bit sequence 2.1 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2, and the intermediate bit sequence 2.2 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2. The first sequence processing apparatus may further obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0451] In this example, the relationship between the to-be-processed bit sequence, initial bit sequence 1, initial bit sequence 2, bit subsequence 1.1, bit subsequence 1.2, bit subsequence 2.1 and bit subsequence 2.2 may be as shown in FIG. 11 .

[0452] As another example, assuming there are two initial bit sequences, namely initial bit sequence 1 and initial bit sequence 2, as shown in FIG12 , the first sequence processing device may split the bit sequence to be processed into bit subsequence 1.1, bit subsequence 1.2, bit subsequence 2.1, and bit subsequence 2.2. Initial bit sequence 1 includes bit subsequence 1.1 and bit subsequence 1.2, and initial bit sequence 2 includes bit subsequence 2.1 and bit subsequence 2.2.

[0453] The first sequence processing device can obtain an intermediate bit sequence 1.1 and an intermediate bit sequence 1.2 based on the initial bit sequence 1 (including the bit subsequence 1.1 and the bit subsequence 1.2). The intermediate bit sequence 1.1 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2, and the intermediate bit sequence 1.2 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2. The first sequence processing device can also obtain a target bit sequence 1.1 based on the intermediate bit sequence 1.1 and obtain a target bit sequence 1.2 based on the intermediate bit sequence 1.2.

[0454] The first sequence processing device may also obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2 (including the bit subsequence 2.1 and the bit subsequence 2.2). The intermediate bit sequence 2.1 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2, and the intermediate bit sequence 2.2 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2. The first sequence processing device may also obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0455] In this example, the relationship between the to-be-processed bit sequence, the initial bit sequence 1, the initial bit sequence 2, the bit subsequence 1.1, the bit subsequence 1.2, the bit subsequence 2.1 and the bit subsequence 2.2 may also be as shown in FIG. 11 .

[0456] In the embodiment of the present application, the number of initial bit sequences is taken as 2 as an example. It can be understood that the number of initial bit sequences can also be greater than 2.

[0457] Optionally, in the embodiment of the present application, the number of bits in the to-be-processed bit sequence is 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained by merging the target bit sequence (i.e., the bit sequence obtained after merging) is 64 or 128. It is understandable that the number of bits in the to-be-processed bit sequence may not be 58, 72, 73, 96, 106, or 116, and the number of bits in the bit sequence obtained after merging may not be 64 or 128, and this embodiment of the present application is not limited thereto.

[0458] For example, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; or, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64.

[0459] The distribution matching process performed on the intermediate bit sequence in S102 may be implemented in a lookup table manner.

[0460] When using a lookup table for distribution matching, a table can be searched based on an intermediate bit sequence to obtain a target bit sequence corresponding to the intermediate bit sequence. The lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences. The tables searched by the first sequence processing device in obtaining corresponding target bit sequences based on different index bit sequences can be the same or different.

[0461] Optionally, when a 0 bit is mapped to a higher amplitude bit and a 1 bit is mapped to a lower amplitude bit, the value of the index bit sequence is positively correlated with the number of 0 bits in the result bit sequence. When a 1 bit is mapped to a higher amplitude bit and a 0 bit is mapped to a lower amplitude bit, the value of the index bit sequence is positively correlated with the number of 1 bits in the result bit sequence.

[0462] The multiple index bit sequences may be arranged in order of increasing or decreasing values. Of course, the multiple index bit sequences may not be arranged in this order, and this application does not limit this.

[0463] For example, taking the case where bit 0 is mapped to a higher amplitude bit and bit 1 is mapped to a lower amplitude bit, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be shown in Table 19 below. The index bit sequence includes Y bits, Y>1, and the first to Yth bits of the index bit sequence are represented as [1:Y]. The Yth bit is the most significant bit. The result bit sequence includes N bits, N>1, and the first bit in the result bit sequence is represented as N[1], the second bit in the result bit sequence is represented as N[2], and so on.

[0464] Table 19

[0465] Assume that there are X index bit sequences, the number of 0 bits in the result bit sequence corresponding to the first index bit sequence is 0, and the number of 0 bits in the result bit sequence corresponding to the first index bit sequence is 0. The index bit sequence to the The number of 0 bits in the result bit sequence corresponding to the index bit sequence is s, and the number of 1 bits is NS, where s is a positive integer and 1≤s≤N. It represents the number of combinations, which means the number of all combinations of c (c≤N) elements taken from N different elements. It is called the number of combinations of c elements taken from N different elements. "!" means factorial. For example,

[0466] For example, as shown in Table 19, the number of 0 bits in the result bit sequence corresponding to the 1st index bit sequence is 0; the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence is 1; the number of 0 bits in the result bit sequence corresponding to the 2+Nth index bit sequence to the 1+N+N(N-1) / 2th index bit sequence is 2; and so on.

[0467] It is worth noting that The index bit sequence to the The number of 0 bits in the result bit sequence corresponding to the index bit sequences is s, and the number of 1 bits is Ns. Therefore, there is no fixed order between these index bit sequences, and the order of these index bit sequences can be interchanged arbitrarily.

[0468] Optionally, the index bit sequences can be sorted based on the preference for placing 0 bits in the low bit positions of the result bit sequence. In a group of index bit sequences with the same number of 0 bits in the corresponding result bit sequences, the smaller the value of the index bit sequence, the smaller the sum of the number of 0 bits in the result bit sequence corresponding to the index bit sequence. For example, referring to Table 19, the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence is 1, the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence is 1, and the 0 bit is the lowest 1st bit in the result bit sequence; the number of 0 bits in the result bit sequence corresponding to the 1+Nth index bit sequence is 1+N, and the 0 bit is higher than the 1st bit 1+Nth bit in the result bit sequence; it can be seen that the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence increases successively.

[0469] Alternatively, the index bit sequences can be sorted based on the probability of each bit in the result bit sequence being 0, so that the probability of each bit being 0 in multiple result bit sequences is the same. Bits of different orders have the same proportion of 0 bits in the multiple values ​​of the multiple result bit sequences. In other words, the index bit sequences can be sorted based on the principle of making the probability of each bit being 0 in all possible result bit sequences as close as possible. Which result bit sequences in the lookup table are usable is determined by the value range of the index bit sequence.

[0470] The number of index bit sequences in the above multiple index bit sequences is X≤2 N , and X≤2 Y .

[0471] Optionally, the number of bits in each of the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, the first sequence processing device can use multiple methods to perform distribution matching processing on any intermediate bit sequence in the multiple intermediate bit sequences.

[0472] For example, when the first sequence processing device adopts the first method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, it can use the first result bit sequence corresponding to the first index bit sequence in the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence.

[0473] For example, when the first sequence processing device uses the second method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, when the t-th bit of the intermediate bit sequence is a target class bit, the first sequence processing device uses the first result bit sequence corresponding to the first index bit sequence in the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence; the target class bit is 0 bit or 1 bit; when the t-th bit is not the target class bit, the first sequence processing device performs inversion processing on the valid bit segment (the inversion processing is used to update the 0 bit to 1 bit, and update the 1 bit to 0 bit); then, the first sequence processing device obtains a second result bit sequence corresponding to the second index bit sequence in the multiple index bit sequences based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences (the second index bit sequence includes: the valid bit segment after the inversion processing), and performs inversion processing on the second result bit sequence to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0474] In the second distributed matching process, in the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, fewer index bit sequences can be used. Therefore, the index bit sequences and their corresponding result bit sequences that are not used in the correspondence can be deleted from the correspondence. In this way, the number of index bit sequences and the number of result bit sequences in the correspondence can be smaller.

[0475] For example, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be less than the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method. Furthermore, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be greater than or equal to half the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method.

[0476] The number of index bit sequences X ≥ 2 (u-t-1) .

[0477] It can be understood that the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distribution matching processing method can also be the same as the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distribution matching processing method.

[0478] In general, the value of the number X of index bit sequences is divided into the following three cases.

[0479] The first case, X>2 (u-t) , at this time there is an index bit sequence that will not be found. When the number of bits Y in the index bit sequence exceeds ut (there are an additional Yut fixed bits), when looking up the table, the valid bit segment composed of the 1st to t-1th bits in the intermediate bit sequence and the additional Yut fixed bits can be combined to obtain a new bit sequence, and then the bit sequence is compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. Among them, the above-mentioned additional Yut fixed bits can be the same as or different from the ut fixed bits in the intermediate bit sequence. When Y=u, when looking up the table, the intermediate bit sequence can be directly compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. It can be seen that in the first case, the distribution matching processing of the first method mentioned above can be used to find the target bit sequence.

[0480] The second case, X = 2 (u-t) , there are no index bit sequences that will not be found. In this case, Y can be equal to ut. When looking up the table, the valid bit segment from bit 1 to bit t-1 in the intermediate bit sequence is directly compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. Therefore, in the second case, the distribution matching process described in the first method can be used to find the target bit sequence.

[0481] The third case, 2 (u-t-1) ≤X<2 (u-t) In this case, the number of index bit sequences is small, and all rows in the table match at least half of all possible intermediate bit sequences. In this case, the number of bits Y in the index bit sequence can be ut-1. In the third case, the distribution matching process described in the second method can be used to find the target bit sequence.

[0482] Since the operation performed by the second sequence processing device is inverse to the operation performed by the first sequence processing device, the second sequence processing device can also use multiple methods to perform the inverse process of the distribution matching process on any target bit sequence among the multiple target bit sequences.

[0483] For example, if the number of bits in the intermediate bit sequence is equal to the number of bits in the index bit sequence, the first method can be used to perform the inverse distribution matching processing on the target bit sequence; if the number of bits in the intermediate bit sequence is less than the number of bits in the result bit sequence, the second method can be used to perform the inverse distribution matching processing on the target bit sequence.

[0484] When the first method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the first index bit sequence corresponding to the first result bit sequence in the multiple result bit sequences can be used as the intermediate bit sequence corresponding to the target bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first result bit sequence includes: the target bit sequence.

[0485] When the second method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the above-mentioned first index bit sequence can be inverted, and then the target class bit (or the target class bit and at least one fixed bit in sequence) can be added after the highest bit to obtain the intermediate bit sequence corresponding to the target bit sequence.

[0486] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0487] For example, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10;

[0488] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0489] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; and in yet another portion of bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0490] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72; the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is respectively: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0491] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 116, and the numbers of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0492] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 106, and the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 9 bits are obtained from two bit subsequences with 8 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0493] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 73, and the numbers of bits in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the numbers of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits; in another portion of bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on one bit subsequence with 6 bits and one bit subsequence with 7 bits;

[0494] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0495] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the to-be-processed bit sequence is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 8 bits; in another portion of bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0496] Alternatively, the number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 9 bits are obtained based on two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 8 bits.

[0497] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; wherein, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

[0498] Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, respectively; 4 intermediate bit sequences with a number of 10 bits are obtained based on 4 bit subsequences with a number of 9 bits, and 4 intermediate bit sequences with a number of 11 bits are obtained based on 4 bit subsequences with a number of 10 bits.

[0499] Alternatively, the number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; the bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences is 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10.

[0500] The present embodiment does not limit the order of the bit subsequences. Accordingly, the order of the intermediate bit sequences obtained based on the bit subsequences is also not limited. Furthermore, elements in a bit subsequence may or may not be continuous within the bit sequence to be processed, and multiple bit subsequences may or may not be continuous within the bit sequence to be processed.

[0501] The sequence processing method provided in the embodiments of the present application will be further described through the following examples.

[0502] Example 1: As shown in FIG13 , the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128.

[0503] The bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively.

[0504] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 bit subsequences constitute a total of 6 initial bit sequences. Moreover, among the 6 initial bit sequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1.

[0505] As shown in Figure 13, the bit subsequence represents the pth bit subsequence in the mth initial bit sequence (also called initial bit sequence m), m≥1, p≥1. For example, represents the first bit subsequence in the first initial bit sequence, Represents the second bit subsequence in the first initial bit sequence. represents the first bit subsequence in the second initial bit sequence, Represents the second bit subsequence in the second initial bit sequence. Similarly, the embodiments of the present application are not described in detail here.

[0506] k[B:C] represents: bit subsequence Includes A bits, which are bits B to C in the bit sequence to be processed. A>1, 1≤B<C. For example, k[1:9] represents: bit subsequence It includes 9 bits, which are the 1st bit to the 9th bit in the bit sequence to be processed. k[10:18] represents: bit subsequence The 9 bits are from the 10th bit to the 18th bit in the bit sequence to be processed. Similarly, the embodiments of the present application are not described in detail here. The bits are arranged from left to right in the order of low to high bit position.

[0507] The first sequence processing module needs to perform bit processing 1 on initial bit sequence 1, bit processing 2 on initial bit sequence 2, bit processing 3 on initial bit sequence 3, bit processing 4 on initial bit sequence 4, bit processing 5 on initial bit sequence 5, and bit processing 6 on initial bit sequence 6. The numbers of bits in the intermediate bit sequences obtained by the first sequence processing module based on the first to sixth initial bit sequences of the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0508] As shown in FIG13 , the first sequence processing module performs bit processing on the mth initial bit sequence, and the obtained qth intermediate bit sequence is expressed as express: It includes D bits, D>1. For example, the first sequence processing module performs bit processing on the first initial bit sequence, and the first intermediate bit sequence obtained is expressed as express: The first sequence processing module performs bit processing on the first initial bit sequence, and the obtained second intermediate bit sequence is expressed as express: The embodiment of the present application will not be described in detail here.

[0509] The first sequence processing module can query the one-to-one correspondence between multiple first bit sequences and multiple bit sequence groups (as shown in Table 4) based on the first type of bit segments in multiple subsequences in the initial bit sequence, and obtain the second type of bit segments in the multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in the multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0510] In the process of the first sequence processing module obtaining intermediate bit sequences based on different initial bit sequences, the one-to-one correspondences between the multiple queried first bit sequences and the multiple bit sequence groups can be the same or different. Here, the one-to-one correspondences shown in Table 4 are used as an example. Furthermore, in each bit subsequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the three most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these three bits.

[0511] For example, the above bit subsequence and In each bit subsequence in , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]).

[0512] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 9th to 10th bits of the most significant bits from left to right in the bit subsequence (expressed as [9:10]), and the third type of bit segment includes the 1st to 8th bits of the most significant bits from left to right in the bit subsequence (expressed as [1:8]).

[0513] The above intermediate bit sequence and In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0514] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 9th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in the intermediate bit sequence (expressed as [1:8]).

[0515] The first sequence processing module performs bit processing on the mth initial bit sequence to obtain the intermediate bit sequence The distribution matching process performed is called distribution matching process mq. For example, the first sequence processing module performs bit processing on the first initial bit sequence, and the intermediate bit sequence obtained is The distribution matching process 1-1 is performed.

[0516] N[V:Z] represents the middle bit sequence Corresponding target bit sequence Including G bits, G>1, target bit sequence Including the Vth bit to the Zth bit in the combined bit sequence, 1≤V<Z. For example, N[1:10] represents the middle bit sequence Corresponding target bit sequence Contains 10 bits, target bit sequence Including the 1st bit to the 10th bit in the combined bit sequence. N[11:20] represents the middle bit sequence Corresponding target bit sequence Contains 10 bits, target bit sequence Including the 11th bit to the 20th bit in the combined bit sequence.

[0517] The first sequence processing module processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 20. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0518] Table 20

[0519] Table 21

[0520] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 36.58%.

[0521] Example 2: As shown in FIG14 , the number of bits in the to-be-processed bit sequence is 106, and the number of bits in the bit sequence obtained after merging is 128.

[0522] The meanings of the various symbols in FIG14 can refer to the meanings of the various symbols in FIG13 , and this application will not elaborate on them here.

[0523] The bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively.

[0524] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 bit subsequences constitute a total of 6 initial bit sequences. Moreover, among the 6 initial bit sequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1.

[0525] The first sequence processing module needs to perform bit processing 1 on initial bit sequence 1, bit processing 2 on initial bit sequence 2, bit processing 3 on initial bit sequence 3, bit processing 4 on initial bit sequence 4, bit processing 55 on initial bit sequence 5, and bit processing 6 on initial bit sequence 6. The first sequence processing module obtains intermediate bit sequences with the following numbers of bits, respectively, based on the first to sixth initial bit sequences of the six initial bit sequences: 10, 10, 11, 11, 11, and 11.

[0526] The first sequence processing module can query the corresponding relationship shown in Table 6 based on the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0527] In the process of the first sequence processing module obtaining intermediate bit sequences based on different initial bit sequences, the one-to-one correspondences between the multiple queried first bit sequences and the multiple bit sequence groups can be the same or different. Here, the one-to-one correspondences shown in Table 6 are used as an example. Furthermore, in each bit subsequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the three most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these three bits.

[0528] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]).

[0529] The above bit subsequence and In each bit subsequence in , the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (expressed as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]).

[0530] The above intermediate bit sequence and In each intermediate bit sequence in the , the second type of bit segment includes the 7th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [7:10]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (expressed as [1:6]).

[0531] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0532] The first sequence processing module processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 20. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0533] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 30.75%.

[0534] Example 3: As shown in FIG15 , the number of bits in the to-be-processed bit sequence is 73, and the number of bits in the bit sequence obtained after merging is 128.

[0535] The meanings of the various symbols in FIG15 can refer to the meanings of the various symbols in FIG13 , and this application will not elaborate on them here.

[0536] Referring to FIG15 , the to-be-processed bit sequence is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the to-be-processed bit sequence, and the r-th bit subsequence and the r+1-th bit subsequence in the 12 bit subsequences are continuous in the to-be-processed bit sequence, where r ≥ 1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6, respectively;

[0537] In the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence. In the 6 initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s ≥ 1;

[0538] The numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0539] The first sequence processing module can query the corresponding relationship shown in Table 16 based on the first type of bit segments in multiple subsequences in the initial bit sequence 1 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence 1. Specifically, in each bit subsequence of the initial bit sequence 1, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In some intermediate bit sequences, the second type of bit segment includes the five most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these five bits. In another part of the intermediate bit sequence, the second type of bit segment includes the six most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these six bits.

[0540] The first sequence processing module can also query the corresponding relationship shown in Table 10 based on the first type of bit segments in multiple subsequences in the initial bit sequence 2 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence 2. Among them, in each bit subsequence of the initial bit sequence 2, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the six most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these six bits.

[0541] The first sequence processing module can also query the corresponding relationship shown in Table 12 based on the first type of bit segments in multiple subsequences in each initial bit sequence from initial bit sequence 3 to initial bit sequence 6 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the seven most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these seven bits.

[0542] For example, the above bit subsequence In the bit sequence, the first type of bit segment includes the 6th to 7th bits of the most significant bit in the bit subsequence (expressed as [6:7]), and the third type of bit segment includes the 1st to 5th bits in the bit subsequence (expressed as [1:5]).

[0543] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (expressed as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (expressed as [1:4]).

[0544] The above intermediate bit sequence and In each intermediate bit sequence in the , the second type of bit segment includes the 6th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [6:10]), and the fourth type of bit segment includes the 1st bit to the 5th bit from left to right in the intermediate bit sequence (expressed as [1:5]).

[0545] The above intermediate bit sequence In the embodiment, the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0546] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0547] The first sequence processing module processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 20. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0548] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 17.59%.

[0549] Example 4: As shown in FIG16 , the number of bits in the to-be-processed bit sequence is 72; the number of bits in the bit sequence obtained after merging is 128.

[0550] The meanings of the various symbols in FIG16 can refer to the meanings of the various symbols in FIG13 , and this application will not elaborate on them here.

[0551] Referring to Figure 16, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; the number of bits in the 1st to 12th bit subsequences in the 12 bit subsequences is 6; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the 6 initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the numbers of bits in the intermediate bit sequences obtained from the 1st to 6th initial bit sequences in the 6 initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively.

[0552] The first sequence processing module can also query the corresponding relationship shown in Table 10 based on the first type of bit segments in multiple subsequences in each initial bit sequence in the initial bit sequences 1 and 2 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the six most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these six bits.

[0553] The first sequence processing module can also query the corresponding relationship shown in Table 12 based on the first type of bit segments in multiple subsequences in each initial bit sequence from initial bit sequence 3 to initial bit sequence 6 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the seven most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these seven bits.

[0554] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (expressed as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (expressed as [1:4]).

[0555] The above intermediate bit sequence and In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0556] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0557] The first sequence processing module processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 20. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0558] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 17.26%.

[0559] Example 5: As shown in FIG17 , the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128.

[0560] The meanings of the various symbols in Figure 17 can refer to the meanings of the various symbols in Figure 13, and this application will not elaborate on them here.

[0561] The bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r ≥ 1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s ≥ 1; the numbers of bits in the first to the twelfth bit subsequences in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; and the numbers of bits in intermediate bit sequences obtained from the first to the sixth initial bit sequences in the six initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0562] The first sequence processing module can query the corresponding relationship shown in Table 4 based on the first type of bit segments in multiple subsequences in each initial bit sequence from initial bit sequence 1 to initial bit sequence 6, and obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the three most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these three bits.

[0563] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (expressed as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]).

[0564] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 9th bit to the 10th bit from left to right in the bit subsequence (expressed as [9:10]), and the third type of bit segment includes the 1st bit to the 8th bit from left to right in the bit subsequence (expressed as [1:8]).

[0565] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 7th bit to the 9th bit from left to right in the intermediate bit sequence (expressed as [7:9]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (expressed as [1:6]).

[0566] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 9th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in the intermediate bit sequence (expressed as [1:8]).

[0567] The first sequence processing module processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 22 below. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0568] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 36.43%.

[0569] Table 22

[0570] Example 6: As shown in FIG18 , the number of bits in the to-be-processed bit sequence is 106, and the number of bits in the bit sequence obtained after merging is 128.

[0571] The meanings of the various symbols in Figure 18 can refer to the meanings of the various symbols in Figure 13, and this application will not elaborate on them here.

[0572] Referring to FIG. 18 , the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, where r ≥ 1. In the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence. In the six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, where s ≥ 1. The number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, respectively. The number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively.

[0573] The first sequence processing module can query the corresponding relationship shown in Table 4 based on the first type of bit segments in multiple subsequences in the initial bit sequence 1 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the three most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these three bits.

[0574] The first sequence processing module can also query the corresponding relationship shown in Table 6 based on the first type of bit segments in multiple subsequences in each initial bit sequence from initial bit sequence 2 to initial bit sequence 6 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the four most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these four bits.

[0575] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (expressed as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]).

[0576] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]).

[0577] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 7th bit to the 9th bit from left to right in the intermediate bit sequence (expressed as [7:9]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (expressed as [1:6]).

[0578] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0579] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 22 below. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0580] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 30.63%.

[0581] Example 7: As shown in FIG19 , the number of bits in the to-be-processed bit sequence is 73, and the number of bits in the bit sequence obtained after merging is 128.

[0582] The meaning of each symbol in Figure 19 can refer to the meaning of each symbol in Figure 13, and this application will not elaborate on it here.

[0583] Referring to Figure 19, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; and the number of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences is 9, 11, 11, 11, 11, 11, respectively.

[0584] The first sequence processing module can query the corresponding relationship shown in Table 14 based on the first type of bit segments in multiple subsequences in the initial bit sequence 1 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence 1. Specifically, in each bit subsequence of the initial bit sequence 1, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In some intermediate bit sequences, the second type of bit segment includes the four most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these four bits. In another part of the intermediate bit sequence, the second type of bit segment includes the five most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these five bits.

[0585] The first sequence processing module can also query the corresponding relationship shown in Table 12 based on the first type of bit segments in multiple subsequences in each initial bit sequence from initial bit sequence 2 to initial bit sequence 6 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first type of bit segment includes the two most significant bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence other than these two bits. In each intermediate bit sequence, the second type of bit segment includes the seven most significant bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence other than these seven bits.

[0586] For example, the above bit subsequence In the bit sequence, the first type of bit segment includes the 6th bit to the 7th bit from left to right in the bit subsequence (expressed as [6:7]), and the third type of bit segment includes the 1st bit to the 5th bit from left to right in the bit subsequence (expressed as [1:5]).

[0587] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (expressed as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (expressed as [1:4]).

[0588] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 6th bit to the 9th bit from left to right in the intermediate bit sequence (expressed as [6:9]), and the fourth type of bit segment includes the 1st bit to the 5th bit from left to right in the intermediate bit sequence (expressed as [1:5]).

[0589] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0590] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 22. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 21.

[0591] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 17.66%.

[0592] Example 8: As shown in FIG20 , the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the bit sequence obtained after merging is 128.

[0593] The meanings of the various symbols in Figure 20 can refer to the meanings of the various symbols in Figure 13, and this application will not elaborate on them here.

[0594] Please refer to Figure 20. The bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; in the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the 6 initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s≥1; the number of bits in the 1st to 12th bit subsequences in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences obtained from the 1st to 6th initial bit sequences in the 6 initial bit sequences are 9, 11, 11, 11, 11, and 11, respectively.

[0595] The first sequence processing module can query the corresponding relationship shown in Table 8 based on the first type of bit segments in multiple subsequences in the initial bit sequence 1 to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence. Among them, in each bit subsequence of the initial bit sequence, the first t...

Claims

1. A sequence processing method, characterized in that: The method comprises: According to an initial bit sequence, a plurality of intermediate bit sequences are obtained; the initial bit sequence includes a plurality of bit subsequences, and at least one of the plurality of intermediate bit sequences is related to at least two of the plurality of bit subsequences; Performing distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences corresponding to the multiple intermediate bit sequences one by one; The target bit sequence obtained by merging.

2. The method according to claim 1, characterized in that Each of the plurality of intermediate bit sequences is associated with all of the bit subsequences of the plurality of bit subsequences.

3. The method according to claim 1 or 2, characterized in that: The bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; The at least two bit subsequences include: a first bit subsequence and a second bit subsequence, wherein the value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; The at least one intermediate bit sequence comprises: a first intermediate bit sequence and a second intermediate bit sequence, wherein the value of the second type of bit segment in the first intermediate bit sequence is a third value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth value; The method satisfies at least one of the following conditions: The absolute value of the difference between the first value and the second value is smaller than the absolute value of the difference between the third value and the fourth value; The third value is greater than the first value and the second value; The fourth value is smaller than the first value and the second value.

4. The method according to any one of claim 3, characterized in that: The method satisfies at least one of the following conditions: The first type of bit segment includes one bit or two bits, and the second type of bit segment includes at least three bits; The multiple bit subsequences are two of the bit subsequences, and the multiple intermediate bit sequences are two of the intermediate bit sequences.

5. The method according to any one of claims 1 to 4, characterized in that: The bit subsequence includes a first type of bit segment, the intermediate bit sequence includes a second type of bit segment, and the second type of bit segment includes the most significant bit in the intermediate bit sequence; There is a one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups, wherein the first bit sequence includes: the first type of bit segments in the multiple bit subsequences, and the bit sequence group includes the second type of bit segments in the multiple intermediate bit sequences.

6. The method according to claim 5, characterized in that The value of at least one second-type bit segment in at least one bit sequence group is greater than the value of each first-type bit segment in the plurality of first bit sequences.

7. The method according to claim 6, characterized in that The bit sequence group includes two second-type bit segments, and the one-to-one correspondence between the multiple first bit sequences and the multiple bit sequence groups includes: The correspondence between the first bit sequence (0, 0, 0, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0); The correspondence between the first bit sequence (0, 0, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0); The correspondence between the first bit sequence (0, 0, 1, 0), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0); The correspondence between the first bit sequence (0, 0, 1, 1), a second-type bit segment whose lowest three bits are (0, 0, 0), and another second-type bit segment whose lowest three bits are (1, 1, 0); The correspondence between the first bit sequence (0, 1, 0, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0); The correspondence between the first bit sequence (0, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 1); The correspondence between a first bit sequence (0, 1, 1, 0), a second-category bit segment whose lowest three bits are (0, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0); The correspondence between a first bit sequence (0, 1, 1, 1), a second-category bit segment whose lowest three bits are (0, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 1); The correspondence between the first bit sequence (1, 0, 0, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0); The correspondence between the first bit sequence (1, 0, 0, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (0, 1, 0); The correspondence between the first bit sequence (1, 0, 1, 0), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0); A correspondence between a first bit sequence (1, 0, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 0), and another second-category bit segment whose lowest three bits are (1, 1, 0); The correspondence between the first bit sequence (1, 1, 0, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (0, 0, 0); The correspondence between a first bit sequence (1, 1, 0, 1), a second-category bit segment whose lowest three bits are (0, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0); A correspondence between a first bit sequence (1, 1, 1, 0), a second-category bit segment whose lowest three bits are (1, 1, 0), and another second-category bit segment whose lowest three bits are (1, 0, 0); The correspondence between a first bit sequence (1, 1, 1, 1), a second-category bit segment whose lowest three bits are (1, 0, 1), and another second-category bit segment whose lowest three bits are (0, 0, 0); The bits in the bit sequence are arranged from left to right in the order of low to high bit positions.

8. The method according to any one of claims 3 to 7, characterized in that: The bit subsequence further includes a third type of bit segment in addition to the first type of bit segment; the intermediate bit sequence further includes a fourth type of bit segment in addition to the second type of bit segment; The fourth type of bit segments in the multiple intermediate bit sequences include: bits in the third type of bit segments in the multiple bit subsequences.

9. The method according to claim 8, characterized in that The multiple intermediate bit sequences correspond one-to-one to the multiple bit subsequences, and the fourth type of bit segment in the intermediate bit sequence includes: the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

10. The method according to any one of claims 1 to 9, characterized in that: The sum of the numbers of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence.

11. The method according to any one of claims 1 to 10, characterized in that: The method further comprises: The multiple bit subsequences in the initial bit sequence are divided from the bit sequence to be processed.

12. The method according to any one of claims 1 to 11, characterized in that: The method meets any of the following conditions: The number of bits in the bit subsequence is 6, and the number of bits in the intermediate bit sequence is 9, 10 or 11; The number of bits in the bit subsequence is 7, and the number of bits in the intermediate bit sequence is 9 or 10; The number of bits in the bit subsequence is 8, and the number of bits in the intermediate bit sequence is 9, 10 or 11; The number of bits in the bit subsequence is 9, and the number of bits in the intermediate bit sequence is 10 or 11; The number of bits in the bit subsequence is 10, and the number of bits in the intermediate bit sequence is 11.

13. The method according to any one of claims 1 to 12, characterized in that: The method further comprises: Dividing the bit sequence to be processed to obtain a plurality of the initial bit sequences; The method meets any of the following conditions: The number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; The number of bits in the bit sequence to be processed is 106, and the number of bits in the bit sequence obtained after merging is 128; The number of bits in the bit sequence to be processed is 73, and the number of bits in the bit sequence obtained after merging is 128; The number of bits in the bit sequence to be processed is 72, and the number of bits in the bit sequence obtained after merging is 128; The number of bits in the to-be-processed bit sequence is 58, and the number of bits in the bit sequence obtained after merging is 64.

14. The method according to claim 13, characterized in that The number of bits in the bit sequence obtained after merging is 128, and the bit sequence to be processed is divided into 12 bit subsequences; The number of bits in the bit sequence to be processed is 116, and the number of bits in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10 and 10 respectively; the number of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained according to two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained according to two bit subsequences with a bit number of 10; Alternatively, the number of bits in the bit sequence to be processed is 106, and the number of bits of the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, 9 and 9 respectively; the number of bits of the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 are obtained according to two bit subsequences with a number of 8 bits; in a part of the bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained according to two bit subsequences with a number of 9 bits; in another part of the bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained according to two bit subsequences with a number of 9 bits; Alternatively, the number of bits in the to-be-processed bit sequence is 73, and the number of bits in the 12 bit subsequences is 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, and 6 respectively; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained according to two bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained according to two bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained according to one bit subsequence with 6 bits and one bit subsequence with 7 bits; Alternatively, the number of bits in the bit sequence to be processed is 72; the number of bits of the 12 bit subsequences is 6; the number of bits of the 12 intermediate bit sequences is respectively: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained according to two bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained according to two bit subsequences with 6 bits; Alternatively, the number of bits in the bit sequence to be processed is 116, and the number of bits in the 12 bit subsequences are 8, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 respectively; the number of bits in the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 9 are obtained according to two bit subsequences with a bit number of 8; two intermediate bit sequences with a bit number of 11 are obtained according to two bit subsequences with a bit number of 10; Alternatively, the number of bits in the bit sequence to be processed is 106, and the number of bits of the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9 respectively; the number of bits of the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 9 are obtained according to two bit subsequences with a bit number of 8; two intermediate bit sequences with a bit number of 11 are obtained according to two bit subsequences with a bit number of 9; Alternatively, the number of bits in the bit sequence to be processed is 73, and the number of bits of the 12 bit subsequences are 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, respectively; the number of bits of the intermediate bit sequences are 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained according to two bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained according to one bit subsequence with 6 bits and one bit subsequence with 7 bits; Alternatively, the number of bits in the bit sequence to be processed is 72, the number of bits in the 12 bit subsequences is 6; the number of bits in the intermediate bit sequences is 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained according to two bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, two intermediate bit sequences with 9 bits are obtained according to two bit subsequences with 6 bits; In the bit subsequence with a special number of 6, two intermediate bit sequences with a number of 11 bits are obtained according to two bit subsequences with a number of 6 bits; Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 8 bits, two intermediate bit sequences with 10 bits are obtained according to two bit subsequences with 8 bits; in another part of the bit subsequences with 8 bits, two intermediate bit sequences with 11 bits are obtained according to two bit subsequences with 6 bits; Alternatively, the number of bits in the bit sequence to be processed is 96, and the number of bits in the 12 bit subsequences is 8; the number of bits in the intermediate bit sequences are: 9, 9, 11, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with a bit number of 8, two intermediate bit sequences with a bit number of 9 are obtained according to two bit subsequences with a bit number of 8; in another part of the bit subsequences with a bit number of 8, two intermediate bit sequences with a bit number of 11 are obtained according to two bit subsequences with a bit number of 8.

15. The method according to claim 13, characterized in that The number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; The number of bits of the six initial bit sequences into which the bit sequence to be processed is divided are 18, 18, 20, 20, 20 and 20 respectively; The number of bits in the intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; among them, two intermediate bit sequences with a bit number of 10 are obtained based on an initial bit sequence with a bit number of 18; and two intermediate bit sequences with a bit number of 11 are obtained based on an initial bit sequence with a bit number of 20.

16. The method according to claim 13, characterized in that The number of bits in the bit sequence to be processed is 116, and the number of bits in the bit sequence obtained after merging is 128; The to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits of the 12 bit subsequences is 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11 respectively; Four intermediate bit sequences with a number of 10 bits are obtained according to four bit subsequences with a number of 9 bits, and four intermediate bit sequences with a number of 11 bits are obtained according to four bit subsequences with a number of 10 bits.

17. The method according to claim 13, characterized in that The number of bits in the bit sequence to be processed is 58, and the number of bits in the bit sequence obtained after merging is 64; The bit sequence to be processed is divided into 6 bit subsequences; the number of bits of the 6 bit subsequences is 9, 9, 10, 10, 10 and 10 respectively; the number of bits of the intermediate bit sequence is 10, 10, 11, 11, 11, 11 respectively; Two intermediate bit sequences with a bit number of 10 are obtained according to two bit subsequences with a bit number of 9, and two intermediate bit sequences with a bit number of 11 are obtained according to two bit subsequences with a bit number of 10.

18. The method according to any one of claims 1 to 17, characterized in that: The number of bits in the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits; 1<t=u; Or, 1<t<u, and any bit from the t+1th bit to the uth bit of the plurality of intermediate bit sequences is the same; Performing distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences corresponding to the multiple intermediate bit sequences one by one, including: When the t-th bit of the intermediate bit sequence is a target class bit, according to a one-to-one correspondence between a plurality of index bit sequences and a plurality of result bit sequences, a first result bit sequence corresponding to a first index bit sequence in the plurality of index bit sequences is used as a target bit sequence corresponding to the intermediate bit sequence; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence; the target class bit is a 0 bit or a 1 bit; When the t-th bit is not the target class bit, the valid bit segment is inverted; the inversion process is used to update the 0 bit to 1 bit, and update the 1 bit to 0 bit; According to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, the second one of the multiple index bit sequences is obtained. a second result bit sequence corresponding to the index bit sequence; the second index bit sequence comprising: the valid bit segment after the inversion process; The second result bit sequence is subjected to the inversion processing to obtain a target bit sequence corresponding to the intermediate bit sequence.

19. A sequence processing method, characterized in that: The method comprises: Splitting a plurality of target bit sequences from a bit sequence; Performing an inverse process of the distribution matching process on the multiple target bit sequences to obtain a plurality of intermediate bit sequences corresponding to the multiple target bit sequences one by one; An initial bit sequence is obtained according to the multiple intermediate bit sequences; the initial bit sequence includes multiple bit subsequences, and each intermediate bit sequence in at least two intermediate bit sequences in the multiple intermediate bit sequences is related to at least two bit subsequences in the multiple bit subsequences.

20. A sequence processing device, characterized in that: The sequence processing device comprises: A first processing module is configured to obtain a plurality of intermediate bit sequences according to an initial bit sequence; the initial bit sequence includes a plurality of bit subsequences, at least one of the plurality of intermediate bit sequences is correlated with at least two of the plurality of bit subsequences; A second processing module is used to perform distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences corresponding to the multiple intermediate bit sequences one by one; A merging module is used to merge the obtained target bit sequence.

21. A sequence processing device, characterized in that: The sequence processing device comprises: A splitting module, used for splitting a plurality of target bit sequences from a bit sequence; A third processing module is used to perform an inverse process of the distribution matching process on the multiple target bit sequences to obtain a plurality of intermediate bit sequences corresponding to the multiple target bit sequences one by one; A fourth processing module is used to obtain an initial bit sequence according to the multiple intermediate bit sequences; the initial bit sequence includes multiple bit subsequences, and each intermediate bit sequence in at least two intermediate bit sequences in the multiple intermediate bit sequences is related to at least two bit subsequences in the multiple bit subsequences.

22. A chip, characterized in that: The chip includes a programmable logic circuit and / or program instructions, and when the chip is running, it is used to implement the sequence processing method as described in any one of claims 1 to 19.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the sequence processing method according to any one of claims 1 to 19.

24. A sequence processing device, characterized in that: The communication device includes: a processor and a memory, wherein the memory stores a program, and the processor is used to execute the program stored in the memory to implement the sequence processing method described in any one of claims 1 to 18.

25. A sequence processing device, characterized in that: The communication device includes: a processor and a memory, wherein the memory stores a program, and the processor is used to execute the program stored in the memory to implement the sequence processing method described in claim 19.

26. A communication system, characterized in that: include: Sending node and receiving node; The sending node includes the sequence processing device according to claim 20, and the receiving node includes the sequence processing device according to claim 21; Alternatively, the sending node includes the sequence processing device described in claim 24, and the receiving node includes the sequence processing device described in claim 25.

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