Display substrate and manufacturing method therefor, and display motherboard

Abstract

Provided in the present disclosure are a display substrate and a manufacturing method therefor, and a display motherboard. The display substrate comprises a central area and an edge area located on the periphery of the central area, wherein the central area comprises a plurality of panel units which are distributed in an array. The display substrate comprises: a base substrate; a panel circuit, which is located on the base substrate, and comprises at least one of a touch-control circuit and a display circuit; and a test circuit, wherein the panel circuit is electrically connected to the test circuit, and the orthographic projection of the panel circuit on the base substrate and the orthographic projection of the test circuit on the base substrate are both located in the central area, such that a gap is reserved between each of the panel circuit and the test circuit and the edge of the base substrate. The display substrate and the manufacturing method therefor, and the display motherboard provided in the embodiments of the present disclosure can reduce electrostatic damage, thereby improving an electrostatic protection effect.

Description

Display substrate and manufacturing method thereof, and display motherboard

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No.: 202311086624.5 filed in China on August 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display motherboard. Background Art

[0004] When display screens are produced on the production line, static electricity burns the internal circuits, resulting in a large number of NG (unqualified) products being detected and causing great losses.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, and a display motherboard, which can reduce electrostatic damage and improve electrostatic protection effects.

[0007] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0008] According to a first aspect of the present disclosure, there is provided a display substrate, comprising a middle region and an edge region located outside the middle region, wherein the middle region comprises a plurality of panel units distributed in an array; the display substrate comprises:

[0009] substrate;

[0010] a panel circuit, the panel circuit being located on the base substrate, the panel circuit including at least one of a touch circuit and a display circuit; and

[0011] The panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the substrate are both located in the middle area, so that a distance is maintained between the panel circuit and the test circuit and the edge of the substrate.

[0012] Exemplarily, the test circuit includes multiple first test lines and multiple second test lines, and the multiple first test lines and the multiple second test lines are cross-connected to each other to form a mesh circuit structure. The first test lines are electrically connected to the panel circuit for applying electrical test signals to the panel circuit.

[0013] Exemplarily, the test traces; the plurality of second test traces include a third edge test trace and a fourth edge test trace that are arranged closest to the edge area; wherein, each of the first test traces has its two opposite ends along its own extension direction respectively connected to the third edge test trace and the fourth edge test trace, and each of the second test traces has its two opposite ends along its own extension direction respectively connected to the first edge test trace and the second edge test trace.

[0014] Exemplarily, the first test line and the second test line intersect each other to define a plurality of sub-areas, and each sub-area includes at least two panel units.

[0015] Exemplarily, the display substrate further includes:

[0016] The peripheral circuit is arranged in the edge area around the middle area, and any one of the panel circuit and the test circuit is separated from the peripheral circuit to be disconnected from each other, and the routing of the peripheral circuit is led out to the edge of the substrate.

[0017] Exemplarily, the peripheral circuit includes:

[0018] a closed loop disposed around the middle region; and

[0019] At least one lead is connected to the closed loop and extends from the closed loop to an edge of the base substrate.

[0020] Exemplarily, the peripheral circuit also includes: multiple electrostatic release points, a gap is maintained between the electrostatic release points and the closed loop, the gap is configured to be broken down by static electricity, and the multiple electrostatic release points are distributed in sequence along the routing direction of the closed loop, and the orthographic projection on the substrate is located between the orthographic projection of the closed loop on the substrate and the middle area.

[0021] Exemplarily, the display substrate further includes an alignment mark pattern distributed in the edge region; the orthographic projection of the electrostatic discharge point on the base substrate and the orthographic projection of the alignment mark pattern on the base substrate are separated from each other and disconnected from each other.

[0022] Exemplarily, there are a plurality of leads, and the plurality of leads are sequentially spaced apart along the routing direction of the closed loop, and the orthographic projections of the plurality of leads on the substrate are located at the periphery of the closed loop.

[0023] Exemplarily, the test circuit includes multiple first test lines and multiple second test lines, and the multiple first test lines and the multiple second test lines are cross-connected to each other; the multiple leads include multiple first leads and / or multiple second leads; wherein, the first leads are parallel to and staggered with the extension direction of the first test lines, and the second leads are parallel to and staggered with the extension direction of the second test lines.

[0024] Exemplarily, at least one of the test circuit and the panel circuit includes a metal trace pattern, and the metal trace pattern is provided on the same layer and with the same material as the peripheral circuit.

[0025] According to the second aspect of the present disclosure, an embodiment of the present disclosure provides a display motherboard, comprising a plurality of substrate units, with a cutting line area between adjacent substrate units, and the substrate units are constructed to form the display substrate described above after being cut along the cutting line area.

[0026] According to a second aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a display substrate, wherein the display substrate includes a middle region and an edge region located outside the middle region, wherein the middle region includes a plurality of panel units distributed in an array; the method includes the following steps:

[0027] providing a substrate;

[0028] forming a pattern of the test circuit on the base substrate;

[0029] A pattern of the panel circuit is formed on the base substrate, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the base substrate are both located in the middle area, so that a distance is maintained between the panel circuit and the test circuit and the edge of the base substrate.

[0030] Exemplarily, the method further includes:

[0031] A pattern of peripheral circuits is formed on the base substrate, wherein the peripheral circuits are arranged in the edge area around the middle area, and any one of the panel circuit and the test circuit is separated from the peripheral circuits to be disconnected from each other.

[0032] Exemplarily, at least one of the test circuit and the panel circuit includes a metal wiring pattern, and the pattern of the peripheral circuit and the metal wiring pattern are formed by a same patterning process.

[0033] The beneficial effects brought about by the embodiments of the present disclosure are as follows:

[0034] In the display substrate and its manufacturing method, and the display motherboard provided by the embodiments of the present disclosure, the panel circuit and the test circuit in the display substrate are both located in the middle area of ​​the base substrate, and a distance is maintained between the panel circuit and the test circuit and the edge of the base substrate. In this way, static electricity can be prevented from being introduced into the panel circuit and the test circuit from the edge of the base substrate, thereby reducing the damage to the panel circuit and the test circuit caused by static electricity and improving the electrostatic protection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0036] FIG2 is a schematic structural diagram of a display motherboard provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] Before describing in detail the display substrate and its manufacturing method, and the display motherboard provided by the embodiments of the present disclosure, it is necessary to describe the related technologies as follows:

[0040] In the related art, in the display panel manufacturing process, in the array production process, the product is a large glass substrate with touch circuits and / or display circuits formed on it, namely a Q-Panel. Each Q-Panel contains several small single cells (panel units). In order to prevent defective panel units in the Q-Panel from flowing into the next process, each Q-Panel needs to be inspected. Therefore, a test circuit for applying electrical test signals to the panel circuits is also arranged on the Q-Panel.

[0041] Display panels, such as touch screens (TSPs), are often inspected and tested as defective (NG) products during production, resulting in significant losses. The inventors of this disclosure, through microscopic inspection of the internal circuitry of the display, discovered that electrostatic discharge (ESD) burns are common in vulnerable locations within the display, such as bonding pins (for bonding) and the bridges between the Tx (transmitting) and Rx (receiving) touch traces within the touchscreen.

[0042] Q-Panel is cut from a large motherboard, and each Q-Panel includes multiple panel units. Each Q-Panel can be electrically tested before being cut into a single panel unit. The inventors of the present disclosure have found through research that the reason for the above-mentioned electrostatic burn phenomenon is that when the motherboard is cut, the test circuit will be cut and disconnected at the cutting position between two adjacent Q-Panels. Therefore, the test circuit on the Q-Panel formed after cutting is led out to the edge of the substrate, that is, the internal panel circuit of the panel unit is led out to the edge of the substrate. In the subsequent production and manufacturing process, static electricity is introduced into the internal panel circuit of the panel unit through the edge of the substrate, causing the most vulnerable area of ​​the panel circuit inside the panel unit to be burned.

[0043] In order to solve the above problems, the embodiments of the present disclosure provide a display substrate (Q-Panel) and a manufacturing method thereof, as well as a display motherboard, which can improve the electrostatic protection effect of the product and reduce the circuit burn phenomenon caused by static electricity.

[0044] The embodiment of the present disclosure provides a display substrate, which can be formed by cutting a large display motherboard, and the display substrate can be cut into a plurality of single panels (single cells).

[0045] As shown in FIG1 , a display substrate 10 provided in an embodiment of the present disclosure includes a middle region S1 and an edge region S2 located outside the middle region S1 . The middle region S1 includes a plurality of panel units A distributed in an array. The display substrate 10 includes:

[0046] Base substrate 11;

[0047] a panel circuit (not shown in the figure), the panel circuit being located on the base substrate 11, the panel circuit including at least one of a touch circuit for realizing a touch function and a display circuit for realizing a display function; and

[0048] The test circuit 12, the panel circuit is electrically connected to the test circuit 12, and the orthographic projections of the panel circuit and the test circuit 12 on the base substrate 11 are both located in the middle area S1, so that a distance is maintained between the panel circuit and the test circuit 12 and the edge of the base substrate 11, and they are no longer led out to the edge of the base substrate 11.

[0049] In the above scheme, the display substrate 10 provided in the embodiment of the present disclosure is a Q-Panel, and its panel circuit refers to various internal wiring of the panel used to realize the panel function. For example, the panel circuit may include at least one of a touch circuit and a display circuit, the touch circuit is used to realize the touch function of the display panel, and the display circuit is used to realize the display function of the display panel. It should be understood that the figure is only a schematic diagram of the distribution position of the panel circuit, and does not represent the actual wiring of the panel circuit. The test circuit 12 can be used to apply electrical test signals to the panel circuit. Either the panel circuit or the test circuit 12 is constructed to be located in the middle area S1 of the base substrate 11, and to maintain a gap between it and the edge of the base substrate 11, and no longer lead to the edge of the base substrate 11. In this way, static electricity introduced from the edge of the base substrate 11 can be avoided from being introduced into the panel circuit and the test circuit 12, thereby reducing the damage of static electricity to the panel circuit and the test circuit 12, and improving the electrostatic protection effect.

[0050] It should be noted that touch screens can be divided into four categories based on their operating principles and the medium used to transmit information: resistive, capacitive, infrared, and surface acoustic wave. Resistive and capacitive touch screens are the most widely used, with projected capacitive being the most widely used due to its ability to achieve multi-touch applications. However, their main drawbacks are high cost and relatively heavy weight. Low cost and thinness are becoming the new trend in the touch screen industry. To achieve thinner and lighter touch panels, research into integrating touch panels with liquid crystal display panels is gaining popularity. In-cell touch solutions, where the touch panel is embedded within the LCD panel, are attracting widespread attention.

[0051] There are three types of in-cell touch technologies: resistive, capacitive, and optical. Among them, the capacitive solution includes self-capacitive touch and mutual capacitance touch. The self-capacitive touch method is to divide the transparent conductive layer used as the common electrode (Vcom) on the array substrate into several blocks as touch electrodes, and use the touch signal line (Tx touch trace) to connect to the touch electrode through a via at one end, and the other end to the driver integrated circuit. When the finger touches the array substrate, it will cause the capacitance value of the touch electrode at the corresponding position to fluctuate. The driver integrated circuit can determine the position of the touch point by detecting the fluctuation of the capacitance value, thereby realizing the touch function.

[0052] FIC (Full In Cell Touch) touchscreens integrate both touch electrodes and touch signal lines within an array substrate. This allows the touch electrodes and touch signal lines used to implement touch functions to be integrated within the LCD panel when the array substrate is used to manufacture a liquid crystal display panel, creating an embedded touch structure. Full In Cell Touch LCD touchscreen panels integrate touch and display functions, enabling seamless, one-stop production and offering advantages such as integration, lightweight design, low cost, low power consumption, high image quality, and the ability to implement multiple touch modes (i.e., Multi-Touch).

[0053] In some embodiments of the present disclosure, a display substrate 10 includes a plurality of panel units A. A touch circuit may include a plurality of touch units A' corresponding to the plurality of panel units A. Each touch unit A' is configured to implement a touch function for its corresponding display panel. The touch circuit may include, but is not limited to, circuits that utilize self-capacitive touch or mutual-capacitive touch to implement the touch function.

[0054] In some exemplary embodiments of the present disclosure, as shown in the figure, the test circuit 12 includes a plurality of first test traces 121 and a plurality of second test traces 122. The plurality of first test traces 121 and the plurality of second test traces 122 are cross-connected to form a mesh circuit structure, wherein the first test traces 121 are electrically connected to the panel circuits for applying electrical test signals to the panel circuits. As shown in the figure, the orthographic projections of the first test traces 121 and the second test traces 122 on the substrate 11 can be located between adjacent panel units A.

[0055] Taking the panel circuit including the touch circuit as an example, the touch lines of the touch circuit (for example, the Tx touch line and the Rx touch line) can all be connected to the first test line 121 to apply an electrical test signal to the touch circuit through the first test line 121, and the second test line 122 is used to connect multiple first test lines 121.

[0056] Taking FIG. 1 as an example, the sides of the display substrate 10 can be divided into a first side 10A, a third side 10B, a second side 10C, and a fourth side 10D surrounding the middle region S1. The first side 10A is opposite the second side 10C, and the third side 10B is opposite the fourth side 10D. In some exemplary embodiments, as shown in the figure, the routing direction of the first test trace 121 is consistent with the routing direction of the first side 10A, and the routing direction of the second test trace 122 is consistent with the routing direction of the third side 10B. Of the two test traces closest to the edge region S2 among the multiple first test traces 121, one is closest to the first side 10A and is recorded as the first edge test trace 121A, and the other is closest to the second side 10C and is recorded as the second edge test trace 121B. Among the two test lines closest to the edge area S2 among the plurality of second test lines 122 , one line is closest to the third side 10B and is recorded as the third edge test line 122A, and the other line is closest to the fourth side 10D and is recorded as the fourth edge test line 122B.

[0057] As shown in Figure 1 , each first test trace 121 has two opposite ends along its own extension direction connected to the third edge test trace 122A and the fourth edge test trace 122B, respectively. Each second test trace 122 has two opposite ends along its own extension direction connected to the first edge test trace 121A and the second edge test trace 121B, respectively. In other words, each first test trace 121 has its end connected to the second test trace 122 and does not extend outside the second test trace 122. Similarly, each second test trace 122 has its end connected to the first test trace 121 and does not extend outside the first test trace 121.

[0058] In this way, the four test lines located closest to the edge area S2, namely the first edge test line 121A, the second edge test line 121B, the third edge test line 122A and the fourth edge test line 122B, are connected to form a closed loop, and the entire grid-shaped circuit is a closed-loop grid circuit, which can further prevent static electricity from being introduced into the panel circuit.

[0059] In some exemplary embodiments of the present disclosure, as shown in Figure 1, the first test trace 121 and the second test trace 122 intersect with each other to define a plurality of sub-areas, each sub-area including at least two panel units A. In this way, each display substrate 10 is divided into a plurality of panel unit groups (Group), each panel unit group corresponds to a sub-area, and the touch circuits of each panel unit A in each panel unit group can be connected to the same test trace. Taking the figure as an example, a display substrate 10 includes 44 panel unit groups, and each panel unit group consists of 8 panel units A. Of course, it can be understood that the above is only an example. In actual applications, the distribution number of panel unit groups and the number of panel units A in each panel unit group are not limited to this.

[0060] In some exemplary embodiments of the present disclosure, as shown in Figure 1, the display substrate 10 further includes: a peripheral circuit 13, which is arranged in the edge area S2 around the middle area S1, and any one of the panel circuit and the test circuit 12 is separated from the peripheral circuit 13 to be disconnected from each other, and the routing of the peripheral circuit 13 is led out to the edge of the base substrate 11.

[0061] By adopting the above solution, the peripheral circuit 13 is set in the edge area S2 of the display substrate 10, that is, the peripheral circuit 13 is set around the panel circuit and the test circuit 12, and the routing of the peripheral circuit 13 can be led to the edge of the base substrate 11. In this way, the static electricity introduced into the display substrate 10 can be guided to the peripheral circuit 13 and suppressed or conducted away by the peripheral circuit 13 to protect the panel circuit in the panel unit A.

[0062] In some exemplary embodiments of the present disclosure, as shown in FIG1 , the peripheral circuit 13 includes a closed loop 131 and at least one lead 132 . The closed loop 131 is arranged around the middle area S1 . The lead 132 is connected to the closed loop 131 and extends from the closed loop 131 to the edge of the base substrate 11 .

[0063] By adopting the above solution, a closed loop 131 is provided around the middle area S1 in the entire edge area S2, and the closed loop 131 can be led out to the edge of the base substrate 11 through the lead 132. In this way, the closed loop 131 can effectively prevent static electricity introduced into the display substrate 10 from entering the various circuits in the middle area S1.

[0064] In some exemplary embodiments of the present disclosure, as shown in FIG1 , the peripheral circuit 13 further includes: a plurality of electrostatic discharge points 133 , each maintaining a gap between the electrostatic discharge points 133 and the closed loop 131 , the gap being configured to be broken down by static electricity. The plurality of electrostatic discharge points 133 are sequentially spaced along the routing direction of the closed loop 131 , and their orthographic projections on the substrate 11 are located between the orthographic projection of the closed loop 131 on the substrate 11 and the intermediate region S1 . By adopting this solution, the provision of the electrostatic discharge points 133 further effectively discharges static electricity.

[0065] In some exemplary embodiments, as shown in FIG1 , the display substrate 10 further includes an alignment mark pattern 14 distributed in the edge area S2 ; the orthographic projection of the electrostatic release point 133 on the base substrate 11 and the orthographic projection of the alignment mark pattern 14 on the base substrate 11 are separated from each other to be disconnected from each other.

[0066] In the above solution, since the base substrate 11 needs to be aligned during the manufacturing process of the display substrate 10, an alignment mark pattern 14 is provided in the edge region S2 of the base substrate 11. The electrostatic discharge point 133 is positioned to avoid the alignment mark pattern 14. As shown in the figure, the electrostatic discharge point 133 is configured with a line width greater than the line width of the closed loop 131 to facilitate static discharge. For example, the electrostatic discharge point 133 can be configured as a conductive strip or conductive block structure.

[0067] In some exemplary embodiments, as shown in FIG1 , there are multiple leads 132 , and these leads 132 are sequentially spaced along the direction of the closed loop 131 , with their orthographic projections on the base substrate 11 positioned outside the closed loop 131 . This arrangement, with multiple leads 132 sequentially spaced along the direction of the closed loop 131 , effectively protects the display substrate 10 from excessive static electricity entering from all four sides. It will be appreciated that the specific location and number of the multiple leads 132 are not limited.

[0068] In addition, in some exemplary embodiments of the present disclosure, as shown in Figure 1, the multiple leads 132 include multiple first leads 132A and multiple second leads 132B; wherein, the first leads 132A are parallel to and staggered with the extension direction of the first test trace 121, and the second leads 132B are parallel to and staggered with the extension direction of the second test trace 122.

[0069] That is, as shown in the figure, the first lead 132A is parallel to the first test trace 121 and is not located on a straight line extending from the first test trace 121. The second lead 132B is parallel to the second test trace 122 and is not located on a straight line extending from the second test trace 122. This allows for a maximum spacing between the first lead 132A and the first test trace 121, and between the second lead 132B and the second test trace 122, compared to a solution where the first lead 132A is located on a straight line extending from the first test trace 121. This further prevents static electricity from flowing from the lead 132 to the test traces. For example, the spacing between the first lead 132A and the first test trace 121 is approximately 15 to 20 mm, and the spacing between the second lead 132B and the second test trace 122 is approximately 15 to 20 mm. This provides better static electricity protection.

[0070] Furthermore, in some exemplary embodiments of the present disclosure, to further facilitate electrostatic discharge, the peripheral circuit 13 may be made of a metal material. Exemplarily, at least one of the test circuit 12 and the panel circuit includes a metal trace pattern, which is formed on the same layer and made of the same material as the peripheral circuit 13. Using this approach, the test circuit 12 and the metal trace pattern can be formed simultaneously using the same patterning process, simplifying the process steps.

[0071] Specifically, for example, the wiring in the test circuit 12 is made of metal material, and the test wiring is a metal wiring pattern, and the peripheral wiring 13 is made of the same material and arranged on the same layer as the test circuit 12. Of course, it is understandable that when other patterns in the panel wiring arranged in the middle area S1 are made of metal material, the peripheral wiring 13 can also be made of the same material and arranged on the same layer as the film layer.

[0072] Furthermore, it should be noted that, as shown in Figures 1 and 2, the display substrate 10 provided in the embodiment of the present disclosure is formed by cutting a display motherboard 1, wherein the display motherboard 1 may include multiple substrate units 10'. A cutting line region is defined between adjacent substrate units 10'. By cutting the entire motherboard along the cutting line region, multiple substrate units 10' are obtained. One substrate unit 10' is a display substrate 10 provided in the embodiment of the present disclosure. In other words, each substrate unit 10' is constructed to have the same circuit structure as the display substrate 10.

[0073] In addition, as shown in FIG2 , an embodiment of the present disclosure further provides a display motherboard 1 comprising a plurality of substrate units 10′, with cutting lines defined between adjacent substrate units 10′. The substrate units 10′ are configured to be cut along the cutting lines to form the display substrate 10 provided in the embodiment of the present disclosure. Obviously, the display motherboard 1 provided in the embodiment of the present disclosure can also provide the beneficial effects of the display substrate 10 provided in the embodiment of the present disclosure, and this will not be further elaborated.

[0074] In addition, in some exemplary embodiments, as shown in FIG2 , the leads 132 between two adjacent substrate units 10 ′ may be connected as one, and the leads 132 may be arranged in the cutting line area. When the display motherboard 1 is cut, the leads 132 between two adjacent substrate units 10 ′ may be cut and separated.

[0075] In addition, the present disclosure also provides a method for manufacturing a display substrate 10, which is used to manufacture the display substrate 10 provided in the present disclosure. The display substrate 10 includes a middle region S1 and an edge region S2 located outside the middle region S1. The middle region S1 includes a plurality of panel units A distributed in an array. The method includes the following steps:

[0076] Step S01, providing a base substrate 11;

[0077] Step S02: forming a pattern of the test circuit 12 on the base substrate 11;

[0078] Step S03: forming a pattern of the panel circuit on the base substrate 11, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit 12, and the orthographic projections of the panel circuit and the test circuit 12 on the base substrate 11 are both located within the middle area S1, so that a distance is maintained between the panel circuit and the test circuit 12 and the edge of the base substrate 11.

[0079] In the above scheme, the display substrate 10 provided in the embodiment of the present disclosure is a Q-Panel, and its panel circuit refers to various internal wirings of the panel for realizing the functions of the panel. For example, the panel circuit may include at least one of a touch circuit and a display circuit. The touch circuit is used to realize the touch function of the display panel, and the display circuit is used to realize the display and other functions of the display panel. The test circuit 12 can be used to apply electrical test signals to the panel circuit. Any of the panel circuit and the test circuit 12 is constructed to be located in the middle area S1 of the base substrate 11, and to maintain a spacing between it and the edge of the base substrate 11, and no longer lead out to the edge of the base substrate 11. In this way, static electricity introduced from the edge of the base substrate 11 can be avoided from being introduced into the panel circuit and the test circuit 12, thereby reducing the damage of static electricity to the panel circuit and the test circuit 12, and improving the electrostatic protection effect.

[0080] Wherein, when the panel circuit includes a touch circuit, the touch circuit may include but is not limited to a self-capacitive touch circuit or a mutual-capacitive touch circuit.

[0081] In some exemplary embodiments, the method further comprises:

[0082] Step S04: forming a pattern of a peripheral circuit 13 on the base substrate 11, wherein the peripheral circuit 13 is arranged in the edge area S2 around the middle area S1, and any one of the panel circuit and the test circuit 12 is separated from the peripheral circuit 13 to be disconnected from each other.

[0083] By adopting the above solution, the peripheral circuit 13 is set in the edge area S2 of the display substrate 10, that is, the peripheral circuit 13 is set on the periphery of the closed grid-like circuit structure, and the routing of the peripheral circuit 13 can be led to the edge of the base substrate 11. In this way, static electricity introduced into the display substrate 10 can be guided to the peripheral circuit 13 and suppressed or guided away by the peripheral circuit 13 to protect the panel circuit in the panel unit A.

[0084] In some exemplary embodiments, in the method, at least one of the test circuit 12 and the panel circuit includes a metal trace pattern, and the pattern of the peripheral circuit 13 and the metal trace pattern are formed using the same patterning process, thereby simplifying the process steps.

[0085] In addition, it should be noted that in the above step S01, the base substrate 11 may be the base substrate of the display motherboard 1. In the above steps S02 and S03, after forming the test circuit 12 and the panel circuit on the base substrate 11, a display motherboard is obtained. The method may further include:

[0086] Step S04 : cutting the display motherboard 1 to obtain the display substrate 10 .

[0087] There are a few points to note:

[0088] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0089] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0090] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0091] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising a middle area and an edge area located outside the middle area, wherein the middle area comprises a plurality of panel units distributed in an array; characterized in that: The display substrate comprises: substrate substrate; A panel circuit, the panel circuit is located on the base substrate, and the panel circuit includes at least one of a touch circuit and a display circuit; and The panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the substrate are both located in the middle area, so that a distance is maintained between the panel circuit and the test circuit and the edge of the substrate.

2. The display substrate according to claim 1, characterized in that: The test circuit includes multiple first test lines and multiple second test lines, which are cross-connected to each other to form a mesh circuit structure. The first test lines are electrically connected to the panel circuit for applying electrical test signals to the panel circuit.

3. The display substrate according to claim 2, characterized in that: The multiple first test lines include a first edge test line and a second edge test line that are arranged closest to the edge area; the multiple second test lines include a third edge test line and a fourth edge test line that are arranged closest to the edge area; wherein, each of the first test lines has its two opposite ends along its own extension direction respectively connected to the third edge test line and the fourth edge test line, and each of the second test lines has its two opposite ends along its own extension direction respectively connected to the first edge test line and the second edge test line.

4. The display substrate according to claim 2, characterized in that: The first test line and the second test line cross each other to define a plurality of sub-areas, and each sub-area includes at least two of the panel units.

5. The display substrate according to claim 1, characterized in that: The display substrate further comprises: The peripheral circuit is arranged in the edge area around the middle area, and any one of the panel circuit and the test circuit is separated from the peripheral circuit to be disconnected from each other, and the routing of the peripheral circuit is led out to the edge of the substrate.

6. The display substrate according to claim 5, characterized in that: The peripheral circuit includes: a closed loop, the closed loop being disposed around the middle area; and At least one lead is connected to the closed loop and extends from the closed loop to the edge of the substrate.

7. The display substrate according to claim 6, characterized in that: The peripheral circuit also includes: A plurality of electrostatic release points are provided, wherein a gap is maintained between the electrostatic release point and the closed loop, wherein the gap is configured to be broken down by static electricity, wherein the plurality of electrostatic release points are distributed in sequence along the routing direction of the closed loop, and the orthographic projection of the electrostatic release point on the substrate is located between the orthographic projection of the closed loop on the substrate and the middle area.

8. The display substrate according to claim 7, characterized in that: The display substrate further includes an alignment mark pattern distributed in the edge region; the orthographic projection of the electrostatic discharge point on the base substrate and the orthographic projection of the alignment mark pattern on the base substrate are separated from each other to be disconnected from each other.

9. The display substrate according to claim 6, characterized in that: There are a plurality of leads, and the plurality of leads are sequentially spaced and distributed along the routing direction of the closed loop, and the orthographic projections of the plurality of leads on the base substrate are located at the periphery of the closed loop.

10. The display substrate according to claim 9, characterized in that: The test circuit includes multiple first test lines and multiple second test lines, and the multiple first test lines and the multiple second test lines are cross-connected to each other; the multiple leads include multiple first leads and / or multiple second leads; wherein, the first leads are parallel to and staggered in the extension direction of the first test lines, and the second leads are parallel to and staggered in the extension direction of the second test lines.

11. The display substrate according to claim 5, characterized in that: At least one of the test circuit and the panel circuit includes a metal routing pattern, and the metal routing pattern is provided in the same layer and with the same material as the peripheral circuit.

12. A display motherboard, characterized in that: The display device comprises a plurality of substrate units, wherein a cutting line area is formed between adjacent substrate units, and the substrate units are configured to form a display substrate as claimed in any one of claims 1 to 11 after being cut along the cutting line area.

13. A method for manufacturing a display substrate, wherein the display substrate comprises a middle area and an edge area located outside the middle area, wherein the middle area comprises a plurality of panel units distributed in an array; characterized in that: The method comprises the following steps: Providing a substrate; forming a pattern of a test circuit on the substrate; A pattern of a panel circuit is formed on the base substrate, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the base substrate are both located in the middle area, so that a spacing is maintained between the panel circuit and the test circuit and the edge of the base substrate.

14. The method according to claim 13, characterized in that The method further comprises: A pattern of peripheral circuits is formed on the base substrate, wherein the peripheral circuits are arranged in the edge area around the middle area, and any one of the panel circuits and the test circuits is separated from the peripheral circuits to be disconnected from each other.

15. The method according to claim 14, characterized in that At least one of the test circuit and the panel circuit includes a metal wiring pattern, and the pattern of the peripheral circuit and the metal wiring pattern are formed by a same patterning process.

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