Clock calibration circuit

Abstract

Provided in the embodiments of the present disclosure is a clock calibration circuit. The circuit comprises a first sampling circuit, and a second sampling circuit which is connected in series with the first sampling circuit. The first sampling circuit comprises: a phase locked loop (PLL); a first duty cycle calibrator (DCC), which is connected in series with the PLL; a first phase interpolator (PI), which is connected in series with the first DCC; a first clock tree, which is connected in series with the first PI; a first data serializer, which is connected in series with the first clock tree; a first transmit driver, which is connected in series with the first data serializer; a second data serializer, which is connected in series with the first DCC; and a second transmit driver, which is connected in series with the second data serializer, wherein the PLL is configured to output a clock signal, so as to drive the first data serializer to transmit, to the first transmit driver, data to be transmitted, and drive the second data serializer to transmit a forward clock signal to the second transmit driver; and the second transmit driver is configured to transmit the forward clock signal to a first receive driver of the second sampling circuit, so as to determine the forward clock signal as a sampling clock of the second sampling circuit.

Description

Clock calibration circuit

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on August 31, 2023, with application number 202311116565.1 and invention name “Clock Calibration Circuit,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of communications, and in particular, to a clock calibration circuit. Background Art

[0003] Prior art has seen widespread adoption of integrated packaging of multiple bare die in the semiconductor industry, including mainstream central processing units (CPUs) and general-purpose graphics processing units (GP-GPUs). The development of in-package chiplets is driven by a variety of factors. Currently, cross-die (unpackaged chip particles) or cross-package sampling clock calibration technologies in the chiplet (chiplet interconnect) field primarily include CDR (Clock and Data Recovery) technology, commonly used in serdes (serializer / deserializer) devices; and clock-forwarding technology, used in protocols like AIB and UCIe (Universal Chiplet Interconnect Express), which feeds the clock used to transmit data to the receiving side for sampling and receiving data.

[0004] Figure 1 shows a chiplet sampling diagram from the prior art. As shown in Figure 1, data clock layout and routing must be aligned on the backend. When DQS is sampled to the RX, it passes through the DLL (R90), causing a 90-degree phase shift from the DQS output to the RX FIFO clock input, as shown in Figure 1, right at the data center. The technical difficulty in implementing this solution lies in ensuring that the total DLL + clock tree delay equals T / 4. This technology is based on a 4GHz clock, meaning T / 4 = 62.5ps. For parallel port architectures driving multiple lanes, such as 40 to 64 lanes, the clock tree delay is typically 70 to 80ps at the best corner (the optimal range of process parameter variations) in 3nm or 5nm processes, and can reach over 120ps at the worst corner (the process corner that causes the greatest clock tree delay).

[0005] Figure 2 shows a conventional structure for generating a 90-degree phase shift on the transmitter side. As shown in Figure 2, the implementation method in Figure 2 involves aligning the data and clock on both the TX and RX sides. During operation, detection can generate a 90-degree phase shift on the transmitter side, aligning the sampling clock forwarded to the receiver side with the data center. The implementation in Figure 2 has the following drawbacks: the transmitter fwdclk (the transmitter clock signal) must copy the txclk (the transmitter clock) to drive the distributed clock tree of multiple lanes to ensure that the IO output txdat of the left circuit is aligned with the fwdclk (after the fwdclk is adjusted by 90 degrees, the fwdclk edge is aligned with the data center).

[0006] In the prior art clock calibration circuit, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes problems such as delay deviation in the circuit, and no effective solution has been proposed yet.

[0007] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology.

[0008] Summary of the Invention

[0009] The embodiments of the present disclosure provide a clock calibration circuit to at least solve the problem that, in the conventional clock calibration circuit, the clock calibration process of the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes delay deviation in the circuit.

[0010] According to one aspect of an embodiment of the present disclosure, a clock calibration circuit is provided, comprising: a first sampling circuit; a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit comprises: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmit driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC; and a second transmit driver connected in series with the second data serializer, wherein the PLL is configured to output a clock signal to drive the first data serializer to send data to be sent to the first transmit driver, and to drive the second data serializer to send a feedforward clock signal to the second transmit driver; and the second transmit driver is configured to send the feedforward clock signal to a first receive driver in the second sampling circuit to determine the feedforward clock signal as a sampling clock for the second sampling circuit.

[0011] In an exemplary embodiment, the second sampling circuit includes: a second receiving driver connected in series with the first transmitting driver, configured to receive the data to be transmitted sent by the first transmitting driver, and send the data to be transmitted to a first data deserializer connected in series with the small delay buffer through a small delay buffer connected in series with the second receiving driver.

[0012] In an exemplary embodiment, the second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer, respectively, and is configured to compensate for the intrinsic delay of the first DCC.

[0013] In an exemplary embodiment, the second sampling circuit includes: a second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree. The first receiving driver is configured to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI, and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock for the first data deserializer and the second data deserializer.

[0014] In an exemplary embodiment, the second sampling circuit includes a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer, respectively, and is configured to supplement the intrinsic delay of the second PI.

[0015] In an exemplary embodiment, the second sampling circuit includes: a third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is configured to be set to a fixed phase shift after training of multiple data links and a TRACK link is completed, and the multiple data links and the TRACK link respectively correspond to different transmit drivers.

[0016] In an exemplary embodiment, the first sampling circuit includes: a third PI connected in series with the first clock tree and the first data serializer, respectively, and configured to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links respectively correspond to different transmit drivers.

[0017] In an exemplary embodiment, the second sampling circuit includes: a first data checking module, connected in series with the first data deserializer and the second PI, respectively, and configured to adjust the delay value of the second PI during data link training; and / or a second data checking module, connected in series with the second data deserializer and the second PI, respectively, and configured to adjust the delay value of the second PI during TRACK link training.

[0018] In an exemplary embodiment, the second sampling circuit includes: a first delay-locked loop (DLL) connected in series with the second clock tree and the first data deserializer; and the second sampling circuit further includes: a second DLL connected in series with the second clock tree and the second data deserializer.

[0019] In an exemplary embodiment, the second sampling circuit includes: a third DLL, connected in series with the second DCC and the second PI, respectively, and configured to perform delay processing on multiple data links and TRACK links, wherein the multiple data links and the TRACK links correspond to different transmission drivers respectively.

[0020] According to the present disclosure, a clock calibration circuit includes: a first sampling circuit; a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit includes: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC; and a second transmission driver connected in series with the second data serializer, wherein the PLL is configured to output a clock signal to drive the first data serializer to send data to be transmitted to the first transmission driver. The second transmitting driver is configured to transmit the feedforward clock signal to the first receiving driver in the second sampling circuit, so as to determine the feedforward clock signal as the sampling clock of the second sampling circuit. This solves the problem that, in the clock calibration circuit of the prior art, the clock calibration process between the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes a time delay deviation in the circuit. As a result, the second sampling circuit on the receiving side can perform clock calibration according to the feedforward clock signal sent by the first sampling circuit, thereby avoiding the problem that, in the prior art, the clock calibration process between the first sampling circuit on the transmitting side and the second sampling circuit on the receiving side easily causes a time delay deviation in the circuit.

[0021] The present disclosure does not require adding a compensating delay device to the receiving data path to align the sampling clock, thereby solving the problem of signal deterioration caused by the compensating delay device in the data path under high-speed signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0023] FIG1 is a schematic diagram of chiplet sampling in the prior art;

[0024] FIG2 is a schematic diagram of a structure in which a 90-degree phase shift is generated on the transmitting side in the prior art;

[0025] FIG3 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure;

[0026] FIG4 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure;

[0027] FIG5 is a PI logic block diagram according to an embodiment of the present disclosure;

[0028] FIG6 is a diagram of an optional calibration process according to an embodiment of the present disclosure;

[0029] FIG7 is a schematic diagram of eye diagram alignment according to an embodiment of the present disclosure;

[0030] FIG8 is a diagram illustrating alignment of TRACK data boundaries and clock edges according to an embodiment of the present disclosure;

[0031] FIG9 is a diagram showing a sampling clock drifting to the right according to an embodiment of the present disclosure;

[0032] FIG10 is a circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure;

[0033] FIG. 11 is another circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] FIG3 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure. As shown in FIG3 , the clock calibration circuit includes:

[0037] a first sampling circuit; and a second sampling circuit connected in series with the first sampling circuit; wherein,

[0038] The first sampling circuit includes: a phase-locked loop (PLL) 30; a first duty cycle calibrator (DCC) 31 connected in series with the PLL; a first phase interpolator (PI) 32 connected in series with the first DCC 31; a first clock tree 33 connected in series with the first PI 32; a first data serializer 34 connected in series with the first clock tree 33; and a first transmit driver 35 connected in series with the first data serializer 34.

[0039] a second data serializer 36 connected in series with the first DCC 31, and a second transmit driver 37 connected in series with the second data serializer 36, wherein the PLL 30 is configured to output a clock signal to drive the first data serializer 34 to send the to-be-transmitted data to the first transmit driver 35, and to drive the second data serializer 36 to send a feedforward clock signal to the second transmit driver 37;

[0040] The second transmitting driver 37 is configured to transmit the feedforward clock signal to the first receiving driver 38 in the second sampling circuit, so as to determine the feedforward clock signal as the sampling clock of the second sampling circuit.

[0041] The embodiment of the present disclosure provides a clock calibration circuit, comprising: a first sampling circuit; a second sampling circuit connected in series with the first sampling circuit; wherein the first sampling circuit comprises: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC; and a second transmission driver connected in series with the second data serializer, wherein the PLL is configured to output a clock signal to drive the first data serializer to send data to be transmitted to the first transmission driver. , and drives the second data serializer to send a feedforward clock signal to the second sending driver; the second sending driver is configured to send the feedforward clock signal to the first receiving driver in the second sampling circuit to determine the feedforward clock signal as the sampling clock of the second sampling circuit, which solves the problem that in the clock calibration circuit of the prior art, the clock calibration process of the first sampling circuit on the sending side and the second sampling circuit on the receiving side is prone to cause delay deviation in the circuit, and then the second sampling circuit on the receiving side can perform clock calibration according to the feedforward clock signal sent by the first sampling circuit, avoiding the problem that in the prior art, the clock calibration process of the first sampling circuit on the sending side and the second sampling circuit on the receiving side is prone to cause delay deviation in the circuit.

[0042] In an exemplary embodiment, the second sampling circuit includes: a second receiving driver connected in series with the first transmitting driver, configured to receive the data to be transmitted sent by the first transmitting driver, and send the data to be transmitted to a first data deserializer connected in series with the small delay buffer through a small delay buffer connected in series with the second receiving driver.

[0043] It is understood that the second receiving driver is configured to receive the data to be transmitted from the first transmitting driver in the first sampling circuit. Upon receiving the data to be transmitted, the second receiving driver transmits the data to be transmitted to the first data deserializer via the small delay buffer. In other words, the transmission path of the data to be transmitted is: from the first transmitting driver to the second receiving driver, through the small delay buffer, and to the first data deserializer.

[0044] In an exemplary embodiment, the second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer, respectively, and is configured to compensate for the intrinsic delay of the first DCC.

[0045] It can be understood that in the above circuit, the DCC buffer is connected in series with the second receiving driver and the small delay buffer respectively, and the DCC buffer can be used to compensate for the intrinsic delay of the first DCC in the circuit. That is, the DCC buffer is used to compensate for the inherent delay of the DCC in the above circuit, that is, the time it takes for the data to be transmitted to pass through the DCC from input to output.

[0046] In an exemplary embodiment, the second sampling circuit includes: a second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree. The first receiving driver is configured to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI, and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock for the first data deserializer and the second data deserializer.

[0047] It can be understood that the above-mentioned second sampling circuit is composed of a second DCC, a second PI, a second clock tree, a first data deserializer, and a second data deserializer, etc., wherein the feedforward clock signal is sent to the first data deserializer and the second data deserializer respectively through the above-mentioned second DCC, the second PI, and the second clock tree, in order to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

[0048] In an exemplary embodiment, the second sampling circuit includes a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer, respectively, and is configured to supplement the intrinsic delay of the second PI.

[0049] It can be understood that in the above circuit, the PI cache is connected in series with the second clock tree and the first data deserializer respectively, and the PI cache can be used to supplement the intrinsic delay of the second PI in the circuit. That is, the PI cache is used to supplement the inherent delay of the second PI in the above circuit, that is, the time it takes for the data to be sent to pass through the second PI from input to output.

[0050] In an exemplary embodiment, the second sampling circuit includes: a third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is configured to be set to a fixed phase shift after training of multiple data links and a TRACK link is completed, and the multiple data links and the TRACK link (which are substantially consistent with a circuit implementing multiple data lanes and can serve as a representative of data path delay) respectively correspond to different transmit drivers.

[0051] It can be understood that the second sampling circuit further includes: a third PI and a second data deserializer, wherein the third PI can be used to be set to a fixed phase shift after the training of multiple data links and TRACK links is completed.

[0052] In an exemplary embodiment, the first sampling circuit includes: a third PI connected in series with the first clock tree and the first data serializer, respectively, and configured to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links respectively correspond to different transmit drivers.

[0053] In an exemplary embodiment, the second sampling circuit includes: a first data checking module, connected in series with the first data deserializer and the second PI, respectively, and configured to adjust the delay value of the second PI during data link training; and / or a second data checking module, connected in series with the second data deserializer and the second PI, respectively, and configured to adjust the delay value of the second PI during TRACK link training.

[0054] It is understandable that the second sampling circuit further includes: a first data checking module and / or a second data checking module, which can be used to adjust the delay value of the second PI during data link training and / or TRACK link training.

[0055] In an exemplary embodiment, the second sampling circuit includes: a first delay-locked loop (DLL) connected in series with the second clock tree and the first data deserializer; and the second sampling circuit further includes: a second DLL connected in series with the second clock tree and the second data deserializer.

[0056] It can be understood that the second sampling circuit further includes: a first delay phase-locked loop DLL and a second DLL.

[0057] In an exemplary embodiment, the second sampling circuit includes: a third DLL, connected in series with the second DCC and the second PI, respectively, and configured to perform delay processing on multiple data links and TRACK links, wherein the multiple data links and the TRACK links correspond to different transmission drivers respectively.

[0058] It is understandable that the above-mentioned second sampling circuit also includes: a third DLL, which is configured to delay processing the signals of the data link and the TRACK link. It can generate corresponding delay signals based on the input reference clock signal and the control signal, thereby realizing delay control of the data link and the TRACK link signals.

[0059] The second DCC can control the delay of the third DLL and adjust the delay of the third DLL according to the input control signal, thereby achieving precise control of the data link and TRACK link signal delays.

[0060] In order to better understand the process of the above-mentioned clock calibration circuit, the implementation process of the above-mentioned clock calibration circuit is described below in combination with optional embodiments, but it is not intended to limit the technical solution of the embodiment of the present disclosure.

[0061] Next, the clock calibration circuit will be further described in conjunction with the following embodiments.

[0062] Embodiments of the present disclosure relate to a cross-die sampling clock calibration method, and more particularly to a cross-die sampling clock calibration technology in the chiplet field.

[0063] Cross-die or cross-package sampling clock calibration is a key technology in the chiplet field. Currently, cross-die or cross-package sampling clock calibration technologies in the chiplet field mainly include CDR (Clock Data Recovery) technology, commonly used in SerDes (Serdes), and clock feedforwarding technology used in AIB, UCIe, and other platforms, which feeds the clock of the transmitted data forward to the receiving side to sample the received data.

[0064] The disclosed embodiments utilize clock feedforwarding technology, a technique widely used in digital circuits to address the problems of clock signal propagation delay and clock jitter in circuits. In digital systems, clock signals are used to synchronize the operation of various components to ensure that they operate at the correct time. However, as clock signals propagate through circuits, factors such as delays and noise in the circuits may cause jitter or delay in the clock signal, thereby affecting the stability and performance of the system.

[0065] Clock feed-forward technology introduces an additional delay path in the circuit, allowing the clock signal to reach the target component earlier, thereby offsetting propagation delay and reducing jitter. Based on the principle that clock signals propagate faster than data signals, clock feed-forward technology delivers the clock signal to the target component requiring synchronization in advance during the clock signal propagation process, ensuring that the target component receives the clock signal at the correct time.

[0066] Clock feedforward technology can improve the reliability and performance of digital systems, reduce the impact of clock jitter on circuit operation, and enable more stable system operation. It is widely used in high-speed digital circuits, sequential circuits, and synchronous circuits.

[0067] One of the main functions of clock feedforward technology is sampling clock calibration, which is described as follows:

[0068] The feedforward clock is calibrated to align with the receiving data center location, and can follow the voltage and temperature drift during operation to meet the UCIe eye diagram width requirements.

[0069] Figures 1 and 2 show methods for aligning the transmit output clock and data. One approach involves directly generating a 90-degree phase-shifted sampling clock on the receive side. However, the challenge is shortening the receive clock tree, and the clock frequency cannot reach the 8 GHz required by UCIe. The other approach involves aligning the clock and data on both the transmit and receive sides, using a copied clock tree and data pads to compensate for the receive clock delay. However, this approach significantly increases latency, power consumption, and delay skew, failing to meet the UCIe eye width standard.

[0070] A clock tree is a tree-like structure used to synchronize the delivery and distribution of clock signals within a circuit. In digital circuit design, clock signals synchronize the operation of various logic gates, ensuring they execute at the correct intervals. The clock tree is designed to ensure that clock signals are delivered accurately and stably to each logic gate, guaranteeing proper circuit operation.

[0071] FIG4 is an overall circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure, as shown in FIG4 :

[0072] Among them, PLL: the abbreviation of Phase Locked Loop, refers to the phase-locked loop; DLL: the abbreviation of Delay Loop Lock, refers to the delay phase-locked loop; DCC: the abbreviation of Duty Cycle Calibrater, refers to the accuracy requirement determined by the specific implementation frequency, usually requiring -0.02UI to 0.02UI; DCC dummy: is a buffer to compensate for the DCC intrinsic delay, usually with a delay of <10ps; Ser: the abbreviation of Serializer, refers to the data serializer; Des: the abbreviation of De-Serializer, refers to the data deserializer; PI: the abbreviation of Pahse interpolators, refers to the phase interpolator; PI dummy: is a buffer to compensate for the PI intrinsic delay, with an intrinsic delay of <2ps; TX: refers to the transmit driver; RX: refers to the receiver; PD: Phase Detect stands for phase detector; Deskew is an adjustable small delay line, approximately 0.04 UI ​​(maximum delay 5 ps at 8 Gbps); SBTX is the abbreviation for sideband, referring to the sideband transmitter, typically operating at 800 MHz; SBRX is the abbreviation for sideband, referring to the sideband receiver, typically operating at 800 MHz. (Sideband data communication does not require calibration; SBTX outputs data on the falling edge, and SBRX samples on the rising edge.) TRACK is essentially the same circuit implementation as multiple data lanes and represents data path delay. Unlike data lanes, the DES module clock input has a PI3 to achieve a 90-degree phase shift on the sampling clock.

[0073] The PLL output clock then passes through the DCC (duty cycle calibrator) and the phase interpolator PI1. It then passes through the clock distribution (clock tree) and drives the SER modules (parallel-to-serial) in multiple data lanes, which then transmit data to the TX (transmitter driver). This in turn drives the SER modules in the TRACK lanes, which transmit fixed pattern data to the TX. The DCC clock then drives the SER modules in the fwdclk lanes, which transmit the fwdclk signal to the TX as the sampling clock for the other die. The fwdclk path and the transmit data path do not need to have the same delay.

[0074] On the receiving side, the data lanes (equivalent to the link in the above embodiment) and the track lanes pass through the RX (receiver), the DCC dummy (DCC intrinsic delay compensation buffer), the deskew (a buffer with adjusted small delay to align the skew between data lanes), and the deserializer (DSE). The fwdclk signal is received by the RX, passes through the DCC, and distributed clock tree to the DES modules in each data lane and track lane as the sampling clock input. The receive data path does not require any additional delay to align with the sampling clock.

[0075] In Figure 4, the DCC dummy and PI dummy are buffers that compensate for the intrinsic delays of DCC and PI.

[0076] Figure 5 is a PI logic block diagram according to an embodiment of the present disclosure. As shown in Figure 5, there are 8-phase tap outputs in the PI. Since there is a phase detector tracking VT in 360 degrees to maintain synchronization with the cycle, the phase delay of each of the 8 phases maintains a ratio with 360 degrees, so the 8-phase output clock is VT tracking compensated.

[0077] When 8:2, the 90-degree and 135-degree phase outputs are selected, PI=0, and the FOUT output is the FIN 90-degree phase-shifted clock.

[0078] It should be noted that this is only an example based on the embodiment of the present disclosure and is not limited to the use of this structure. For example, PI1 and PI2 in the embodiment can also be replaced by DLL1 and DLL2.

[0079] As shown in Figures 4 and 5, the transmit side data lane inputs: PRBS (Pseudo-Random Binary Sequence) pseudo-random sequence / fixed pattern and tx_dat (upper layer normal data); the track lane inputs: PRBS pseudo-random sequence / fixed pattern; the PRBS pseudo-random sequence / fixed pattern is used for initialization training.

[0080] The transmit clock tree on the transmit side connects to PI1, the receive sampling clock tree connects to PI2, and the sampling clock, after passing through the clock tree, connects to PI3 to the DES module clock input of the track lane (link channel). PI1 and PI2 are variable delay lines used for training or VT tracking. PI3 initially only provides intrinsic delay. After training is complete for the data lane and track lane, it must be set to a fixed 90-degree phase shift before normal operation to ensure that the sampling clock is located at the right edge of the track data.

[0081] On the receiving side, the PD phase detector is located at the data input and sampling clock input of the DES module in the TRACK lane. During initialization, it phase-locks the TRACK clock to the fwdclk clock. Because the TRACK is essentially equivalent to one of the data lanes, locking the TRACK and fwdclk clocks is equivalent to locking the data lane and fwdclk clock delay. The PD output is sidebanded to the transmitting end to adjust the PI1 delay value or directly adjust the PI2 delay value on this side.

[0082] Among them, the data check module on the data lane is used to adjust the PI2 delay value during data lane training; the data check module on the TRACK lane is used to adjust the PI2 delay value during data lane training, and track VT to adjust the PI2 delay value during normal operation.

[0083] It should be noted that in the back-end implementation of the optional embodiment of the present disclosure, 1) the delay deviation between path2 and path3 needs to be minimized (for example, UCIe requires <0.14UI, where UI is a data width, usually txclk period / 2); 2) the delay deviation between multiple data lanes and multiple Path2s of the TRACK lane needs to be minimized (according to UCIe requirements, <0.04UI); 3) path1 and path4 are located in different dies, involving different processes and different conners, and the deviation requirements are relatively loose, generally <0.5UI, but the clock tree is made as short as possible, and the deviation between the two clock trees is as small as possible to reduce the delay variation when VT changes;

[0084] It should be noted that the embodiment of the present disclosure initializes and calibrates path1+path2=path3+path4 after power-on reset. At this time, the deskew buffer (buffer used to correct signal delay) of the entire link has only intrinsic delay, generally about 1ps. Path1+path2=path3+path4 is calibrated by the PD phase detection located at die2. If path1+path2 is short, PI1 is increased, and vice versa. At this time, PI3 has only intrinsic delay. The control signal 1 output by the PD on Die2 can directly adjust the local PI2, or be sent to Die1 through a sideband signal to adjust PI1. Among them, the sideband implementation method is not limited, and the delay adjustment step is determined by the selected algorithm. The steps are different at different stages in the adjustment process. The initial step is large, and the subsequent two clock edges are getting closer and closer, and the steps should also become smaller and smaller. Repeat this step many times, and when the edge error between the clock and TRACK reaches a certain value according to the algorithm, the lock is completed. This clock and data path are already edge-aligned within a certain error.

[0085] Figure 6 illustrates the Path1+path2=path3+path4 calibration process according to an embodiment of the present disclosure. As shown in Figure 6, CLKA represents the TRACK signal, and CLKB represents the fwdclk signal. Based on PI1-up and PI2-up, a multi-bit control signal 1 is generated and sent to PI1 and PI2, respectively, to adjust their delays. The signal must pass through the sideband to reach PI1.

[0086] In an optional embodiment of the present disclosure, the PD output of Die2 is disconnected, and PI2 scans the eye width for each data lane and TRACK lane based on the basic value of step 4 to find the respective midpoint positions. Specifically, random data or fixed pattern data is used to drive a data lane or TRACK on die1, and the PI value is recorded through testing on the receiving side of die2 based on different PI comparison results. A series of data is recorded from small to large to find the midpoint value. Each lane is tested one by one (including the TRACK lane) to obtain a series of PI midpoint values.

[0087] Based on the PI midpoint values ​​obtained for each lane using the maximum PI midpoint value as a reference, the deskew of the lane with the maximum PI midpoint value remains unchanged, and the deskew of other lanes is adjusted by equalizing the maximum PI midpoint value minus the PI midpoint value of the lane to be adjusted. After each lane adjustment, retest to ensure correct received data. Figure 7 shows a schematic diagram of eye diagram alignment according to an embodiment of the present disclosure.

[0088] In an optional embodiment of the present disclosure, a fixed 90-degree phase shift is applied to PI3, the DES clock input on the Track lane, causing the sampling clock to align with its center to its right edge, making it impossible to stably sample data. Figure 8 shows the alignment of the TRACK data boundary and clock edge according to an embodiment of the present disclosure. As shown in Figure 8, the data is normal.

[0089] As shown in Figure 8, SAM_CLK refers to the sampling clock before PI3 and is also the clock that aligns the eye centers of all data lanes and track lanes. SAM_CLKP is the clock used to sample the track lanes after SAM_CLK is phase-shifted 90 degrees by PI3. SAM_CLKN is the inverse clock of SAM_CLKP. SAM_CLKP and SAM_CLKN are the two-phase sampling clocks in DDR mode.

[0090] Figure 9 shows a rightward drift of the sampling clock according to an embodiment of the present disclosure. As shown in Figure 9 , when the sampling clock drifts rightward, the sampled even path stability is 1, and the odd path stability is 0. PI2 can be controlled to reduce the delay until the rx_TRACK data reaches the value shown in Figure 8 , indicating that the clock offset has been tracked and compensated.

[0091] The sampling clock drifts to the left, the sampled even path is stable = 0, and the odd path is stable = 1. PI2 can be controlled to increase the delay until the rx_TRACK data shows the value shown in Figure 8, indicating that the clock offset has been tracked and compensated.

[0092] The steps of controlling PI2 to reduce or increase the delay are determined by the selected algorithm.

[0093] It should be noted that the above clock drift relative to the data path is not necessarily caused by the change in clock path delay. It may actually be caused by data path drift, or both paths may drift.

[0094] In another optional embodiment, FIG10 is a circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure. As shown in FIG10 , the implementation scheme is:

[0095] 1. Path 1 + path 2 = path 3 + path 4 are no longer initially calibrated. Path 1 and path 4 are initially phase-locked to 1UI (or 2UI, 3UI, or 4UI), depending on the designed data rate. For example, at 16Gbps, 1UI = 62.5ps. A typical clock tree is 70ps to 120ps, so setting path 1 and path 4 to 2UI is appropriate.

[0096] 2. Each track lane has a DLL1, and each data lane has a DLL2 (Figure 10 shows only one DLL2 for each data lane). The maximum delay value of DLL2 must be greater than 1UI, and the maximum delay value of DLL1 must be greater than 1.5UI.

[0097] 3. Add DLL dummy to each data lane and TRACK lane to compensate for the intrinsic delay of DLL1 or DLL2.

[0098] The implementation steps shown in FIG10 are different from those in FIG4 , specifically:

[0099] 1. The aforementioned steps for initializing and calibrating path1 + path2 = path3 + path4 after power-on reset can be changed to: At the start of operation, deskew = DLL2 intrinsic delay, calibrating Path1 and Path4. Using the PD phase detection on each die, the PDs are locked to 2UI (or other integer UI, depending on the data rate). After locking, the data path and clock path are essentially aligned, within the UCIe specification's maximum permissible deviation of 0.14UI.

[0100] 2. For the step-disconnected PD output of Die2, the TRACK and data lanes can be calibrated separately, one lane at a time. This is done by sending prbs or fixed parttern data from Die1 and adjusting DLL1 and DLL2 on the receive path of Die2 to obtain a range of DLL delay values ​​that accurately detect the data and find the midpoint.

[0101] 3. The lane PI midpoint values ​​obtained in the above steps can be modified by finding the maximum midpoint value among multiple data lanes and the track lane. Using this value as a guide, adjust the deskew of other lanes to achieve a delay equal to the maximum DLL midpoint value - the DLL midpoint value of the lane to be adjusted. Retest after each lane adjustment to ensure correct data reception.

[0102] 4. In step 4, the fixed 90-degree phase shift applied to PI3 at the DES clock input on the track lane corresponds to step 10, which increases the delay of DLL1 at the DES clock input on the track lane, causing the sampling clock to align with its center instead of its right edge, making it impossible to sample stable data. When the track detects stable data, DLL1 scans the track's eye diagram to find the DLL1 delay value at the eye center. The DLL2s in the other data lanes are then adjusted to match the delay of DLL1. Because DLL1 and DLL2 are different instantiations of the same device, they maintain high consistency. Finally, DLL2 delay is increased until the sampling clock no longer samples stable data on the track.

[0103] DLL1 and DLL2 support a minimum data rate of 8 Gbps. For example, 1 UI = 125 ps. Therefore, DLL2 is designed with a maximum delay of 128 ps, sufficient to scan the eye width. There are 16 levels of coarse adjustment and 8 levels of fine adjustment. Each level of coarse adjustment is slightly larger than the 8 levels of fine adjustment, and each level of fine adjustment has a delay of 1 ps. DLL1 requires 128 + 64 = 192 ps, with 24 levels of coarse adjustment and a scanning range of 0 to 1.5 UI.

[0104] It is important to note that to support the minimum data rate of 4Gbps, DLL2 requires a maximum delay of 256ps, which consumes a large amount of power and area.

[0105] 2) FIG. 11 is another circuit diagram of a clock calibration circuit according to an embodiment of the present disclosure. As shown in FIG. 11 , the difference between the embodiment and the embodiment of FIG. 10 is that:

[0106] 1. DLL2 is shared by multiple data lanes and TRACK lanes, with a maximum delay of >1UI, reducing area and power consumption;

[0107] 2. DLL1 connected to the DES input clock port in the Track lane is replaced with PI3. The 90-degree phase shift generated by the PI when tracking the VT is locked to the VT, resulting in better tracking accuracy. Because the sampling clock drift output by DLL1 in Alternative Solution 1 is caused by the delay value of DLL1's own delay unit varying with VT (voltage and temperature), DLL2 must also vary by the same amount. The difference between the two will affect tracking accuracy.

[0108] The difference between the implementation steps and the implementation steps of Figure 10 above is that during training and VT following, DLL1 and DLL2 of each data lane are adjusted, while Alternative Scheme 2 adjusts PI3 and DLL2 common to all data lanes.

[0109] The above embodiment has the following four characteristics:

[0110] 1. The transmit data on the transmitting side is not aligned with the feedforward clock fwdclk. This solves the problem of fwdclk duplicating the transmit txclk clock tree in the prior art.

[0111] 2. The receiving side does not need to compensate for the sampling clock tree delay on the data path, and the sampling clock tree does not need to be delayed within 0.5UI. This solves the problem of the data path needing to compensate for the sampling clock tree delay in the existing technology, and does not require the back-end to optimize the clock tree delay;

[0112] 3. Align the entire data path and clock path by using the method of offsetting the delays of the sending clock tree on the sending side and the sampling clock tree on the receiving side. The specific implementation is to perform phase detection on the receiving side for the TRACK data (carrying the clock signal) and the sampling clock fwdclk (or alternatively, phase lock the sending clock tree on the sending side and the sampling clock tree on the receiving side, generally locked to 2UI or 4UI, determined according to the clock tree delay and UI value) to ensure that the delays of the two are the same. The phase-locking method can achieve higher accuracy than the existing technology. In addition, the overall path delay does not increase, and the impact of jitter caused by changes in temperature and voltage is relatively small;

[0113] 4. It has a temperature and voltage tracking mechanism. Before operation, the sampling clock is aligned to the center of the track data through training to ensure accurate track data sampling. During operation, the phase shift is performed 90 degrees to the right edge of the track data using the PI3 on ​​the track. This ensures that the sampled parity bits do not receive stable data (the transmitting side sends a fixed pattern of 1010 on the track lane). If the sampled parity bits are stable at 1 or 0, it indicates sampling clock delay drift. The PI connected to the sampling clock tree can be adjusted to compensate for this drift delay.

[0114] The disclosed embodiments utilize the fact that the delays of the sending clock tree on the data path and the sampling clock tree on the clock path are similar and can offset each other. Instead of aligning the data clock edges on each side of the sending and receiving sides, the entire data path and clock path on both sides are considered together, and the delays are equalized through PD locking. This reduces the need for various clock tree replication, clock tree delay compensation, and other circuits. Specifically, it has the following advantages:

[0115] 1. Avoid adding clock tree delay compensation circuits to the data path. This does not increase the total delay, minimizes jitter caused by temperature and voltage variations, and eliminates deviations between the compensation circuit and the clock tree. Furthermore, for high-speed data signals (current simulations have found that adding a delay of approximately 100ps to the data path at speeds above 24Gbps can cause signal degradation and close the sampling eye diagram).

[0116] 2. Overall PD phase locking covers the complete data and clock paths, minimizing skew. Alternatively, the transmit and receive clock trees can be phase-locked separately, covering the maximum delay portion, which is also the primary variable when VT changes. This also minimizes overall delay and clock data skew.

[0117] 3. Back-end implementation is simpler. There is no need to add clock tree compensation circuits on the data path.

[0118] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A clock calibration circuit, comprising: a first sampling circuit; A second sampling circuit connected in series with the first sampling circuit; wherein, The first sampling circuit includes: a phase-locked loop PLL; a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; and a first transmission driver connected in series with the first data serializer. a second data serializer connected in series with the first DCC, and a second transmit driver connected in series with the second data serializer, wherein the PLL is configured to output a clock signal to drive the first data serializer to send the data to be sent to the first transmit driver, and to drive the second data serializer to send a feedforward clock signal to the second transmit driver; The second transmitting driver is configured to transmit the feedforward clock signal to the first receiving driver in the second sampling circuit, so as to determine the feedforward clock signal as a sampling clock of the second sampling circuit.

2. The clock calibration circuit according to claim 1, wherein: The second sampling circuit includes: a second receiving driver, which is connected in series with the first sending driver and is configured to receive the data to be sent sent by the first sending driver, and send the data to be sent to a first data deserializer connected in series with the small delay buffer through a small delay buffer connected in series with the second receiving driver.

3. The clock calibration circuit according to claim 2, wherein: The second sampling circuit further includes: a DCC buffer, which is connected in series with the second receiving driver and the small delay buffer respectively, and is configured to compensate for the intrinsic delay of the first DCC.

4. The clock calibration circuit according to claim 2, wherein: The second sampling circuit comprises: A second DCC connected in series with the first receiving driver, a second PI connected in series with the second DCC, a second clock tree connected in series with the second PI, and the first data deserializer and the second data deserializer connected in series with the second clock tree, wherein the first receiving driver is configured to send the feedforward clock signal to the first data deserializer and the second data deserializer through the second DCC, the second PI and the second clock tree, respectively, so as to determine the feedforward clock signal as the sampling clock of the first data deserializer and the second data deserializer.

5. The clock calibration circuit according to claim 4, wherein: The second sampling circuit includes: a PI buffer, wherein the PI buffer is connected in series with the second clock tree and the first data deserializer respectively, and is configured to supplement the intrinsic delay of the second PI.

6. The clock calibration circuit according to claim 4, wherein: The second sampling circuit comprises: A third PI connected in series with the second clock tree, and a second data deserializer connected in series with the third PI, wherein the third PI is set to be set to a fixed phase shift after training of multiple data links and TRACK links is completed, and the multiple data links and the TRACK links correspond to different transmission drivers respectively.

7. The clock calibration circuit according to claim 4, wherein: The first sampling circuit comprises: The third PI connected in series with the first clock tree and the first data serializer is configured to connect multiple data links and After the TRACK link training is completed, it is set to a fixed phase shift, and the multiple data links and the TRACK link correspond to different transmission drivers respectively.

8. The clock calibration circuit according to claim 4, wherein: The second sampling circuit comprises: a first data checking module, connected in series with the first data deserializer and the second PI respectively, and configured to adjust the delay value of the second PI during data link training; and / or The second data checking module is connected in series with the second data deserializer and the second PI respectively, and is configured to adjust the delay value of the second PI during TRACK link training.

9. The clock calibration circuit according to claim 4, wherein: The second sampling circuit comprises: a first delay phase-locked loop DLL, connected in series with the second clock tree and the first data deserializer respectively; The second sampling circuit further includes: a second DLL connected in series with the second clock tree and the second data deserializer respectively.

10. The clock calibration circuit according to claim 4, wherein: The second sampling circuit comprises: The third DLL is connected in series with the second DCC and the second PI respectively, and is configured to perform delay processing on multiple data links and TRACK links, wherein the multiple data links and the TRACK links correspond to different sending drivers respectively.

11. The clock calibration circuit according to any one of claims 1 to 10, wherein: The first sampling circuit includes: a first DIE sampling circuit; the second sampling circuit includes: a second DIE sampling circuit.

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