Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a display area and a frame area, and a storage capacitor comprises a first electrode plate, a second electrode plate and a third electrode plate; the display substrate comprises a first conductive layer, a second conductive layer and a third conductive layer, wherein the first electrode plate is arranged in the first conductive layer, a first signal line and the second electrode plate are arranged in the second conductive layer, and a second signal line and the third electrode plate are arranged in the third conductive layer; and two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projections of the notches on the substrate are configured to overlap with the orthographic projection of a first input end on the substrate, or to overlap with the orthographic projection of a second input end on the substrate. In the present disclosure, by means of providing notches, two electrode plates of the storage capacitor are prevented from being short-circuited after melting during maintenance on the basis of not influencing the charge storage capability of the capacitor, thus improving the maintenance success rate, reducing the screen rejection rate caused by poor capacitance, and improving the product yield and quality.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 28, 2023, with application number 202311092105.X and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the technical field of display devices, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] At present, the success rate of capacitor repair in the process of manufacturing large-size transparent products is low.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] At least one embodiment of the present disclosure provides a display substrate, comprising a display area and a frame area located on at least one side of the display area, wherein the frame area at least includes a gate drive circuit, the gate drive circuit at least includes a storage capacitor, a first signal line and a second signal line, and the storage capacitor includes a stacked first plate, a second plate, and a third plate;

[0008] In a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on a base in a direction away from the base;

[0009] The first electrode plate is disposed in the first conductive layer;

[0010] The first signal line and the second electrode plate are arranged in the second conductive layer, and the second electrode plate has a first input terminal connected to the first signal line;

[0011] The second signal line and the third electrode plate are arranged in the third conductive layer, and the third electrode plate has a second input terminal connected to the second signal line;

[0012] Two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projection of the notches on the substrate is set to overlap with the orthographic projection of the first input end on the substrate, or overlap with the orthographic projection of the second input end on the substrate.

[0013] In some exemplary embodiments, both the first electrode plate and the third electrode plate are provided with a notch, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first input terminal on the substrate;

[0014] Alternatively, both the first electrode plate and the second electrode plate are provided with a notch, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the second input end on the substrate.

[0015] In some exemplary embodiments, a first groove recessed inward is provided on a circumferential edge of the first electrode plate, and the first groove extends in a direction perpendicular to the substrate and penetrates the first electrode plate;

[0016] A second groove recessed inward is provided on the circumferential edge of the third electrode plate, and the second groove extends in a direction perpendicular to the substrate and passes through the third electrode plate;

[0017] The first groove and the second groove both constitute the notch.

[0018] In some exemplary embodiments, the circumferential edge of the first electrode plate includes at least a first edge, the first edge is located on a side of the first electrode plate close to the first input end, and the first groove is provided on the first edge;

[0019] The circumferential edge of the third electrode plate includes at least a second edge, the second edge is located on a side of the third electrode plate close to the first input end, and the second groove is provided on the second edge;

[0020] The first edge and the second edge are flush in a direction perpendicular to the substrate, and an orthographic projection of the first groove on the substrate and an orthographic projection of the second groove on the substrate at least partially overlap.

[0021] In some exemplary embodiments, the orthographic projection of the first groove on the substrate is within the range of the orthographic projection of the second groove on the substrate; or, the orthographic projection of the second groove on the substrate is within the range of the orthographic projection of the first groove on the substrate; or, the orthographic projection of the first groove on the substrate and the orthographic projection of the second groove on the substrate overlap.

[0022] In some exemplary embodiments, in a direction parallel to the substrate, the first groove and the second groove are both shaped as rectangular grooves or arc-shaped grooves.

[0023] In some exemplary embodiments, the width of the first groove and the second groove are both 15 μm to 30 μm, and the depth of the first groove and the second groove are both 7 μm to 15 μm.

[0024] In some exemplary embodiments, a third groove recessed inward is provided on a circumferential edge of the first electrode plate, and the third groove extends in a direction perpendicular to the substrate and penetrates the first electrode plate;

[0025] A fourth groove recessed inward is provided on the circumferential edge of the second electrode plate, and the fourth groove extends in a direction perpendicular to the substrate and passes through the second electrode plate;

[0026] The third groove and the fourth groove both constitute the notch, and the orthographic projection of the third groove on the substrate and the orthographic projection of the fourth groove on the substrate at least partially overlap.

[0027] In some exemplary embodiments, the orthographic projection of the third groove on the substrate overlaps with the orthographic projection of the fourth groove on the substrate, the groove width of the third groove is 15 μm to 30 μm, and the groove depth of the third groove is 7 μm to 15 μm.

[0028] In some exemplary embodiments, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate are arranged to at least partially overlap;

[0029] The first electrode plate and the third electrode plate are electrically connected via a metal hole structure, and the second electrode plate is provided with a first opening for avoiding the metal hole structure.

[0030] In some exemplary embodiments, a plurality of the first input terminals are provided on the second electrode plate, and a plurality of the second input terminals are provided on the third electrode plate;

[0031] There are multiple notches on the first electrode plate and multiple notches on the third electrode plate, and they correspond one-to-one with the first input terminals; or there are multiple notches on the first electrode plate and multiple notches on the second electrode plate, and they correspond one-to-one with the second input terminals.

[0032] In some exemplary embodiments, the display substrate further includes a buffer layer and a first insulating layer, wherein the buffer layer is arranged to cover a surface of the first conductive layer away from the substrate, and the first insulating layer is arranged to cover a surface of the second conductive layer away from the substrate.

[0033] At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0034] At least one embodiment of the present disclosure provides a method for preparing a display substrate, wherein the display substrate includes a display area and a frame area located on at least one side of the display area, the frame area includes at least a gate drive circuit, the gate drive circuit includes at least a storage capacitor, a first signal line and a second signal line, and the storage capacitor includes a stacked first plate, a second plate, and a third plate;

[0035] The preparation method comprises: forming a first conductive layer on a substrate, wherein the first electrode plate is disposed in the first conductive layer;

[0036] A second conductive layer is formed on a side of the first conductive layer away from the substrate, the first signal line and the second electrode plate are arranged in the second conductive layer, and the second electrode plate has a first input terminal connected to the first signal line;

[0037] forming a third conductive layer on a side of the second conductive layer away from the substrate, wherein the second signal line and the third electrode plate are arranged in the third conductive layer, and the third electrode plate has a second input terminal connected to the second signal line;

[0038] Two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projection of the notches on the substrate is set to overlap with the orthographic projection of the first input end on the substrate, or overlap with the orthographic projection of the second input end on the substrate.

[0039] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0040] Summary of the Figures

[0041] FIG1 is a schematic structural diagram of a display device;

[0042] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0043] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0044] FIG4 is a schematic diagram of the maintenance of the related storage capacitor structure;

[0045] FIG5 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG6 is a schematic diagram of the AA section in FIG5 ;

[0047] FIG7 is a partial schematic diagram of the gate drive circuit in FIG5 ;

[0048] FIG8 is a schematic diagram of a first conductive layer according to an exemplary embodiment of the present disclosure;

[0049] FIG9 is a schematic diagram of the first electrode plate in FIG8 ;

[0050] FIG10 is another schematic diagram of the first electrode plate in FIG8;

[0051] FIG11 is a schematic diagram of a buffer layer according to an exemplary embodiment of the present disclosure;

[0052] FIG12 is a schematic diagram of a second conductive layer according to an exemplary embodiment of the present disclosure;

[0053] FIG13 is a schematic diagram of the second electrode plate in FIG12;

[0054] FIG14 is another schematic diagram of the second electrode plate in FIG12;

[0055] FIG15 is a schematic diagram of a first insulating layer of an exemplary embodiment of the present disclosure;

[0056] FIG16 is a schematic diagram of a first via hole of an exemplary embodiment of the present disclosure;

[0057] FIG17 is a schematic diagram of a third conductive layer according to an exemplary embodiment of the present disclosure;

[0058] FIG18 is a schematic diagram of the third electrode plate in FIG17;

[0059] FIG19 is another schematic diagram of the third electrode plate;

[0060] FIG20 is an isometric view of a storage capacitor according to an exemplary embodiment of the present disclosure;

[0061] FIG21 is a schematic cross-sectional view taken along line BB in FIG5 ;

[0062] FIG22 is another cross-sectional schematic diagram of the storage capacitor in FIG5 ;

[0063] FIG23 is a schematic diagram of laser cutting of a storage capacitor according to an exemplary embodiment of the present disclosure;

[0064] FIG24 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG25 is a schematic diagram of the storage capacitor in FIG24;

[0066] FIG26 is a schematic diagram of the second electrode plate in FIG25;

[0067] FIG27 is a schematic diagram of the third electrode plate in FIG25;

[0068] FIG28 is a schematic diagram of the first electrode plate in FIG25;

[0069] FIG29 is a schematic diagram of another storage capacitor according to an exemplary embodiment of the present disclosure;

[0070] FIG30 is a schematic diagram of the second electrode plate in FIG29;

[0071] FIG31 is a schematic diagram of the first electrode plate in FIG29 .

[0072] Description of the accompanying drawings:

[0073] 10-substrate; 20-driving circuit layer; 30-light-emitting structure layer;

[0074] 40-packaging structure layer; 21-gate drive circuit; 22-first conductive layer;

[0075] 23-second conductive layer; 24-third conductive layer; 25-buffer layer;

[0076] 26-first insulating layer; 50-storage capacitor; 51-first electrode;

[0077] 52-second electrode plate; 53-third electrode plate; 54-metal hole structure;

[0078] 511 - first groove; 512 - first edge; 513 - fifth edge;

[0079] 514 - third edge; 515 - third groove; 521 - sixth edge;

[0080] 522 - seventh edge; 523 - first opening; 524 - first position;

[0081] 525 - first input end; 526 - fourth edge; 527 - fourth groove;

[0082] 531 - second groove; 532 - second edge; 533 - eighth edge;

[0083] 534 - via metal structure; 535 - second position; 536 - second input terminal;

[0084] 27-first via hole; 100-display area; 200-binding area;

[0085] 300-border area.

[0086] Details

[0087] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0088] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0089] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0090] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0091] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0092] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0093] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0094] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0095] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0096] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0097] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0098] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0099] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0100] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals and scan start signals suitable for the specifications of the scan driver to the scan driver, and may provide clock signals and emission stop signals suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0101] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0102] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0103] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0104] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 20 disposed on a substrate 10, a light-emitting structure layer 30 disposed on the side of the drive circuit layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0105] In an exemplary embodiment, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 20 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 30 may include a plurality of light-emitting devices, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 40 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 30.

[0106] At present, in the gate drive circuit process of the relevant display substrate, there is a situation where foreign matter falls into the capacitor area or electrostatic discharge (ESD) occurs, which will cause the storage capacitor to fail and become a problem capacitor. Figure 4 is a schematic diagram of the relevant storage capacitor structure maintenance. As shown in Figure 4, the storage capacitor 50 includes a first plate (Shield) 51, a second plate (Gate) 52 and a third plate (SD) 53, wherein the second plate 52 is located between the third plate 53 and the first plate 51. When foreign matter falls off, it will cause the second plate (Gate) 52 and the third plate (SD) 53 to short-circuit, becoming a problem capacitor, unable to store or release charge, and the transistor of the gate drive circuit 21 (not shown in the figure) cannot be turned on and transmitted normally. The display area of ​​the display substrate cannot receive the gate signal, forming a through Y dark line. Laser is usually used to cut the gate metal wire connected to the problem capacitor, severing the connection between the problem capacitor and the adjacent normal capacitor. The inventors of this application have found that the laser radiation area generated by the maintenance is large, and the edge of the normal storage capacitor adjacent to the problem capacitor is often cut during the maintenance process. As shown in Figure 4, the edge of the storage capacitor 50 is cut by laser, and the third plate 53 and the second plate 52 are cut at the same time. The thermal radiation of the laser can cause the third plate 53 and the second plate 52 to melt and short-circuit, causing the adjacent storage capacitors to fail, making more storage capacitors unable to work normally, and the maintenance effect is poor.

[0107] Figure 5 is a schematic diagram of a display substrate of an exemplary embodiment of the present disclosure, Figure 6 is a schematic diagram of the AA section in Figure 5, and Figure 7 is a partial schematic diagram of the gate drive circuit in Figure 5. The present disclosure provides a display substrate, as shown in Figures 5, 6 and 7. The display substrate may include a display area 100 and a frame area 300 located on at least one side of the display area 100. The frame area 300 may include at least a gate drive circuit 21. The gate drive circuit 21 includes at least a storage capacitor 50, a first signal line 71 and a second signal line 72. The storage capacitor 50 includes a stacked first electrode 51, a second electrode 52 and a third electrode 53. In a direction perpendicular to the display substrate 10, the display substrate includes a first conductive layer 22, a second conductive layer 23, and a third conductive layer 24, sequentially arranged on the substrate 10 in a direction away from the substrate 10. A first electrode plate 51 is disposed in the first conductive layer 22, a first signal line 71, and a second electrode plate 52 are disposed in the second conductive layer 23. The second electrode plate 52 has a first input terminal 525 connected to the first signal line 71. The second signal line 72 and the third electrode plate 53 are disposed in the third conductive layer 24, and the third electrode plate 53 has a second input terminal 536 connected to the second signal line 72. Two of the first electrode plate 51, the second electrode plate 52, and the third electrode plate 53 have notches, and the orthographic projection of the notch 70 on the substrate 10 is arranged to overlap with the orthographic projection of the first input terminal 525 on the substrate 10, or overlap with the orthographic projection of the second input terminal 526 on the substrate 10. In some exemplary embodiments, the first electrode plate 51 and the third electrode plate 53 are both provided with a notch 70. In a direction perpendicular to the substrate 10, the notch 70 corresponds to the first input end 525. The first electrode plate 51 and the third electrode plate 53 are both staggered from the first input end 525. The orthographic projections of the first electrode plate 51 and the third electrode plate 53 on the substrate 10 do not overlap with the orthographic projection of the first input end 525 on the substrate 10. The orthographic projection of the notch 70 on the substrate 10 overlaps with the orthographic projection of the first input end 525 on the substrate 10. But not limited to this, for example, the first electrode plate 51 and the second electrode plate 52 are both provided with a notch 70, and in the direction perpendicular to the substrate 10, the notch 70 corresponds to the second input end 536, the first electrode plate 51 and the second electrode plate 52 are both staggered from the second input end 536, and the orthographic projections of the first electrode plate 51 and the second electrode plate 52 on the substrate 10 do not overlap with the orthographic projection of the second input end 536 on the substrate 10, and the orthographic projection of the notch 70 on the substrate 10 overlaps with the orthographic projection of the second input end 536 on the substrate 10.

[0108] In some exemplary embodiments, as shown in Figures 5, 6, and 7, the circumferential edge of the first electrode plate 51 may be provided with a first groove 511 that is recessed inward. The first groove 511 may extend in a direction perpendicular to the substrate 10 and may penetrate the first electrode plate 51. The circumferential edge of the third electrode plate 53 may be provided with a second groove 531 that is recessed inward. The second groove 531 may extend in a direction perpendicular to the substrate 10 and may penetrate the third electrode plate 53. The orthographic projections of the first groove 511 and the second groove 531 on the substrate 10 may at least partially overlap.

[0109] In some exemplary embodiments, as shown in Figures 5, 6 and 7, the orthographic projection of the first groove 511 on the substrate 10 may completely overlap with the orthographic projection of the second groove 531 on the substrate 10, and the first groove 511 and the second groove 531 may both be set as rectangular grooves, but are not limited thereto. For example, they may both be arc-shaped grooves.

[0110] In some exemplary embodiments, as shown in Figures 5, 6 and 7, the groove body shape, groove width and groove depth of the first groove 511 and the second groove 531 may be consistent, the groove width of the first groove 511 and the second groove 531 may be set to 15μm to 30μm, and the groove depth of the first groove 511 and the second groove 531 may be set to 7μm to 15μm.

[0111] In some exemplary embodiments, as shown in Figures 5, 6 and 7, the display substrate further includes a buffer layer 25, a first insulating layer 26 and a passivation layer (not shown in the figures). The buffer layer 25 may be located at least between the first electrode plate 51 and the second electrode plate 52, and in the first groove 511; the first insulating layer 26 may be located at least between the second electrode plate 52 and the third electrode plate 53; the passivation layer (not shown in the figures) is located at least on the surface of the third electrode plate 53 away from the second electrode plate 52, and in the second groove 531.

[0112] In some exemplary embodiments, as shown in Figures 5, 6, and 7, the orthographic projection of the first electrode plate 51 on the substrate 10 and the orthographic projection of the third electrode plate 53 on the substrate 10 may at least partially overlap. In this example, the orthographic projection of the first electrode plate 51 on the substrate 10 and the orthographic projection of the third electrode plate 53 on the substrate 10 completely overlap. The first electrode plate 51 and the third electrode plate 53 can be electrically connected through the metal hole structure 54. The second electrode plate 52 has a first opening 523 to avoid the metal hole structure 54.

[0113] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating, and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching. This disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0114] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0115] (1) A first conductive layer is prepared on the substrate 10 .

[0116] In some exemplary embodiments, preparing a first conductive layer on a substrate may include: first depositing a first conductive film on the substrate 10, then coating a photoresist on the first conductive film, exposing and developing, and then etching the first conductive film to form a shielding first conductive layer 22, wherein the first conductive layer 22 includes at least a first electrode 51, as shown in FIG8 .

[0117] In some exemplary embodiments, the mask used to form the first conductive layer 22 is designed based on the first electrode plate 51 having the first groove 511. The photoresist pattern formed after exposure and development using the mask has exposed areas and unexposed areas. The photoresist remains in the exposed areas, while the photoresist in the unexposed areas is removed, exposing the surface of the first conductive film. The etching process removes the first conductive film in the unexposed areas, while retaining the first conductive film in the exposed areas, thereby forming at least the first electrode plate 51 having the first groove 11.

[0118] Figure 9 is a schematic diagram of the first electrode plate in Figure 8, and Figure 10 is another schematic diagram of the first electrode plate in Figure 8. In some exemplary embodiments, as shown in Figures 8, 9, and 10, the first electrode plate 51 can be set on the substrate 10, and the material of the first electrode plate 51 can be a metal material, such as copper (Cu) or aluminum (Al). The first electrode plate 51 may be in the shape of a rectangular plate. The circumferential edge B1 of the first electrode plate 51 may be an edge surrounding the geometric center of the first electrode plate 51 in a plane parallel to the substrate 10. The circumferential edge B1 of the first electrode plate 51 may include a first edge 512 and three fifth edges 513. The first edge 512 and the three fifth edges 513 may form a rectangular ring. The first edge 512 is located at one end of the first electrode plate 51 in the second direction and may extend along the third direction. A fifth edge 513 is located at the other end of the second direction and may extend along the third direction. The other two fifth edges 513 may be respectively located at both ends of the first electrode plate 51 in the third direction and may extend along two directions. The second direction is perpendicular to the third direction, and both the second direction and the third direction are parallel to the substrate 10. A first groove 511 may be provided on the first edge 512, extending through the first electrode plate 51 in a direction perpendicular to the substrate 10. The first groove 511 may be formed by the first edge 512 being recessed toward the inner side of the first electrode plate 51. The inner side of the first electrode plate 51 may be the portion of the first electrode plate 51 near its geometric center. The first groove 511 constitutes the notch 70. The first groove 511 may be recessed toward an opposing fifth edge 513. The first groove 511 may be a rectangular groove, but is not limited thereto. For example, it may be an arc-shaped groove or an irregularly shaped groove. The groove width of the first groove 511 may be the maximum dimension of the first groove 511 in the third direction, i.e., L1. The groove depth of the first groove 511 may be the maximum dimension of the first groove 511 in the second direction, i.e., L2. In some exemplary embodiments, the groove width L1 of the first groove 511 may be 20 μm, and the groove depth L2 of the first groove 511 may be 10 μm, but is not limited thereto. The groove width L1 of the first groove 511 may be other values ​​within the range of 15 μm to 30 μm, and the groove depth L2 of the first groove 511 may be other values ​​within the range of 7 μm to 15 μm.

[0119] (2) Prepare the buffer layer, active layer and gate insulation layer in sequence.

[0120] In some exemplary embodiments, sequentially preparing the buffer layer and the active layer may include: first forming an inorganic material thin film on the substrate 10 having the first conductive layer 22 to form the buffer layer 25. Then, depositing an active layer film on the buffer layer 25, and treating the active layer film to form the active layer. Subsequently, depositing a gate insulating layer film on the substrate 10 having the active layer, and treating the gate insulating layer film to form the gate insulating layer.

[0121] FIG11 is a schematic diagram of a buffer layer according to an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG11 , the buffer layer 25 covers the first conductive layer 22 and also covers portions of the substrate 10 not provided with the first conductive layer 22. In this example, portions of the buffer layer 25 may be formed within the first recess 511 of the first electrode plate 51. The buffer layer 25 may be made of an inorganic insulating material, specifically any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The buffer layer 25 may be a single layer, multiple layers, or a composite layer. The buffer layer 25 may improve the substrate 10's resistance to water and oxygen.

[0122] In some exemplary embodiments, after depositing an active layer film on the buffer layer 25, a photoresist may be coated on the active layer film, exposed and developed, and then the active layer film may be etched to form an active layer pattern, thereby obtaining an active layer (not shown in the figure). After depositing a gate insulating layer film on the substrate 10 having the active layer, a photoresist may be coated on the gate insulating layer film, exposed and developed, and then the gate insulating layer film may be etched to form a gate insulating layer (not shown in the figure).

[0123] (3) Prepare the second conductive layer.

[0124] In some exemplary embodiments, preparing the second conductive layer includes: depositing a second conductive film on a substrate 10 having a gate insulating layer and a buffer layer 25, coating a photoresist on the second conductive film, exposing and developing, and then etching the second conductive film to form a second conductive layer 23. The second conductive layer 23 includes at least a second electrode 52 and a first signal line 71, as shown in Figure 12.

[0125] FIG13 is a schematic diagram of the second electrode plate in FIG12 , and FIG14 is another schematic diagram of the second electrode plate in FIG12 . In some exemplary embodiments, as shown in FIG12 , FIG13 , and FIG14 , the second electrode plate 51 may be disposed on a surface of the buffer layer 25 away from the substrate 10 . The second electrode plate 51 may be made of a metal material, such as copper (Cu) or aluminum (Al), and may serve as a gate metal electrode. The circumferential edge B2 of the second electrode plate 52 may be an edge surrounding the geometric center of the second electrode plate 52 in a plane parallel to the substrate 10 . The circumferential edge B2 of the second electrode plate 52 may include a sixth edge 521 and three seventh edges 522 . The sixth edge 521 is located at one end of the second electrode plate 52 in the second direction and may extend in a third direction. The seventh edge 522 is located at the other end of the second direction and may extend in the third direction. The other two seventh edges 522 may be located at either end of the second electrode plate 52 in the third direction and may extend in both directions. The second direction is perpendicular to the third direction, and both the second and third directions are parallel to the substrate 10 . A first location 524 may be defined on the sixth edge 521. One end of the first signal line 71 is connected to the first location 524, and the first location 524 serves as the first input terminal 525 of the second plate 51. A first opening 523 is defined at the connection between the two seventh edges 522. The first opening 523 may be rectangular, but is not limited thereto. For example, the shape of the first opening 523 may be triangular, or the first opening 523 may be located at other locations along the circumferential edge B2 of the second plate 52. In some exemplary embodiments, the first signal line 71 may be located on the same layer as the second plate 52. One end of the first signal line 71 is connected to the first input terminal 525. The material of the first signal line 71 may be the same as that of the second plate 52, and the first signal line 71 may serve as a gate metal line.

[0126] (4) Prepare the first insulating layer.

[0127] In some exemplary embodiments, preparing the first insulating layer includes: first depositing an interlayer dielectric film on the substrate of the formed second conductive layer 23, the interlayer dielectric film covering the gate metal layer, the gate insulating layer and the active layer, and the interlayer dielectric film constituting the first insulating layer 26, as shown in FIG14; and then opening vias on the first insulating layer 26 and the buffer layer 25, the vias including at least a first via 27 for exposing the first electrode 51, as shown in FIG15.

[0128] FIG15 is a schematic diagram of a first insulating layer in an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG15 , the first insulating layer 26 covers the surface of the second conductive layer 23 away from the substrate 10 and also covers the exposed portion of the buffer layer 25 away from the substrate 10. The first insulating layer 26 can be made of an inorganic insulating material, specifically any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer.

[0129] FIG16 is a schematic diagram of a first via hole in an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG16 , a first via hole 27 extends from the surface of the first insulating layer 26 away from the substrate 10 to the surface of the first electrode plate 51 away from the substrate 10. The first via hole 27 corresponds to the first opening 523 in a direction perpendicular to the substrate 10. When processing the first via hole 27, a hole can be first opened in the first insulating layer 26 to expose a portion of the surface of the buffer layer 25 away from the substrate 10. A further via hole can be opened in the exposed buffer layer 25 to expose a portion of the surface of the first electrode plate 51 away from the substrate 10, thereby forming the first via hole 27. In addition to the first via hole, other via holes can be provided, such as a via hole for exposing the active layer. When processing this via hole, a hole needs to be opened in the first insulating layer 26 until the active layer is away from the substrate 10.

[0130] (5) Prepare the third conductive layer.

[0131] In some exemplary embodiments, preparing the third conductive layer includes: depositing a third conductive film on a substrate 10 having a first insulating layer 26, coating a photoresist on the third conductive film, exposing and developing, and then etching the third conductive film to form a third conductive layer 24. The third conductive layer 24 includes at least a third electrode 53 and a second signal line 72, as shown in Figure 17.

[0132] In some exemplary embodiments, the mask used to form the third conductive layer 24 is designed based on the third electrode plate 53 having the second groove 531. The photoresist pattern formed after exposure and development using the mask has exposed areas and unexposed areas. The photoresist remains in the exposed areas, while the photoresist in the unexposed areas is removed, exposing the surface of the third conductive film. The etching process removes the third conductive film in the unexposed areas, while retaining the third conductive film in the exposed areas, thereby forming at least the third electrode plate 53 having the second groove 531.

[0133] FIG18 is a schematic diagram of the third electrode plate in FIG17 , and FIG19 is another schematic diagram of the third electrode plate in FIG17 . In some exemplary embodiments, as shown in FIG17 , FIG18 , and FIG19 , the third electrode plate 53 may be disposed on a surface of the first insulating layer 26 away from the substrate 10 . The third electrode plate 53 may be made of a metal material, such as copper (Cu) or aluminum (Al), and may serve as a source / drain electrode. A circumferential edge B3 of the third electrode plate 53 may be an edge surrounding the geometric center of the third electrode plate 53 in a plane parallel to the substrate 10 . The circumferential edge B3 of the third electrode plate 53 may include a second edge 532 and three eighth edges 533 . The second edge 532 is located at one end of the third electrode plate 53 in the second direction and may extend along a third direction. The eighth edge 533 is located at the other end of the second direction and may extend along the third direction. The other two eighth edges 533 may be located at either end of the third electrode plate 53 in the third direction and may extend in two directions, with the second direction being perpendicular to the third direction, and both the second and third directions being parallel to the substrate 10 . A second groove 531 may be provided on the second edge 532, extending through the third electrode plate 53 in a direction perpendicular to the substrate 10. The second groove 531 may be formed by recessing the second edge 532 toward the inner side of the third electrode plate 53. The inner side of the third electrode plate 53 may be the portion of the third electrode plate 53 near its geometric center. The second groove 531 forms a notch 70. The second groove 531 may be recessed toward the opposite eighth edge 533. The second groove 531 may be a rectangular groove, but is not limited thereto. For example, it may be an arc-shaped groove or an irregularly shaped groove. The groove width of the second groove 531 may be the maximum dimension of the second groove 531 in the third direction, i.e., L3. The groove depth of the second groove 531 may be the maximum dimension of the second groove 531 in the second direction, i.e., L4. In some exemplary embodiments, the groove width L3 of the second groove 531 may be 20 μm, and the groove depth L4 of the second groove 531 may be 10 μm, but is not limited thereto. The groove width L3 of the second groove 531 may be other values ​​within the range of 15 μm to 30 μm, and the groove depth L4 of the second groove 531 may be other values ​​within the range of 7 μm to 15 μm.

[0134] In some exemplary embodiments, as shown in Figures 17, 18, and 19, a second location 535 may be provided on the second edge 532. One end of the first signal line 72 is connected to the second location 535, and the second location 535 serves as a second input terminal 536. However, this is not limited to this. For example, the second location 535 may be located on the eighth edge 533. A via metal structure 534 is provided at the connection between the two eighth edges 533. However, this is not limited to this. For example, the via metal structure 534 may be located at other locations along the circumferential edge B3 of the third plate 53. In some exemplary embodiments, the second signal line 72 may be located on the same layer as the third plate 53. One end of the second signal line 72 is connected to the second input terminal 536. The material of the second signal line 72 may be the same as that of the third plate 53. The second signal line 72 may serve as a source / drain metal line.

[0135] After the third conductive layer 24 is prepared, the storage capacitor 50, the first signal line 71, and the second signal line 72 are all formed. FIG5 is a schematic diagram of a display substrate of an exemplary embodiment of the present disclosure, and FIG6 is a schematic cross-sectional diagram along the AA line in FIG5. In some exemplary embodiments, as shown in FIG5 and FIG6, the storage capacitor 50 may include a first electrode plate 51, a second electrode plate 52, and a third electrode plate 53 stacked in sequence on a square perpendicular to the substrate 10. The first electrode plate 51 may be disposed on the substrate 10, and the second electrode plate 52 may have a first input terminal 525 for connecting to the first signal line. The first electrode plate 51 and the third electrode plate 53 are both provided with a notch 70. In a direction perpendicular to the substrate, the notch 70 corresponds to the first input terminal 525, so that the first electrode plate 51 and the third electrode plate 53 are staggered from the first input terminal 525.

[0136] In some exemplary embodiments, as shown in FIG5 and FIG6 , the orthographic projection of the first electrode plate 51 on the substrate 10 may overlap with the orthographic projection of the third electrode plate 53 on the substrate 10, and the first electrode plate 51 and the third electrode plate 53 may be electrically connected via a metal hole structure 54. The metal hole structure 54 includes a first via 27 and a via metal structure 534 located within the first via 27. The via metal structure 534 may extend to the surface of the first electrode plate 51 away from the substrate 10. The first opening 523 of the second electrode plate 52 is arranged to correspond to the metal hole structure 54, so that the second electrode plate 52 avoids the metal hole structure 54.

[0137] FIG20 is an isometric view of a storage capacitor according to an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG6 and FIG20 , the circumferential edge of the first electrode plate 51 may include a first edge 512, on which a first groove 511 is provided, and the first groove 511 forms a notch 70. The circumferential edge of the third electrode plate 53 may include a second edge 532, on which a second groove 531 is provided, and the second groove 531 forms another notch 70. The circumferential edge of the second electrode plate 52 may include a sixth edge 521, on which a first input terminal 525 is provided. The first groove 511, the second groove 531, and the first input terminal 525 correspond in a direction perpendicular to the substrate 10, so that the first input terminal 525 can be staggered with both the first electrode plate 51 and the third electrode plate 53. The first edge 512, the second edge 532 and the sixth edge 521 are flush in a direction perpendicular to the substrate 10, the first groove 511 and the second groove 531 have the same groove shape, groove depth and groove width, the orthographic projection of the first groove 511 on the substrate 10 and the orthographic projection of the second groove 531 on the substrate 10 overlap, and the orthographic projection of the first input end 525 on the substrate 10 is approximately at the orthographic projection position of the groove opening of the first groove 511 on the substrate 10, but is not limited to this. For example, the first edge 512, the second edge 532 and the sixth edge 521 are staggered in a direction perpendicular to the substrate 10, and for example, at least one of the groove shape, groove depth and groove width of the first groove 511 and the second groove 531 is inconsistent, so that the orthographic projection of the first groove 511 on the substrate 10 and the orthographic projection of the second groove 531 on the substrate 10 partially overlap. The display substrate further includes a buffer layer 25, a first insulating layer 26 and a passivation layer (not shown in the figure). The buffer layer 25 is located at least between the first electrode plate 51 and the second electrode plate 52, and is also located in the first groove 511. The first insulating layer 26 is located at least between the second electrode plate 52 and the third electrode plate 53. The passivation layer is located at least on the surface of the third electrode plate 53 away from the second electrode plate 52 and is located in the second groove 531.

[0138] FIG21 is a schematic cross-sectional view taken along line BB in FIG5 , and FIG22 is another schematic cross-sectional view of the storage capacitor in FIG5 . In some exemplary embodiments, as shown in FIG5 , FIG21 , and FIG22 , the first signal line 71 and the second signal line 72 extend in the same direction. The first signal line 71 extends along the second direction, and one end of the first signal line 71 is connected to the first input terminal 525. The first signal line 71 and the second signal line 72 are arranged on different layers. The first signal line 71 is located on the surface of the buffer layer 25 away from the substrate 10, while the second signal line 72 is located on the surface of the first insulating layer 26 away from the substrate 10. Furthermore, the first signal line 71 and the second signal line 72 are staggered in a direction perpendicular to the substrate 10, such that the first input terminal 525 and the second input terminal are also staggered in a direction perpendicular to the substrate 10.

[0139] FIG23 is a schematic diagram of laser cutting of a storage capacitor according to an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG23 , when laser repair is used, the first signal line connected to the problematic capacitor is cut, and the cutting may reach the first position 521 adjacent to the storage capacitor and continue downward in a direction perpendicular to the substrate 10, reaching the substrate 10. In particular, the laser cutting position corresponds to the notch 70, so that only the first signal line and a small portion of the second electrode plate 52 are cut, while the third electrode plate 53 and the first electrode plate 51 are not cut. Even if the cut portion of the second electrode plate 52 melts, it will not contact the first electrode plate 51, thus avoiding a short circuit and allowing normal use, thereby improving the success rate of repairs.

[0140] Figure 24 is a schematic diagram of another display substrate of an exemplary embodiment of the present disclosure, and Figure 25 is a schematic diagram of the storage capacitor in Figure 24. In some exemplary embodiments, as shown in Figures 24 and 25, the storage capacitor 50 may have multiple first input terminals 525 and multiple second input terminals 536, and the storage capacitor 50 is connected to multiple adjacent other storage capacitors 50 through the first signal line 71 and the second signal line 72. In this example, the storage capacitor 50 may have three first input terminals 525 and three second input terminals 536, and the storage capacitor 50 is connected to three adjacent storage capacitors 50.

[0141] FIG26 is a schematic diagram of the second electrode plate in FIG25 . In some exemplary embodiments, as shown in FIG25 and FIG26 , the circumferential edge of the second electrode plate 52 may include three sixth edges 521 and one seventh edge 522. Each sixth edge 521 may have a first position 524, forming three first input terminals 525. This is not limiting. For example, the circumferential edge of the second electrode plate 52 may have two first positions 524, forming two first input terminals 525.

[0142] FIG27 is a schematic diagram of the third electrode plate in FIG25 . In some exemplary embodiments, as shown in FIG25 and FIG27 , the circumferential edge of the third electrode plate 53 may include three second edges 532 and one eighth edge 533. Each second edge 532 may have a second groove 531, forming three notches 70. The three second grooves 531 may all be rectangular grooves, and the groove depth and groove width of the three second grooves 531 may all be the same, but are not limited to this. For example, the groove body shapes of the three second grooves 531 may be different, and the groove depth and groove width of the three second grooves 531 may all be different. Each second edge 532 may have a second position 535, forming three second input terminals 536.

[0143] Figure 28 is a schematic diagram of the first electrode plate in Figure 25. In some exemplary embodiments, as shown in Figures 25 and 28, the circumferential edge of the first electrode plate 51 may include three first edges 512 and a fifth edge 513. Each first edge 512 may have a first groove 511, forming three notches 70. The three first grooves 511 may all be rectangular grooves. The groove depth and groove width of the three first grooves 511 may be the same, but not limited to this. For example, the groove body shapes of the three first grooves 511 may be different. For another example, the groove depth and groove width of the three first grooves 511 may be different.

[0144] In some exemplary embodiments, as shown in Figures 25 to 28, the three second grooves 531 may correspond one-to-one with the three first positions 5, and the three first grooves 511 may also correspond one-to-one with the three first positions 5, resulting in a one-to-one correspondence between the three second grooves 531 and the three first grooves 511. The orthographic projections of the second grooves 531 on the substrate and the orthographic projections of the first grooves 511 on the substrate also overlap one-to-one, and the orthographic projections of the first electrode plate 51 and the second electrode plate 52 on the substrate 10 do not overlap with the orthographic projection of the second input terminal 536 on the substrate 10.

[0145] In some exemplary embodiments, as shown in Figures 25 to 28, when laser repair is used, the second signal line connected to the problematic capacitor is cut, and the cutting may reach the second position 531 adjacent to the storage capacitor and continue downward in a direction perpendicular to the substrate 10, cutting to the substrate 10. In particular, the laser cutting position corresponds to the notch 70, so that only the second signal line and a small portion of the third electrode plate 53 are cut, and the second electrode plate 52 and the first electrode plate 51 are not cut. Even if the cut portion of the third electrode plate 53 melts, it will not contact the second electrode plate 52, thus avoiding a short circuit and allowing normal use, thereby improving the success rate of the repair.

[0146] FIG29 is a schematic diagram of another storage capacitor according to an exemplary embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG29 , the first plate 51 and the second plate 52 may both have a notch 70. The third plate 53 does not have a groove structure, but has a second input terminal 536, and the second plate 52 has a first input terminal 525. In a direction perpendicular to the substrate, the notch 70 corresponds to the second input terminal 536 on the third plate 53, so that the first plate 51 and the second plate 52 are staggered from the second input terminal 536; the first input terminal 525 and the second input terminal 536 are also staggered. However, this is not limiting. For example, the third plate 53 may have multiple second input terminals 536, and the first plate 51 and the second plate 52 may both have multiple notches 70. The notches 70 of the first plate 51 may correspond one-to-one with the second input terminal 536, and the notches 70 of the second plate 52 may correspond one-to-one with the second input terminal 536.

[0147] FIG30 is a schematic diagram of the second electrode plate in FIG29 , and FIG31 is a schematic diagram of the first electrode plate in FIG29 . In some exemplary embodiments, as shown in FIG29 to FIG31 , the circumferential edge of the first electrode plate 51 may include a third edge 514 having a third inwardly recessed groove 515 extending through the first electrode plate 51. The third groove 515 may be a rectangular groove, forming a notch 70. The width of the third groove 515 may be 15 μm to 30 μm, and the depth of the third groove 515 may be 7 μm to 15 μm. The circumferential edge of the second electrode plate 52 may include a fourth edge 526 having a fourth inwardly recessed groove 527 extending through the second electrode plate 52. The fourth groove 527 may be a rectangular groove, forming another notch 70. The third groove 515 and the fourth groove 527 have the same groove shape, groove width and groove depth, so that the orthographic projection of the third groove 515 on the substrate and the orthographic projection of the fourth groove 527 on the substrate overlap, but are not limited to this. For example, at least one of the groove shape, groove width and groove depth of the third groove 515 and the fourth groove 527 is inconsistent, so that the orthographic projection of the third groove 515 on the substrate and the orthographic projection of the fourth groove 527 on the substrate partially overlap, but do not completely overlap.

[0148] In some exemplary embodiments, as shown in FIG. 29 , when preparing the display substrate of this example, a first conductive layer 22, a buffer layer 25, an active layer (not shown), a gate insulating layer (not shown), a second conductive layer 23, a first insulating layer 26, and a third conductive layer 24 can be sequentially formed on the substrate to form the storage capacitor of this example. The mask used when preparing the first conductive layer 22 needs to be designed based on the first electrode plate 51 having the third groove 515, and the mask used when preparing the second conductive layer 23 needs to be designed based on the second electrode plate 52 having the fourth groove 527. When preparing the buffer layer 25, the buffer layer 25 is formed at least between the first electrode plate 51 and the second electrode plate 52, and also within the third groove 515 of the first electrode plate 51. When preparing the first insulating layer 26, the first insulating layer 26 is formed at least on the surface of the second electrode plate 52 near the third electrode plate 53, and also within the fourth groove 527 on the second electrode plate 52.

[0149] (6) Prepare a passivation layer.

[0150] In some exemplary embodiments, preparing the passivation layer includes depositing a passivation layer film on the third conductive layer to form a passivation layer, wherein the passivation layer covers the third conductive layer and the first insulating layer. The passivation layer film can be deposited using chemical vapor deposition technology. After the passivation layer is formed, the drive circuit layer of the display substrate is substantially completed.

[0151] (7) Prepare the light-emitting structure layer and the encapsulation structure layer.

[0152] In some exemplary embodiments, preparing the light-emitting structure layer and the encapsulation structure layer includes sequentially evaporating the light-emitting structure layer and depositing the encapsulation structure layer on the driving circuit layer obtained above to complete the preparation of the display substrate.

[0153] In combination with the above embodiments, the present disclosure displays a substrate with a notch, so that the storage capacitor will not affect the charge storage capacity of the capacitor. Even if the laser cuts to the first input end or the second output end during maintenance, it will not cause the two plates to melt and short-circuit, thereby improving the repair success rate, reducing screen scrapping caused by poor capacitance, and improving product yield and quality.

[0154] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a display area and a frame area located on at least one side of the display area, the frame area includes at least a gate drive circuit, the gate drive circuit includes at least a storage capacitor, a first signal line and a second signal line, and the storage capacitor includes a stacked first plate, a second plate and a third plate;

[0155] The preparation method comprises: forming a first conductive layer on a substrate, and disposing a first electrode in the first conductive layer;

[0156] A second conductive layer is formed on a side of the first conductive layer away from the substrate, the first signal line and the second electrode plate are arranged in the second conductive layer, and the second electrode plate has a first input terminal connected to the first signal line;

[0157] A third conductive layer is formed on a side of the second conductive layer away from the substrate, the second signal line and the third electrode plate are arranged in the third conductive layer, and the third electrode plate has a second input terminal connected to the second signal line;

[0158] Two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projection of the notches on the substrate is arranged to overlap with the orthographic projection of the first input terminal on the substrate, or overlap with the orthographic projection of the second input terminal on the substrate.

[0159] In some exemplary embodiments, a display device includes the aforementioned display substrate. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the present invention is not limited thereto.

[0160] The above-described embodiments merely represent several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed. However, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall still be defined by the appended claims.

Claims

1. A display substrate, wherein: The device comprises a display area and a frame area located at least on one side of the display area, wherein the frame area at least comprises a gate drive circuit, the gate drive circuit at least comprises a storage capacitor, a first signal line and a second signal line, and the storage capacitor comprises a first electrode plate, a second electrode plate and a third electrode plate stacked together; In a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer and a third conductive layer which are sequentially arranged on a substrate in a direction away from the substrate; The first electrode plate is disposed in the first conductive layer; The first signal line and the second electrode plate are arranged in the second conductive layer, and the second electrode plate has a first input terminal connected to the first signal line; The second signal line and the third electrode plate are arranged in the third conductive layer, and the third electrode plate has a second input terminal connected to the second signal line; Two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projection of the notches on the substrate is arranged to overlap with the orthographic projection of the first input end on the substrate, or overlap with the orthographic projection of the second input end on the substrate.

2. The display substrate according to claim 1, wherein: The first electrode plate and the third electrode plate are both provided with a notch, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the first input end on the substrate; Alternatively, both the first electrode plate and the second electrode plate are provided with a notch, and the orthographic projection of the notch on the substrate overlaps with the orthographic projection of the second input end on the substrate.

3. The display substrate according to claim 2, wherein: A first groove recessed inward is provided at a circumferential edge of the first electrode plate, and the first groove extends in a direction perpendicular to the substrate and penetrates the first electrode plate; A second groove recessed inward is provided on the circumferential edge of the third electrode plate, and the second groove extends in a direction perpendicular to the substrate and penetrates the third electrode plate; The first groove and the second groove both constitute the notch.

4. The display substrate according to claim 3, wherein: The circumferential edge of the first electrode plate at least includes a first edge, the first edge is located on a side of the first electrode plate close to the first input end, and the first groove is arranged on the first edge; The circumferential edge of the third electrode plate at least includes a second edge, the second edge is located on a side of the third electrode plate close to the first input end, and the second groove is arranged on the second edge; The first edge and the second edge are flush in a direction perpendicular to the substrate, and an orthographic projection of the first groove on the substrate and an orthographic projection of the second groove on the substrate at least partially overlap.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first groove on the substrate is within the range of the orthographic projection of the second groove on the substrate; or, the orthographic projection of the second groove on the substrate is within the range of the orthographic projection of the first groove on the substrate; Alternatively, the orthographic projection of the first groove on the substrate overlaps with the orthographic projection of the second groove on the substrate.

6. The display substrate according to claim 5, wherein: In a direction parallel to the base, the first groove and the second groove are both in the shape of a rectangular groove or an arc groove.

7. The display substrate according to claim 5, wherein: The width of the first groove and the second groove are both 15 μm to 30 μm, and the depth of the first groove and the second groove are both 7 μm to 15 μm.

8. The display substrate according to claim 2, wherein: A third groove recessed inward is provided on the circumferential edge of the first electrode plate, and the third groove extends in a direction perpendicular to the substrate and penetrates the first electrode plate; A fourth groove recessed inward is provided on the circumferential edge of the second electrode plate, and the fourth groove extends in a direction perpendicular to the substrate and penetrates the second electrode plate; The third groove and the fourth groove both constitute the notch, and the orthographic projection of the third groove on the substrate and the orthographic projection of the fourth groove on the substrate at least partially overlap.

9. The display substrate according to claim 8, wherein: The orthographic projection of the third groove on the substrate overlaps with the orthographic projection of the fourth groove on the substrate, the groove width of the third groove is 15 μm to 30 μm, and the groove depth of the third groove is 7 μm to 15 μm.

10. The display substrate according to any one of claims 1 to 9, wherein: The orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate are arranged to at least partially overlap; The first electrode plate and the third electrode plate are electrically connected via a metal hole structure, and the second electrode plate is provided with a first opening for avoiding the metal hole structure.

11. The display substrate according to any one of claims 2 to 9, wherein: The second electrode plate is provided with a plurality of the first input terminals, and the third electrode plate is provided with a plurality of the second input terminals; There are multiple notches on the first electrode plate and multiple notches on the third electrode plate, and they correspond one-to-one to the first input terminals; or there are multiple notches on the first electrode plate and multiple notches on the second electrode plate, and they correspond one-to-one to the second input terminals.

12. The display substrate according to any one of claims 1 to 9, wherein: The display substrate further includes a buffer layer and a first insulating layer. The buffer layer is arranged to cover a surface of the first conductive layer away from the base, and the first insulating layer is arranged to cover a surface of the second conductive layer away from the base.

13. A display device, wherein: It comprises the display substrate as claimed in any one of claims 1 to 12.

14. A method for preparing a display substrate, wherein: The display substrate includes a display area and a frame area located at least on one side of the display area, the frame area includes at least a gate drive circuit, the gate drive circuit includes at least a storage capacitor, a first signal line and a second signal line, and the storage capacitor includes a stacked first plate, a second plate and a third plate; The preparation method comprises: forming a first conductive layer on a substrate, wherein the first electrode plate is disposed in the first conductive layer; A second conductive layer is formed on a side of the first conductive layer away from the substrate, the first signal line and the second electrode plate are arranged in the second conductive layer, and the second electrode plate has a first input terminal connected to the first signal line; A third conductive layer is formed on a side of the second conductive layer away from the substrate, the second signal line and the third electrode plate are arranged in the third conductive layer, and the third electrode plate has a second input terminal connected to the second signal line; Two of the first electrode plate, the second electrode plate and the third electrode plate are provided with notches, and the orthographic projection of the notches on the substrate is arranged to overlap with the orthographic projection of the first input end on the substrate, or overlap with the orthographic projection of the second input end on the substrate.

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