Operation method for memory apparatus, and memory apparatus, device and storage medium

Abstract

Provided in the present disclosure are an operation method for a memory apparatus, and a memory apparatus, a device and a storage medium. The operation method for a memory apparatus comprises: providing a semiconductor device, which comprises: a substrate, a deep N-well region located in the substrate, a P-well region located in the deep N-well region, and a plurality of transistor structures located in the P-well region, wherein each of the transistor structures comprises a gate, and a source and a drain that are located at two sides of the gate respectively; and applying a first voltage to a port of the gate, applying a second voltage to a port of the deep N-well region, and applying a third voltage to a port of the P-well region, wherein when a first operation is executed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; and when a second operation is executed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

Description

Memory device operating method, memory device, apparatus, and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 1, 2023, with application number 202311125480.X, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and more particularly to an operating method of a memory device, a memory device, an apparatus, and a storage medium. Background Art

[0004] Resistive random access memory (RRAM) is a type of non-volatile memory that can store data by changing its resistance state.

[0005] The purpose of a reset is to change the RRAM's resistance state from a low resistance state (LRS) to a high resistance state (HRS). At this point, the RRAM's resistance is low and the IR drop effect is significant. After the current flows through the MOS transistor, most of the voltage is divided away, resulting in a low current flowing through the RRAM and making it difficult to reset.

[0006] As the feature size of process nodes continues to decrease, the distance between the source and drain terminals of the device is getting shorter and shorter. However, in RRAM circuits, the operating voltage cannot be reduced due to the influence of RRAM characteristics, resulting in an enhanced electric field between the source and drain, drain-induced barrier lowering (DIBL) and subsequent bulk punch-through.

[0007] Therefore, it is necessary to propose a solution to solve the problems arising from the above different situations.

[0008] Summary of the Invention

[0009] The present disclosure provides a memory device operating method, a memory device, an apparatus, and a storage medium to at least solve the above technical problems existing in the prior art.

[0010] According to a first aspect of the present disclosure, there is provided a method for operating a memory device, comprising:

[0011] A semiconductor device is provided, comprising: a substrate, a deep N-well region located in the substrate, a P-well region located in the deep N-well region, and a plurality of transistor structures located in the P-well region, wherein the transistor structures include a gate, and a source and a drain located on both sides of the gate, respectively;

[0012] A first voltage is applied to the port of the gate, a second voltage is applied to the port of the deep N-well region, and a third voltage is applied to the port of the P-well region; wherein,

[0013] When performing the first operation, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage;

[0014] When the second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0015] In one embodiment, the method further comprises:

[0016] When the third operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0017] In one embodiment, the second operation is an initialization operation, and the third operation is a reset operation.

[0018] In one embodiment, the semiconductor device further includes: a resistive switching unit, one end of which is connected to the drain through a first connection layer; a bit line, which is connected to the other end of the resistive switching unit; a source line, which is connected to the source through a second connection layer; and a word line, which is connected to the gate.

[0019] The applying the first voltage to the port of the gate comprises: applying the first voltage to the port of the gate via the word line;

[0020] The method further includes applying a fourth voltage to the drain via the bit line, wherein the fourth voltage is a positive voltage; and grounding the source via the source line.

[0021] In one embodiment, when the first operation is performed, the third voltage is greater than or equal to -1V and less than 0V;

[0022] When the second operation or the third operation is performed, the third voltage is in a range greater than 0V and less than or equal to 1V.

[0023] According to a second aspect of the present disclosure, a memory device is provided, comprising:

[0024] A semiconductor device comprising: a substrate, a deep N-well region within the substrate, a P-well region within the deep N-well region, and a plurality of transistor structures within the P-well region, the transistor structures comprising a gate, and a source and a drain respectively located on either side of the gate;

[0025] A voltage module is configured to apply a first voltage to the port of the gate, a second voltage to the port of the deep N-well region, and a third voltage to the port of the P-well region; wherein,

[0026] When performing the first operation, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage;

[0027] When the second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0028] In one embodiment, when the third operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0029] In one embodiment, the second operation is an initialization operation, and the third operation is a reset operation.

[0030] In one embodiment, the semiconductor device further includes: a resistive switching unit, one end of which is connected to the drain through a first connection layer; a bit line, which is connected to the other end of the resistive switching unit; a source line, which is connected to the source through a second connection layer; and a word line, which is connected to the gate.

[0031] The voltage module is further configured to apply a first voltage to the terminal of the gate via the word line;

[0032] The voltage module is further configured to apply a fourth voltage to the drain via the bit line, wherein the fourth voltage is a positive voltage; and to ground the source via the source line.

[0033] In one embodiment, when the first operation is performed, the third voltage is greater than or equal to -1V and less than 0V;

[0034] When the second operation or the third operation is performed, the third voltage is in a range greater than 0V and less than or equal to 1V.

[0035] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0036] at least one processor; and

[0037] a memory communicatively connected to the at least one processor; wherein,

[0038] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0039] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0040] The memory device operating method, memory device, equipment, and storage medium disclosed herein form a deep N-well region in the substrate, which isolates the substrate from the P-well region. This allows for independent control of the voltage in the P-well region. By applying a negative voltage to the P-well region, the transistor structure is less likely to turn on, effectively reducing leakage current caused by punch-through. Furthermore, during normal initialization (forming), a positive voltage is applied to the P-well region, making the transistor structure more likely to turn on. This reduces the transistor threshold voltage and increases the on-state current (Idsat).

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0043] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0044] FIG1 is a circuit diagram of a semiconductor device in the related art.

[0045] FIG. 2 is a circuit diagram of a transistor structure in the related art.

[0046] FIG3 is a diagram showing the drain current characteristics of a transistor structure under the body punch-through effect.

[0047] FIG4 is a flow chart of an operating method of a memory device according to an embodiment of the present disclosure.

[0048] FIG5 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure.

[0049] FIG6 is a circuit diagram of a transistor structure provided by an embodiment of the present disclosure.

[0050] FIG. 7 is a diagram showing circuit simulation results of performing the first operation.

[0051] FIG8 is a diagram showing circuit simulation results of performing the second operation.

[0052] FIG9 shows a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0054] Figure 1 is a circuit diagram of a semiconductor device in related art. In related art, the transistor structure used in RRAM is a 0.9V device. During operation, a high voltage is applied to BL0. This increases the probability of leakage-induced barrier lowering and body punch-through in the entire memory chip, and the voltage drop can lead to insufficient excitation.

[0055] FIG2 is a circuit diagram of a transistor structure in the related art. Because the transistor structure in the related art does not have a deep N-well region, it is impossible to independently control the potential of the P-well region, that is, the BULK end in the figure. Therefore, the semiconductor device in the related art is more prone to drain-induced barrier lowering and body punch-through effects.

[0056] Figure 3 shows the drain current characteristics of a transistor structure under the body punchthrough effect. Figure 3(a) shows an example of a severe body punchthrough effect in the region above the threshold. For the drain voltage range shown in Figure 3(a), the device operates under punchthrough conditions. Figure 3(b) shows the drain-induced barrier lowering effect and body punchthrough effect on the subthreshold current of devices with different channel lengths. The device with a channel length of 7μm exhibits long channel characteristics, that is, the subthreshold current is independent of the drain voltage. However, for the device with a channel length of 1.5μm, the long channel characteristics completely disappear, the subthreshold swing is even worse, and the device cannot be turned off. Therefore, the occurrence of drain-induced barrier lowering and body punchthrough in semiconductor devices will affect the performance of the device itself, causing the device to malfunction.

[0057] An operating method of a memory device provided by an embodiment of the present disclosure will be introduced below. FIG4 is a flowchart of the operating method of the memory device provided by an embodiment of the present disclosure, and steps 401-402 of FIG4 will be described in detail below.

[0058] Step 401, see Figure 5, provide a semiconductor device 100, the semiconductor device 100 includes: a substrate 10, a deep N-well region 11 located in the substrate 10, and a P-well region 12 located in the deep N-well region 11, and a plurality of transistor structures located in the P-well region 12, the transistor structure including a gate 21, and a source 22 and a drain 23 respectively located on both sides of the gate 21.

[0059] In some embodiments, the substrate 10 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

[0060] Then, a deep N-well region 11 is formed in the substrate 10, a P-well region 12 is formed in the deep N-well region 11, and multiple transistor structures are formed in the P-well region 12. The deep N-well region 11 isolates the substrate 10 from the P-well region 12, so that the voltage of the P-well region can be controlled separately.

[0061] In one embodiment, the transistor structure includes a gate 21, which includes a gate dielectric layer 211 located on the P-well region 12 and a gate conductive layer 212 located on the gate dielectric layer 211. The material of the gate dielectric layer 211 includes, but is not limited to, an oxide, such as silicon oxide. The material of the gate conductive layer 212 can be any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0062] The transistor structure further includes a source 22 and a drain 23 located on both sides of the gate 21. Specifically, as shown in FIG5 , the source 22 and the drain 23 are located in the P-well region 12. In the embodiment of the present disclosure, the source 22 and the drain 23 are N-type doped regions.

[0063] In one embodiment, the semiconductor device 100 further includes: a resistive switching unit 40, one end of which is connected to the drain 23 through a first connection layer 31; a bit line BL, which is connected to the other end of the resistive switching unit 40; a source line SL, which is connected to the source 22 through a second connection layer 32; and a word line WL, which is connected to the gate 21.

[0064] Specifically, the first connection layer 31 includes a first connection line 311 , a first conductive layer 312 , and a second connection line 313 , which are sequentially arranged from bottom to top.

[0065] In one embodiment, the materials of the first connecting wires 311 and the second connecting wires 313 and the first conductive layer 312 may include suitable conductive materials such as metal materials, barrier metal materials, or combinations thereof. The materials of the first connecting wires 311 and the second connecting wires 313 may be the same as or different from the material of the first conductive layer 312.

[0066] In one embodiment, materials of the bit lines BL, the source lines SL, and the word lines WL include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0067] In one embodiment, the semiconductor device 100 further includes: a first doped region 51 located in the P-well region 12, a second doped region 52 located in the deep N-well region 11, and a third doped region 53 located in the substrate 10. The first doped region 51 is configured to receive a voltage applied to the P-well region 12, the second doped region 52 is configured to receive a voltage applied to the deep N-well region 11, and the third doped region 53 is configured to receive a voltage applied to the substrate 10. The first doped region 51 is a P-type doped region, the second doped region 52 is an N-type doped region, and the third doped region 53 is a P-type doped region.

[0068] Figure 6 is a circuit diagram of a transistor structure provided by an embodiment of the present disclosure. As shown in Figure 6, the transistor structure of the present disclosure, compared to transistor structures in related art, has an additional deep N-well region (DNW), allowing for independent control of the potentials at the ends of the deep N-well region (DNW) and the P-well region (BULK).

[0069] Step 402, applying a first voltage to the port of the gate 21, applying a second voltage to the port of the deep N-well region 11, and applying a third voltage to the port of the P-well region 12; wherein, when performing the first operation, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; when performing the second operation, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0070] In the disclosed embodiments, a deep N-well region is formed in the substrate to isolate the substrate from the P-well region, allowing the voltage of the P-well region to be independently controlled. By applying a negative voltage to the P-well region, the transistor structure is less likely to turn on, effectively reducing the leakage current caused by punch-through. Simultaneously, during normal initialization (forming), a positive voltage is applied to the P-well region, making the transistor structure more likely to turn on, thereby reducing the transistor threshold voltage and increasing the on-state current (Idsat).

[0071] In one embodiment, the method further includes: when performing the third operation, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0072] In the disclosed embodiment, a positive voltage is applied to the P-well region, so that the reset loop is turned on from the P-well region through the PN junction. There is no voltage division of the transistor, which is easier to operate and has a high success rate. In addition, all RRAMs share the same P-well region, so they can be reset in batches, reducing operation time.

[0073] In one embodiment, the second operation is an initialization (Forming) operation, and the third operation is a reset (Reset) operation.

[0074] In one embodiment, applying the first voltage to the port of the gate 21 includes: applying the first voltage to the port of the gate 21 via the word line WL;

[0075] The method further includes: applying a fourth voltage to the drain 23 via the bit line BL, wherein the fourth voltage is a positive voltage; and grounding the source 22 via the source line SL.

[0076] As shown in FIG6 , the port (PSUB) of the substrate 10 is also grounded.

[0077] For MOS devices, the substrate and gate serve the same purpose. Since a positive voltage on the gate turns on the transistor, a negative voltage on the substrate can counteract this effect. Therefore, a negative voltage on the substrate increases the threshold voltage of the gate, making it more difficult for the transistor to turn on. In the disclosed embodiments, the P-well region serves as the substrate.

[0078] The first operation is further explained below in conjunction with the following formula (1):

[0079] In formula (1), V th is the threshold voltage, V th0 is the threshold voltage under zero bias conditions, γ is the swing coefficient, is the surface barrier height, V SB is the reverse voltage between the source / drain and the substrate, that is, V SB =V s -V B , usually V B =V S , but when the substrate voltage is negative, that is, V B When it drops, V SB increases, thereby increasing the threshold voltage V th .

[0080] FIG. 7 is a diagram showing circuit simulation results of performing the first operation.

[0081] In this embodiment, when the semiconductor device is turned off, a first voltage Vgs applied to the gate port is 0 V, a second voltage Vdnw applied to the deep N-well port is 0.9 V, and a third voltage Vbulk applied to the P-well port is -0.5 V. When 1024 NMOS transistors are connected in series in the RRAM array and the width-to-length ratio of the NMOS transistors is 270 μm / 270 μm, the simulation results are shown in FIG7 .

[0082] As shown in FIG7 , curve M0 is a simulation curve of the transistor structure in the embodiment of the present disclosure, and curve M1 is a simulation curve of the transistor structure in the related art. When the drain voltage Vd=2.5V is selected, the leakage current of M0 is 3.596nA, and the leakage current of M1 is 27.3291nA. It can be seen that after adding the deep N-well region, by giving the P-well region a negative voltage, the transistor structure is not easily turned on. When the device is in the off state, the off current Ioff is significantly reduced, thereby achieving the effect of reducing punch-through.

[0083] The second operation is further explained below in conjunction with formula (2):

[0084] Among them, I in formula (2) d is the drain current, is the width-to-length ratio of the MOS tube, μ n is the electron mobility, C ox is the oxide layer capacitance, V GS is the gate-source voltage, V th is the threshold voltage, V DS is the drain-source voltage.

[0085] Combined with the above formula (1), in this embodiment, when a positive voltage is applied to the substrate, that is, when Vbulk is a positive voltage, the threshold voltage V in formula (1) is th Decreases when V th When it decreases, substitute it into formula (2) to get the drain current I d Increase.

[0086] FIG8 is a diagram showing circuit simulation results of performing the second operation.

[0087] When the semiconductor device is turned on, a first voltage Vgs = 1V is applied to the gate port, a second voltage Vdnw = 0.9V is applied to the deep N-well port, and a third voltage Vbulk = 1V is applied to the P-well port. When 1024 NMOS transistors are connected in series in the RRAM array and the width-to-length ratio of the NMOS transistors is 270μm / 270μm, the simulation results are shown in FIG8 .

[0088] As shown in Figure 8, curve M0 in the figure is a simulation curve of the transistor structure in the embodiment of the present disclosure, and curve M1 is a simulation curve of the transistor structure in the related art. When the drain voltage Vd=2.5V is selected, the on-current Idsat of M0 is 35.7456mA, and the on-current Idsat of M1 is 31.96mA. It can be seen that after adding the deep N-well region, the transistor structure is easily turned on by giving a positive voltage to the P-well region, thereby reducing the transistor threshold voltage and increasing the on-current (Idsat), thereby enhancing the on-characteristics of the device during normal conduction.

[0089] In one embodiment, when the first operation is performed, the third voltage is greater than or equal to -1V and less than 0V; when the second operation or the third operation is performed, the third voltage is greater than 0V and less than or equal to 1V.

[0090] The present disclosure also provides a memory device, comprising:

[0091] A semiconductor device 100 includes a substrate 10, a deep N-well region 11 within the substrate 10, a P-well region 12 within the deep N-well region 11, and a plurality of transistor structures within the P-well region 12, wherein the transistor structures include a gate 21, and a source 22 and a drain 23 located on either side of the gate 21 (see FIG. 5 ).

[0092] A voltage module (not shown) is configured to apply a first voltage to the port of the gate 21, a second voltage to the port of the deep N-well region 11, and a third voltage to the port of the P-well region 12; wherein,

[0093] When performing the first operation, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage;

[0094] When the second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0095] In some embodiments, the substrate 10 can be a single-element semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0096] Then, a deep N-well region 11 is formed in the substrate 10, a P-well region 12 is formed in the deep N-well region 11, and multiple transistor structures are formed in the P-well region 12. The deep N-well region 11 isolates the substrate 10 from the P-well region 12, so that the voltage of the P-well region can be controlled separately.

[0097] In one embodiment, the transistor structure includes a gate 21, which includes a gate dielectric layer 211 located on the P-well region 12 and a gate conductive layer 212 located on the gate dielectric layer 211. The material of the gate dielectric layer 211 includes, but is not limited to, an oxide, such as silicon oxide. The material of the gate conductive layer 212 can be any material with good conductivity, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), or copper (Cu).

[0098] The transistor structure further includes a source 22 and a drain 23 located on both sides of the gate 21. Specifically, as shown in FIG5 , the source 22 and the drain 23 are located in the P-well region 12. In the embodiment of the present disclosure, the source 22 and the drain 23 are N-type doped regions.

[0099] In one embodiment, the semiconductor device 100 further includes: a resistive switching unit 40, one end of which is connected to the drain 23 through a first connection layer 31; a bit line BL, which is connected to the other end of the resistive switching unit 40; a source line SL, which is connected to the source 22 through a second connection layer 32; and a word line WL, which is connected to the gate 21.

[0100] Specifically, the first connection layer 31 includes a first connection line 311 , a first conductive layer 312 , and a second connection line 313 , which are sequentially arranged from bottom to top.

[0101] In one embodiment, the materials of the first connecting wires 311 and the second connecting wires 313 and the first conductive layer 312 may include suitable conductive materials such as metal materials, barrier metal materials, or combinations thereof. The materials of the first connecting wires 311 and the second connecting wires 313 may be the same as or different from the material of the first conductive layer 312.

[0102] In one embodiment, materials of the bit lines BL, the source lines SL, and the word lines WL include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0103] In one embodiment, the semiconductor device 100 further includes: a first doped region 51 located in the P-well region 12, a second doped region 52 located in the deep N-well region 11, and a third doped region 53 located in the substrate 10. The first doped region 51 is configured to receive a voltage applied to the P-well region 12, the second doped region 52 is configured to receive a voltage applied to the deep N-well region 11, and the third doped region 53 is configured to receive a voltage applied to the substrate 10. The first doped region 51 is a P-type doped region, the second doped region 52 is an N-type doped region, and the third doped region 53 is a P-type doped region.

[0104] In one embodiment, when the third operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

[0105] In the disclosed embodiment, a positive voltage is applied to the P-well region, so that the reset loop is turned on from the P-well region through the PN junction. There is no voltage division of the transistor, which is easier to operate and has a high success rate. In addition, all RRAMs share the same P-well region, so they can be reset in batches, reducing operation time.

[0106] In one embodiment, the second operation is an initialization operation, and the third operation is a reset operation.

[0107] In one embodiment, the voltage module is configured to apply the first voltage to the port of the gate 21 , comprising: the voltage module applying the first voltage to the port of the gate 21 via the word line WL;

[0108] The voltage module is further configured to apply a fourth voltage to the drain 23 via the bit line BL, wherein the fourth voltage is a positive voltage; and to ground the source 22 via the source line SL.

[0109] As shown in FIG6 , the port (PSUB) of the substrate 10 is also grounded.

[0110] In one embodiment, when the first operation is performed, the third voltage range is greater than or equal to -1V and less than 0V; when the second operation or the third operation is performed, the third voltage range is greater than 0V and less than or equal to 1V.

[0111] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0112] FIG9 shows a schematic block diagram of an example electronic device 900 that can be used to implement an embodiment of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0113] As shown in Figure 9, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, ROM 902, and RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0114] Various components in the device 900 are connected to the I / O interface 905, including an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0115] The computing unit 901 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the method for operating a memory device. For example, in some embodiments, the method for operating a memory device can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 908. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the method for operating a memory device described above can be performed. Alternatively, in other embodiments, the computing unit 901 can be configured to perform the method for operating a memory device by any other appropriate means (e.g., by means of firmware).

[0116] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system comprising at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0118] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0120] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0121] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0122] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0123] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0124] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for operating a memory device, wherein: include: A semiconductor device is provided, the semiconductor device comprising: a substrate, a deep N-well region located in the substrate, a P-well region located in the deep N-well region, and a plurality of transistor structures located in the P-well region, the transistor structure comprising a gate, and a source and a drain located at both sides of the gate respectively; A first voltage is applied to the port of the gate, a second voltage is applied to the port of the deep N-well region, and a third voltage is applied to the port of the P-well region; wherein, When the first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; When the second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

2. The method according to claim 1, wherein: The method further comprises: When the third operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

3. The method according to claim 2, wherein: The second operation is an initialization operation, and the third operation is a reset operation.

4. The method according to claim 1, wherein: The semiconductor device further comprises: a resistive switching unit, one end of which is connected to the drain through a first connection layer; a bit line, which is connected to the other end of the resistive switching unit; a source line, which is connected to the source through a second connection layer; and a word line, which is connected to the gate. The applying the first voltage to the port of the gate comprises: applying the first voltage to the port of the gate via the word line; The method further includes: applying a fourth voltage to the drain via the bit line, wherein the fourth voltage is a positive voltage; and grounding the source via the source line.

5. The method according to claim 2, wherein: When the first operation is performed, the third voltage is greater than or equal to -1V and less than 0V; When the second operation or the third operation is performed, the third voltage is in a range greater than 0V and less than or equal to 1V.

6. A memory device, wherein: The memory device comprises: A semiconductor device, comprising: a substrate, a deep N-well region located in the substrate, a P-well region located in the deep N-well region, and a plurality of transistor structures located in the P-well region, The transistor structure includes a gate, and a source and a drain respectively located on both sides of the gate; A voltage module is configured to apply a first voltage to the port of the gate, a second voltage to the port of the deep N-well region, and a third voltage to the port of the P-well region; wherein, When the first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; When the second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

7. The memory device according to claim 6, wherein: When the third operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a positive voltage.

8. The memory device according to claim 7, wherein: The second operation is an initialization operation, and the third operation is a reset operation.

9. The memory device according to claim 6, wherein: The semiconductor device further comprises: a resistive switching unit, one end of which is connected to the drain through a first connection layer; a bit line, which is connected to the other end of the resistive switching unit; a source line, which is connected to the source through a second connection layer; and a word line, which is connected to the gate. The voltage module is further configured to apply a first voltage to the port of the gate via the word line; The voltage module is further configured to apply a fourth voltage to the drain via the bit line, wherein the fourth voltage is a positive voltage; and to ground the source via the source line.

10. The memory device according to claim 7, wherein: When the first operation is performed, the third voltage is in a range of greater than or equal to -1V and less than 0V; When the second operation or the third operation is performed, the third voltage is in a range greater than 0V and less than or equal to 1V.

11. An electronic device, wherein: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-5.

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