Semi-insulating sic-substrate for a semiconductor device

Abstract

Method for manufacturing a semiconductor device (1), comprising the steps of providing a semi-insulating SiC-substrate (100) with a predefined first thickness ( d1), incorporating an interstitial (i) on a Si-face (110 ) and / or on a C-face (120) of the semi-insulating SiC-substrate (100) and forming a doped SiC-substrate (100) of a first conductivity type or a second conductivity type by diffusing the interstitial (i).

Description

[0001] P2023,0858 WO E / P220366WO01 August 28, 2023 - 1 - Description Semi-insulating SiC-substrate for a semiconductor device The present disclosure relates to a method of manufacturing a semiconductor device by doping semi-insulating (SI) SiC- substrates for high voltage (HV) applications and a semiconductor device comprising a doped semi-insulating SiC- substrate. For the manufacture of high-voltage devices, a thick, lightly doped layer is usually required. Devices with a blocking voltage above 10kV need an epilayer, which is much thicker than 100µm with a doping concentration of less than 1E14 cm-3 to reach an electrical resistivity of approximately 1E5 Ohm*cm. Unfortunately, these layers are extremely expensive. SiC semi-insulating (SI) substrates are inexpensive. But the issue is that the resistivity of SI SiC-substrates is higher than 1E7 Ohm*cm. There is a need for inexpensive layers for high-voltage devices with sufficiently low resistivity. It is an object to manufacture a low coat semiconductor device while still obtaining a semiconductor device with a sufficiently low resistivity for high voltage applications. This object is solved by the features of the independent claims. Advantageous embodiments are indicated in the dependent claims. Embodiments of the disclosure, for instance as claimed in the independent claims, address the above shortcomings in the art in whole or in part. Further embodiments of the semiconductor P2023,0858 WO E / P220366WO01 August 28, 2023 - 2 - device and of the method for manufacturing the semiconductor device are subject matter of the further claims. There is provided a method for manufacturing a semiconductor device, comprising the steps of providing a semi-insulating SiC-substrate with a predefined first thickness, incorporating an interstitial on a Si-face and / or on a C-face of the semi-insulating SiC-substrate and forming a doped SiC- substrate of a first conductivity type or a second conductivity type by diffusing the interstitial. The main advantage of a semi-insulating SiC-substrate is the cost. Unlike conductive SiC, SI-SiC does not need to be cut 4° off-axis for epigrowth. The reduced loss of material makes SI SiC-substrates less expensive than conductive SiC- substrates. A less expensive material will allow the manufacture of less expensive high-voltage devices. A semi-insulating SiC-substrate is provided with a predefined thickness. The thickness depends on a preferred application and a preferred parameter, like the blocking voltage. A semi-insulating SiC-substrate is a substrate whose resistivity ranges between 1E5-1E9 Ohm*cm at RT. In order to obtain SI-SiC the background doping concentration (N_d) must be reduced and the concentration of semiconductor deep levels (N_t), which can trap charge carriers must be increased. This second step is necessary, because it is difficult to reduce the background doping concentrations (N_d) to below 1E10 cm- 3. A semi-insulating SiC is obtained when the concentration of semiconductor deep levels (N_t) is larger than the background doping concentrations (N_d). In this case, charge carriers are trapped by the deep levels and the Fermi level P2023,0858 WO E / P220366WO01 August 28, 2023 - 3 - is pinned close to such deep levels. In the case, where N_t is smaller than N_d, the Fermi level is close to the conduction band, thus little charge carrier trapping occurs and no semi-insulating SiC is obtained. After that, incorporation of the interstitial is carried out on the Si-face or on the C-face or on both faces, such that a doped SiC-substrate is formed by diffusing the interstitial. The doped SiC-substrate is of a first conductivity type, which may be n-type, i.e. it may be n-doped. Alternatively, the doped SiC-substrate is of a second conductivity type, which is opposite to the first conductivity type. The second conductivity type may be p-type, i.e. the SiC-substrate may be p-doped. A SI-SiC substrate, as such, cannot be employed for high- voltage device manufacture due to its poor conductivity. Thus, the resistivity of the SI SiC-substrate, which is approximately 1E9 Ohm*cm has to be decreased. The resistivity is decreased by incorporating interstitials. For incorporating the interstitial a standard ion beam technique is used with energies below 10keV at a dose range of 1E10–1E16 ions / cm2. The smaller the energy for incorporating the interstitial, the further the manufacturing cost of the SiC-substrate are reduced and therefore the cost of a semiconductor device. Alternatively, for incorporating the interstitial a thermal annealing at a first temperature in the range between 1200°C and 1600°C in an environment rich in elements of the interstitial is used. P2023,0858 WO E / P220366WO01 August 28, 2023 - 4 - Alternatively for incorporating the interstitial a plasma- immersion ion implantation (PIII) is used with energies from 1keV to 15keV at a dose range of 1E10-1E16 ions / cm2. Diffusing of the interstitial is facilitated by annealing the semi-insulating SiC-substrate at a second temperature for a second period of time, such that the concentration of the interstitial is uniform along the depth of the doped SiC- substrate. For this annealing step, for example a resistive furnace is used. The second temperature ranges between 1200°C and 1800°C and the second period of time ranges between 20 min and 48h. Furthermore the second temperature ranges preferably between 1500°C and 1700°C and the second period of time ranges preferably between 30 min and 24h. For incorporating the interstitial a group II element is provided. The used material for incorporating the interstitial can be any chemical element from group II elements. For incorporating the interstitial for example Beryllium is provided. In this case an n-type doped SiC- substrate is created. Beryllium interstitials behave as double donor for the Fermi level energy values of interest for semi-insulating SiC. Beryllium interstitials are also a fast diffusing species, via an interstitial mechanism with a low activation barrier of 3.1 eV. For these reasons, Beryllium is used to decrease the resistivity of the SI SiC- substrates, for example, SI-4H-SiC-substrate. The diffusivity of Beryllium interstitials is approximately 6E-9 cm2 / s at 1700°C. This means that for example during an 1h annealing at 1700°C, Beryllium interstitials diffuse more than 50µm. P2023,0858 WO E / P220366WO01 August 28, 2023 - 5 - Diffusion time and temperature can be adjusted so to make the concentration of Beryllium interstitials uniform along the whole substrate depth. Alternatively, for incorporating the interstitial a group VII element is provided. The used material for incorporating the interstitial can be any chemical element from group VII elements. For incorporating the interstitial for example Fluorine is provided. In this case a p-type doped SiC- substrate is created. The use of a SI-SiC substrate for HV can also lead to thinner devices. For example, a device with a blocking voltage above 10 kV, would normally need a 100µm thick epilayer. A 100µm thick epilayer is grown on a 350µm thick substrate. Such a substrate is for example a conductive SiC-substrate. This makes a 450µm thick device. However, if a 350µm thick SI- substrate is used, this can be thinned down to 110 µm. 100µm are employed as drift layer and 10µm are used as cathode. Thus, the semi-insulating SiC-substrate is thinned down to the first thickness before incorporating interstitials depending on a preferred application or a parameter, e.g. depending on a blocking voltage. The doped SiC-substrate can be used for various applications by processing it further. According to an embodiment the method further comprises, implanting of a group III element on a first side of the doped SiC-substrate, thus forming an anode and implanting of a group V element on a second side of the doped SiC- P2023,0858 WO E / P220366WO01 August 28, 2023 - 6 - substrate, which is arranged opposite of the first side, and thus forming a cathode. According to a further embodiment the method comprises, masking the doped SiC-substrate with a mask, forming of a base region, a collector and a contact region in the doped SiC-substrate by implantation using the mask. The method further comprises annealing of the doped SiC-substrate at a third temperature for a third period of time, forming a gate oxide on top of the doped SiC-substrate and metallizing the doped SiC-substrate to form a gate electrode, a first main electrode and a second main electrode. The third annealing temperature ranges between 1500°C and 1800°C and the third amount of time ranges between 10 min and 3h. The third temperature preferably ranges between 1600°C and 1700°C and the third amount of time ranges preferably between 30 min and 1h. There is also provided a semiconductor device, comprising a semi-insulating SiC-substrate of a first conductivity type or a second conductivity type doped with an interstitial. The semi-insulating SiC-substrate has a resistivity in the range between 1E5 Ohm*cm and 1E9 Ohm*cm at room temperature, a background doping concentration (Nd) greater than 1E10 cm-3 and a concentration of semiconductor deep levels (Nt), wherein the concentration of semiconductor deep levels (Nt) is greater than the background doping concentration (Nd). The used substrate is a semi-insulating 4H-SiC-substrate. The crystalline structure of 4H-SiC is often used for power devices owing to its high carrier mobility and high critical electric field strength. Alternatively the semi-insulating P2023,0858 WO E / P220366WO01 August 28, 2023 - 7 - substrate is a SiC polytype of the 6H-SiC structure. Additionally or alternatively, the substrate is a semi- insulating 4H-SiC or a 6H-SiC and / or made of a conductive 4H- SiC or a 6H-SiC. The semi-insulating SiC-substrate can be used for various semiconductor devices. According to an embodiment the semiconductor device comprises an anode comprising a group III element on a first side of the SiC-substrate and a cathode comprising a group V element on a second side of the SiC-substrate, which is arranged opposite of the first side. This corresponds to a simple PiN device. The SI SiC-substrate is not limited to be used in PiN devices. It can further be used for power bipolar devices and comprise for example for PiN-Diodes, PN-Junctions and / or IGBTs. The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and / or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Figure 1 to 4 show different positions in an exemplary embodiment of the method for manufacturing a semiconductor device, Figure 5 shows an exemplary embodiment of the semiconductor device. Figure 1 shows a position in an exemplary embodiment of the method for producing a semiconductor device 1. A semi- insulating SiC-substrate 100’ is provided with a predefined first thickness d1. The semi-insulating SiC-substrate 100’ is P2023,0858 WO E / P220366WO01 August 28, 2023 - 8 - thinned down to the first thickness d1 before incorporating interstitials i. Depending on a preferred application or a parameter, e.g. depending on a blocking voltage the first thickness d1 is chosen. A semi-insulating SiC-substrate 100’ is a substrate whose resistivity ranges between 1E5-1E9 Ohm*cm at room temperature. In order to obtain a SI-SiC the background doping concentration (N_d) must be reduced and the concentration of semiconductor deep levels (N_t), which can trap charge carriers must be increased. This second step is necessary, because it is difficult to reduce the background doping concentrations (N_d) to below 1E10 cm-3. The semi- insulating SiC 100’ is obtained when the concentration of semiconductor deep levels (N_t) is larger than the background doping concentrations (N_d). In this case, charge carriers are trapped by the deep levels and the Fermi level is pinned close to such deep levels. For example a doping with Vanadium can be used to obtain the semi-insulating SiC-substrate 100’. Figure 2 shows a later position, in which the interstitial i is incorporated on a Si-face 110 and on the C-face 120 of the semi-insulating SiC substrate 100’. The interstitial i can also be incorporated just on the Si-face 110 or just on the C-face 120. The interstitial i can be incorporated in various ways. The interstitial i is incorporated for example with a standard ion beam technique with an energy below 10 keV with a dose range of 1E10–1E16 ions / cm2. Alternatively or additionally, the interstitial i is incorporated by thermal annealing in an environment, which is rich in chemical elements of the interstitial i. The used first temperature T1 of the thermal annealing is in the range between 1200°C and 1600°C. Alternatively or additionally, the interstitial i is incorporated by plasma-immersion ion implantation (PIII). The used energies for PIII range from 1keV to 15keV at a dose P2023,0858 WO E / P220366WO01 August 28, 2023 - 9 - range of 1E10-1E16 ions / cm2. The incorporated interstitial i is provided by a group II element or by a group VII element. The used material for incorporating the interstitial i can be any chemical element from group II elements or group VII elements. The used material for incorporating the interstitial i is for example Beryllium or Fluorine. In case of Beryllium is used as interstitial I, an n-type doped SiC- substrate 100 is created. In case of Fluorine is used as interstitial i, a p-type doped SiC-substrate 100 is created. Figure 3 shows a later position, in which the doped SiC- substrate 100 is annealed at a second temperature T2 for a second period of time Z2 to diffuse the interstitial i, such that the concentration of the interstitial i is uniform along the first depth d1 of the doped SiC-substrate 100. The second temperature T2 ranges between 1200°C and 1800°C and the second period of time Z2 ranges between 20 min and 48h. Furthermore the second temperature T2 ranges preferably between 1500°C and 1700°C and the second period of time Z2 ranges preferably between 30 min and 24h. For this annealing step, for example a resistive furnace is used. The diffusivity of Beryllium interstitials is approximately 6E-9 cm2 / s at 1700°C. This means that for example during an 1h annealing at 1700°C, Beryllium interstitials diffuse more than 50µm. Diffusion time and temperature can be adjusted so to make the concentration of Beryllium interstitials uniform along the whole substrate depth. Accordingly, the diffusion time and temperature can be adjusted for different materials, like Fluorine. In the position of figure 4, an anode 113 comprising a group III element is implanted on a first side 111 of the doped P2023,0858 WO E / P220366WO01 August 28, 2023 - 10 - SiC-substrate 100. On a second side 112, which is opposite the first side 111, a cathode 114 comprising a group V element is implanted. The first side 111 can be the Si-face 110 or the C-face 120. Correspondingly, the second side 112 can be the C-face 120 respectively the Si-face 110. At the same time figure 4 shows a finalized semiconductor device 1. The semiconductor device 1 of figure 4 is a PiN device. Figure 5 shows another exemplary embodiment of the semiconductor device 1. By further processing the doped SiC- substrate 100 after the step shown in figure 3, an IGBT is manufactured. To manufacture the semiconductor device 1 of figure 5 the doped SiC-substrate 100 is masked with a mask. Using the mask a base region 11, a collector 12, a buffer 19 and a contact region with an n+ region 13 and a p+ region 14 are formed in the doped SiC-substrate 100 by implantation. The doped SiC-substrate 100 is annealed at a third temperature T3 for a third period of time Z3. After annealing, a gate oxide 15 on top of the doped SiC-substrate 100 is formed and the doped SiC-substrate 100 is metallized to form a gate electrode 16, a first main electrode 17 and a second main electrode 18. The conductivity of the doped SiC- substrate 100 and of the buffer 19 is the same. They are both of the first conductivity type, which may be n-type, i.e. both may be n-doped. Alternatively, the doped SiC-substrate 100 is of a second conductivity type, which is opposite to the first conductivity type. The second conductivity type may be p-type, i.e. the SiC-substrate 100 and the buffer 19 may be p-doped. The base region 11 and the collector 12 are of the opposite conductivity type of the SiC-substrate 100. They are for example of the second conductivity type, which may be p-type, i.e. both may be p-doped. Alternatively, the base region 11 and the collector 12 are of the first conductivity type, which may be n-type, i.e. both may be n-doped. The P2023,0858 WO E / P220366WO01 August 28, 2023 - 11 - third annealing temperature T3 ranges between 1500°C and 1800°C and the third amount of time Z3 ranges between 10 min and 3h. The third temperature T3 preferably ranges between 1600°C and 1700°C and the third amount of time Z3 ranges preferably between 30 min and 1h. At the same time figure 5 shows a finalized semiconductor device 1. The semiconductor device 1 of figure 5 is an IGBT. The embodiments shown in the Figures 1 to 5 as stated represent exemplary embodiments of the semiconductor device and the method for manufacturing the semiconductor device; therefore, they do not constitute a complete list of all embodiments according to the semiconductor device and method. Actual semiconductor devices and methods may vary from the embodiments shown in terms of arrangements, elements and regions, for example.

[0002] P2023,0858 WO E / P220366WO01 August 28, 2023 - 12 - Reference Signs 1 semiconductor device 11 base 12 collector 13 n+ region 14 p+ region 15 gate oxide 16 gate electrode 17 first main electrode 18 second main electrode 19 buffer 100’ semi-insulating SiC-substrate 100 doped SiC-substrate 110 Si-face 111 first side 112 second side 113 anode 114 cathode 120 C-face i interstitial d1 first thickness T1 first temperature T2 second temperature Z2 second amount of time T3 third temperature Z3 third amount of time

Claims

P2023,0858 WO E / P220366WO01 August 28, 2023 - 13 - 1. Method for manufacturing a semiconductor device (1), comprising the steps of - providing a semi-insulating SiC-substrate (100’) with a predefined first thickness (d1), - incorporating an interstitial (i) on a Si-face (110) and / or on a C-face (120) of the semi-insulating SiC- substrate (100’) and - forming a doped SiC-substrate (100) of a first conductivity type or a second conductivity type by diffusing the interstitial (i).

2. Method according to claim 1, wherein for incorporating the interstitial (i) a standard ion beam technique is used with energies below 10keV at a dose range of 1E10–1E16 ions / cm2.

3. Method according to claim 1, wherein for incorporating the interstitial (i) a thermal annealing at a first temperature (T1) in the range between 1200°C and 1600°C in an environment rich in elements of the interstitial (i) is used.

4. Method according to claim 1, wherein for incorporating the interstitial (i) a plasma-immersion ion implantation (PIII) is used with energies from 1keV to 15keV at a dose range of 1E10-1E16 ions / cm2.

5. Method according to any preceding claim, wherein diffusing of the interstitial (i) is facilitated by annealing the semi- insulating SiC-substrate (100’) at a second temperature (T2) for a second period of time (Z2), such that the concentration of the interstitial (i) is uniform along the depth of the doped SiC-substrate (100).P2023,0858 WO E / P220366WO01 August 28, 2023 - 14 - 6. Method according to claim 5, wherein the second temperature (T2) ranges between 1200°C and 1800°C and the second period of time (Z2) ranges between 20 min and 48h.

7. Method according to any preceding claim, wherein for incorporating the interstitial (i) a group II element is provided.

8. Method according to claim 7, wherein for incorporating the interstitial (i) Beryllium is provided.

9. Method according to claims 1 to 6, wherein for incorporating the interstitial (i) a group VII element is provided.

10. Method according to claim 9, wherein for incorporating the interstitial (i) Fluorine is provided.

11. Method according to any of the preceding claims, comprising thinning down the semi-insulating SiC-substrate (100’) to the first thickness (d1) depending on a preferred blocking voltage.

12. Method according to any of the preceding claims, comprising - implanting of a group III element on a first side (111) of the doped SiC-substrate (100), forming an anode (113) and - implanting of a group V element on a second side (112) of the doped SiC-substrate (100), which is arranged opposite of the first side (111), forming a cathode (114).

13. Method according to any of claims 1 to 11, comprising - masking the doped SiC-substrate (100) with a mask,P2023,0858 WO E / P220366WO01 August 28, 2023 - 15 - - forming of a base region (11), a collector (12), and a contact region (13) in the doped SiC-substrate (100) by implantation using the mask, - annealing of the doped SiC-substrate (100) at a third temperature (T3) for a third period of time (Z3), - forming a gate oxide (15) on top of the doped SiC- substrate (100) and - metallizing the doped SiC-substrate (100) to form a gate electrode (16), a first main electrode (17) and a second main electrode (18).

14. Method according to any preceding claim, wherein the third annealing temperature (T3) ranges between 1500°C and 1800°C and the third amount of time (Z3) ranges between 10 min and 3h.

15. Semiconductor device (1), comprising - a doped SiC-substrate (100) of a first conductivity type or a second conductivity type, which is a semi-insulating SiC-substrate (100’) doped with an interstitial (i), wherein - a concentration of semiconductor deep levels (Nt) is greater than a background doping concentration (Nd) of the semi-insulating SiC-substrate (100’).

16. Semiconductor device (1) according to claim 15, wherein the semi-insulating SiC-substrate (100’) is a semi-insulating 4H-SiC or a 6H-SiC and / or made of a conductive 4H-SiC or a 6H-SiC.

17. Semiconductor device (1) according to claim 15 or 16, comprisingP2023,0858 WO E / P220366WO01 August 28, 2023 - 16 - - an anode (113) comprising a group III element on a first side (111) of the doped SiC-substrate (100) and - a cathode (114) comprising a group V element on a second side (112) of the doped SiC-substrate (100), which is arranged opposite of the first side (111).

18. Semiconductor device (1) according to claim 15 to 17, wherein the semiconductor device (1) is a power bipolar device.

19. Semiconductor device (1) according to claims 15 to 18, wherein the semiconductor device (1) comprises a PN-junction.

20. Semiconductor device (1) according to claims 15 to 18, wherein the semiconductor device (1) comprises a PiN-Diode or an IGBT.

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