Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device with a small footprint. The semiconductor device has a first and a second transistor and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and first to third conductive layers. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer and has a second opening. The first semiconductor layer has a first region in contact with the upper surface of the first conductive layer and a second region in contact with the side surface of the first insulating layer. The second insulating layer is located on the first semiconductor layer. The third conductive layer has a region overlapping the first semiconductor layer. The second transistor has a second semiconductor layer, a second insulating layer, and a fourth conductive layer. The second semiconductor layer is located between the first insulating layer and the second insulating layer, and has a third region overlapping the fourth conductive layer and a fourth region not overlapping the fourth conductive layer. The first region and the fourth region contain boron or phosphorus.

Description

Semiconductor device and method for manufacturing the same

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with high saturation. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first insulating layer is located over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located over the first insulating layer. The second conductive layer has a second opening in a region overlapping with the first opening. The first semiconductor layer has a first region in contact with a top surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a region in contact with a side surface of the second conductive layer in the second opening. The second insulating layer is located over the first semiconductor layer and has a region in contact with the first semiconductor layer. The third conductive layer has a region that overlaps with the first semiconductor layer through the second insulating layer in the first opening and the second opening. The first region contains a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The second transistor has a second semiconductor layer, a second insulating layer, and a fourth conductive layer. The second semiconductor layer is located between the first insulating layer and the second insulating layer. The second semiconductor layer has a third region that overlaps with the fourth conductive layer through the second insulating layer and a fourth region that does not overlap with the fourth conductive layer. The fourth region contains a second element. The second element is boron or phosphorus. The fourth region has a portion where the concentration of the second element is higher than that of the third region.

[0012] In the above-described semiconductor device, the portion of the second insulating layer in contact with the first region preferably contains the first element.

[0013] In the semiconductor device, the first semiconductor layer preferably has a fifth region in contact with an upper surface of the second conductive layer and overlapping with the third conductive layer via the second insulating layer. The fifth region preferably contains the first element. The fifth region preferably has a portion having a higher concentration of the first element than the second region.

[0014] In the semiconductor device, the first semiconductor layer preferably has a sixth region that is in contact with an upper surface of the second conductive layer and does not overlap with the third conductive layer. The sixth region preferably contains the first element and the second element. The sixth region preferably has a portion having a higher concentration of the first element than the second region.

[0015] In the above-described semiconductor device, the first element and the second element are preferably the same.

[0016] Alternatively, in the above-described semiconductor device, the first element and the second element are preferably different from each other.

[0017] In the semiconductor device described above, it is preferable that the angle formed between the side surface of the first insulating layer and the top surface of the first conductive layer in the first opening be 65 degrees or more and 90 degrees or less.

[0018] In the above-described semiconductor device, the first semiconductor layer and the second semiconductor layer preferably each contain a metal oxide.

[0019] In the above-described semiconductor device, the first insulating layer preferably includes a third insulating layer, a fourth insulating layer on the third insulating layer, a fifth insulating layer on the fourth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer. The fifth insulating layer preferably includes silicon and oxygen. The third insulating layer, the fourth insulating layer, the sixth insulating layer, and the seventh insulating layer preferably include silicon and nitrogen, respectively. The third insulating layer preferably includes a portion having a higher hydrogen concentration than the fourth insulating layer. The seventh insulating layer preferably includes a portion having a higher hydrogen concentration than the sixth insulating layer.

[0020] The aforementioned semiconductor device preferably includes a third insulating layer. The third insulating layer preferably has a region in contact with the lower surface of the first conductive layer. The first insulating layer preferably includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. The fifth insulating layer preferably includes silicon and oxygen. The third insulating layer and the sixth insulating layer preferably include silicon and nitrogen, respectively. The third insulating layer preferably includes a portion having a higher hydrogen concentration than the fourth insulating layer.

[0021] One embodiment of the present invention includes forming a first conductive layer over a substrate, forming an insulating film over the first conductive layer, forming a second conductive layer over the insulating film to have a region overlapping with the first conductive layer, and processing the insulating film and the second conductive layer to form a first insulating layer having a first opening reaching the first conductive layer and a third conductive layer having a second opening overlapping with the first opening, forming a first semiconductor layer having a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the third conductive layer, and forming a second semiconductor layer over the first insulating layer. a second insulating layer is formed on the first semiconductor layer and the second semiconductor layer; a mask layer is formed on the second insulating layer in a region overlapping with the second semiconductor layer; a first element is supplied to the first semiconductor layer using the mask layer as a mask; the mask layer is removed; a fourth conductive layer having a region overlapping with the first semiconductor layer is formed on the second insulating layer; and a fifth conductive layer having a region overlapping with the second semiconductor layer is formed; a second element is supplied to the second semiconductor layer using the fifth conductive layer as a mask; the first element is boron or phosphorus, and the second element is boron or phosphorus.

[0022] In the above-described method for manufacturing a semiconductor device, the first element and the second element are preferably supplied by ion implantation.

[0023] In the above-described method for manufacturing a semiconductor device, the first element and the second element are preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate.

[0024] In the above-described method for manufacturing a semiconductor device, the first element and the second element are preferably the same.

[0025] Alternatively, in the above-described method for manufacturing a semiconductor device, the first element and the second element are preferably different from each other.

[0026] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with high saturation can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIG. 3A is a top view showing an example of a semiconductor device. FIGS. 3B and 3C are cross-sectional views showing an example of a semiconductor device. FIG. 4A is a top view showing an example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing an example of a semiconductor device. FIG. 5A is a top view showing an example of a semiconductor device. FIG. 5B is a cross-sectional view showing an example of a semiconductor device. FIG. 6A is a top view showing an example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a semiconductor device. FIG. 7 is a cross-sectional view showing an example of a semiconductor device. FIGS. 8A to 8D are cross-sectional views showing an example of a semiconductor device. FIG. 9 is a cross-sectional view showing an example of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A to 12C are cross-sectional views showing an example of a semiconductor device. FIG. 13 is a cross-sectional view showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIG. 15B is a cross-sectional view showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIGS. 17B and 17C are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a top view showing an example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a top view showing an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a semiconductor device. FIGS. 20A to 20D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 21A to 21C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 22A to 22C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 23A and 23B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 24A and 24B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 25A and 25B are cross-sectional views showing an example of a method for manufacturing a semiconductor device.26A and 26B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 27A is a perspective view showing an example of a display device. FIG. 27B is a block diagram showing an example of a display device. FIGS. 28A and 28B are circuit diagrams of a pixel circuit. FIG. 28C is a cross-sectional view showing an example of a pixel circuit. FIG. 29 is a circuit diagram of a pixel circuit. FIGS. 30A and 30B are cross-sectional views showing an example of a display device. FIG. 31 is a cross-sectional view showing an example of a display device. FIGS. 32A to 32C are cross-sectional views showing an example of a display device. FIGS. 33A and 33B are cross-sectional views showing an example of a display device. FIG. 34 is a cross-sectional view showing an example of a display device. FIG. 35 is a cross-sectional view showing an example of a display device. FIG. 36 is a cross-sectional view showing an example of a display device. FIGS. 37A and 37B are cross-sectional views showing an example of a display device. FIGS. 38A to 38F are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 39A to 39D are diagrams showing examples of electronic devices. FIGS. 40A to 40F are diagrams showing examples of electronic devices. 41A to 41G are diagrams showing an example of an electronic device.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0034] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0035] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0036] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0037] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0038] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the gate-source voltage (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the gate-source voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0039] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0040] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0041] In this specification, the phrase "top surface shapes are approximately the same" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned.

[0042] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0044] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0045] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0046] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0047] In this specification, the sacrificial layer is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0048] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0049] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0050] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer.

[0051] The first transistor includes a first semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first insulating layer is located on the first conductive layer, and the first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer, and the second conductive layer has a second opening in a region overlapping the first opening. The first semiconductor layer has a first region contacting a top surface of the first conductive layer in the first opening, a second region contacting a side surface of the first insulating layer in the first opening, and a region contacting a side surface of the second conductive layer in the second opening. The second insulating layer has regions contacting a top surface and a side surface of the first semiconductor layer. The third conductive layer has regions overlapping the first semiconductor layer through the second insulating layer in the first opening and the second opening. In the first transistor, the first conductive layer serves as one of a source electrode and a drain electrode, the second conductive layer serves as the other of the source electrode and the drain electrode, the second insulating layer serves as a gate insulating layer, and the third conductive layer serves as a gate electrode.

[0052] The second transistor includes a second semiconductor layer, a second insulating layer, and a fourth conductive layer. The second semiconductor layer is located between the first insulating layer and the second insulating layer, and the second semiconductor layer includes a third region that overlaps with the fourth conductive layer via the second insulating layer and a fourth region that does not overlap with the fourth conductive layer. In the second transistor, the second insulating layer functions as a gate insulating layer, and the fourth conductive layer functions as a gate electrode.

[0053] The channel length of the first transistor can be controlled by the thickness of the insulating layer sandwiched between the first conductive layer and the second conductive layer. In other words, the channel length of the first transistor is not affected by the exposure performance of the exposure equipment used for fabrication. Therefore, the channel length of the first transistor can be made shorter than the minimum dimension that the exposure equipment can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, a transistor with a large on-state current can be obtained. Furthermore, since the source electrode, the semiconductor layer, and the drain electrode can be provided overlapping with each other, the area occupied by the semiconductor device can be significantly reduced.

[0054] The second transistor has a different structure from the first transistor. The channel length of the second transistor is affected by the performance of an exposure tool used for fabrication and is equal to or greater than the minimum dimension of the exposure tool. Therefore, the channel length of the second transistor can be made longer than that of the first transistor. By increasing the channel length, the second transistor can have high saturation properties.

[0055] A first transistor having a short channel length and a second transistor having a long channel length can be formed over the same substrate by sharing some of the steps. For example, a high-performance semiconductor device can be obtained by applying the first transistor to a transistor that requires a large on-state current and the second transistor to a transistor that requires high saturation.

[0056] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0057] The first semiconductor layer preferably has a fifth region in contact with the upper surface of the second conductive layer and overlapping with the third conductive layer via the second insulating layer. In the first semiconductor layer, the first region and the fifth region each contain a first element. The first element is boron or phosphorus. The first region and the fifth region each have a portion having a higher concentration of the first element than the second region. By containing the first element in the first region and the fifth region, the electrical resistance of the first region and the fifth region can be reduced, thereby reducing the electrical resistance of the source region and the drain region of the first transistor and increasing the on-current.

[0058] In the second semiconductor layer, the fourth region contains a second element. The second element is boron or phosphorus. The fourth region has a portion where the concentration of the second element is higher than that of the third region. The fourth region contains the second element, which can reduce the electrical resistance of the fourth region, thereby reducing the electrical resistance of the source region and drain region of the second transistor and increasing the on-current.

[0059] <Configuration Example 1> A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows cross-sectional views of cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4. Note that some components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some components are also omitted in the top views of the semiconductor device in the following drawings.

[0060] The semiconductor device 10 includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIGS. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film. The transistor 100 and the transistor 200 have different structures and can be formed on the same substrate using some common processes.

[0061] Perspective views of the transistor 100 are shown in FIGS. 2A to 2D. FIG. 2B shows a cross section taken along dashed line C1-C2 in FIG. 2A. FIG. 2C shows a perspective view of the insulating layer shown in FIG. 2A, with the outline indicated by a dashed line. Similarly, FIG. 2D shows a perspective view of the insulating layer shown in FIG. 2B, with the outline indicated by a dashed line. Enlarged views of the transistor 100 shown in FIGS. 1A and 1B are shown in FIGS. 3A to 3C. Enlarged views of the transistor 200 shown in FIGS. 1A to 1C are shown in FIGS. 4A to 4C.

[0062] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and drain electrode. A region of the semiconductor layer 108 that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0063] The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, a conductive layer 212b, an insulating layer 120, and a conductive layer 202. In the transistor 200, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode), and the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 202 functions as a back gate electrode (also referred to as a second gate electrode), and the insulating layer 120 functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 208 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region.

[0064] A conductive layer 112a is provided over a substrate 102, an insulating layer 110 is provided over the conductive layer 112a, and a conductive layer 112b and a conductive layer 202 are provided over the insulating layer 110. The insulating layer 110 has regions in contact with the conductive layer 112a, the conductive layer 112b, and the conductive layer 202. The conductive layer 202 can be formed in the same process as the conductive layer 112b. For example, the conductive layer 112b and the conductive layer 202 can be formed by forming a film that will become the conductive layer 112b and the conductive layer 202 and processing the film. Alternatively, the conductive layer 202 can be formed in a process different from that for the conductive layer 112b.

[0065] The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112a and the conductive layer 112b. The insulating layer 110 has an opening 141 reaching the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. Note that in FIG. 1B and other figures, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, it can be said that the insulating layer 110 and the conductive layer 112b have openings reaching the conductive layer 112a.

[0066] The semiconductor layer 108 is provided so as to cover the openings 141 and 143. The semiconductor layer 108 is provided along the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0067] By configuring the semiconductor layer 108 to be in contact with not only the side surface but also the top surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b can be increased, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. This can increase the on-state current of the transistor 100. Note that although FIG. 1B and other drawings illustrate a structure in which an end portion of the semiconductor layer 108 is in contact with the top surface of the conductive layer 112b, one embodiment of the present invention is not limited to this structure. The end portion of the semiconductor layer 108 can be aligned or approximately aligned with an end portion of the conductive layer 112b on a side that does not face the opening 143. Alternatively, the semiconductor layer 108 can cover the end portion of the conductive layer 112b on the side that does not face the opening 143, and the end portion of the semiconductor layer 108 can be in contact with the top surface of the insulating layer 110. Note that the semiconductor layer 108 can also be in contact with only the side surface of the conductive layer 112b on the opening 143 side, without being in contact with the top surface of the conductive layer 112b.

[0068] The insulating layer 120 is provided so as to cover the conductive layer 202. The insulating layer 120 has a region in contact with the top surface and side surfaces of the conductive layer 202 and the top surface of the insulating layer 110. The insulating layer 120 preferably covers the entire conductive layer 202. In a top view (also referred to as a plan view), the insulating layer 120 preferably includes the conductive layer 202. The insulating layer 120 has a portion that protrudes beyond an end of the conductive layer 202. An end of the insulating layer 120 is in contact with the top surface of the insulating layer 110.

[0069] The semiconductor layer 208 is provided over the insulating layer 120. The semiconductor layer 208 has a region overlapping with the conductive layer 202 with the insulating layer 120 interposed therebetween. The semiconductor layer 208 can be formed in the same process as the semiconductor layer 108. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming films that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the films. Note that the semiconductor layer 108 and the semiconductor layer 208 can also be formed in different processes.

[0070] The insulating layer 120 is provided in at least a region overlapping with a channel formation region of the semiconductor layer 208. FIG. 1A and other drawings show a structure in which the semiconductor layer 208 has a portion protruding from an end portion of the insulating layer 120. The semiconductor layer 208 has a region in contact with a side surface of the insulating layer 120. A part of the end portion of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120, and another part is in contact with the top surface of the insulating layer 110. It can also be said that a part of the bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120, and another part is in contact with the top surface of the insulating layer 110. Alternatively, the insulating layer 120 can be provided in a region where the semiconductor layer 208 is provided, and the entire bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120.

[0071] An insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the insulating layer 120, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the insulating layer 120, and the top surface of the insulating layer 110. Part of the insulating layer 106 functions as a gate insulating layer of the transistor 100, and the other part functions as a gate insulating layer of the transistor 200. In the transistor 100, the insulating layer 106 is provided to cover the openings 141 and 143, and has a shape following the shapes of the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110.

[0072] The conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 and the conductive layer 204 each have a region in contact with the insulating layer 106 and have shapes that follow the shapes of the top surface and side surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 with the insulating layer 106 interposed therebetween. In the transistor 100, the conductive layer 104 is provided to cover the openings 141 and 143 and has a shape that follows the shapes of the top surface and side surface of the insulating layer 106. The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming and processing films that will become the conductive layer 104 and the conductive layer 204. Note that the conductive layer 104 and the conductive layer 204 can also be formed in different processes.

[0073] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 208. The conductive layers 212a and 212b are provided so as to cover part of the openings 147a and 147b. The conductive layer 212a has a region in contact with the semiconductor layer 208 in the opening 147a, and the conductive layer 212b has a region in contact with the semiconductor layer 208 in the opening 147b. It can also be said that the conductive layer 212a is electrically connected to the semiconductor layer 208 in the opening 147a, and the conductive layer 212b is electrically connected to the semiconductor layer 208 in the opening 147b. The conductive layers 212a and 212b can be formed in the same process as the conductive layers 104 and 204. For example, after forming the insulating layer 106 having the openings 147a and 147b, a film to be the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is formed and then processed to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b. Note that the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be partially formed in different steps.

[0074] In the transistor 100, the source electrode and the drain electrode are located at different heights relative to the surface of the substrate 102, which is the surface on which the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), and therefore the transistor 100 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0075] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, the transistor 100 having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the variation in characteristics among the plurality of transistors 100 is reduced, thereby stabilizing the operation of the semiconductor device 10 and improving its reliability. Furthermore, the reduced variation in transistor characteristics increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device 10 to be lowered. Therefore, the power consumption of the semiconductor device 10 can be reduced.

[0076] The transistor 100 can have a source electrode, a semiconductor layer, and a drain electrode stacked together, and therefore can occupy a significantly smaller area than a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0077] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by these can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0078] The transistor 200 is a planar transistor in which a semiconductor layer 208 is disposed in a planar shape. The transistor 200 is also a so-called top-gate transistor in which a gate electrode is provided above the semiconductor layer 208.

[0079] The channel length of the transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of the transistor 200 is equal to or greater than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor. That is, the channel length of the transistor 200 can be made longer than the channel length of the transistor 100. By increasing the channel length, the transistor can have high saturation properties.

[0080] The transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed over the same substrate by sharing some of the steps. For example, by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation, a high-performance semiconductor device can be obtained. Furthermore, by using the transistor 100 with a small occupation area, a semiconductor device with a small occupation area can be obtained.

[0081] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0082] Since the transistor 200 includes the conductive layer 202 that functions as a back gate electrode, the potential of the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 208 is fixed, and saturation can be further improved. Furthermore, the potential of the back channel side of the semiconductor layer 208 is fixed, which can suppress a shift in the threshold voltage. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0083] The conductive layer 202 can be electrically connected to the conductive layer 212a or the conductive layer 212b. For example, by providing an opening in a region of the insulating layer 120 overlapping with the conductive layer 202 and providing the conductive layer 212a or the conductive layer 212b to cover the opening, the conductive layer 202 can be in contact with the conductive layer 212a or the conductive layer 212b. This allows the back gate electrode and the source electrode or the drain electrode of the transistor 200 to have the same potential. For example, when the back gate electrode and the source electrode have the same potential, a shift in the threshold voltage of the transistor 200 can be suppressed. Furthermore, the reliability of the transistor 200 can be improved. Alternatively, the conductive layer 202 can be electrically connected to the conductive layer 204. For example, by providing an opening in a region of the insulating layer 106 and the insulating layer 120 overlapping with the conductive layer 202 and providing the conductive layer 204 to cover the opening, the conductive layer 202 can be in contact with the conductive layer 204. By setting the back gate electrode and the gate electrode to the same potential, it is possible to increase the on-state current of the transistor 200. Note that the transistor 200 may not include the conductive layer 202.

[0084] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer for the transistor 100 and the transistor 200. Note that the insulating layer 195 is omitted in FIGS. 2A to 2D.

[0085] The semiconductor layer 108 includes a region 108Da, a region 108Db, and a region 108Dc. The semiconductor layer 208 includes a pair of regions 208L and a pair of regions 208D. The regions 108Da, 108Db, 108Dc, 208L, and 208D each contain an impurity element.

[0086] The regions 108Da, 108Db, and 108Dc each have a higher concentration of impurity elements and a lower electrical resistance than other regions (eg, the channel formation region) of the semiconductor layer 108.

[0087] 3B and other figures show an example in which region 108Da is formed in a region of semiconductor layer 108 that is in contact with the top surface of conductive layer 112a and is located between the top surface of conductive layer 112a and the bottom surface of conductive layer 104, and region 108Db and region 108Dc are formed in a region of semiconductor layer 108 that is in contact with the top surface of conductive layer 112b. Region 108Db is provided in a position that overlaps with conductive layer 104, and region 108Dc is provided in a position that does not overlap with conductive layer 104. The region in which region 108Da is formed is not limited thereto, and for example, region 108Da may be formed over the entire region that is in contact with the top surface of conductive layer 112a. Region 108Db may also be provided in a region of semiconductor layer 108 that is in contact with the side surface of conductive layer 112b. Region 108Db may also be provided in a portion of the region of semiconductor layer 108 that is in contact with the side surface of insulating layer 110. For example, the impurity element may diffuse due to heat applied when the impurity element is supplied to the semiconductor layer 108 or in a process after the impurity element is supplied. Although the cross-sectional views such as FIG. 3B show two regions of the semiconductor layer 108 that contact the upper surface of the conductive layer 112b, the regions 108Db are connected to one another in top view. The region 108Db being connected to one another increases the contact area between the region 108Db and the conductive layer 112b, thereby reducing the contact resistance between the semiconductor layer 108 and the conductive layer 112b. The semiconductor layer 108 may also have a configuration including multiple regions 108Db that are separated from one another.

[0088] The semiconductor layer 108 includes the regions 108Da and 108Db containing the impurity element, which can reduce the electrical resistance of the source region and the drain region of the semiconductor layer 108. Furthermore, the contact resistance between the semiconductor layer 108 and the conductive layer 112a and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. Therefore, the on-state current of the transistor 100 can be increased.

[0089] In the semiconductor layer 208, a region in contact with the conductive layer 212a and a region 208D in contact with the conductive layer 212a function as one of the source and drain regions of the transistor 200, and a region in contact with the conductive layer 212b and a region 208D in contact with the conductive layer 212b function as the other of the source and drain regions. As shown in FIG. 4B , the semiconductor layer 208 includes a region 208M that overlaps with the conductive layer 204 with the insulating layer 106 interposed therebetween. The region 208M functions as a channel formation region of the transistor 200. The regions 208D and 208L have a higher impurity element concentration and lower electrical resistance than the channel formation region (here, the region 208M) of the semiconductor layer 208. The region 208D has a higher impurity element concentration and lower electrical resistance than the region 208L. In the semiconductor layer 208, the channel formation region is located between the pair of regions 208L. The pair of regions 208D are located outside the pair of regions 208L.

[0090] Using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks, an impurity element can be supplied (also referred to as added or injected) to the semiconductor layer 208. 4B illustrates a structure in which a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106.

[0091] The region 208L functions as a buffer region for alleviating the drain electric field. The region 208L does not overlap with the conductive layer 204, and therefore, a channel is hardly formed in the region 208L even when a gate voltage is applied to the conductive layer 204. The region 208L preferably has a higher carrier concentration than the channel formation region. This allows the region 208L to function as an LDD (lightly doped drain) region. By providing the region 208L functioning as an LDD region between the channel formation region and the region 208D, the transistor 200 can have a high drain breakdown voltage.

[0092] The carrier concentration in the semiconductor layer 208 is preferably lowest in the channel formation region and increases in the order of the region 208L and the region 208D. By providing the region 208L between the channel formation region and the region 208D, the carrier concentration in the channel formation region can be kept extremely low even if impurities such as hydrogen diffuse from the region 208D during the manufacturing process, for example.

[0093] The carrier concentration in the region 208L may not be uniform, and may have a gradient such that the carrier concentration decreases from the region 208D side toward the channel formation region. For example, either one or both of the hydrogen concentration and the oxygen vacancy concentration in the region 208L may have a gradient such that the concentration decreases from the region 208D side toward the channel formation region.

[0094] The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0095] The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0096] The semiconductor layer 108 and the semiconductor layer 208 can each be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for a channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for a channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for a channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for a semiconductor layer may be referred to as a Si transistor. A transistor using LTPS for a semiconductor layer may be referred to as an LTPS transistor.

[0097] The semiconductor layer 108 and the semiconductor layer 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The band gap of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0098] The insulating layer 110 will now be described.

[0099] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0100] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0101] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region.

[0102] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ: Oxygen Vacancy), and oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ H) can be reduced.

[0103] Here, V is added to the metal oxide. Ｏ As H increases, V Ｏ Carriers may be generated by H, increasing the carrier concentration. In particular, if the carrier concentration in the channel formation region is high, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may increase. For example, in the case of an n-channel transistor, the threshold voltage may shift to the negative side, increasing the cutoff current. In addition, the reliability of the transistor may decrease. Oxygen vacancies (V Ｏ ) and V Ｏ By reducing H, it is possible to prevent the carrier concentration in the channel formation region from increasing. As a result, a shift in threshold voltage is prevented, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained. In addition, a highly reliable transistor and semiconductor device can be obtained.

[0104] The insulating layer 110 preferably releases a small amount of impurities from itself. In particular, it is preferable that the amount of impurities containing hydrogen elements (for example, hydrogen and water) released from the insulating layer 110 is small. Furthermore, it is preferable that the insulating layer 110 has as little impurities containing hydrogen elements as possible. This prevents oxygen deficiency (V Ｏ ) and V Ｏ The increase in H can be suppressed.

[0105] The insulating layer 110 preferably has a stacked structure. In Fig. 1B and other figures, an example is shown in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layers 110a, 110b, and 110c can each be made of the materials listed in the description of the insulating layer 110.

[0106] As shown in FIG. 3B , the semiconductor layer 108 has a region 108M in contact with the side surface of the insulating layer 110b. The insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. This allows at least the region 108M to function as a channel formation region of the transistor 100. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b. Note that although two regions of the semiconductor layer 108 in contact with the side surface of the insulating layer 110b are shown in the cross-sectional views of FIG. 3B and the like, the regions 108M are connected as one in top view. Note that the semiconductor layer 108 may also have a structure having multiple regions 108M that are separated from each other.

[0107] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ It is also possible to reduce H. Therefore, the transistor 100 can have favorable electrical characteristics and high reliability.

[0108] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. Then, the film can be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0109] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0110] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region of the semiconductor layer 108. Therefore, the transistor 100 can have favorable electrical characteristics and high reliability.

[0111] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a and to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V ＯH can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layers 112a and 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layers 112a and 112b from increasing. Therefore, the transistor 100 can have a large on-state current.

[0112] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0113] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0114] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0115] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 to be increased, and oxygen deficiency (V Ｏ ) and VＯ H can be reduced efficiently.

[0116] The insulating layer 110b can also function as a barrier film. The above-described materials can be used as the barrier film. For example, silicon nitride can be suitably used as the insulating layer 110b. The insulating layer 110 can have a single-layer structure of a silicon nitride film. The insulating layer 110b functions as a barrier film, thereby suppressing impurity diffusion into the channel formation region of the semiconductor layer 108, thereby enabling the transistor 100 to exhibit favorable electrical characteristics and high reliability. Note that depending on the material used for the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may be reduced. In this case, it is preferable that at least the portion of the insulating layer 106 in contact with the channel formation region of the semiconductor layer 108 contains oxygen. Furthermore, it is more preferable to use a material that releases oxygen when heat is applied to this portion. The insulating layer 106 releases oxygen due to heat applied during the manufacturing process of the semiconductor device 10, thereby supplying oxygen to the semiconductor layer 108. Supplying oxygen from the insulating layer 106 to the semiconductor layer 108, particularly to the channel formation region, reduces oxygen vacancies (V Ｏ ) and V Ｏ Similarly, oxygen vacancies (V Ｏ ) and V Ｏ It is also possible to reduce H. For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be suitably used in a portion of the insulating layer 106 in contact with the semiconductor layer 108 and the semiconductor layer 208.

[0117] The insulating layer 120 will now be described.

[0118] The insulating layer 120 has a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 208, it is preferable that at least a part of the region of the insulating layer 120 in contact with the semiconductor layer 208 contains oxygen in order to improve the interface characteristics between the semiconductor layer 208 and the insulating layer 120. The insulating layer 120 can be made of any material that can be used for the insulating layer 110.

[0119] The insulating layer 120 preferably has a stacked structure. In Fig. 4B and other figures, the insulating layer 120 has a stacked structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a. The insulating layer 120a and the insulating layer 120b can each be made of a material that can be used for the insulating layer 110.

[0120] The insulating layer 120b having a region in contact with the semiconductor layer 208 preferably contains oxygen, and it is preferable to use one or more of the oxides and oxynitrides described above. It is more preferable to use a film that releases oxygen when heat is applied as the insulating layer 120b. When heat is applied during the manufacturing process of the transistor 200, the insulating layer 120b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 208. This reduces oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 200 can have favorable electrical characteristics and high reliability. The insulating layer 120b can be formed using any of the materials that can be used for the insulating layer 110b.

[0121] The insulating layer 120a provided on the conductive layer 202 side preferably releases a small amount of impurities (for example, hydrogen and water) from itself and is less permeable to impurities. This can prevent the impurities contained in the insulating layer 120a from diffusing into the channel formation region of the semiconductor layer 208. Therefore, the transistor 200 can have favorable electrical characteristics and high reliability.

[0122] The insulating layer 120a is preferably made of a material that is difficult for oxygen to permeate. The insulating layer 120a can also be said to function as a barrier film. By providing the insulating layer 120a that functions as a barrier film, oxygen contained in the insulating layer 120b can be prevented from diffusing into the conductive layer 202 through the insulating layer 120a. This can prevent the conductive layer 202 from being oxidized and its electrical resistance from increasing. At the same time, since the oxygen contained in the insulating layer 120b is prevented from diffusing toward the insulating layer 120a, the amount of oxygen supplied from the insulating layer 120b to the channel formation region increases, and oxygen vacancies (V Ｏ ) and VＯ H can be reduced.

[0123] The insulating layer 120a is preferably made of a material that does not easily diffuse the metal element contained in the conductive layer 202. This can prevent the metal element contained in the conductive layer 202 from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layer 120.

[0124] The insulating layer 120a can be preferably made of a material that can be used for the insulating layer 110a and the insulating layer 110c. Note that the insulating layer 120a, the insulating layer 110a, and the insulating layer 110c can be made of the same material. Alternatively, different materials can be used for some or all of these layers.

[0125] Note that although the insulating layer 120 has a two-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 120 can have a stacked structure of three or more layers or a single-layer structure.

[0126] The regions 108M, 108Da, 108Db, 108Dc, 208M, 208L, and 208D will be specifically described.

[0127] Regions 108Da and 108Db each contain a first element as an impurity element. Region 108Dc contains a first element and a second element as impurity elements. Regions 208L and 208D each contain a second element as an impurity element. The first element is preferably one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.). Furthermore, the first element is not limited to the above elements, and one or more of elements included in the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and rare earth elements can also be used. As the second element, one or more of the elements that can be used as the first element can be used.

[0128] By supplying (or adding or injecting) a first element to the semiconductor layer 108, the regions 108Da and 108Db can be formed. By supplying a first element and a second element to the semiconductor layer 108, the region 108Dc can be formed. By supplying a second element to the semiconductor layer 208, the regions 208L and 208D can be formed. By supplying the first element or the second element to the regions 108Da, 108Db, 108Dc, 208L, and 208D, oxygen vacancies (V Ｏ ) occurs. Then, the oxygen deficiency (V Ｏ ) with hydrogen in it. Ｏ Carriers are generated by H, and the electrical resistance of these regions can be reduced.

[0129] When elements that easily bond with oxygen are used as the first element and the second element, the first element and the second element remove oxygen from the semiconductor layer 108 and the semiconductor layer 208 and exist in a state of being bonded to oxygen. Ｏ ) occurs. When elements that become stable when bonded with oxygen are used as the first element and the second element, the first element and the second element in the semiconductor layer 108 and the semiconductor layer 208 exist stably in an oxidized state, and are therefore less likely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device 10, thereby enabling the electrical resistance to be maintained low. For this reason, it is preferable to use elements whose oxides can exist in a solid state at least at the temperature during the manufacturing process as the first element and the second element. Specifically, preferred first elements include typical nonmetal elements other than hydrogen, typical metal elements, and transition elements (transition metals). Specifically, it is more preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements. It is even more preferable to use boron or phosphorus as one of the first elements. The same applies to the second element.

[0130] The first element can be supplied to the regions 108Da, 108Db, and 108Dc in the same process. The second element can be supplied to the regions 108Dc, 208L, and 208D in the same process. Furthermore, it is preferable to supply the first element and the second element in different processes. By supplying the first element in a different process from the second element in a different process, the region to which the first element is supplied and the region to which the second element is supplied can be controlled.

[0131] The first element and the second element can be the same. By using the same elements, a common device can be used to supply the first element and the second element, thereby increasing productivity and reducing manufacturing costs. Alternatively, the first element and the second element can be different from each other. By using different elements, the range of choices for the elements used as the first element and the second element can be expanded.

[0132] Each of the regions 108Da, 108Db, and 108Dc preferably has a portion having a higher concentration of the first element than the region 108M.

[0133] The region 108Da and the region 108Db each have a concentration of the first element of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5×10, more preferably １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３It is preferable that the region 108Da and the region 108Db include a portion where the concentration of the first element is less than or equal to 108Da. If the concentration of the first element is low, the electrical resistance of the region 108Da and the region 108Db may be high. On the other hand, if the concentration of the first element is high, that is, if a large amount of the first element is supplied, damage may be caused to the semiconductor layer 108 during supply, which may result in an increase in the electrical resistance of the region 108Da and the region 108Db. Therefore, by setting the concentration of the first element in the region 108Da and the region 108Db within the above-mentioned range, the electrical resistance of the region 108Da and the region 108Db can be reduced, and the transistor 100 can have a large on-current.

[0134] When the region 108Da contains two or more first elements, it is preferable that at least one of the first elements has a concentration within the above range. It is more preferable that the concentration of each of the first elements has a concentration within the above range. The same applies to the region 108Db.

[0135] The region 108Dc may be damaged by the supply of both the first element and the second element, and may have a higher electrical resistance than both the region 108Da and the region 108Db. However, because the region 108Db, which has low electrical resistance, is provided between the region 108Dc and the channel formation region (here, the region 108M), the electrical resistance of the region 108Dc has little effect on the electrical characteristics of the transistor 100. Therefore, the electrical resistance of the region 108Dc is not particularly important. Note that when the first element and the second element are different from each other, the concentration of the first element in the region 108Dc is the same or approximately the same as the concentration of the first element in the region 108Da and the region 108Db. When the first element and the second element are the same from each other, the region 108Dc has a portion with a higher concentration of the first element (which can also be called the second element) than both the region 108Da and the region 108Db.

[0136] 3B and the like illustrate a configuration in which the region 108Dc is provided in a position that is in contact with the top surface of the conductive layer 112b and does not overlap with the conductive layer 104. By configuring the transistor 100 to include the region 108Dc, that is, by reducing the area where the conductive layer 112b and the conductive layer 104 overlap, the parasitic capacitance generated by the conductive layer 112b and the conductive layer 104 can be reduced.

[0137] When the first element is supplied, the first element may also be supplied to the channel formation region (here, region 108M) of the semiconductor layer 108. Alternatively, due to heat or the like applied during the manufacturing process, a portion of the first element contained in each of regions 108Da, 108Db, and 108Dc may diffuse into the channel formation region. The concentration of the first element in region 108M is preferably low. The concentration of the first element in region 108M is preferably lower than the concentrations of the first element in each of regions 108Da, 108Db, and 108Dc.

[0138] By reducing the concentration of the first element in the region 108M, an increase in the carrier concentration in the channel formation region can be suppressed. By suppressing an increase in the carrier concentration in the channel formation region, a shift in the threshold voltage can be suppressed, and the transistor 100 can have a small cutoff current. Therefore, a semiconductor device with low power consumption can be obtained.

[0139] The concentration of the first element in the region 108M is 1×10 4 times the concentration of the first element in the region 108Da. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ Similarly, the concentration of the first element in the region 108M is preferably 1×10 or less times the concentration of the first element in the region 108Db. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４The concentration of the first element in the region 108M is preferably 1×10 or less times the concentration of the first element in the region 108Dc. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ This allows the transistor 100 to have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0140] The first element is preferably supplied to the semiconductor layer 108 through the insulating layer 106. For example, the first element can be supplied to the semiconductor layer 108 through the insulating layer 106 after the insulating layer 106 is formed and before the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b are formed. By supplying the first element to the semiconductor layer 108 through the insulating layer 106, the first element can be preferentially supplied to the regions 108Da, 108Db, and 108Dc in the semiconductor layer 108. Furthermore, by supplying the first element through the insulating layer 106, damage to the semiconductor layer 108 during supply can be reduced.

[0141] When the first element is supplied to the semiconductor layer 108, it is preferable that the first element is supplied as little as possible to the semiconductor layer 208. In particular, it is preferable that the first element is supplied as little as possible to the region 208M. For example, it is preferable to provide a layer that functions as a mask (hereinafter also referred to as a mask layer) on the semiconductor layer 208 and supply the first element to the semiconductor layer 108 using the mask layer as a mask. It is preferable that the mask layer is provided at least in a region that overlaps with the semiconductor layer 208, but not in a region that overlaps with the semiconductor layer 108. This allows the first element to be selectively supplied to the semiconductor layer 108. Specifically, it is preferable to form the insulating layer 106 over the semiconductor layer 108 and the semiconductor layer 208, form a mask layer on the insulating layer 106 in a region that overlaps with the semiconductor layer 208, and supply the first element to the semiconductor layer 108 using the mask layer as a mask. A resist mask or a hard mask can be used as the mask layer. It is preferable to determine the material and thickness of the mask layer and the conditions for supplying the first element so that the first element is supplied to the semiconductor layer 208 as little as possible.

[0142] The concentration of the first element in the semiconductor layer 208 is preferably low. In particular, the concentration of the first element in the region 208M is preferably low. The concentration of the first element in the region 208M is preferably lower than the concentrations of the first element in the regions 108Da, 108Db, and 108Dc. The concentration of the first element in the region 208M is preferably 1×10 lower than the concentration of the first element in the region 108Da. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ Similarly, the concentration of the first element in the region 208M is preferably 1×10 or less times the concentration of the first element in the region 108Db. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４The concentration of the first element in the region 208M is preferably 1×10 times or less of the concentration of the first element in the region 108Dc. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ It is preferable that the ratio is 1:1 or less.

[0143] When the first element is supplied to the semiconductor layer 108 through the insulating layer 106, a portion of the insulating layer 106 may also contain the first element. When the first element is supplied using a mask layer, a region of the insulating layer 106 where the mask layer is not provided may contain the first element. For example, a region of the insulating layer 106 that is in contact with the semiconductor layer 108 may contain the first element. It is preferable that the regions 108Da and 108Db each have a portion where the concentration of the first element is higher than that of the insulating layer 106, because this can reduce the electrical resistance of the regions 108Da and 108Db.

[0144] The second element is preferably supplied to the semiconductor layer 208 using at least the conductive layer 204 as a mask. For example, after the conductive layers 104, 204, 212a, and 212b are formed on the insulating layer 106, the second element can be supplied to the semiconductor layer 208 using these conductive layers as a mask. As a result, a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layers 204, 212a, and 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layers 204, 212a, and 212b, but overlaps with the insulating layer 106. The second element is supplied to the region 208L via the insulating layer 106. By supplying the second element to the semiconductor layer 208 using the conductive layer 204, which functions as a gate electrode, as a mask, the regions 208L and 208D can be formed in a self-aligned manner. The transistor 200 can be said to be a TGSA (Top Gate Self-Aligned) type transistor.

[0145] Preferably, each of the regions 208D and 208L has a portion with a higher concentration of the second element than the region 208M.

[0146] The region 208D has a concentration of the second element of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5×10, more preferably １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３ It is preferable that the region 208D includes a portion that satisfies the following conditions: This can reduce the electrical resistance of the region 208D, resulting in a transistor 200 with a large on-state current.

[0147] The concentration of the second element in region 208M is preferably low. The concentration of the second element in region 208M is preferably 1×10 lower than the concentration of the second element in region 208D. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ This allows the transistor 200 to have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0148] When the second element is supplied to the semiconductor layer 208, the second element is supplied to the semiconductor layer 108 through the insulating layer 106, using the conductive layer 104 as a mask. As a result, the second element is supplied to a region 108Dc of the semiconductor layer 108 that does not overlap with the conductive layer 104. The region 108Dc preferably has a portion having a higher concentration of the second element than the regions 108Da, 108Db, and 108M. Note that when the first element and the second element are the same, the region 108Dc has a portion having a higher concentration of the first element (which can also be called the second element) than the regions 108Da, 108Db, and 108M.

[0149] When the second element is supplied to the semiconductor layer 208, it is preferable that the second element be supplied as little as possible to the regions 108M, 108Da, and 108Db. In particular, it is preferable that the second element be supplied as little as possible to the region 108M. When the second element is supplied, the conductive layer 104 functions as a mask, thereby preventing the second element from being supplied to the regions 108M, 108Da, and 108Db that overlap with the conductive layer 104.

[0150] The concentration of the second element in region 108M is preferably low. The concentration of the second element in region 108M is preferably lower than the concentrations of the second element in regions 208L and 208D. The concentration of the second element in region 108M is preferably 1×10 lower than the concentration of the first element in region 208D. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ It is preferable to determine the material and thickness of the conductive layer 104 and the conditions for supplying the second element so that the second element is supplied to the region 108M as little as possible.

[0151] When the second element is supplied to the semiconductor layer 208, part of the insulating layer 106 may also contain the second element. Specifically, a region of the insulating layer 106 that does not overlap with any of the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may contain the second element.

[0152] The concentrations of the first element and the second element in the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 106 can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA). When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in low concentration regions, quantification may be difficult or the concentration may be below the detection limit.

[0153] In manufacturing the semiconductor device of one embodiment of the present invention, the first element is preferably more easily supplied to the source and drain regions of the semiconductor layer 108 than to the channel formation region. The first element is preferably supplied to the semiconductor layer 108 from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. At this time, the amount of the first element supplied to a region of the semiconductor layer 108 that is inclined with respect to the top surface of the substrate 102 is smaller than that to a region that is parallel or substantially parallel to the top surface of the substrate 102. That is, the amount of the first element supplied to the source and drain regions of the semiconductor layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source and drain regions in the semiconductor layer 108 can be preferentially reduced. The second element is preferably supplied to the semiconductor layer 208 from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102 using the conductive layer 204 as a mask. This allows the regions 208L and 208D to be formed in a self-aligned manner in the semiconductor layer 208.

[0154] Ion implantation can be suitably used for supplying the first element and the second element, respectively. The ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurity element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. The method of supplying ions after mass separation is sometimes called an ion implantation method, and the method of supplying ions without mass separation is sometimes called an ion doping method.

[0155] When boron is used as the first element and the second element, the source gas may be, for example, BF ３ When phosphorus is used as the first element and the second element, the source gas may be, for example, PH ３ Furthermore, by mass-separating ions generated from these gases and supplying them, ions of specific masses can be supplied to the regions 108Da, 108Db, 108Dc, 208L, and 208D, which is more preferable.

[0156] When a plurality of elements are used as the first element, it is preferable to use an element that easily bonds with oxygen and an element that has a larger mass number than the element. When the mass number of the supplied element is large, the number of metal-oxygen bonds that are broken in the metal oxide of the semiconductor layer 108 increases. In other words, in the region to which the element is supplied, oxygen vacancies (V Ｏ) occurs more frequently. By supplying an element with a large mass number to break bonds between many metals and oxygen, elements that easily bond with oxygen can bond with oxygen more efficiently. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced. For example, when boron, phosphorus, magnesium, aluminum, or silicon is used as an element that easily bonds with oxygen, argon, krypton, or xenon can be used as an element with a large mass number. More specifically, boron and argon can be preferably used as the first element. The same applies to the second element.

[0157] When multiple elements are supplied as the first element, a gas containing these elements can be used as the source gas. For example, when boron and argon are used as the first element, a gas containing boron and argon can be used as the source gas. Alternatively, multiple elements can be supplied separately. For example, when an element that easily bonds with oxygen and an element with a large mass number are used as the first element, it is preferable to supply the element that easily bonds with oxygen after supplying the element with the large mass number. For example, argon can be supplied to the semiconductor layer 108 using a gas containing argon, and then boron can be supplied to the semiconductor layer 108 using a gas containing boron. This can efficiently reduce the electrical resistance of the regions 108Da and 108Db. The same applies to the second element.

[0158] When the first element is supplied to the regions 108Da, 108Db, and 108Dc, hydrogen can also be supplied to these regions. Similarly, when the second element is supplied to the regions 208L, 208D, and 108Dc, hydrogen can also be supplied to these regions. The supply of hydrogen reduces oxygen vacancies (V Ｏ ) occurs, and oxygen deficiency (V Ｏ ) by entering V ＯSupplying hydrogen in addition to the first element or the second element makes it possible to easily reduce the electrical resistance of each of the regions 108Da, 108Db, 108Dc, 208L, and 208D, and to maintain the electrical resistance at a low level.

[0159] When both the first element and hydrogen are supplied, a gas containing the first element and hydrogen (for example, PH ３ Gas and B ２ H ６ Alternatively, a mixed gas of a gas containing the first element and a gas containing hydrogen can be used as the source gas. By using a source gas containing the first element and hydrogen, ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity. For example, a source gas containing B ２ H ６ By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using gas, phosphorus and hydrogen can be supplied as impurity elements, and the same applies to the supply of the second element.

[0160] Note that, in this example, the insulating layer 106 is formed over the semiconductor layer 108 and the semiconductor layer 208, and then the first element is supplied to the regions 108Da, 108Db, and 108Dc. The conductive layer 104 and the conductive layer 204 are formed over the insulating layer 106, and then the second element is supplied to the regions 108Dc, 208L, and 208D. However, one embodiment of the present invention is not limited to this example. The first element can be supplied to the semiconductor layer 108, and the second element can be supplied to the semiconductor layer 208 in the same process. In this case, the first element and the second element are the same. For example, after the insulating layer 106 is formed, a mask layer is formed in the position where the conductive layer 204 is to be formed. Then, the first element (which can also be called the second element) can be supplied to the semiconductor layer 108 and the semiconductor layer 208 using the mask layer as a mask. As a result, the regions 108Da, 108Db, 108Dc, 208L, and 208D contain the first element, and the electrical resistance of these regions can be reduced. After the first element is supplied, the mask layer is removed, and the conductive layer 104 and the conductive layer 204 can be formed on the insulating layer 106.

[0161] Since the insulating layer 106 is provided so as to cover the openings 141 and 143, it is preferable to form the insulating layer 106 by a method with high coverage. The insulating layer 106 is preferably formed by a sputtering method, a PECVD method, or an atomic layer deposition (ALD) method. As the ALD method, a thermal ALD method or a PEALD (Plasma Enhanced ALD) method can be used. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it exhibits high coverage and allows low-temperature film formation.

[0162] 3B shows the thickness Ta of the insulating layer 106 at a portion thereof in contact with the region 108Da, the thickness Tb of the portion thereof in contact with the region 108Db, and the thickness Tc of the portion thereof in contact with the region 108M. The thicknesses Ta, Tb, and Tc are each the thickness in a direction perpendicular or substantially perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112a and the top surface of the insulating layer 106. The thickness Tb is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112b and the top surface of the insulating layer 106. The thickness Tc is the shortest distance between the side surface of the semiconductor layer 108 provided along the side surface of the insulating layer 110 on the insulating layer 106 side and the side surface of the insulating layer 106 on the conductive layer 104 side.

[0163] 3B illustrates a structure in which the thicknesses Ta, Tb, and Tc are the same, but one embodiment of the present invention is not limited to this. The thicknesses Ta, Tb, and Tc may be partially or entirely different from each other. The thickness Tc of the region of the insulating layer 106 provided along the side surface of the insulating layer 110 may be thinner than the thicknesses Ta and Tb of the region of the insulating layer 106 provided along the top surface of the conductive layer 112a or 112b. For example, when the insulating layer 106 is formed by a PECVD method or a sputtering method, the thickness Tc may be thinner than both the thicknesses Ta and Tb. Furthermore, when the insulating layer 106 is formed by an ALD method, the thickness Tc can be closer to the thicknesses Ta and Tb. Alternatively, the thickness Tc can be the same as or approximately the same as the thicknesses Ta and Tb.

[0164] As described above, the insulating layer 106 functions as a gate insulating layer in the transistor 100. The thickness Tc of the portion of the insulating layer 106 in contact with the region 108M is preferably 1 nm to 200 nm, more preferably 1 nm to 150 nm, and even more preferably 1 nm to 100 nm. For example, when the channel length is 100 nm to 500 nm, the thickness Tc is preferably 30 nm to 100 nm. Furthermore, for example, when the channel length is 10 nm to 100 nm, the thickness Tc is preferably 1 nm to 50 nm. Furthermore, for example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm. Furthermore, for example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm.

[0165] The supply of the first element to the semiconductor layer 108 will be described. Here, an example will be described in which the first element is supplied from a direction perpendicular to the top surface of the substrate 102. Note that the cross-sectional view shown in FIG. 3B illustrates a configuration in which the surface of the insulating layer 106 (specifically, the top surface and side surface of the insulating layer 106) is parallel to the top surface and side surface of the semiconductor layer 108, which is the surface on which the insulating layer 106 is formed.

[0166] As described above, the first element is preferably supplied to the semiconductor layer 108 through the insulating layer 106. When the first element is supplied to the semiconductor layer 108 through the insulating layer 106, the first element penetrates from the surface of the insulating layer 106, passes through the insulating layer 106, and then reaches the semiconductor layer 108 through the interface between the insulating layer 106 and the semiconductor layer 108. In this case, the thickness of the insulating layer 106 in the direction in which the first element is supplied can also be said to be the depth from the surface of the insulating layer 106 to the semiconductor layer 108. Specifically, the thickness Ta can be said to be the depth from the surface of the insulating layer 106 to the region 108Da of the first element, and the thickness Tb can be said to be the depth from the surface of the insulating layer 106 to the region 108Db of the first element.

[0167] 3B shows the thickness Td of the insulating layer 106 in a region along the side surface of the insulating layer 110 in a direction perpendicular to the top surface of the substrate 102. For example, the thickness Td can be the thickness of the insulating layer 106 on a line extending from the midpoint between the top and bottom edges of the insulating layer 110b in a direction perpendicular to the top surface of the substrate 102. The thickness Td can also be considered the depth to which the first element reaches the region 108M from the surface of the insulating layer 106. Compared to the thickness Td, the thicknesses Ta and Tb are thinner. As a result, a larger amount of the first element is supplied to the regions of the semiconductor layer 108 along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b (e.g., regions 108Da, 108Db, and 108Dc) than to the regions along the side surface of the insulating layer 110 (e.g., region 108M). In this manner, the supply of the first element to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical resistance of the source region and the drain region can be preferentially reduced.

[0168] The thicker the insulating layer 106, the larger the difference between the thickness Ta and the thickness Td and the difference between the thickness Tb and the thickness Td can be. This can suppress the first element from being supplied to the channel formation region of the semiconductor layer 108, and can preferentially reduce the electrical resistance of the source and drain regions. On the other hand, in order to miniaturize transistors or fabricate transistors with extremely short channel lengths, a smaller thickness Tc is preferable from the viewpoints of improving on-current and suppressing the short channel effect.

[0169] The insulating layer 106 preferably includes an insulating layer containing oxygen. When an element that easily bonds with oxygen is used as the first element, the first element exists in a state bonded to oxygen in the insulating layer 106 as in the semiconductor layer 108. When oxygen and the first element are bonded and stabilized, oxygen is less likely to be released from the region containing the first element even when heat is applied, thereby suppressing oxygen diffusion to other layers. This suppresses oxygen supply from the insulating layer 106 to the regions 108Da, 108Db, and 108Dc while efficiently supplying oxygen to the channel formation region. Therefore, oxygen vacancies in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da, 108Db, and 108Dc from increasing. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0170] For example, when boron is used as the first element, the boron contained in the regions 108Da, 108Db, 108Dc, and the insulating layer 106 may exist in a state of being bonded to oxygen. ２ O ３ This can be confirmed by observing peaks due to bonding. Furthermore, in XPS analysis, spectral peaks due to the state in which boron element exists as a single element are not observed, or the peak intensity is extremely small, down to the background level. Similarly, when boron is used as the second element, the boron contained in region 208L and region 208D may exist in a state in which it is bonded to oxygen.

[0171] Note that a layer to which an impurity element (here, a first element and a second element) is supplied may be referred to as an implanted layer. For example, when the first element is supplied to the semiconductor layer 108 through the insulating layer 106, each of the insulating layer 106 and the semiconductor layer 108 may be referred to as an implanted layer.

[0172] The acceleration energy used to supply the impurity element is preferably set according to the type of impurity element (specifically, the type of ion), the composition, film density, and thickness of the implanted layer, and the composition, film density, and thickness of the mask layer. If the acceleration energy used to supply the first element is too high, the first element may also be supplied to region 108M and the semiconductor layer 208 (specifically, regions 208M, 208L, and 208D), potentially increasing the concentration of the first element in these regions. Therefore, it is preferable to set the acceleration energy so that the first element is supplied as little as possible to region 108M and the semiconductor layer 208. For example, it is preferable to set the acceleration energy used to supply the first element so that the concentration of the first element is highest at or near the interface between region 108Da and the insulating layer 106 and the interface between region 108Db and the insulating layer 106. Similarly, if the acceleration energy for supplying the second element is too high, the second element may also be supplied to regions 108M, 108Da, 108Db, and 208M, resulting in high concentrations of the second element in these regions. Therefore, it is preferable to set the acceleration energy so that the second element is supplied to regions 108M, 108Da, 108Db, and 208M as little as possible. For example, it is preferable to set the acceleration energy used for supplying the second element so that the concentration of the second element is highest at the interface between region 208L and insulating layer 106, the surface of region 208D, or in the vicinity thereof.

[0173] The concentration of the impurity element in the depth direction can be simulated using software, for example. Examples of simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. Simulation parameters can include the type of impurity element to be supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy. When the first element is supplied to the semiconductor layer 108 through the insulating layer 106, the depth to the region 108Da is "Ta," the depth to the region 108Db is "Tb," and the depth to the region 108M is "Td." It is preferable to select an acceleration energy that results in a high concentration of the first element in the regions 108Da and 108Db and a low concentration of the first element in the region 108M. Furthermore, it is preferable to select an acceleration energy that allows the concentrations of the first element in the regions 108Da, 108Db, and 108M to fall within the aforementioned ranges.

[0174] Although FIG. 1B and other figures illustrate a structure in which the semiconductor layer 108 includes the region 108Dc, one embodiment of the present invention is not limited thereto. An example of a structure in which the region 108Dc is not included is illustrated in FIGS. 5A and 5B . FIG. 5A is a top view of the transistor 100, and FIG. 5B is a cross-sectional view of the cut surface taken along the dashed-dotted line A1-A2 in FIG. 5A . As illustrated in FIGS. 5A and 5B , when the conductive layer 104 covers the entire semiconductor layer 108, that is, when the conductive layer 104 encompasses the semiconductor layer 108 in a top view, the entire semiconductor layer 108 is masked by the conductive layer 104 when the second element is supplied. As a result, the second element is not supplied to the semiconductor layer 108, and the region 108Dc is not formed. Note that although the structure in which the conductive layer 104 has a portion protruding beyond the end of the semiconductor layer 108 is illustrated here, the end of the conductive layer 104 may coincide or approximately coincide with the end of the semiconductor layer 108.

[0175] 1B and the like show a structure in which the conductive layer 212a and the conductive layer 212b are formed in the same process as the conductive layer 204, but one embodiment of the present invention is not limited to this. A structure example in which the conductive layer 212a and the conductive layer 212b are formed in a process different from that of the conductive layer 204 is shown in FIGS. 6A to 6C. FIG. 6A is a top view of the semiconductor device 10A, and FIG. 6B is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 6A.

[0176] The semiconductor device 10A includes a transistor 100, a transistor 200A, and an insulating layer 110. An enlarged view of the transistor 200 shown in FIG. 6B is shown in FIG.

[0177] 6B and 6C show a configuration in which the region 208D is formed in the entire region of the semiconductor layer 208 that does not overlap with the conductive layer 204. Openings 147a and 147b that reach the region 208D are provided in the insulating layer 106 and the insulating layer 195. For example, after the conductive layer 104 and the conductive layer 204 are formed on the insulating layer 106, the region 208D is formed in the region of the semiconductor layer 208 that does not overlap with the conductive layer 204 by supplying a second element to the semiconductor layer 208 using the conductive layer 204 as a mask. Then, an insulating layer 195 is formed over the conductive layer 104 and the conductive layer 204, openings 147a and 147b are formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 212a and the conductive layer 212b can be formed to cover the openings 147a and 147b. By forming the conductive layer 212a and the conductive layer 212b and the conductive layer 204 in different processes, different materials can be used for the conductive layer 212a and the conductive layer 212b and the conductive layer 204, thereby widening the range of material selection. Furthermore, the conductive layer formed in the same process as the conductive layer 212a and the conductive layer 212b and the conductive layer formed in the same process as the conductive layer 204 can each be used as a wiring, which increases the degree of freedom in layout and reduces the area occupied by the circuit.

[0178] 1B and the like illustrate an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143 in the transistor 100; however, one embodiment of the present invention is not limited to this. A structure can be used in which a step is formed between the insulating layer 110 and the conductive layer 112b and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, a structure can be used in which a step is formed between the insulating layer 110 and the conductive layer 212b and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0179] [Semiconductor Layer 108, Semiconductor Layer 208] Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. Examples of metal oxides include indium oxide (also referred to as indium oxide), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0180] The semiconductor layer 108 and the semiconductor layer 208 may be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al— Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0181] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0182] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0183] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0184] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0185] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0186] The electrical characteristics and reliability of the transistor 100 and the transistor 200 vary depending on the composition of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0187] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0188] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0189] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0190] By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or the field-effect mobility of the transistor 100 and the transistor 200 can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ ) can be suppressed. The content of element M in the metal oxide contained in the semiconductor layer 108 and the semiconductor layer 208 is preferably 0.1% to 25% inclusive, more preferably 0.1% to 20% inclusive, even more preferably 0.1% to 10% inclusive, even more preferably 0.1% to 8% inclusive, even more preferably 0.1% to 6% inclusive, and even more preferably 0.1% to 4% inclusive. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide of In:M:Zn=40:1:10 or a metal oxide thereof in the same range. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn=40:1:10 or a metal oxide thereof in the same range can be preferably used. Alternatively, metal oxides of In:Al:Zn=40:1:10 or a metal oxide thereof in the same range can be preferably used.

[0191] Here, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, the unevenness of the surfaces of the semiconductor layers 108 and 208 may increase. This may increase the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layers 108 and 208, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layers 108 and 208 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0192] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When ITSO is used, the silicon content is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0193] A metal oxide that does not contain element M can be applied to the semiconductor layer 108 and the semiconductor layer 208. When the metal oxide is an In—Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, the atomic ratio of In is more preferably equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0194] The compositions of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis can be performed by combining a plurality of these techniques. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0195] The sputtering method or the ALD method can be suitably used for forming the metal oxide. As the ALD method, the thermal ALD method or the PEALD method can be used. When the metal oxide is formed by the sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target. The PECVD method can also be used for forming the metal oxide.

[0196] It is preferable to use a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0197] The semiconductor layer 108 and the semiconductor layer 208 are preferably formed using a CAAC-OS or an nc-OS.

[0198] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are aligned in the normal direction to the surface where the semiconductor layer 108 and the semiconductor layer 208 are preferably formed. For example, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b, and layered crystals parallel to or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the side surface of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed, in the opening 141. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel to or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current. Similarly, the layered crystals of the semiconductor layer 208 are formed parallel to or approximately parallel to the channel length direction of the transistor 200, thereby enabling the transistor to have a large on-state current.

[0199] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0200] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total flow rate of film formation gas (hereinafter also referred to as oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0201] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0202] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0203] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of each of the regions 108M and 208M that function as channel formation regions is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0204] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0205] The semiconductor layer 108 and the semiconductor layer 208 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0206] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0207] The semiconductor layer 108 and the semiconductor layer 208 can have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 are the same or approximately the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0208] When the semiconductor layer 108 and the semiconductor layer 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, and therefore the crystallinity of the second metal oxide layer may be increased. Furthermore, by performing heat treatment after the second metal oxide layer is formed, the crystallinity of the first metal oxide layer can be increased. This heat treatment can also be called a crystallization treatment.

[0209] A first metal oxide layer is formed, and then a second metal oxide layer having higher crystallinity than the first layer is formed. For example, ALD can be suitably used to form the first metal oxide, and sputtering can be suitably used to form the second metal oxide layer. By performing heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. In this case, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to serve as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

[0210] A three-layer structure having a third metal oxide on the second metal oxide layer can be formed. For example, an ALD method can be suitably used to form the first metal oxide and the third metal oxide, and a sputtering method can be suitably used to form the second metal oxide layer. By performing a heat treatment after the formation of the third metal oxide layer, the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer can be increased. In this case, crystals contained in the second metal oxide grow continuously toward the first metal oxide and the third metal oxide, and the boundary between the first metal oxide layer and the second metal oxide layer and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. When the second metal oxide layer has a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

[0211] By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. This allows for a highly reliable transistor to be realized. Note that the thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the semiconductor layer is formed. A metal oxide layer with increased crystallinity in this manner can be called an axial growth CAAC (AG CAAC). Note that, in addition to crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the semiconductor layer is formed.

[0212] The temperature of the heat treatment can be set to 100°C or higher and lower than the strain point of the substrate. Specifically, a temperature of 100°C or higher and 800°C or lower is preferable, more preferably a temperature of 250°C or higher and 650°C or lower, and even more preferably a temperature of 350°C or higher and 550°C or lower is preferable. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C to 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by thermal conduction or thermal radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0213] [Insulating Layer 110] As described above, the insulating layer 110 preferably has a stacked-layer structure. The insulating layer 110b has a function of supplying oxygen to a channel formation region of the semiconductor layer 108. The insulating layer 110a and the insulating layer 110c function as barrier films.

[0214] If the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a or 112b via the insulating layer 110a or 110c, thereby reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. On the other hand, if the thicknesses T110a and T110c are large, the amount of impurities released from the insulating layer 110a or 110c may increase, resulting in a large amount of impurities diffusing into the channel formation region. As shown in FIG. 3B , the thickness T110a may be the shortest distance between the surface on which the insulating layer 110a is to be formed (here, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a in a cross-sectional view. The thickness T110c may be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c in a cross-sectional view.

[0215] The thickness T110c is preferably a value that allows the film to function as a barrier film against oxygen. The thickness T110c is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 3 nm to 50 nm, even more preferably 3 nm to 30 nm, even more preferably 3 nm to 20 nm, even more preferably 3 nm to 10 nm, and even more preferably 5 nm to 10 nm.

[0216] The thickness T110a can be thicker than the thickness T110c of the insulating layer 110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or the drain region to the gate electrode more uniform. This can make the electric field of the gate electrode applied to the channel formation region more uniform. The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm.

[0217] By setting the thickness T110a and the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ The thickness T110a and the thickness T110c are not limited to the above ranges.

[0218] At least one of the regions of the semiconductor layer 108 in contact with the insulating layer 110a and the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low resistance region can function as a buffer region for alleviating the drain electric field. Note that the low resistance region can also function as a source region or a drain region.

[0219] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0220] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0221] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0222] When the insulating layer 110c has a stacked structure, the materials listed in the description of the insulating layer 110c can be used for each of the layers constituting the insulating layer 110c. An oxide or oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0223] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0224] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. The top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 112b on the opening 143 side.

[0225] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be made to match or approximately match each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be made to match or approximately match the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. Note that the top shapes of the openings 141 and 143 may not be made to match each other. Note that when the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric.

[0226] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 3A to 3C.

[0227] In FIG. 3C , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0228] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0229] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0230] The channel length L100 can be controlled by adjusting the thickness T110b and the angle θ110.

[0231] The thickness T110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b may be appropriately set to obtain a desired channel length L100. As shown in FIG. 3B , the thickness T110b may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0232] The angle θ110 is preferably 90 degrees or less. By reducing the angle θ110, it is possible to improve the coverage of a layer (e.g., the semiconductor layer 108) formed on the insulating layer 110. Furthermore, when the angle θ110 is 90 degrees or less, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0233] When the angle θ110 is less than 90 degrees, the larger the angle θ110, the larger the difference between the thickness Ta and the thickness Td, and the difference between the thickness Tb and the thickness Td. Therefore, the supply of the first element to the region 108M is suppressed, and the first element is preferentially supplied to the regions 108Da, 108Db, and 108Dc. This allows the electrical resistance of the source region and the drain region of the semiconductor layer 108 to be efficiently reduced.

[0234] 3B and other figures, the angle θ110 is shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. For example, as shown in Fig. 7, the angle θ110 can be set to 90 degrees or approximately 90 degrees. This allows the channel length L100 to be shortened.

[0235] In a configuration in which the angle θ110 is 90 degrees, when the first element is supplied through the insulating layer 106, the first element must pass through the insulating layer 106, the region of the semiconductor layer 108 that contacts the side surface of the conductive layer 112b, and the region that contacts the side surface of the insulating layer 110c before reaching the region 108M. Therefore, the depth in the region 108M is deeper than the depths in the regions 108Da, 108Db, and 108Dc. Therefore, the concentration of the first element in the region 108M is lower than the concentrations of the first element in the regions 108Da, 108Db, and 108Dc. Note that the higher the film density of the material used for the semiconductor layer 108, the higher the stopping power in ion implantation, and the smaller the amount of the first element that reaches the channel formation region. For example, if the film density of the semiconductor layer 108 is higher than that of the insulating layer 106, the amount of the first element supplied to the semiconductor layer 108 will be smaller even at the same depth. Furthermore, since the stopping power in ion implantation differs depending on the type of element, the amount of the first element supplied also differs depending on the composition of the implanted layer.

[0236] The angle θ110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be 90 degrees or less, 85 degrees or less, or 80 degrees or less. The angle θ110 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angle θ110 can be set appropriately to obtain the desired channel length L100.

[0237] As described above, the larger the angle θ110, the more the first element can be preferentially supplied to the regions 108Da, 108Db, and 108Dc. However, if the angle θ110 is large, there is a risk that the coverage of the layers (e.g., the semiconductor layer 108 and the insulating layer 106) provided in the openings 141 and 143 will be reduced. Therefore, the angle θ110 is preferably 65 degrees or more and 90 degrees or less, more preferably 70 degrees or more and 90 degrees or less, and even more preferably 75 degrees or more and 90 degrees or less.

[0238] Note that when the angle θ110 is large, it is preferable to use a film formation method with higher coverage for forming the layers provided in the openings 141 and 143. For example, when the angle θ110 is 85 degrees or more and 90 degrees or less, the ALD method can be suitably used for forming the insulating layer 106 and the semiconductor layer 108. On the other hand, when the angle θ110 is small, it is preferable to use a film formation method with higher productivity. For example, when the angle θ110 is less than 85 degrees, it is preferable to use the PECVD method for forming the insulating layer 106 and the sputtering method for forming the semiconductor layer 108.

[0239] 1B and the like show a structure in which the shape of the side surface of the insulating layer 110 on the opening 141 side is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side can be curved. Alternatively, a structure in which the shape of the side surface includes both a straight region and a curved region can be used.

[0240] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view.

[0241] 3A and 3C, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 3A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the perimeter of the circle. In other words, the channel width W100 is π×D141. When the top surface shape of the opening 141 is circular, a transistor 100 with a smaller channel width can be realized compared to openings with other shapes.

[0242] The width D141 may vary in the depth direction. For example, the width D141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three diameters of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the width D141 may be any of the diameters at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these diameters of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view.

[0243] When forming opening 141 using photolithography, width D141 is equal to or greater than the minimum exposure dimension of the exposure device. Width D141 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0244] Note that although the structure in which the region 108M functions as a channel formation region of the transistor 100 has been described as an example here, one embodiment of the present invention is not limited to this. A region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. A region of the semiconductor layer 108 in contact with the insulating layer 110c may also function as a channel formation region.

[0245] Next, the channel length and channel width of the transistor 200 will be described with reference to FIGS. 4A to 4C.

[0246] The channel length of the transistor 200 is the length of the region 208M between the pair of regions 208D. In Figures 4A and 4B, the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200 of the transistor 200 is determined by the length of the conductive layer 204 and is equal to or greater than the minimum dimension of an exposure device used to fabricate the transistor. For example, the channel length L200 can be 1.5 µm or greater. By increasing the channel length, the transistor can have high saturation properties.

[0247] The channel width of the transistor 200 is the width of the region 208M in the direction perpendicular to the channel length direction. In Figures 4A and 4C, the channel width W200 of the transistor 200 is indicated by a dashed line with a double-headed arrow. The channel width W200 is also equal to or greater than the minimum dimension of the exposure device.

[0248] Note that although the example in which the region 208M functions as a channel formation region of the transistor 200 has been described here, one embodiment of the present invention is not limited to this. A region of the semiconductor layer 208 that overlaps with the conductive layer 202 but does not overlap with the conductive layer 204 may also function as a channel formation region.

[0249] As described above, the channel length L100 of the transistor 100 can be smaller than the minimum dimension of the exposure tool, and the channel length L200 of the transistor 200 can be equal to or larger than the minimum dimension of the exposure tool. For example, by applying the transistor 100 to a transistor requiring a large on-state current and the transistor 200 to a transistor requiring high saturation, a high-performance semiconductor device can be realized by utilizing the advantages of each transistor. Furthermore, the transistors 100 and 200 can be formed using some common processes. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same process. Part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another part of the insulating layer 106 functions as a gate insulating layer for the transistor 200. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process. Therefore, productivity of the semiconductor device can be improved and manufacturing costs can be reduced.

[0250] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 104, Conductive Layer 204, Conductive Layer 212a, Conductive Layer 212b, and Conductive Layer 202] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each have a single-layer structure or a stacked structure of two or more layers. Examples of materials that can be used for these layers include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals. A conductive material with low electrical resistivity, including one or more of copper, silver, gold, and aluminum, can be preferably used for each of the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0251] A conductive metal oxide (also referred to as an oxide conductor) can be used for each of the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0252] Oxygen deficiency (V) in metal oxides with semiconducting properties Ｏ ) and the oxygen vacancy (V Ｏ When hydrogen is added to a metal oxide, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive. A metal oxide that has become electrically conductive can be called an oxide conductor.

[0253] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0254] The conductive layers 112a, 112b, 104, 204, 212a, and 212b may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, the film can be processed by wet etching, thereby reducing manufacturing costs.

[0255] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can be formed using the same material, or at least one of them can be formed using a different material.

[0256] The semiconductor layer 108 is formed after the conductive layer 112a and the conductive layer 112b are formed. When the semiconductor layer 108 contains oxygen or is formed in an atmosphere containing oxygen, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a and the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112a and the conductive layer 112b.

[0257] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0258] The conductive layer 112 a and the conductive layer 112 b can each be formed using any of the above-described oxide conductors, such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0259] The conductive layer 112a and the conductive layer 112b may each be formed using a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each be formed using the nitride conductor.

[0260] 8A to 8D are cross-sectional views of a transistor 100A that can be used in a semiconductor device according to one embodiment of the present invention. For a top view of the semiconductor device, refer to FIG. 1A. Each of FIGS. 8A to 8D is a cross-sectional view taken along the dashed dotted line B1-B2 in FIG. 1A.

[0261] The transistor 100A differs mainly from the transistor 100 illustrated in FIG. 1B and the like in that the conductive layer 112a has a stacked-layer structure.

[0262] 8A and 8B show a structure in which the conductive layer 112a has a two-layer structure including a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1.

[0263] For the conductive layer 112a_2 having a region in contact with the semiconductor layer 108, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112a_2, the description of the conductive layer 112a can be referred to.

[0264] The conductive layer 112a_1 does not have a region in contact with the semiconductor layer 108, and therefore the material used is not particularly limited. For example, the conductive layer 112a_1 is preferably made of a material having lower electrical resistivity than the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and copper or tungsten can be preferably used for the conductive layer 112a_1.

[0265] 8A, the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_1. For example, the conductive layer 112a can be formed by forming a first film to be the conductive layer 112a_1 and a second film to be the conductive layer 112a_2, and then processing the first film and the second film. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0266] The end of the conductive layer 112a_2 may not be aligned with the end of the conductive layer 112a_1. As shown in FIG. 8B , the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1. The conductive layer 112a_2 has a region in contact with the top surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion protruding beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 may be formed, a film to become the conductive layer 112a_2 may be formed on the conductive layer 112a_1, and the film may be processed to form the conductive layer 112a_2. By making the conductive layer 112a_2 protrude beyond the end of the conductive layer 112a_1, the step of the formation surface of a layer (e.g., the insulating layer 110) formed on the conductive layer 112a is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0267] 8A and 8B show the layers constituting the conductive layer 112a as having the same or approximately the same thickness, but this is not limited to this embodiment of the present invention. The thicknesses of some or all of the layers constituting the conductive layer 112a may be different. For example, it is more preferable to make the thickness of a layer using a material with low electrical resistivity thicker than the other layers, which can reduce the electrical resistance of the conductive layer 112a. Specifically, a material with lower electrical resistivity than the conductive layer 112a_1 can be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 can be made thicker than the thickness of the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a.

[0268] 8C and 8D show a structure in which the conductive layer 112a has a three-layer structure including a conductive layer 112a_3, a conductive layer 112a_1 over the conductive layer 112a_3, and a conductive layer 112a_2 over the conductive layer 112a_1.

[0269] 8C , the end portion of the conductive layer 112a_1 can be in contact with the top surface of the conductive layer 112a_3. The conductive layer 112a_2 has regions in contact with the top surface and side surface of the conductive layer 112a_1 and the top surface of the conductive layer 112a_3. That is, it can be said that the conductive layers 112a_2 and 112a_3 each have portions that protrude beyond the end portion of the conductive layer 112a_1. It can also be said that the top surface, side surface, and bottom surface of the conductive layer 112a_1 are surrounded by the conductive layers 112a_2 and 112a_3. The conductive layer 112a_3 is preferably made of a material that has high adhesion to the surface on which the conductive layer 112a_3 is to be formed (here, the surface of the substrate 102).

[0270] As described above, the conductive layer 112a_1 is preferably formed using a material with low electrical resistivity. However, depending on the material, adhesion between the conductive layer 112a_1 and a surface on which the conductive layer 112a_1 is to be formed (e.g., the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112a_3 that has higher adhesion to the surface on which the conductive layer 112a_1 is to be formed than the conductive layer 112a_1, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112a_3 is preferably a thickness that effectively increases the adhesion of the conductive layer 112a to the surface on which the conductive layer 112a is to be formed, and can be thinner than the thicknesses of the conductive layer 112a_1 and the conductive layer 112a_2. Reducing the thickness of the conductive layer 112a_3 can reduce manufacturing costs.

[0271] For example, it is preferable to use In—Sn—Si oxide (ITSO) for the conductive layer 112a_3, copper for the conductive layer 112a_1, and In—Sn—Si oxide (ITSO) for the conductive layer 112a_2. When a glass substrate is used as the substrate 102, adhesion between the glass substrate and an ITSO film is higher than adhesion between a glass substrate and a copper film. Furthermore, using the same material for the conductive layers 112a_2 and 112a_3 facilitates processing when the conductive layers 112a_2 and 112a_3 are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0272] As shown in FIG. 8C , the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_3. For example, a first film to be the conductive layer 112a_3 is formed, a conductive layer 112a_1 is formed on the first film, and a second film to be the conductive layer 112a_2 is formed on the first film and the conductive layer 112a_1. Then, by processing the first film and the second film, the conductive layer 112a including the conductive layer 112a_3, the conductive layer 112a_1, and the conductive layer 112a_2 can be formed. Processing the first film and the second film in the same process can reduce manufacturing costs. Alternatively, as shown in FIG. 8D , the edge of the conductive layer 112a_1 can be aligned or substantially aligned with the edge of the conductive layer 112a_3.

[0273] Although the conductive layer 112a has a stacked structure of two or three layers in this example, one embodiment of the present invention is not limited to this. The conductive layer 112a can also have a stacked structure of four or more layers.

[0274] The configuration of the conductive layer 112a shown in FIGS. 8A to 8D can also be applied to other configuration examples.

[0275] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0276] The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, any of the above-described oxides and oxynitrides is preferably used for at least the films in contact with the semiconductor layer 108 and the semiconductor layer 208 among the films constituting the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0277] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0278] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0279] 9 is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 9 is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0280] The semiconductor device 10B includes a transistor 100B, a transistor 200B, and an insulating layer 110. The transistors 100B and 200B are different from the transistors 100 and 200 shown in FIG. 1B and the like mainly in that the insulating layer 106 has a stacked-layer structure. FIG. 9 shows a configuration in which the insulating layer 106 has a two-layer structure including an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0281] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer (the insulating layer 106a here) on the semiconductor layer 108 and the semiconductor layer 208 side preferably contains oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0282] It is preferable to use a material that is difficult for substances (e.g., atoms, molecules, and ions) to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100B and the transistor 200B from diffusing into the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ) can be suppressed. In addition, it is possible to suppress an increase in the electrical resistance of the conductive layer 104 and the conductive layer 204 due to oxidation of the conductive layer 104 and the conductive layer 204 by oxygen contained in the semiconductor layer 108 and the semiconductor layer 208. As a result, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of an oxide and an oxynitride can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0283] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b.

[0284] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0285] The configuration of the insulating layer 106 shown in FIG. 9 can also be applied to other configuration examples.

[0286] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer for the transistors 100 and 200, is preferably made of a material through which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0287] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 195 can have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0288] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shapes of the semiconductor substrate and the insulating substrate are not particularly limited and may be circular or rectangular.

[0289] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0290] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0291] 10A is a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, see FIG. 1A. FIG. 10A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0292] The semiconductor device 10C includes a transistor 100C, a transistor 200C, and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0293] FIG. 10B shows an enlarged view of the transistor 100C shown in FIG. 10A , and FIG. 10C shows an enlarged view of the transistor 200C. The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of the same material as the insulating layer 110a and the insulating layer 110c, respectively. The insulating layer 110d and the insulating layer 110e can be made of, for example, silicon nitride or silicon nitride oxide, respectively. Note that the insulating layer 110d and the insulating layer 110e can be made of the same material, or different materials can be used.

[0294] The insulating layer 110d is provided between the conductive layer 112a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 112a. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 108.

[0295] The insulating layer 110e is provided between the conductive layer 112b and the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the bottom surface of the insulating layer 106, the side surface of the semiconductor layer 108, the bottom surface of the semiconductor layer 208, the bottom surface of the insulating layer 120, and the bottom surface of the conductive layer 202.

[0296] It is more preferable that the insulating layers 110d and 110e are made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. This allows the region of the semiconductor layer 108 in contact with the insulating layer 110d and the region of the semiconductor layer 108 in contact with the insulating layer 110e to be low-resistance regions. The semiconductor layer 108 can have low-resistance regions between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region, and between the region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance regions can function as buffer regions for reducing the drain electric field. Note that these low-resistance regions may function as source or drain regions.

[0297] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and the degradation of the transistor. For example, in the transistor 100C, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by forming the region of the semiconductor layer 108 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and the degradation of the transistor. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by forming the region of the semiconductor layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and the degradation of the transistor.

[0298] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0299] It is preferable that the insulating layer 110a be provided between the insulating layer 110d and the insulating layer 110b, and the insulating layer 110c be provided between the insulating layer 110e and the insulating layer 110b. By providing the insulating layer 110a and the insulating layer 110c functioning as barrier films, impurities released from the insulating layer 110d and the insulating layer 110e can be prevented from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layer 110a and the insulating layer 110b or through the insulating layer 110c and the insulating layer 110b. This enables a transistor to exhibit favorable electrical characteristics and high reliability.

[0300] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layers 110d and 110e contain hydrogen elements. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0301] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0302] The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 110d and the insulating layer 110a. Specifically, the deposition conditions for the insulating layer 110d and the insulating layer 110a can be varied by varying one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density for the insulating layer 110d lower than the deposition power density for the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0303] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are formed by PECVD for the insulating layer 110d and the insulating layer 110a, respectively, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under conditions with a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased. For example, the insulating layer 110d can be formed using ammonia gas, and the insulating layer 110a can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form insulating layer 110a can be said to be zero, and the ammonia flow ratio of the deposition gas used to form insulating layer 110d can be said to be higher than the ammonia flow ratio of the deposition gas used to form insulating layer 110a.

[0304] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0305] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0306] The conductive layer 202 included in the transistor 200 is provided over the insulating layer 110e. When the insulating layer 110e is provided, the insulating layer 120 preferably includes a barrier film. For example, as shown in FIG. 10A and other figures, providing an insulating layer 120a that functions as a barrier film can prevent impurities released from the insulating layer 110e from diffusing into the channel formation region of the semiconductor layer 208. Furthermore, when the source region or drain region of the semiconductor layer 208 is in contact with the insulating layer 110e, the impurities released from the insulating layer 110e can reduce the electrical resistance of these regions.

[0307] Although the insulating layer 110 has a five-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a two-layer, three-layer, four-layer, or six or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0308] The configuration of the insulating layer 110 shown in Configuration Example 2 can also be applied to other configuration examples.

[0309] 11A is a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, refer to FIG. 1A. FIG. 11A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A.

[0310] The semiconductor device 10D includes a transistor 100D, a transistor 200D, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG.

[0311] 11B is an enlarged view of the transistor 100D shown in FIG. 11A. The insulating layer 109 is provided between the conductive layer 112a and the insulating layer 110 and the substrate 102. The insulating layer 109 is provided over the substrate 102, the conductive layer 112a is provided over the insulating layer 109, and the insulating layer 110 is provided over the conductive layer 112a and the insulating layer 109. The insulating layer 109 has regions in contact with the bottom surface of the conductive layer 112a, the bottom surface of the insulating layer 110, and the top surface of the substrate 102. The conductive layer 112a has regions in contact with and sandwiched between the insulating layer 109 and the insulating layer 110. The insulating layer 110 has regions in contact with the top surface and side surface of the conductive layer 112a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, and the bottom surface of the conductive layer 112b.

[0312] The insulating layer 109 is preferably made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. The insulating layer 109 can be made of the same material as can be used for the insulating layer 110d and the insulating layer 110e. For example, the insulating layer 109 can be made of silicon nitride or silicon nitride oxide.

[0313] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a also diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This reduces the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0314] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layer 109 contain hydrogen elements. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, and the electrical resistance of one of the source region and the drain region can be reduced.

[0315] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. For example, when a metal oxide is used for the conductive layer 112a, the impurities preferably contain hydrogen elements. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108.

[0316] The materials that can be used for the conductive layer 112a are as described above. Note that the conductive layer 112a preferably easily transmits impurities and more preferably does not easily adsorb impurities.

[0317] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 112a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0318] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0319] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0320] 11A and other drawings show the insulating layer 110 having a four-layer structure of insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a three-layer structure of insulating layers 110a, 110b, and 110c. Alternatively, the insulating layer 110 can have a structure including insulating layers 110a, 110b, 110c, 110d, and 110e.

[0321] The configuration of the insulating layer 109 shown in Configuration Example 3 can also be applied to other configuration examples.

[0322] 12A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, see FIG. 1A. FIG. 12A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0323] The semiconductor device 10E includes a transistor 100E, a transistor 200E, and an insulating layer 110. The transistor 100E differs mainly from the transistor 100 shown in FIG. 1B and the like in that the semiconductor layer 108 has a stacked structure, and the transistor 200E differs mainly from the transistor 200 in that the semiconductor layer 208 has a stacked structure.

[0324] Fig. 12B shows an enlarged view of the transistor 100E shown in Fig. 12A, and Fig. 12C shows an enlarged view of the transistor 200E. Fig. 12A to Fig. 12C show a configuration in which the semiconductor layer 108 has a three-layer structure of a semiconductor layer 108a, a semiconductor layer 108b on the semiconductor layer 108a, and a semiconductor layer 108c on the semiconductor layer 108b, and a configuration in which the semiconductor layer 208 has a three-layer structure of a semiconductor layer 208a, a semiconductor layer 208b on the semiconductor layer 208a, and a semiconductor layer 208c on the semiconductor layer 208b.

[0325] The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c can each be made of the materials listed in the description of the semiconductor layer 108 and the semiconductor layer 208. The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c each preferably contains a metal oxide exhibiting semiconductor properties.

[0326] The semiconductor layer 108a and the semiconductor layer 208a can be formed in the same step, the semiconductor layer 108b and the semiconductor layer 208b can be formed in the same step, and the semiconductor layer 108c and the semiconductor layer 208c can be formed in the same step.

[0327] The band gap of each of the first metal oxide included in the semiconductor layer 108a and the semiconductor layer 208a, the second metal oxide included in the semiconductor layer 108b and the semiconductor layer 208b, and the third metal oxide included in the semiconductor layer 108c and the semiconductor layer 208c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0328] The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide. The semiconductor layer 108b is sandwiched between the semiconductor layers 108a and 108c, which have larger band gaps than the semiconductor layer 108b, to form a buried channel. As a result, the semiconductor layer 108b serves as the main current path in the semiconductor layer 108. Similarly, the semiconductor layer 208b is sandwiched between the semiconductor layers 208a and 208c to form a buried channel. As a result, the semiconductor layer 208b serves as the main current path in the semiconductor layer 208.

[0329] In the following, the semiconductor layer 108 including the semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c will be described as an example, and a description of the semiconductor layer 208 may be omitted.

[0330] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0331] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0332] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0333] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141, and components of the conductive layers 112a and 112b that are attached to the side surfaces of the insulating layer 110 when the opening 141 is formed. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0334] Damage may occur to the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity. By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap states.

[0335] By sandwiching the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, between the semiconductor layer 108a and the semiconductor layer 108c, it is possible to reduce trap levels at the interface of the semiconductor layer 108b and in the vicinity of the interface. This makes it possible to provide a transistor with high on-state current and high reliability. Therefore, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0336] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0337] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0338] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide can have the same structure. Alternatively, some or all of these elements can be different. Furthermore, when one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as the element M contained in the other metal oxide, or some or all of the elements M may be different.

[0339] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0340] The second metal oxide may be free of element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio; the second metal oxide may have an atomic ratio of In:Zn=4:1 or a similar ratio; and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:1 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:4 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition.

[0341] 13 shows an enlarged view of the side surfaces of the semiconductor layer 108 and the insulating layer 110 and their vicinity. In FIG. 13, the thickness T108a of the semiconductor layer 108a, the thickness T108b of the semiconductor layer 108b, and the thickness T108c of the semiconductor layer 108c are indicated by solid arrows. Here, the thickness of the semiconductor layer 108 is defined as the shortest distance between the insulating layer 110b and the insulating layer 106 in the region in contact with the semiconductor layer 108 in a cross-sectional view. The thickness of each layer of the semiconductor layer 108 can be, for example, the thickness of each layer of the semiconductor layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of the insulating layer 110.

[0342] By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path, a transistor with a large on-state current can be obtained. The thickness T108b is preferably greater than the thickness T108a and the thickness T108c. However, if the thickness T108b is too thick, oxygen vacancies (VＯ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. The thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0343] The thickness T108c is preferably thicker than the thickness T108a. By increasing the thickness T108c, the semiconductor layer 108b can be separated from trap levels that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof. Furthermore, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the semiconductor layer 108b increases, which may result in a small on-state current. The thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0344] Oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b via the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces the oxygen vacancy (V Ｏ ) and V ＯH can be reduced. If the thickness T108a is too thin, the distance between the interface between the insulating layer 110 and the semiconductor layer 108 and the trap level near the interface and the semiconductor layer 108b, which is the main current path, becomes short, which may result in a small on-current. Furthermore, reliability may be deteriorated. The thickness T108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.

[0345] It is more preferable that the semiconductor layers 108a, 108b, and 108c each have crystallinity. When the semiconductor layer 108a has crystallinity, the crystallinity of the semiconductor layer 108b formed thereon can be increased. Similarly, when the semiconductor layer 108b has crystallinity, the crystallinity of the semiconductor layer 108c formed thereon can be increased.

[0346] The band gap of the first metal oxide and the band gap of the third metal oxide can be different. The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c located on the conductive layer 104 side functioning as a gate electrode, carriers are prevented from being generated and induced in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (the insulating layer 106 here), thereby making the transistor highly reliable. For example, carriers are prevented from being generated and induced in the semiconductor layer 108c and at the interface thereof by light incident on the transistor, thereby making it possible to suppress fluctuations in the electrical characteristics of the transistor due to light.

[0347] By making the band gap of the first metal oxide in the semiconductor layer 108 a smaller than the band gap of the third metal oxide, the contact resistance between the semiconductor layer 108 a and the conductive layer 112 a and the contact resistance between the semiconductor layer 108 a and the conductive layer 112 b can be reduced, and therefore, a transistor with large on-state current can be obtained.

[0348] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0349] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0350] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0351] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0352] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0353] 12A and the like illustrate an example in which the semiconductor layer 108 and the semiconductor layer 208 each have a three-layer structure, but one embodiment of the present invention is not limited to this. For example, the semiconductor layer 108 may have a structure in which the semiconductor layer 108a and the semiconductor layer 108c are not included or both, and the semiconductor layer 208 may have a structure in which the semiconductor layer 208a and the semiconductor layer 208c are not included or both. Specifically, as shown in FIG. 14A , the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108b and the semiconductor layer 108c, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208b and the semiconductor layer 208c. Alternatively, as shown in FIG. 14B , the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108a and the semiconductor layer 108b, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208a and the semiconductor layer 208b. Alternatively, each of the semiconductor layer 108 and the semiconductor layer 208 can have a stacked structure of four or more layers.

[0354] The structures of the semiconductor layer 108 and the semiconductor layer 208 shown in Structure Example 4 can also be applied to other structure examples.

[0355] 15A is a top view of a semiconductor device 10F of one embodiment of the present invention, FIG. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 15A , and FIG. 16A is a cross-sectional view taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0356] The semiconductor device 10F includes a transistor 100F, a transistor 200F, and an insulating layer 110. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the transistor 100F includes a conductive layer 103 and an insulating layer 107 and in that the configuration of the insulating layer 110 is different.

[0357] FIG. 16B shows an enlarged view of the transistor 100F shown in FIG. 15A . The transistor 100F includes a conductive layer 103 between the insulating layer 110b and the insulating layer 110c. The insulating layer 110 and the conductive layer 103 have an opening 141 that reaches the conductive layer 112a. The insulating layer 107 has a region in contact with the side surfaces of the insulating layer 110 and the conductive layer 103 in the opening 141 and a region in contact with the conductive layer 112b in the opening 143. The insulating layer 107 is provided along the side surfaces of the insulating layer 110 and the conductive layer 112b in the openings 141 and 143, and can therefore be called a sidewall or sidewall insulating layer. Furthermore, the insulating layer 107 has a region in contact with a part of the top surface of the conductive layer 112a in the opening 141. The semiconductor layer 108 has a region in contact with a part of the top surface of the conductive layer 112a and the side surface of the insulating layer 107 in the opening 141, and has a region in contact with the side surface of the insulating layer 107 in the opening 143. The insulating layer 107 is located between the conductive layer 103 and the semiconductor layer 108, and the conductive layer 103 and the semiconductor layer 108 are electrically insulated from each other by the insulating layer 107.

[0358] In the transistor 100F, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween and with the conductive layer 103 with the insulating layer 107 interposed therebetween. In other words, the semiconductor layer 108 has a region that is sandwiched between the conductive layer 104 with the insulating layer 106 interposed therebetween and the conductive layer 103 with the insulating layer 107 interposed therebetween.

[0359] In the transistor 100F, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 107 functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 103 can be formed using the same material as can be formed into the conductive layers 112a, 112b, and 104.

[0360] By providing a back gate electrode in the transistor 100F, the potential on the back channel side of the semiconductor layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0361] 16B and other figures, the height of the upper surface of the insulating layer 107 can be made to coincide or approximately coincide with the height of the upper surface of the conductive layer 112b. For example, the insulating layer 107 can be formed by providing a film to be the insulating layer 107 so as to cover the openings 141 and 143, and then removing a portion of the film to expose at least the upper surfaces of the conductive layers 112a and 112b. For example, anisotropic etching can be suitably used to form the insulating layer 107.

[0362] The insulating layer 107 can be formed using a material that can be used for the insulating layer 106. When a metal oxide is used for the semiconductor layer 108, it is preferable to use any of the above-described oxides and oxynitrides for at least a film that is in contact with the semiconductor layer 108 among the films that form the insulating layer 107. For the insulating layer 107, the description of the insulating layer 106 can be referred to.

[0363] An insulating layer 110f is preferably provided between the insulating layer 110b and the conductive layer 103. An insulating layer 110g and an insulating layer 110h are preferably provided between the conductive layer 103 and the insulating layer 110c. An insulating layer 110a, an insulating layer 110b, an insulating layer 110f, a conductive layer 103, an insulating layer 110g, an insulating layer 110h, and an insulating layer 110c are stacked in this order between the conductive layer 112a and the conductive layer 112b. The insulating layer 110g has a region in contact with the side surface of the conductive layer 103 that is not in contact with the insulating layer 107, the top surface of the conductive layer 103, and the top surface of the insulating layer 110f.

[0364] The insulating layers 110b and 110h are preferably made of a material that releases oxygen when heated. Oxygen released from the insulating layers 110b and 110h by heat applied during the manufacturing process of the semiconductor device 10 is supplied to the insulating layer 107. Furthermore, oxygen released from the insulating layer 107 can be supplied to the semiconductor layer 108. Oxygen is supplied from the insulating layers 110b and 110f to the semiconductor layer 108, particularly the channel formation region, through the insulating layer 107, thereby reducing oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Therefore, the transistor 100F can have favorable electrical characteristics and high reliability. The insulating layer 110h can be made of any of the materials listed in the description of the insulating layer 110b. For example, the insulating layer 110h can be made of silicon oxide, silicon oxynitride, or both. For the insulating layer 110h, the description of the insulating layer 110b can be referred to.

[0365] The insulating layer 110f is provided between the insulating layer 110b and the conductive layer 103. The insulating layer 110g is provided between the insulating layer 110h and the conductive layer 103. The insulating layers 110f and 110g preferably emit a small amount of impurities (e.g., hydrogen and water) and are impermeable to impurities. It is more preferable that the insulating layers 110f and 110g are made of a material that is impermeable to oxygen. The insulating layers 110f and 110g can also function as barrier films. By providing the insulating layers 110f and 110g that function as barrier films, oxygen contained in the insulating layers 110b and 110h can be prevented from diffusing into the conductive layer 103. This prevents the conductive layer 103 from being oxidized and its electrical resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 110b and the insulating layer 110h to the insulating layer 107 increases, which can increase the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Therefore, the oxygen vacancy (V Ｏ ) and V Ｏ H can be reduced. The insulating layers 110f and 110g can be made of the materials listed in the description of the insulating layers 110a and 110c. For example, silicon nitride can be suitably used for the insulating layers 110f and 110g. For the insulating layers 110f and 110g, the description of the insulating layers 110a and 110c can be referred to.

[0366] 16B , the channel length L100 of the transistor 100F is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100F corresponds to the length of the region where the insulating layer 107 and the semiconductor layer 108 contact each other in a cross-sectional view. That is, the channel length L100 is determined by the sum of the thicknesses of the conductive layer 112b, the conductive layer 103, and the insulating layer 110, and the angle θ110 between the side surface of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is to be formed (here, the top surface of the conductive layer 112a). Therefore, the transistor 100F can be manufactured with high accuracy, having a channel length shorter than the minimum exposure dimension of an exposure tool used to manufacture the transistor.

[0367] The conductive layer 103 can be electrically connected to the conductive layer 112a. For example, openings can be formed in regions of the insulating layers 110a, 110b, and 110f that overlap with the conductive layer 112a, and the conductive layer 103 can be provided to cover the openings, thereby enabling the conductive layer 103 to be in contact with the conductive layer 112a. The conductive layer 112a, which functions as a source or drain electrode, is electrically connected to the conductive layer 103, which functions as a back gate electrode, so that the source or drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112a functions as a source electrode, a shift in the threshold voltage of the transistor 100F can be suppressed. Furthermore, the reliability of the transistor 100F can be improved. Note that the conductive layer 103 can also be formed in contact with the top surface of the conductive layer 112a without providing the insulating layers 110a, 110b, and 110f.

[0368] The conductive layer 103 can be electrically connected to the conductive layer 112b. For example, openings are provided in the insulating layers 110g, 110h, and 110c in regions overlapping with the conductive layer 103, and the conductive layer 112b is provided to cover the openings, so that the conductive layer 103 and the conductive layer 112b can be in contact with each other.

[0369] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings are provided in regions of the insulating layers 110g, 110h, 110c, and 106 that overlap with the conductive layer 103, and the conductive layer 104 is provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 103 and the conductive layer 104 are in contact with each other. By electrically connecting the conductive layer 104 that functions as a gate electrode to the conductive layer 103 that functions as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100F can be increased.

[0370] The structures of the conductive layer 103, the insulating layer 107, and the insulating layer 110 shown in Structural Example 5 can also be applied to other structural examples.

[0371] 17A is a top view of a semiconductor device 10G according to one embodiment of the present invention, FIG. 17B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 17A , and FIG. 17C is a cross-sectional view taken along dashed dotted line B5-B6 in FIG.

[0372] The semiconductor device 10G includes a transistor 100G, a transistor 200G, a capacitor 150, and an insulating layer 110. The semiconductor device 10G differs from the semiconductor device 10 shown in FIG.

[0373] For the transistor 100G and the transistor 200G, the description of the transistor 100 and the transistor 200 shown in FIG. 1A and the like can be referred to.

[0374] The capacitor 150 includes a conductive layer 202, an insulating layer 120 over the conductive layer 202, and a conductive layer 112b over the insulating layer 120. In the capacitor 150, the conductive layer 202 and the conductive layer 112b function as a pair of electrodes, and the insulating layer 120 sandwiched between them functions as a dielectric. The insulating layer 120 is provided over the conductive layer 202, and the conductive layer 112b is provided over the insulating layer 120. The conductive layer 112b has a region in contact with the top surface of the insulating layer 110 and the top surface and side surfaces of the insulating layer 120.

[0375] For example, the conductive layer 112b can be formed after the insulating layer 120 is formed over the conductive layer 202. By forming the conductive layer 202 and the conductive layer 112b in different processes, the capacitor 150 can be formed using these layers as a pair of electrodes. Furthermore, by forming the conductive layer 112b and the conductive layer 202 in different processes, different materials can be used for the conductive layer 112b and the conductive layer 202, thereby widening the range of material selection. Furthermore, the conductive layer formed in the same process as the conductive layer 112b and the conductive layer formed in the same process as the conductive layer 202 can each be used as a wiring, which increases the degree of freedom in layout and reduces the area occupied by the circuit.

[0376] The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100 and as one of the pair of electrodes of the capacitor 150. The conductive layer 202 functions as the backgate electrode of the transistor 200 and as the other of the pair of electrodes of the capacitor 150.

[0377] 17C illustrates an example in which the capacitor 150 is formed with the conductive layer 112b, the conductive layer 202, and the insulating layer 120, but there is no particular limitation on the configuration of the capacitor 150. In addition, although the configuration in which the other of the source electrode and the drain electrode of the transistor 100 is electrically connected to one of the pair of electrodes of the capacitor 150 and the backgate electrode of the transistor 200 is electrically connected to the other of the pair of electrodes of the capacitor 150 is illustrated, there is no particular limitation on the electrical connection relationship between the transistor 100, the transistor 200, and the capacitor 150.

[0378] The configuration of the capacitance element 150 shown in Configuration Example 6 can also be applied to other configuration examples.

[0379] 18A is a top view of a semiconductor device 10H according to one embodiment of the present invention, FIG. 18B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 18A , and FIG. 18C is a cross-sectional view taken along dashed dotted line B5-B6 in FIG.

[0380] The semiconductor device 10H includes a transistor 100H, a transistor 200H, a capacitor 150A, and an insulating layer 110. The transistor 200H differs from the transistor 200C shown in FIG. 10A and the like mainly in that a conductive layer 202 is provided between the insulating layer 110c and the insulating layer 110e. The capacitor 150A differs from the capacitor 150 shown in FIG. 17C and the like mainly in that the capacitor 150A includes an insulating layer 110e instead of the insulating layer 120.

[0381] For the transistor 100H, the description of the transistor 100C shown in FIG. 10A and the like can be referred to.

[0382] The conductive layer 202 is provided over the insulating layer 110c, the insulating layer 110e is provided over the conductive layer 202, the conductive layer 112b is provided over the insulating layer 110e, and the insulating layer 120 is provided over the conductive layer 112b. The conductive layer 202 has a region in contact with the top surface of the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c and the top and side surfaces of the conductive layer 202. The conductive layer 112b has a region in contact with the top surface of the insulating layer 110e. The insulating layer 120 has regions in contact with the top surface of the insulating layer 110e and the top and side surfaces of the conductive layer 112b.

[0383] The conductive layer 202 has a region overlapping with the semiconductor layer 208 with the insulating layer 110e and the insulating layer 120 interposed therebetween. The insulating layer 110e and the insulating layer 120 function as a back-gate insulating layer of the transistor 200H.

[0384] The capacitor 150A includes a conductive layer 202, an insulating layer 110e over the conductive layer 202, and a conductive layer 112b over the insulating layer 110e. In the capacitor 150A, the conductive layer 202 and the conductive layer 112b function as a pair of electrodes, and the insulating layer 110e sandwiched between them functions as a dielectric.

[0385] For example, the insulating layer 120 can be formed after the conductive layer 202 is formed over the insulating layer 110c, the insulating layer 110e is formed over the conductive layer 202, and the conductive layer 112b is formed over the insulating layer 110e. Note that the structure in which the insulating layer 120 has a region in contact with the conductive layer 112b and a partial end of the insulating layer 120 is in contact with the top surface of the conductive layer 112b is shown here, but one embodiment of the present invention is not limited to this. A structure in which the insulating layer 120 does not have a region in contact with the conductive layer 112b and a partial end of the insulating layer 120 is in contact with the top surface of the insulating layer 110e is also possible.

[0386] The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100H and as one of the pair of electrodes of the capacitor 150A. The conductive layer 202 functions as the backgate electrode of the transistor 200H and as the other of the pair of electrodes of the capacitor 150A.

[0387] 18C illustrates an example in which the capacitor 150A is formed with the conductive layer 112b, the conductive layer 202, and the insulating layer 110e, but the configuration of the capacitor 150A is not particularly limited. In addition, although the configuration in which the other of the source electrode and the drain electrode of the transistor 100H is electrically connected to one of the pair of electrodes of the capacitor 150A and the backgate electrode of the transistor 200H is electrically connected to the other of the pair of electrodes of the capacitor 150A is illustrated, the electrical connection relationship between the transistor 100H, the transistor 200H, and the capacitor 150A is not particularly limited.

[0388] Note that the configuration of the transistor 200H and the capacitor 150A described in the seventh configuration example can also be applied to other configuration examples.

[0389] 19A is a top view of a semiconductor device 10J according to one embodiment of the present invention, FIG. 19B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 19A , and FIG. 19C is a cross-sectional view taken along dashed dotted line B5-B6 in FIG.

[0390] The semiconductor device 10J includes a transistor 100J, a transistor 200J, a capacitor 150B, an insulating layer 110, and an insulating layer 105. The semiconductor device 10J differs from the semiconductor device 10G shown in FIG. 17A and the like mainly in that the semiconductor device 10J includes the insulating layer 105 and a capacitor 150B instead of the capacitor 150.

[0391] The transistor 100J can refer to the description of the transistor 100 shown in FIG. 1A and the like.

[0392] The insulating layer 105 is provided between the conductive layer 112b and the insulating layer 110 and the conductive layer 202. The insulating layer 105 is provided over the conductive layer 112b and the insulating layer 110, the conductive layer 202 is provided over the insulating layer 105, and the insulating layer 120 is provided over the conductive layer 202. The insulating layer 105 has a region in contact with the top surface of the insulating layer 110 and the top surface and side surfaces of the conductive layer 112b. The conductive layer 202 has a region in contact with the top surface of the insulating layer 105. The insulating layer 120 has a region in contact with the top surface of the insulating layer 105 and the top surface and side surfaces of the conductive layer 202. That is, the conductive layer 202 is enclosed by the insulating layer 105 and the insulating layer 120.

[0393] The insulating layer 105 provided between the conductive layer 112b and the conductive layer 202 has a function of insulating the conductive layer 112b from the conductive layer 202. The insulating layer 105 can be formed using a material that can be used for the insulating layer 110. The insulating layer 105 having a region in contact with the conductive layer 112b and the conductive layer 202 is preferably formed using a material that emits impurities that reduce the electrical resistance of the conductive layer 112b and the conductive layer 202. For example, when a metal oxide is used for the conductive layer 112b, the impurity preferably contains a hydrogen element. For the insulating layer 105, the description of the insulating layer 110d and the insulating layer 110e can be referred to. For example, silicon nitride or silicon nitride oxide can be preferably used for the insulating layer 105.

[0394] 19B and other figures illustrate a configuration in which the end of the insulating layer 105 and the end of the insulating layer 120 are aligned or substantially aligned. It can also be said that the top surface shape of the insulating layer 120 is aligned or substantially aligned with the top surface shape of the insulating layer 105. For example, a first insulating film that will become the insulating layer 105 is formed, a conductive layer 202 is formed on the first insulating film, and a second insulating film that will become the insulating layer 120 is formed on the first insulating film and the conductive layer 202. Then, by processing the first insulating film and the second insulating film, the insulating layer 105 and the insulating layer 120 can be formed with aligned or substantially aligned ends. Forming the insulating layer 105 and the insulating layer 120 in the same process can improve productivity of the semiconductor device 10 and reduce manufacturing costs. Here, a configuration in which the first insulating film and the second insulating film are processed in the same process is shown, but one embodiment of the present invention is not limited to this. The first insulating film and the second insulating film can also be processed in different processes.

[0395] The capacitor 150B includes a conductive layer 112b, an insulating layer 105 over the conductive layer 112b, and a conductive layer 202 over the insulating layer 105. In the capacitor 150B, the conductive layer 202 and the conductive layer 112b function as a pair of electrodes, and the insulating layer 105 sandwiched between them functions as a dielectric.

[0396] The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100J and as one of the pair of electrodes of the capacitor 150B. The conductive layer 202 functions as the backgate electrode of the transistor 200J and as the other of the pair of electrodes of the capacitor 150B.

[0397] 19C illustrates an example in which the capacitor 150B is formed with the conductive layer 112b, the conductive layer 202, and the insulating layer 105, but the configuration of the capacitor 150B is not particularly limited. In addition, although the configuration in which the other of the source electrode and the drain electrode of the transistor 100J is electrically connected to one of the pair of electrodes of the capacitor 150B and the backgate electrode of the transistor 200J is electrically connected to the other of the pair of electrodes of the capacitor 150B is illustrated, the electrical connection relationship between the transistor 100J, the transistor 200J, and the capacitor 150B is not particularly limited.

[0398] The configuration of the insulating layer 105 and the capacitor 150B shown in the eighth structural example can also be applied to other structural examples.

[0399] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0400] 20A to 26. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0401] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0402] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0403] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0404] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0405] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0406] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0407] Here, an example of a method for manufacturing the semiconductor device 10G shown in Fig. 17A will be described with reference to Fig. 20A to Fig. 26B , which show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 17A side by side.

[0408] First, a conductive film is formed over the substrate 102 and then processed to form the conductive layer 112a. The conductive film can be preferably formed by a sputtering method.

[0409] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a (FIG. 20A).

[0410] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf continuously using the same device.

[0411] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above-described range during the formation of the insulating films 110af and 110bf, the amount of impurities (e.g., water and hydrogen) released from the insulating films can be reduced, and the diffusion of impurities into the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0412] Since the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

[0413] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0414] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. Oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion implantation or plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the atmosphere may contain oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or nitric acid can be preferably used. Alternatively, oxygen can be supplied by generating oxygen plasma by irradiating high-frequency electromagnetic waves in an oxygen-containing atmosphere. For example, oxygen can be supplied by performing microwave treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating film 110bf through a film that suppresses oxygen desorption formed on the insulating film 110bf. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0415] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A typical example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave processing can also be called microwave-excited high-density plasma processing.

[0416] After the insulating film 110bf is formed, oxygen can be supplied by performing a plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0417] A film 137 is preferably formed over the insulating film 110bf (FIG. 20B). The film 137 preferably contains oxygen. By forming the film 137, oxygen can be supplied to the insulating film 110bf.

[0418] The conductivity of the film 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 137.

[0419] The film 137 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferably made of a metal oxide applicable to the semiconductor layer 108 and the semiconductor layer 208.

[0420] When forming the film 137, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0421] By forming the film 137 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 137, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0422] Heat treatment can be performed after the film 137 is formed. By performing heat treatment after the film 137 is formed, oxygen can be effectively supplied from the film 137 to the insulating film 110bf.

[0423] The temperature of the heat treatment is preferably 150° C. or higher, 200° C. or higher, 230° C. or higher, or 250° C. or higher, but lower than the strain point of the substrate, i.e., 450° C. or lower, 400° C. or lower, 350° C. or lower, or 300° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. By using an RTA device, the heat treatment time can be shortened.

[0424] After the film 137 is formed or after the above-described heat treatment, oxygen may be supplied to the insulating film 110bf through the film 137. The above description can be referred to for the method of supplying oxygen, and therefore detailed description thereof will be omitted.

[0425] Next, the film 137 is removed. There is no particular limitation on the method for removing the film 137, but wet etching can be suitably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0426] After removing the film 137, oxygen can be further supplied to the insulating film 110bf. The above description can be referred to for the method of supplying oxygen. For example, as shown in FIG. 20C , a film 139 can be formed over the insulating film 110bf, and oxygen can be supplied to the insulating film 110bf through the film 139. For this treatment, plasma treatment in an atmosphere containing oxygen can be used. In FIG. 20C , arrows are used to schematically show how oxygen is supplied to the insulating film 110bf.

[0427] A conductive film or a semiconductor film is preferably used for the film 139. A metal oxide film, a metal film, or an alloy film can be used for the film 139. When a metal oxide film is used for the film 139 and the film 139 is formed by a sputtering method or the like in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf even during the formation of the film 139.

[0428] Because oxygen is supplied to the insulating film 110bf through the film 139, the thickness of the film 139 is preferably small. Specifically, the thickness of the film 139 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. Typically, the thickness can be about 5 nm.

[0429] The substrate temperature during the formation of the film 139 is preferably 350° C. or less, more preferably 340° C. or less, further preferably 330° C. or less, and further preferably 300° C. or less, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0430] By providing the film 139, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, the film 139 tends to attract ionized oxygen, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0431] A dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used as the processing apparatus for supplying oxygen. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage can be set to, for example, 10 V or more and 1 kV or less. Alternatively, the bias power density can be set to, for example, 1 W / cm. ２ More than 5W / cm ２ It can be as follows:

[0432] Next, the film 139 is removed. The film 139 can be removed preferably by wet etching.

[0433] The amount of oxygen released from the insulating layer 110b in contact with the channel formation region of the transistor 100 having a short channel length is preferably larger than that from the insulating layer 120b in contact with the channel formation region of the transistor 200 having a long channel length. By supplying oxygen to the insulating film 110bf that becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b is increased, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 can be increased, so that the transistor 100 having a short channel length can also exhibit good electrical characteristics.

[0434] Next, an insulating film 110cf, which will become the insulating layer 110c, is formed on the insulating film 110bf (FIG. 20D). The description of the formation of the insulating film 110cf can be referred to, and therefore a detailed description thereof will be omitted.

[0435] Subsequently, a conductive layer 202 is formed on the insulating film 110cf (FIG. 21A).

[0436] Subsequently, an insulating film 120af that will become the insulating layer 120a and an insulating film 120bf that will become the insulating layer 120b are formed so as to cover the conductive layer 202 (FIG. 21B).

[0437] The insulating films 120af and 120bf can be preferably formed by sputtering or PECVD. After forming the insulating film 120af, it is preferable to form the insulating film 120bf successively without exposing the surface of the insulating film 120af to the atmosphere. By successively forming the insulating films 120af and 120bf, it is possible to prevent impurities from the atmosphere from adhering to the surface of the insulating film 120af. Examples of such impurities include water and organic substances.

[0438] The substrate temperature during the formation of the insulating films 120af and 120bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 120af and 120bf within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 120af and 120bf can be reduced, and the diffusion of impurities into the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0439] Since the insulating films 120af and 120bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 120af and 120bf.

[0440] After the insulating film 120bf is formed, oxygen can be supplied to the insulating film 120bf. The above description can be referred to for the method of supplying oxygen.

[0441] Subsequently, the insulating films 120af and 120bf are processed to form the insulating layer 120 including the insulating layer 120a and the insulating layer 120b. For example, dry etching can be suitably used to process the insulating films 120af and 120bf.

[0442] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110cf and the insulating layer 120 (FIG. 21C). The conductive film 112bf can be preferably formed by sputtering.

[0443] Next, the conductive film 112bf is processed to form a conductive layer 112B (FIG. 22A). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be preferably formed by, for example, wet etching.

[0444] Subsequently, a part of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be preferably formed by wet etching.

[0445] Subsequently, parts of the insulating films 110af, 110bf, and 110cf are removed to form the insulating layer 110 having an opening 141 ( FIG. 22B ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The insulating layer 110 can be preferably formed by dry etching.

[0446] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 112B, and the opening 143 is formed by removing part of the conductive layer 112B using the resist mask. The opening 141 can be formed by removing parts of the insulating films 110af, 110bf, and 110cf using the resist mask. Using the same resist mask can improve productivity. Note that the opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0447] Next, a semiconductor film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the openings 141 and 143 ( FIG. 22C ). The semiconductor film 108f is provided in contact with the upper surface and side surfaces of the conductive layer 112b, the upper surface and side surfaces of the insulating layer 110, and the upper surface and side surfaces of the insulating layer 120.

[0448] The semiconductor film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the semiconductor film 108f is preferably formed by an ALD method. Because the ALD method has high coverage, it can be suitably used to form the semiconductor film 108f that covers the openings 141 and 143. By using the ALD method, the semiconductor film 108f can be formed with high coverage also on the side surfaces of the insulating layer 110. Furthermore, the ALD method makes it easy to control the film formation rate, so a thin film can be formed with a high yield. Therefore, the ALD method can be suitably used when the semiconductor film 108f is thin. Thermal ALD or PEALD can be used as the ALD method. Alternatively, PECVD can be used to form the semiconductor film 108f.

[0449] The semiconductor film 108f is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film 108f.

[0450] When the metal oxide film is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0451] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later step, and oxygen vacancies and V Ｏ H can be reduced.

[0452] A mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used to form a metal oxide film. Note that the higher the oxygen flow rate or oxygen partial pressure when forming the metal oxide film, the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow rate or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, resulting in a transistor with a large on-state current.

[0453] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film.

[0454] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0455] The substrate temperature during the formation of the metal oxide film is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0456] If the substrate temperature is too high, the metal oxide film may have a polycrystalline structure, so it is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film.

[0457] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0458] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0459] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0460] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0461] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0462] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0463] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0464] Oxidizing agents include, for example, ozone, oxygen, and water.

[0465] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the flow time of the source gases, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film whose composition changes continuously.

[0466] Before forming the metal oxide film, it is preferable to perform at least one of a treatment for removing impurities (for example, water, hydrogen, and organic substances) adsorbed on the surfaces of the insulating layer 110 and the insulating layer 120 and a treatment for supplying oxygen into the insulating layer 110 and the insulating layer 120. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while suitably removing organic substances on the surface of the insulating layer 110. After such treatment, it is preferable to form a metal oxide film successively without exposing the surface of the insulating layer 110 to the air.

[0467] In addition, when the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0468] When the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all of the layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same film formation method (for example, sputtering or ALD). Alternatively, different film formation methods can be used for each layer. For example, when the semiconductor layer 108 and the semiconductor layer 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0469] Subsequently, the semiconductor film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 23A).

[0470] The semiconductor layer 108 and the semiconductor layer 208 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in a region not overlapping with the semiconductor layer 108 and a part of the conductive layer 212b in a region not overlapping with the semiconductor layer 208 may be etched and thinned. Similarly, a part of the insulating layer 110 in a region not overlapping with any of the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, and the conductive layer 212b may be etched and thinned. For example, the insulating layer 110c of the insulating layer 110 may be removed by etching, and the surface of the insulating layer 110b may be exposed. Note that, in etching the semiconductor film 108f, using a material with a high etching selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0471] Heat treatment is preferably performed after the semiconductor film 108f is formed or after the semiconductor film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove impurities (e.g., hydrogen and water) contained in or adsorbed to the surfaces of the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the heat treatment may improve the film quality of the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208 (e.g., reduce defects or improve crystallinity).

[0472] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the semiconductor film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108 and the semiconductor layer 208. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0473] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a later step in which heat is applied (e.g., a film formation step) may also serve as this heat treatment.

[0474] After the semiconductor film 108f is formed or after the semiconductor film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208, oxygen can be supplied to the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. The above description can be referred to for the oxygen supply method. For example, microwave treatment can be performed in an oxygen-containing atmosphere. Furthermore, by supplying oxygen while heating the substrate, the crystallinity of the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be improved, and impurities (e.g., hydrogen and water) contained in or adsorbed on the surface of the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. The substrate temperature during heating is preferably higher than room temperature (e.g., 25°C) and not higher than 600°C, more preferably 100°C to 600°C, and even more preferably 300°C to 450°C. The substrate temperature is preferably 100°C to 700°C, and even more preferably 300°C to 450°C. This can further improve the crystallinity of the semiconductor film 108f or the semiconductor layer 108 and the semiconductor layer 208. When the substrate temperature increases due to the oxygen supply treatment, the crystallinity can sometimes be improved and impurities can sometimes be removed without heating.

[0475] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 (FIG. 23B). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0476] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 suppresses oxygen diffusion, thereby suppressing oxygen desorption from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V ＯIn addition, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is prevented from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106, thereby preventing the conductive layer 104 and the conductive layer 204 from being oxidized. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0477] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, causing oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0478] Before forming the insulating layer 106, plasma treatment can be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interfaces between the semiconductor layer 108 and the insulating layer 106 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0479] After the insulating layer 106 is formed, oxygen can be supplied to the insulating layer 106. The above description can be referred to for the method of supplying oxygen. For example, microwave treatment can be performed in an atmosphere containing oxygen. The oxygen supplied to the insulating layer 106 is further supplied to the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, by supplying oxygen while heating the substrate, impurities (e.g., hydrogen and water) contained in or adsorbed to the surface of the insulating layer 106 can be removed and defects in the insulating layer 106 can be reduced. By reducing defects in the insulating layer 106, which functions as a gate insulating layer for the transistors 100 and 200, the transistors 100 and 200 can be made to have good electrical characteristics. For the substrate temperature during heating, the description of the heat treatment described above can be referred to. Note that when the substrate temperature is increased by the treatment of supplying oxygen, impurities can be removed and defects can be reduced without heating in some cases.

[0480] Subsequently, a mask layer 181 is formed on the insulating layer 106 ( FIG. 24A ). Here, a manufacturing method using a resist mask as the mask layer 181 will be described as an example. The mask layer 181 is provided at least in a region overlapping with the semiconductor layer 208. It is also preferable that the mask layer 181 is not provided in a region overlapping with the semiconductor layer 108.

[0481] Next, the first element 187 is supplied to the semiconductor layer 108 using the mask layer 181 as a mask ( FIG. 24B ). The mask layer 181 is preferably thick enough to prevent the first element 187 from reaching the semiconductor layer 208 as much as possible during supply. The first element 187 is supplied to the semiconductor layer 108 via the insulating layer 106. By supplying the first element 187, regions 108Da, 108Db, and 108Dd are formed. Region 108Dd will later become region 108Dc. Meanwhile, because the semiconductor layer 208 is masked by the mask layer 181, the supply of the first element 187 is suppressed. The thickness of the mask layer 181 can be set depending on the type of first element 187 supplied, the acceleration energy used for supply, the composition of the mask layer 181, and the film density. If the mask layer 181 is too thin, the first element 187 may also be supplied to the semiconductor layer 208. Furthermore, if the thickness of the mask layer 181 is large, productivity decreases. When a resist mask is used as the mask layer 181, the thickness of the mask layer 181 is preferably, for example, 1 μm or more and 5 μm or less, more preferably 1 μm or more and 3 μm or less, and even more preferably 1 μm or more and 2 μm or less. By setting the thickness of the mask layer 181 within the above range, it is possible to suppress the supply of the first element 187 to the semiconductor layer 208 and to increase productivity.

[0482] Although a resist mask has been described as an example of a mask layer used to supply the first element 187, one embodiment of the present invention is not limited to this. A hard mask can be used instead of a resist mask. When using a hard mask, the hard mask can be formed by forming a film to serve as the hard mask over the insulating layer 106, forming a resist mask on the film, and processing the film. The material and conductivity of the hard mask are not particularly limited. The thickness of the hard mask can be set depending on the type of the first element 187 to be supplied, the acceleration energy used for supplying the first element 187, the composition of the hard mask, and the film density.

[0483] The first element 187 is preferably supplied from a direction perpendicular or substantially perpendicular to the upper surface of the substrate 102. In this case, as described above, the amount of the first element 187 supplied to a region of the semiconductor layer 108 that is inclined with respect to the upper surface of the substrate 102 is smaller than that to a region that is parallel or substantially parallel to the upper surface of the substrate 102. That is, the amount of the first element 187 supplied to the source and drain regions of the semiconductor layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source and drain regions can be preferentially reduced. By supplying the first element 187 to the semiconductor layer 108, oxygen vacancies (V Ｏ Alternatively, when the first element 187 is supplied to the semiconductor layer 108, oxygen vacancies (V Ｏ ) may be combined.

[0484] Furthermore, the first element 187 is preferably supplied to the semiconductor layer 108 through the insulating layer 106. The thickness of the insulating layer 106 in the supply direction of the first element 187 varies depending on the location. Therefore, the semiconductor layer 108 has regions where the supply amount of the first element 187 is large and regions where the supply amount is small. Specifically, the amount of the first element 187 supplied is larger in a region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b than in a region provided along the side surface of the insulating layer 110. In this way, the supply of the first element 187 to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical resistance of the source and drain regions can be preferentially reduced. At this time, the first element 187 is also supplied to a region of the insulating layer 106 that does not overlap with the mask layer 181. Furthermore, the first element 187 may be supplied to a region of the insulating layer 110 that does not overlap with any of the mask layer 181, the semiconductor layer 108, and the conductive layer 112b. In this case, in the region of the insulating layer 110, the concentration of the first element 187 increases toward the insulating layer 106. For example, the concentration of the first element 187 in the insulating layer 110c is high.

[0485] The elements that can be used for the first element 187 are as described above. It is more preferable to use boron or phosphorus as the first element. By using an element that becomes stable when bonded with oxygen as the first element 187, it is possible to realize the regions 108Da and 108Db that are stable and have low electrical resistance.

[0486] Ion implantation can be suitably used to supply the impurity elements (specifically, the first element and the second element). By using ion implantation, which ionizes a source gas and supplies the ions after mass separation, the purity of the supplied impurity elements can be increased. Furthermore, since ion implantation equipment is also used in the manufacture of Si transistors such as LTPS transistors, it is possible to reuse equipment from existing LTPS production lines, which is preferable because no new capital investment is required. This reduces the initial capital investment costs associated with the manufacture of semiconductor devices.

[0487] When hydrogen is also supplied as the first element 187, it can be supplied without mass separation, thereby improving productivity. It is preferable to use both the first element and hydrogen as the first element 187, and it is even more preferable to use both boron or phosphorus and hydrogen. By using both an element that becomes stable when bonded with oxygen and hydrogen as the first element 187, it is easy to reduce the electrical resistance of the regions 108Da and 108Db, and the low electrical resistance state can b...

Claims

a first transistor, a second transistor, and a first insulating layer; the first transistor includes a first semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the second conductive layer has a second opening in a region overlapping with the first opening; the first semiconductor layer has a first region in contact with an upper surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a region in contact with a side surface of the second conductive layer in the second opening; the second insulating layer is located on the first semiconductor layer and has a region in contact with the first semiconductor layer; the third conductive layer has a region overlapping with the first semiconductor layer through the second insulating layer in the first opening and the second opening; the first region has a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; the second transistor has a second semiconductor layer, the second insulating layer, and a fourth conductive layer; the second semiconductor layer is located between the first insulating layer and the second insulating layer; the second semiconductor layer has a third region overlapping with the fourth conductive layer via the second insulating layer and a fourth region not overlapping with the fourth conductive layer; the fourth region has a second element; the second element is boron or phosphorus; The fourth region has a portion having a higher concentration of the second element than the third region. 　 In claim 1, a portion of the second insulating layer in contact with the first region, the portion containing the first element. 　 In claim 1, the first semiconductor layer has a fifth region in contact with an upper surface of the second conductive layer and overlapping with the third conductive layer via the second insulating layer; the fifth region has the first element, The fifth region has a portion having a higher concentration of the first element than the second region. 　 In claim 2, the first semiconductor layer has a sixth region that is in contact with an upper surface of the second conductive layer and does not overlap with the third conductive layer; the sixth region has the first element and the second element, The sixth region has a portion having a higher concentration of the first element than the second region. 　 In any one of claims 1 to 4, The first element and the second element are the same as each other. 　 In any one of claims 1 to 4, The first element and the second element are different from each other. 　 In any one of claims 1 to 4, a side surface of the first insulating layer in the first opening and a top surface of the first conductive layer form an angle of 65 degrees or more and 90 degrees or less. 　 In any one of claims 1 to 4, The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer each include a metal oxide. 　 In any one of claims 1 to 4, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, a fifth insulating layer on the fourth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer; the fifth insulating layer comprises silicon and oxygen; the third insulating layer, the fourth insulating layer, the sixth insulating layer, and the seventh insulating layer each include silicon and nitrogen; the third insulating layer has a portion having a higher hydrogen concentration than the fourth insulating layer; The seventh insulating layer has a portion having a higher hydrogen concentration than the sixth insulating layer. 　 In any one of claims 1 to 4, A third insulating layer is provided. the third insulating layer has a region in contact with a lower surface of the first conductive layer, the first insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer; the fifth insulating layer comprises silicon and oxygen; the third insulating layer and the sixth insulating layer each include silicon and nitrogen; The third insulating layer has a portion having a higher hydrogen concentration than the fourth insulating layer. 　 forming a first conductive layer on a substrate; forming an insulating film on the first conductive layer; forming a second conductive layer on the insulating film, the second conductive layer having a region overlapping with the first conductive layer; forming a first insulating layer having a first opening reaching the first conductive layer and a third conductive layer having a second opening overlapping the first opening by processing the insulating film and the second conductive layer; forming a first semiconductor layer having a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the third conductive layer, and forming a second semiconductor layer on the first insulating layer; forming a second insulating layer on the first semiconductor layer and the second semiconductor layer; forming a mask layer on the second insulating layer in a region overlapping the second semiconductor layer; supplying a first element to the first semiconductor layer using the mask layer as a mask; removing the mask layer; forming a fourth conductive layer having a region overlapping with the first semiconductor layer on the second insulating layer, and forming a fifth conductive layer having a region overlapping with the second semiconductor layer; supplying a second element to the second semiconductor layer using the fifth conductive layer as a mask; the first element is boron or phosphorus; The method for manufacturing a semiconductor device, wherein the second element is boron or phosphorus. 　 In claim 11, The method for manufacturing a semiconductor device, wherein the first element and the second element are each supplied by an ion implantation method. 　 In claim 11 or 12, The method for manufacturing a semiconductor device, wherein the first element and the second element are each supplied from a direction perpendicular or approximately perpendicular to an upper surface of the substrate. 　 In claim 11 or 12, The first element and the second element are the same as each other. 　 In claim 11 or 12, The first element and the second element are different from each other.

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