Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device has first to third transistors and first to fifth interconnects. The first to third transistors are superimposed in this order. The first transistor has a first semiconductor layer and a first gate. The second transistor has a second semiconductor layer and second and third gates sandwiching the second semiconductor layer. The third transistor has a third semiconductor layer and fourth and fifth gates sandwiching the third semiconductor layer. The following are connected to one another: the first gate and the first interconnect; one of either the source or the drain of the first transistor and one of either the source or the drain of the second transistor; the other of either the source or the drain of the first transistor and the second interconnect; the other of either the source or the drain of the second transistor and the third interconnect; the second gate and one of either the source or the drain of the third transistor ; the other of either the source or the drain of the third transistor and the fourth interconnect; and the fourth gate and the fifth interconnect.

Description

Semiconductor device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Another embodiment of the present invention relates to a memory device and a manufacturing method of the memory device. Another embodiment of the present invention relates to a transistor and a manufacturing method of the transistor. Another embodiment of the present invention relates to a capacitor and a manufacturing method of the capacitor. Another embodiment of the present invention relates to an electronic device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, development of semiconductor devices has progressed, and for example, large scale integrated circuits (LSIs) are used in semiconductor devices. For example, central processing units (CPUs), memories, etc. are used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as CPUs and memories are mounted on circuit boards, for example, printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has been attracting attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also been attracting attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of memory cells in a superimposed manner.

[0009] Furthermore, if a transistor can be made vertical, it is possible to further increase the density of an integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulating layer.

[0010] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0011] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0012] An object of one embodiment of the present invention is to provide a transistor whose leakage current in an off state can be controlled to be small, or to provide a memory device that can retain stored data for a long period of time.

[0013] Another object of one embodiment of the present invention is to provide a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device, memory device, or transistor. Another object of one embodiment of the present invention is to provide a semiconductor device or memory device with high read accuracy. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a low-cost semiconductor device or memory device. Another object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or memory device with high operating speed. Another object of one embodiment of the present invention is to provide a novel semiconductor device, memory device, or transistor.

[0014] Another object of one embodiment of the present invention is to provide a method for manufacturing a transistor whose leakage current in an off-state can be controlled to be small, or to provide a method for manufacturing a memory device that can retain stored data for a long period of time.

[0015] Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device, memory device, or transistor. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with high read accuracy. Another object of one embodiment of the present invention is to provide a method for manufacturing a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a method for manufacturing a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with high yield. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with low power consumption. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with high operating speed. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device, memory device, or transistor.

[0016] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0017] One embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer, the first transistor, the second transistor, and the third transistor being stacked in this order, the first transistor having a first conductive layer, a second conductive layer, a third conductive layer, a seventh insulating layer, and a first semiconductor layer, the first insulating layer, the third conductive layer, and the second insulating layer being stacked in this order over the first conductive layer, and the first insulating layer, the third conductive layer, and the sixth insulating layer The second insulating layer has a first opening reaching the first conductive layer, the seventh insulating layer is provided in contact with a sidewall of the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer in the first opening, a side surface of the seventh insulating layer in the first opening, and an upper surface of the second insulating layer, the second conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, and the second transistor has a second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an eighth insulating layer, a ninth insulating layer, and the second semiconductor layer, and a third an insulating layer, a fifth conductive layer, a fourth insulating layer, and a fourth conductive layer are stacked in this order; a second opening reaching the second conductive layer is provided in the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer; an eighth insulating layer is provided in contact with a side wall of the second opening; a second semiconductor layer is provided in contact with an upper surface of the second conductive layer in the second opening, a side surface of the eighth insulating layer in the second opening, and an upper surface of the fourth conductive layer; a ninth insulating layer is provided in contact with an upper surface of the second semiconductor layer, the side surface of the second semiconductor layer, an upper surface of the fourth conductive layer, and an upper surface of the fourth insulating layer; The sixth conductive layer is provided on and in contact with the ninth insulating layer so as to fill the second opening. The third transistor has a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a tenth insulating layer, an eleventh insulating layer, and a third semiconductor layer. The seventh conductive layer is provided in contact with an upper surface of the sixth conductive layer. A fifth insulating layer, a ninth conductive layer, a sixth insulating layer, and an eighth conductive layer are stacked in this order on the seventh conductive layer. A third opening reaching the seventh conductive layer is provided in the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer.the third semiconductor layer is provided in contact with a side wall of the third opening, the third semiconductor layer is provided in contact with an upper surface of the seventh conductive layer in the third opening, a side surface of the tenth insulating layer in the third opening, and an upper surface of the eighth conductive layer; the eleventh insulating layer is provided in contact with an upper surface of the third semiconductor layer, the side surface of the third semiconductor layer, an upper surface of the eighth conductive layer, and an upper surface of the sixth insulating layer; and the tenth conductive layer is provided on and in contact with the eleventh insulating layer so as to fill the third opening.

[0018] In the above, at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer preferably contains a metal oxide, the metal oxide containing two or three elements selected from indium, an element M, and zinc, and the element M containing one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0019] In the above, it is preferable that the second conductive layer has an 11th conductive layer and a 12th conductive layer, the 11th conductive layer is provided in contact with the top surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, the 12th conductive layer is provided in contact with the top surface of the 11th conductive layer so as to have a region overlapping with the first conductive layer, and the second semiconductor layer is provided in contact with the top surface of the 12th conductive layer.

[0020] In the above, it is preferable that the second conductive layer has an 11th conductive layer, a 12th conductive layer, and a 13th conductive layer, the 11th conductive layer is provided in contact with the top surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, the 13th conductive layer is provided in contact with the top surface of the 11th conductive layer, the 12th conductive layer is provided in contact with the top surface of the 13th conductive layer so as to have a region overlapping with the first conductive layer, and the second semiconductor layer is provided in contact with the top surface of the 12th conductive layer.

[0021] In the above, it is preferable that a capacitance is provided between the second transistor and the third transistor, and the first transistor, the second transistor, the capacitance, and the third transistor are stacked in this order, the capacitance has a fourteenth conductive layer, a fifteenth conductive layer, and a twelfth insulating layer, the twelfth insulating layer has a region in contact with a side surface of the fourteenth conductive layer, the fifteenth conductive layer covers at least a part of the side surface of the fourteenth conductive layer via the twelfth insulating layer, the fourteenth conductive layer is provided in contact with an upper surface of the sixth conductive layer, and the seventh conductive layer is provided in contact with an upper surface of the fourteenth conductive layer.

[0022] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer, where the first transistor, the second transistor, and the third transistor are stacked in this order, the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a seventh insulating layer, and a first semiconductor layer, and the first insulating layer, the third conductive layer, and the second insulating layer are stacked in this order over the first conductive layer, and the first insulating layer, the third conductive layer, and the second insulating layer are provided with a first opening reaching the first conductive layer, the seventh insulating layer is provided in contact with a side wall of the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer in the first opening, a side surface of the seventh insulating layer in the first opening, and an upper surface of the second insulating layer, the second conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, the third conductive layer is provided so as to surround the first semiconductor layer via the seventh insulating layer in a plan view, and the second transistor is a sixth conductive layer, an eighth insulating layer, a ninth insulating layer, and a second semiconductor layer; a third insulating layer, a fifth conductive layer, a fourth insulating layer, and a fourth conductive layer are stacked in this order on the second conductive layer; a second opening reaching the second conductive layer is provided in the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer; the eighth insulating layer is provided in contact with a side wall of the second opening; the second semiconductor layer is in contact with an upper surface of the second conductive layer in the second opening, a side surface of the eighth insulating layer in the second opening, and an upper surface of the fourth conductive layer; and the ninth insulating layer is provided on the second semiconductor layer. the sixth conductive layer is provided on and in contact with the first surface, a side surface of the second semiconductor layer, an upper surface of the fourth conductive layer, and an upper surface of the fourth insulating layer, the sixth conductive layer is provided on and in contact with the ninth insulating layer so as to fill the second opening, the fifth conductive layer is provided so as to surround the second semiconductor layer with the eighth insulating layer interposed therebetween in a plan view, the second semiconductor layer is provided so as to surround the sixth conductive layer with the ninth insulating layer interposed therebetween in a plan view, the third transistor has a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a tenth insulating layer, an eleventh insulating layer, and the third semiconductor layer, and the seventh conductive layerThe tenth insulating layer is provided in contact with an upper surface of the sixth conductive layer, and a fifth insulating layer, a ninth conductive layer, a sixth insulating layer, and an eighth conductive layer are stacked in this order on the seventh conductive layer, and a third opening reaching the seventh conductive layer is provided in the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer, and the tenth insulating layer is provided in contact with a side wall of the third opening. The third semiconductor layer is provided in contact with an upper surface of the seventh conductive layer in the third opening, a side surface of the tenth insulating layer in the third opening, and a side surface of the eighth conductive layer. the eleventh insulating layer is provided in contact with the top surface of the third semiconductor layer, a side surface of the third semiconductor layer, the top surface of the eighth conductive layer, and the top surface of the sixth insulating layer; the tenth conductive layer is provided in contact with the eleventh insulating layer so as to fill the third opening; the ninth conductive layer is provided so as to surround the third semiconductor layer via the tenth insulating layer in plan view; and the third semiconductor layer is provided so as to surround the tenth conductive layer via the eleventh insulating layer in plan view.

[0023] In the above, at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer preferably contains a metal oxide, the metal oxide containing two or three elements selected from indium, an element M, and zinc, and the element M containing one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0024] In the above, it is preferable that the second conductive layer has an 11th conductive layer and a 12th conductive layer, the 11th conductive layer is provided in contact with the top surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, the 12th conductive layer is provided in contact with the top surface of the 11th conductive layer so as to have a region overlapping with the first conductive layer, and the second semiconductor layer is provided in contact with the top surface of the 12th conductive layer.

[0025] In the above, it is preferable that the second conductive layer has an 11th conductive layer, a 12th conductive layer, and a 13th conductive layer, the 11th conductive layer is provided in contact with the top surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer, the 13th conductive layer is provided in contact with the top surface of the 11th conductive layer, the 12th conductive layer is provided in contact with the top surface of the 13th conductive layer so as to have a region overlapping with the first conductive layer, and the second semiconductor layer is provided in contact with the top surface of the 12th conductive layer.

[0026] In the above, it is preferable that a capacitance is provided between the second transistor and the third transistor, and the first transistor, the second transistor, the capacitance, and the third transistor are stacked in this order, the capacitance has a fourteenth conductive layer, a fifteenth conductive layer, and a twelfth insulating layer, the twelfth insulating layer has a region in contact with a side surface of the fourteenth conductive layer, the fifteenth conductive layer covers at least a part of the side surface of the fourteenth conductive layer via the twelfth insulating layer, the fourteenth conductive layer is provided in contact with an upper surface of the sixth conductive layer, and the seventh conductive layer is provided in contact with an upper surface of the fourteenth conductive layer.

[0027] Another embodiment of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a second insulating layer on the first insulating layer and the second conductive layer, processing the first insulating layer, the second conductive layer, and the second insulating layer, forming a first opening that reaches the first conductive layer, forming a third insulating layer in contact with a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and a side surface of the second insulating layer in the first opening, and forming a top surface of the first conductive layer in the first opening, a side surface of the third insulating layer in the first opening, and forming a first semiconductor layer in contact with an upper surface of the second insulating layer, forming a third conductive layer in contact with an upper surface of the first semiconductor layer, forming a fourth insulating layer on the third conductive layer and on the second insulating layer, forming a fourth conductive layer on the fourth insulating layer, forming a fifth insulating layer on the fourth insulating layer and on the fourth conductive layer, forming a fifth conductive layer on the fifth insulating layer, processing the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, and the fifth conductive layer to form a second opening reaching the third conductive layer, and forming a side surface of the fourth insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, and a side surface of the fourth insulating layer in the second opening. A sixth insulating layer is formed in contact with a side surface of the fifth insulating layer and a side surface of the fifth conductive layer in the second opening; a second semiconductor layer is formed in contact with an upper surface of the third conductive layer in the second opening, a side surface of the sixth insulating layer in the second opening, and an upper surface of the fifth conductive layer; a seventh insulating layer is formed on the second semiconductor layer, the fifth conductive layer, and the fifth insulating layer; a sixth conductive layer having an area overlapping with the second semiconductor layer is formed on the seventh insulating layer; an eighth insulating layer is formed on the seventh insulating layer and the sixth conductive layer; and the upper surface of the eighth insulating layer and the upper surface of the sixth conductive layer are processed to form an eighth insulating layer and an eighth conductive layer, each of which is in contact with a substrate surface. forming a seventh conductive layer in contact with the upper surface of the sixth conductive layer, forming a ninth insulating layer on the eighth insulating layer and on the seventh conductive layer, forming an eighth conductive layer on the ninth insulating layer, forming a tenth insulating layer on the ninth insulating layer and on the eighth conductive layer, forming a ninth conductive layer on the tenth insulating layer, processing the ninth insulating layer, the eighth conductive layer, the tenth insulating layer, and the ninth conductive layer to form a third opening reaching the seventh conductive layer, forming a side surface of the ninth insulating layer in the third opening, a side surface of the eighth conductive layer in the third opening, and a side surface of the tenth insulating layer in the third opening;and forming an eleventh insulating layer in contact with a side surface of the ninth conductive layer in the third opening; forming a third semiconductor layer in contact with an upper surface of the seventh conductive layer in the third opening, the side surface of the eleventh insulating layer in the third opening, and an upper surface of the ninth conductive layer; forming a twelfth insulating layer over the third semiconductor layer, the ninth conductive layer, and the tenth insulating layer; and forming a tenth conductive layer having a region overlapping with the third semiconductor layer over the twelfth insulating layer.

[0028] According to one embodiment of the present invention, a transistor whose leakage current in an off state can be controlled to be small can be provided, or a memory device that can retain stored data for a long period of time can be provided.

[0029] According to one embodiment of the present invention, a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, memory device, or transistor can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with high read accuracy can be provided. According to one embodiment of the present invention, a transistor with high on-state current can be provided. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a low-cost semiconductor device or memory device can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with high operating speed can be provided. According to one embodiment of the present invention, a novel semiconductor device, memory device, or transistor can be provided.

[0030] According to one embodiment of the present invention, a method for manufacturing a transistor whose leakage current in an off state can be controlled to be small can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a memory device that can retain stored data for a long period of time can be provided.

[0031] According to one embodiment of the present invention, a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device, memory device, or transistor can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or memory device that has high read accuracy can be provided. According to one embodiment of the present invention, a method for manufacturing a transistor with high on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or memory device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device or memory device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device, memory device, or transistor can be provided.

[0032] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0033] FIG. 1A is a block diagram showing an example of the configuration of a semiconductor device. FIGS. 1B and 1C are circuit diagrams showing an example of the configuration of a memory cell. FIGS. 2A and 2B are circuit diagrams showing an example of the configuration of a memory cell. FIG. 3A is a block diagram showing an example of the configuration of a semiconductor device. FIGS. 3B and 3C are circuit diagrams showing an example of the configuration of a memory cell. FIG. 4A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 5A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 5B and 5C are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of the configuration of a transistor. FIG. 7A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 7B and 7C are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 8A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 8B and 8C are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 9A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 9B and 9C are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 10A is a plan view showing an example of the configuration of a semiconductor device. FIGS. 10B and 10C are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 11A to 11C are plan views showing a configuration example of a semiconductor device. FIGS. 12A to 12C are plan views showing a configuration example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 19A is a block diagram showing a configuration example of a display device. FIG. 19B is a plan view showing a configuration example of a pixel. FIG. 19C is a circuit diagram showing a configuration example of a pixel. FIGS. 20A and 20B are plan views showing a configuration example of a semiconductor device. FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 22 is a cross-sectional view showing a configuration example of a semiconductor device. 23A and 23B are plan views showing examples of the configuration of a semiconductor device, and Fig. 24A and Fig. 24B are plan views showing examples of the configuration of a semiconductor device.25A and 25B are plan views showing a structural example of a semiconductor device. FIGS. 26A and 26B are plan views showing a structural example of a semiconductor device. FIGS. 27A and 27B are plan views showing a structural example of a semiconductor device. FIG. 28A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 28B and 28C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 29A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 29B and 29C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 30A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 30B and 30C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 31A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 31B and 31C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 32A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 32B and 32C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 33A is a plan view showing an example of a manufacturing method of a semiconductor device. 33B and 33C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 34B and 34C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 35A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 35B and 35C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 36A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 36B and 36C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 37A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 37B and 37C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 38A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 38B and 38C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 39A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 39B and 39C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 40A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 40B and 40C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 41A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 41B and 41C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 42A is a plan view illustrating an example of a method for manufacturing a semiconductor device.42B and 42C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 43A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 43B and 43C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 44A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 44B and 44C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 45A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 45B and 45C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 46A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 46B and 46C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 47A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 47B and 47C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 48A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 48B and 48C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 49A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 49B and 49C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 50A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 50B and 50C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 51A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 51B and 51C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 52A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 52B and 52C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 53A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 53B and 53C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 54 is a perspective view illustrating an example of a configuration of a semiconductor device. FIG. 55 is a cross-sectional view illustrating an example of a configuration of a semiconductor device. FIG. 56 is a cross-sectional view illustrating an example of a configuration of a semiconductor device. FIGS. 57A and 57B are diagrams illustrating an example of an electronic component. FIGS. 58A and 58B are diagrams illustrating an example of an electronic device. FIGS. 58C to 58E are diagrams illustrating an example of a mainframe computer. Fig. 59 is a diagram showing an example of space equipment. Fig. 60 is a diagram showing an example of a storage system applicable to a data center. Figs. 61A to 61C are circuit diagrams showing examples of the configuration of a memory cell. Figs. 62A to 62C are circuit diagrams showing examples of the configuration of a memory cell.Figs. 63A to 63C are circuit diagrams showing an example of the configuration of a memory cell. Figs. 64A and 64B are circuit diagrams showing an example of the configuration of a memory cell. Figs. 65A and 65B are circuit diagrams showing an example of the configuration of a memory cell. Fig. 66A is a plan view showing an example of the configuration of a semiconductor device. Figs. 66B and 66C are cross-sectional views showing an example of the configuration of a semiconductor device. Fig. 67A is a plan view showing an example of the configuration of a semiconductor device. Figs. 67B and 67C are cross-sectional views showing an example of the configuration of a semiconductor device. Figs. 68A and 68B are cross-sectional views showing an example of the configuration of a semiconductor device. Figs. 69A and 69B are cross-sectional views showing an example of the configuration of a semiconductor device.

[0034] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0035] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0036] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally thinned by a process such as etching, but this may not be reflected in the drawings for ease of understanding.

[0037] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0038] A transistor is a type of semiconductor element and can perform operations such as amplifying a current or a voltage, and switching to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0039] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0040] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0041] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the defect state density of the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. Furthermore, for example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also referred to as "(semi-transitional)") may be formed.

[0042] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0043] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0044] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film", and the term "conductive film" can be changed to the term "conductive layer". Furthermore, for example, the term "insulating film" can be changed to the term "insulating layer", and the term "insulating layer" can be changed to the term "insulating film". Furthermore, for example, the term "semiconductor film" can be changed to the term "semiconductor layer", and the term "semiconductor layer" can be changed to the term "semiconductor film".

[0045] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0046] In addition, in this specification, "connection" includes "electrical connection."

[0047] "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when exchange of electrical signals or interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time when exchange of electrical signals or interaction of potentials does not occur between A and B during circuit operation, it can be said that "A and B are electrically connected" as long as there is a time when exchange of electrical signals or interaction of potentials occurs between A and B.

[0048] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0049] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, or when A and B are connected via the source and drain of one or more transistors. However, this is premised on the fact that there is a timing when an electrical signal is exchanged or an interaction of potential occurs between A and B.

[0050] An example in which it cannot be said that "A and B are electrically connected" because A and B are connected via an insulator is when a dielectric of a capacitive element, a gate insulating film of a transistor, etc. is interposed between A and B.

[0051] Examples of cases where A and B are connected without an insulator between them, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power supply, signal source, etc. (however, this does not include a case where the potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, but there is no timing at which both the transistor TrP and the transistor TrQ are turned on simultaneously.

[0052] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0053] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0054] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. When a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0055] For example, in this specification, a transistor having a multi-gate structure with two or more gates can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0056] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0057] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. Also, a terminal, a wiring, etc. can be referred to as a node.

[0058] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0059] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0060] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0061] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0062] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0063] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0064] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0065] In this specification and the like, when it is stated that A is located on B, it means that at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0066] In this specification and the like, when it is stated that A covers B, it means that at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has a region that covers B.

[0067] In this specification and the like, when it is stated that A overlaps with B, it means that at least a part of A overlaps with B. Therefore, for example, it can be rephrased as saying that A has an overlapping region with B.

[0068] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0069] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0070] In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. In this embodiment, a memory device will be mainly taken as an example of a semiconductor device according to one embodiment of the present invention.

[0071] One embodiment of the present invention relates to a memory device including a memory portion in which memory cells are arranged in a matrix. Each memory cell includes a first transistor, a second transistor, and a third transistor. In the memory device, the first transistor has a function of writing data to the memory cell. The second transistor and the third transistor have a function of reading data stored in the memory cell.

[0072] In a memory device of one embodiment of the present invention, two transistors, a second transistor and a third transistor connected in series with the second transistor, are used to read data stored in a memory cell. By including the third transistor, the memory device of one embodiment of the present invention can read data stored in the memory cell more stably than a memory device without the third transistor. Therefore, a memory device with high read accuracy can be realized.

[0073] In a memory device according to one embodiment of the present invention, a first transistor for writing data to a memory cell has two gate electrodes (a first gate electrode (also simply referred to as a gate electrode) and a second gate electrode (also referred to as a backgate electrode)) sandwiching a semiconductor layer therebetween. For example, by applying a potential that turns the first gate electrode off while applying GND (ground potential) or an arbitrary constant potential (a potential at which the first transistor is normally off) to the second gate electrode, leakage current of the first transistor can be reduced compared to a case in which the second gate electrode is not provided. Therefore, data stored in the memory cell can be retained for a longer period than a case in which the first transistor does not have a second gate electrode. Furthermore, power consumption of the memory device can be further reduced.

[0074] For example, by applying a potential to the first gate electrode that causes the first transistor to be in an on state while applying a potential to the second gate electrode that causes the first transistor to be in a normally on state, the on-state current of the first transistor can be made larger than when the first transistor does not have the second gate electrode, thereby improving the speed at which data can be written to the memory cell compared to when the first transistor does not have the second gate electrode.

[0075] In addition, in the memory device of one embodiment of the present invention, the second transistor that reads data held in the memory cell has two gate electrodes (a third gate electrode (also simply referred to as a gate electrode) and a fourth gate electrode (also referred to as a back gate electrode)) that are provided with a semiconductor layer sandwiched therebetween. For example, in the second transistor included in a memory cell that is not a data read target, by applying a potential that turns the second transistor into an off state to the fourth gate electrode while applying GND (ground potential) or an arbitrary constant potential (a potential at which the second transistor is normally off) to the third gate electrode, the leakage current of the second transistor can be reduced compared to when the fourth gate electrode is not provided. Therefore, when data is read from a memory cell, fluctuations in the potential held in other memory cells via the second transistor can be suppressed. Therefore, data held in the memory cell can be read more stably than when the second transistor does not have a fourth gate electrode, and a memory device with extremely high read accuracy can be realized.

[0076] In addition, in a memory device according to one embodiment of the present invention, the first transistor, the second transistor, and the third transistor are arranged so as to overlap with each other. Therefore, the area occupied by the memory cell in a plan view can be reduced. Therefore, the memory cell can be miniaturized and highly integrated, and a memory device capable of miniaturization and high integration can be provided.

[0077] In addition, each of the first transistor, the second transistor, and the third transistor in the memory device of one embodiment of the present invention has a structure in which the source electrode and the drain electrode are provided at different heights with respect to the substrate surface and overlap with each other, and a drain current flows in the height direction (vertical direction). Therefore, the memory device can be miniaturized more than a transistor having a structure in which the source electrode and the drain electrode are provided on the same plane. When the memory device of one embodiment of the present invention includes a transistor with the above structure, miniaturization and high integration of the memory device can be further achieved.

[0078] 1A is a block diagram showing a configuration example of a semiconductor device 10. The semiconductor device 10 can be a memory device.

[0079] The semiconductor device 10 includes a memory unit 20, a word line driving circuit 11, a bit line driving circuit 13, and a power supply circuit 15. The memory unit 20 includes a plurality of memory cells 21 arranged in a matrix. The power supply circuit 15 may be provided outside the semiconductor device 10.

[0080] The word line driving circuit 11 is connected to the memory cells 21 via wiring 31. The wiring 31 extends, for example, in the row direction of the matrix. The wiring 31 functions as a word line. In FIG. 1A, wiring 31R and wiring 31W are shown as the wiring 31.

[0081] The bit line driving circuit 13 is connected to the memory cells 21 via wiring 33. The wiring 33 extends, for example, in the column direction of the matrix. The wiring 33 functions as a bit line. In FIG. 1A, wiring 33R and wiring 33W are shown as the wiring 33.

[0082] In FIG. 1A , as shown in the figure, the direction in which the wiring 31 functioning as a word line extends is the X direction, and the direction in which the wiring 33 functioning as a bit line extends is the Y direction. As described above, the wiring 31 extends in the row direction of the matrix, and the wiring 33 extends in the column direction of the matrix. Therefore, the X direction can be the row direction, and the Y direction can be the column direction. The X direction and the Y direction can be directions that intersect with each other, specifically, directions that are perpendicular to each other. Furthermore, a direction that intersects both the X direction and the Y direction, specifically, a direction that is perpendicular to both the X direction and the Y direction, can be the Z direction. Note that in subsequent drawings, directions are indicated as the X direction, the Y direction, and the Z direction, but these definitions may be the same as or different from those in FIG. 1A . Furthermore, in FIG. 1A , the X direction, the Y direction, and the Z direction are indicated by arrows, but no distinction is made between the forward direction and the reverse direction unless explicitly stated. This also applies to subsequent drawings.

[0083] The power supply circuit 15 is connected to the memory cells 21 via wiring 35. In Fig. 1A, the wiring 35 extends in the column direction of the matrix. The wiring 35 functions as a power supply line.

[0084] 1A, the wiring 31, the wiring 33, and the wiring 35 are shown as straight lines, but one straight line does not necessarily represent one wiring, and multiple wirings may be represented by one straight line. In the block diagrams, circuit diagrams, etc. that follow, multiple wirings may also be represented by one straight line. Furthermore, multiple wirings other than the wiring 31, the wiring 33, and the wiring 35 may also be represented by one straight line.

[0085] The word line driver circuit 11 has a function of selecting, for each row, a memory cell 21 to which data is to be written. The word line driver circuit 11 also has a function of selecting, for each row, a memory cell 21 from which data is to be read, specifically, a memory cell 21 from which data is to be output to a wiring 33. The word line driver circuit 11 can select a memory cell 21 to which data is to be written or a memory cell 21 from which data is to be read by supplying a signal to a wiring 31. Specifically, the word line driver circuit 11 has a function of selecting a memory cell 21 to which data is to be written by supplying a signal to a wiring 31W. The word line driver circuit 11 also has a function of selecting a memory cell 21 from which data is to be read, specifically, a memory cell 21 from which data is to be output to a wiring 33R, by supplying a signal to a wiring 31R. Here, the wiring 31W is also referred to as a write word line, and the wiring 31R is also referred to as a read word line. The signal supplied to the wiring 31W by the word line driver circuit 11 is also referred to as a write selection signal, and the signal supplied to the wiring 31R is also referred to as a read selection signal.

[0086] As described above, the word line driver circuit 11 has a function of controlling writing of data to the memory cell 21 by supplying a write selection signal to the wiring 31W. The word line driver circuit 11 also has a function of controlling reading of data from the memory cell 21 by supplying a read selection signal to the wiring 31R.

[0087] Specifically, the bit line driver circuit 13 has a function of writing data to the memory cell 21 selected by the word line driver circuit 11 using a write selection signal via the wiring 33W. The bit line driver circuit 13 also has a function of reading data stored in the memory cell 21. Specifically, the bit line driver circuit 13 has a function of amplifying a potential corresponding to the data to a potential that can be handled by other circuits. The bit line driver circuit 13 also has a function of precharging the wiring 33R before reading data from the memory cell 21. Here, the wiring 33W is also referred to as a write bit line, and the wiring 33R is also referred to as a read bit line.

[0088] As described above, the bit line driver circuit 13 has a function of writing data to the memory cell 21 via the wiring 33W, and also has a function of reading the data via the wiring 33R.

[0089] The power supply circuit 15 has a function of supplying a power supply potential to the wiring 35, specifically, a function of supplying a constant potential to the wiring 35. The power supply circuit 15 has a function of generating, for example, a high potential or a low potential and supplying it to the wiring 35. Note that the power supply circuit 15 may also have a function of supplying a power supply potential to one or both of the word line driver circuit 11 and the bit line driver circuit 13.

[0090] 1B is a circuit diagram illustrating a configuration example of a memory cell 21 having a problem to be solved by one embodiment of the present invention. The memory cell 21 having this configuration includes a transistor 41 and a transistor 42.

[0091] One of the source and the drain of the transistor 41 is connected to the wiring 33R. The other of the source and the drain of the transistor 41 is connected to the wiring 35. The gate of the transistor 41 is connected to one of the source and the drain of the transistor 42. The other of the source and the drain of the transistor 42 is connected to the wiring 33W. The gate of the transistor 42 is connected to the wiring 31W. Here, a node where the gate of the transistor 41 and the one of the source and the drain of the transistor 42 are connected is referred to as a node N.

[0092] The transistor 42 has a function of writing data to the memory cell 21. The transistor 41 also has a function of reading data stored in the memory cell 21. The memory cell 21 shown in FIG. 1B does not have a capacity for storing data. In the memory cell 21, data is written to the node N. For example, by using an OS transistor as the transistor 42, data can be stored in the node N for a longer period of time than in the case of using a transistor having silicon in its semiconductor layer (also referred to as a Si transistor) due to the low leakage current of the OS transistor. Therefore, even without a capacitance (C), a memory cell can be formed using only two transistors (Tr), which simplifies the manufacturing process of the memory cell. A memory cell with the above configuration can be referred to as a 2Tr0C memory cell.

[0093] A well-known example of a simple memory cell configuration is the dynamic random access memory (DRAM), which is a 1Tr1C memory cell consisting of one transistor and one capacitor. However, due to its configuration, DRAM requires that the same transistor be used for both data writing and data reading, and this poses a problem in that when stored data is read (when the transistor is turned on to read data), the data is lost via the transistor (a so-called destructive read).

[0094] 1B has a configuration in which a transistor for writing data (transistor 42) and a transistor for reading data (transistor 41) are provided separately, so that the transistor for writing data (transistor 42) does not need to be turned on when reading data, and non-destructive reading is possible.

[0095] Specifically, potentials of different magnitudes are supplied to the wiring 33R and the wiring 35, respectively, to generate a potential difference between the source and drain of the transistor 41. At this time, a potential of a magnitude corresponding to the data written to the node N is applied to the gate of the transistor 41. Therefore, whether the transistor 41 is turned on or off depends on the magnitude relationship between the threshold voltage of the transistor 41 and the data written to the node N (i.e., the potential applied to the gate of the transistor 41). If the memory cell 21 is a binary memory cell that stores data of either "0" or "1," when the transistor 41 is on, a current flows between the source and drain of the transistor 41, and the current is output to the wiring 33R, making it possible to detect that data "1" has been written to the node N. On the other hand, when the transistor 41 is off, no current flows between the source and drain of the transistor 41, so no current is output to the wiring 33R, making it possible to detect that data "0" has been written to the node N.

[0096] However, in the above-described data read method, a potential must be applied to each of the wiring 33R and the wiring 35 when reading data, and therefore, each time data is read, the applied potential is applied to the node N via parasitic capacitance (such as a capacitance component of the transistor 41). Therefore, there is an inherent problem that the amount of data originally written changes in all memory cells 21 (including memory cells 21 that are not the target for data reading) connected to the wiring 33R and the wiring 35 to which the potential is applied.

[0097] 1C , a memory cell of one embodiment of the present invention includes a transistor 43 connected in series to the transistor 41. Specifically, one of the source and the drain of the transistor 41 is connected to one of the source and the drain of the transistor 43. The other of the source and the drain of the transistor 43 is connected to a wiring 33R. The gate of the transistor 43 is connected to a wiring 31R. For other configurations, refer to the description of the memory cell 21 shown in FIG. 1B .

[0098] 1B , the memory cell of one embodiment of the present invention includes a back gate (second gate) for each of the transistors 41 and 42. Note that although FIG. 1C does not explicitly show where the back gates of the transistors 41 and 42 are connected, they can be connected to, for example, the source, gate (first gate), or wiring 35 of each transistor. Alternatively, they can be connected to, for example, a wiring included in a semiconductor device (not shown) other than the semiconductor device 10 shown in FIG. 1A .

[0099] When the back gates of the transistors 41 and 42 are connected to the sources of the respective transistors, the same potential can be applied to the sources and back gates of the respective transistors. For example, the potential of the semiconductor layer of the transistor can be fixed by applying GND (ground potential) or any constant potential to the sources and back gates of the transistors. Therefore, more stable transistor characteristics with less variation can be obtained than in the configuration having only one gate as shown in FIG. 1B.

[0100] When the back gates of the transistors 41 and 42 are connected to the gates of the respective transistors, potentials of the same magnitude can be applied to the semiconductor layers from the gates and back gates of the respective transistors. Therefore, the influence of the gate electric field on carriers in the semiconductor layers can be strengthened compared to the configuration having only one gate as shown in FIG. 1B . For example, when a potential that turns on the transistor is applied to the gate and back gate of the transistor, a larger on-state current can be obtained than in a configuration having only one gate. Furthermore, when a potential that turns off the transistor is applied to the gate and back gate of the transistor, the off-state current can be reduced compared to a configuration having only one gate.

[0101] When the back gates of the transistor 41 and the transistor 42 are connected to a wiring to which a constant potential is supplied, such as the wiring 35, the potential of the semiconductor layer of the transistor can be fixed. Therefore, more stable transistor characteristics with less variation can be obtained than in the configuration having only one gate as shown in FIG.

[0102] As described above, by providing the back gates to the transistors 41 and 42, the on-state current can be increased and the off-state current can be reduced compared to when the transistors 41 and 42 do not have back gates. Therefore, the speed at which data can be written to the node N can be increased compared to when the transistors 41 and 42 do not have back gates. Furthermore, data can be held in the node N for a long period of time. Furthermore, the potential of the semiconductor layer can be fixed at a constant potential, which can suppress operational variations between memory cells.

[0103] 1C , the transistor 42 has a function of writing data, and the transistors 41 and 43 have a function of reading data held in the memory cell 21.

[0104] Note that although FIG. 1C and other figures illustrate a configuration example in which the transistors 41 and 42 included in the memory cell 21 have back gates and the transistor 43 does not have a back gate, this is not limiting. In one embodiment of the present invention, the transistor 43 can also have a back gate. Regarding the connection destination of the back gate of the transistor 43, the above description of the connection destination of the back gates of the transistors 41 and 42 can be referred to. When the transistor 43 has a back gate, the on-state current can be made larger than when the transistor 43 does not have a back gate, thereby improving the speed at which data stored in the memory cell 21 is read. Furthermore, when the transistor 43 has a back gate, the off-state current can be made smaller than when the transistor 43 does not have a back gate, thereby preventing problems such as the transistor 43 in a memory cell 21 not targeted for data read from being unintentionally turned on. Therefore, when data is read from a memory cell 21, potentials from the wiring 33R and the wiring 35 can prevent data stored in the memory cell 21 not targeted for data read from being changed via the transistor 43 included in the memory cell.

[0105] Although some of the details overlap with those of the memory cell 21 illustrated in FIG. 1B, a method for operating the memory cell 21 according to one embodiment of the present invention illustrated in FIG. 1C will be described in detail below.

[0106] The transistor 42 functions as a switch for writing data to the memory cell 21. For example, if the transistor 42 is an n-channel transistor, the transistor 42 can be turned on by setting the potential of the wiring 31W to a high potential (a voltage at which the potential difference between the source and gate of the transistor 42 is equal to or greater than the threshold voltage), and can be turned off by setting the potential of the wiring 31W to a low potential (a voltage at which the potential difference between the source and gate of the transistor 42 is less than the threshold voltage). The transistor 42 has a function of controlling conduction and non-conduction between the wiring 33W and the node N based on the potential of the wiring 31W. By turning on the transistor 42, data is written to the memory cell 21 through the wiring 33W, and by turning off the transistor 42, the written data is retained. Specifically, by turning on the transistor 42, charge corresponding to data is accumulated in the node N, and by turning off the transistor 42, the charge in the node N is retained. During the above series of operations (when writing data to the memory cell 21 and when holding the data), a constant potential (GND (ground potential) or low potential) is always applied to the wiring 35.

[0107] In the following, transistors 41, 42, and 43 will be described as n-channel transistors, but the following description can be applied even if any one, any two, or all of transistors 41, 42, and 43 are p-channel transistors by appropriately reversing the potential magnitude relationships, for example.

[0108] The transistors 41 and 43 have a function of controlling reading of data stored in the memory cell 21. A method of reading data stored in the memory cell 21 will be described below. The memory cell 21 stores binary data having a value of "0" or "1" as the potential of the node N, and "1" is represented by a potential higher than "0."

[0109] When reading data stored in the memory cell 21, the wiring 33R is first precharged to a high potential. The potential of the wiring 35 is set to a constant potential (GND or a low potential) as in the above-described data write and data retention. Furthermore, the potential of the wiring 31R is set to a high potential (i.e., the transistor 43 is turned on), thereby establishing electrical continuity between the wiring 33R and either the source or the drain of the transistor 41.

[0110] At this time, a high potential is applied to one of the source or drain of the transistor 41, and GND or a low potential is applied to the other of the source or drain. Also, a potential of a magnitude corresponding to the data held in the memory cell 21 (i.e., the data written to the node N) is applied to the gate of the transistor 41. In other words, whether the transistor 41 is in an on state or an off state is determined depending on the type of data.

[0111] Here, when the data stored in the memory cell 21 is "0," the difference between the gate potential and the source potential of the transistor 41 is assumed to be less than the threshold voltage of the transistor 41. When the data stored in the memory cell 21 is "1," the difference between the gate potential and the source potential of the transistor 41 is assumed to be greater than the threshold voltage of the transistor 41. In this case, if the data stored in the memory cell 21 is "0," the transistor 41 is turned off and the transistor 43 is turned on, so that no current flows from the wiring 33R to the wiring 35. On the other hand, if the data stored in the memory cell 21 is "1," both the transistors 43 and 41 are turned on, so that a current flows from the wiring 33R to the wiring 35. Therefore, the bit line driver circuit 13 can read the data stored in the memory cell 21 from the current flowing through the wiring 33R or the potential of the wiring 33R. Whether the data stored in the memory cell 21 is "0" or "1," the difference between the gate potential and the source potential of the transistor 41 may exceed the threshold voltage of the transistor 41. Even in this case, the bit line driving circuit 13 can read the data held in the memory cell 21 by, for example, reading the magnitude of the current flowing through the wiring 33R.

[0112] As described above, in the memory cell 21 illustrated in FIG. 1C according to one embodiment of the present invention, the potential of the wiring 35 is always fixed to a constant level (GND or a low potential) during any of the data write, data retention, and data read operations. Furthermore, during data read (when a high potential is applied to the wiring 33R), only the transistor 43 included in the memory cell 21 from which data is to be read can be turned on via the wiring 31R. Meanwhile, in the memory cells 21 other than the memory cell 21 from which data is to be read, the transistor 43 is turned off. This prevents a potential from being applied to the node N from the wiring 33R via the gate capacitance of the transistor 41 or the like, thereby preventing fluctuations in the magnitude of the data retained in the memory cell 21. Therefore, the memory cell 21 illustrated in FIG. 1C according to one embodiment of the present invention can read retained data more stably than the memory cell 21 illustrated in FIG. 1B, thereby realizing a memory device with high read accuracy.

[0113] 2A is a modified example of the memory cell 21 shown in FIG. 1C , and illustrates an example in which the wiring 31R is connected to the other of the source or the drain of the transistor 41, and the wiring 35 is connected to the gate of the transistor 43. The memory cell 21 shown in FIG. 2A can be written to and retained in the same manner as the memory cell 21 shown in FIG. 1C. Data can be read from the memory cell 21 by applying the description regarding the wiring 35 in the memory cell 21 shown in FIG. 1C to the wiring 31R in the memory cell 21 shown in FIG. 2A, applying the description regarding the wiring 31R in the memory cell 21 shown in FIG. 1C to the wiring 35 in the memory cell 21 shown in FIG. 2A, and by interchanging the functions of the power supply circuit 15 and the word line driver circuit 11 in the semiconductor device 10 shown in FIG. 1A.

[0114] 1C and 2A are 3TrOC memory cells each including three transistors and having no capacitance. Therefore, it is preferable to use OS transistors as the transistors 41, 42, and 43, for example. In particular, it is preferable to use an OS transistor as the transistor 42, whose off-state current affects the data retention period of the memory cell 21. Examples of metal oxides contained in the channel formation region of an OS transistor include indium oxide, gallium oxide, and zinc oxide.

[0115] The transistors 41 and 43 may be transistors other than OS transistors. For example, Si transistors having silicon in their channel formation regions can be used as the transistors 41 and 43. Examples of silicon that can be used include single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, and polycrystalline silicon (including low-temperature polycrystalline silicon). Si transistors have higher on-state current and higher field-effect mobility than OS transistors. Therefore, by using Si transistors as the transistors 41 and 43, a memory cell 21 with a high data read speed can be realized.

[0116] The transistors 41 and 43 may have the same structure or different structures. For example, the transistors 41 and 43 may each be an OS transistor, or the transistor 41 may be a Si transistor and the transistor 43 may be an OS transistor. Alternatively, the transistor 41 may be an OS transistor and the transistor 43 may be a Si transistor.

[0117] Figure 61A is a modified example of memory cell 21 shown in Figure 1C, and differs from memory cell 21 shown in Figure 1C in that, of transistors 41 and 42, only transistor 42 has a back gate, and transistor 41 does not have a back gate.

[0118] As described above, the transistor 42 has a function of writing data to the memory cell 21. Therefore, the transistor 42 having a back gate can have a larger on-state current than a transistor without a back gate. Therefore, the speed at which data can be written to the node N can be increased compared to a transistor without a back gate. Furthermore, the transistor 42 having a back gate can have a smaller off-state current than a transistor without a back gate. Therefore, data can be retained in the node N for a long period of time. Furthermore, the potential of the semiconductor layer can be fixed at a constant potential, thereby suppressing operational variations between memory cells. Furthermore, the transistor 41 not having a back gate can reduce the number of manufacturing steps compared to the memory cell 21 shown in FIG. 1C .

[0119] Figure 61B is a modified example of the memory cell 21 shown in Figure 1C, and differs from the memory cell 21 shown in Figure 1C in that, of the transistors 41 and 42, only the transistor 41 has a back gate, and the transistor 42 does not have a back gate.

[0120] As described above, the transistor 41 has a function of reading data stored in the memory cell 21. Therefore, the transistor 41 having a back gate can have a larger on-state current than a transistor without a back gate. Therefore, the speed at which data is read from the memory cell 21 can be improved compared to a transistor without a back gate. Furthermore, the potential of the semiconductor layer can be fixed to a constant potential, which can suppress operational variations between memory cells. Furthermore, the transistor 42 not having a back gate can reduce the number of manufacturing steps compared to the memory cell 21 shown in FIG. 1C.

[0121] FIG. 61C is a modification of the memory cell 21 shown in FIG. 1C, and differs from the memory cell 21 shown in FIG. 1C in that neither the transistor 41 nor the transistor 42 has a back gate.

[0122] 61C , even in a configuration in which neither the transistor 41 nor the transistor 42 has a back gate, the presence of the transistor 43 allows stored data to be read more stably than in the memory cell 21 shown in FIG. 1B. Furthermore, since neither the transistor 41 nor the transistor 42 has a back gate, the number of manufacturing steps can be reduced compared to the memory cell 21 shown in FIGS. 1C , 61A, and 61B.

[0123] FIG. 2B shows a modification of the memory cell 21 shown in FIG. 1C, and differs from the memory cell 21 shown in FIG. 1C in that it has a capacitor 51 .

[0124] 2B, one electrode of the capacitor 51 is connected to the other of the source or the drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is connected to the wiring 35. Here, a node to which the gate of the transistor 41, the other of the source or the drain of the transistor 42, and one electrode of the capacitor 51 are connected is referred to as a node N. For other configurations of the memory cell 21 shown in FIG. 2B, the description of the memory cell 21 shown in FIG. 1C can be referred to.

[0125] The memory cell 21 shown in Figure 2B can perform data write, data retention, and data read operations in the same manner as the memory cell 21 shown in Figure 1C. The memory cell 21 shown in Figure 2B has the capacitor 51, and thus can retain data written to the node N more stably than the memory cell 21 shown in Figure 1C. Therefore, data can be retained more stably for a longer period of time than the memory cell 21 shown in Figure 1C, which does not have the capacitor 51.

[0126] FIG. 62A is a modified example of the memory cell 21 shown in FIG. 2B , and differs from the memory cell 21 shown in FIG. 2B in that the back gate of the transistor 42 is connected to a wiring. As described above, the wiring can be, for example, a wiring connected to the source or gate (first gate) of the transistor 42, or the wiring 35. Furthermore, the wiring can be connected to, for example, a wiring included in a semiconductor device (not shown) other than the semiconductor device 10 shown in FIG. 1A. This configuration can increase the data write speed. It can also achieve long-term data retention in the node N. Furthermore, it can suppress operational variations between memory cells.

[0127] FIG. 62B is a modified example of the memory cell 21 shown in FIG. 2B , and differs from the memory cell 21 shown in FIG. 2B in that the back gate of the transistor 41 is connected to a wiring. As described above, the wiring may be, for example, a wiring connected to the source or gate (first gate) of the transistor 41, or the wiring 35. Furthermore, the wiring may be connected to, for example, a wiring included in a semiconductor device (not shown) other than the semiconductor device 10 shown in FIG. 1A. This configuration can improve the speed at which data stored in the memory cell 21 can be read. Furthermore, it can suppress operational variations between memory cells.

[0128] Figure 62C is a modification of the memory cell 21 shown in Figure 2B, and differs from the memory cell 21 shown in Figure 2B in that the back gates of the transistors 41 and 42 are connected to wirings. The memory cell 21 shown in Figure 62C can be said to have a configuration that combines the memory cell 21 shown in Figure 62A and the memory cell 21 shown in Figure 62B. This configuration makes it possible to enjoy both the effects obtained by the memory cell 21 shown in Figure 62A and the effects obtained by the memory cell 21 shown in Figure 62B.

[0129] 63A is a modification of the memory cell 21 shown in FIG. 62A , and is similar in that the back gate of the transistor 42 is connected to a wiring, but the extension direction of the wiring is different from that of the memory cell 21 shown in FIG. 62A . Specifically, in the memory cell 21 shown in FIG. 62A , the wiring connected to the back gate of the transistor 42 extends in the same direction as the wiring 33R, the wiring 33W, and the wiring 35, whereas in the memory cell 21 shown in FIG. 63A , the wiring connected to the back gate of the transistor 42 extends in the same direction as the wiring 31R and the wiring 31W. This configuration can provide the same effects as those obtained by the memory cell 21 shown in FIG. 62A .

[0130] 63B is a modification of the memory cell 21 shown in FIG. 62B , and is similar in that the back gate of the transistor 41 is connected to a wiring, but the extension direction of the wiring is different from that of the memory cell 21 shown in FIG. 62B . Specifically, in the memory cell 21 shown in FIG. 62B , the wiring connected to the back gate of the transistor 41 extends in the same direction as the wiring 33R, the wiring 33W, and the wiring 35, whereas in the memory cell 21 shown in FIG. 63B , the wiring connected to the back gate of the transistor 41 extends in the same direction as the wiring 31R and the wiring 31W. This configuration can provide the same effects as those obtained by the memory cell 21 shown in FIG. 62B .

[0131] 63C is a modification of the memory cell 21 shown in FIG. 62C , and is similar in that the back gates of the transistors 41 and 42 are connected to wirings, but the direction in which the wirings extend is different from that of the memory cell 21 shown in FIG. 62C . Specifically, in the memory cell 21 shown in FIG. 62C , the wirings connected to the back gates of the transistors 41 and 42 extend in the same direction as the wirings 33R, 33W, and 35, whereas in the memory cell 21 shown in FIG. 63C , the wirings connected to the back gates of the transistors 41 and 42 extend in the same direction as the wirings 31R and 31W. This configuration can provide the same effects as those achieved by the memory cell 21 shown in FIG. 62C .

[0132] Figure 64A is a modification of memory cell 21 shown in Figure 62A, and differs from memory cell 21 shown in Figure 62A in that wiring connected to the back gate of transistor 42 (wiring 33R, wiring 33W, and wiring 35 extending in the same direction) is connected to another wiring (wiring 31R and wiring 31W) extending in the same direction. This configuration makes it possible to enjoy the same effects as those obtained by memory cell 21 shown in Figure 62A.

[0133] Figure 64B is a modification of memory cell 21 shown in Figure 62B, and differs from memory cell 21 shown in Figure 62B in that the wiring connected to the back gate of transistor 41 (wiring 33R, wiring 33W, and wiring 35 extending in the same direction) is connected to another wiring (wiring 31R and wiring 31W) extending in the same direction. This configuration can provide the same effects as those obtained by memory cell 21 shown in Figure 62B.

[0134] Fig. 65A shows a memory cell 21 having a configuration that combines the configuration of wiring connected to the back gate of transistor 42 shown in Fig. 64A and the configuration of wiring connected to the back gate of transistor 41 shown in Fig. 64B. This configuration makes it possible to enjoy both the effects obtained by the memory cell 21 shown in Fig. 64A and the effects obtained by the memory cell 21 shown in Fig. 64B.

[0135] Fig. 65B shows a memory cell 21 having a configuration that combines the configuration of wiring connected to the back gate of transistor 42 shown in Fig. 62A and the configuration of wiring connected to the back gate of transistor 41 shown in Fig. 63B. This configuration makes it possible to enjoy both the effects obtained by the memory cell 21 shown in Fig. 62A and the effects obtained by the memory cell 21 shown in Fig. 63B.

[0136] Fig. 3A is a block diagram showing a configuration example of a semiconductor device 10 different from that shown in Fig. 1A. The semiconductor device 10 shown in Fig. 3A differs from the semiconductor device 10 shown in Fig. 1A in that it has wiring 36.

[0137] The memory cells 21 arranged in the same row are connected to the word line driving circuit 11 via a common wiring 36. The wiring 36 functions as a capacitance line.

[0138] Regarding the configuration of the semiconductor device 10 shown in FIG. 3A other than the above, the description of the semiconductor device 10 shown in FIG. 1A can be referred to.

[0139] Fig. 3B is a circuit diagram showing an example of the configuration of a memory cell 21 included in the semiconductor device 10 shown in Fig. 3A. The memory cell 21 having this configuration differs from the memory cell 21 shown in Fig. 1B in that it has a capacitance 51 in addition to the wiring 36 described above.

[0140] 3B, one electrode of the capacitor 51 is connected to the other of the source or the drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is connected to the wiring 36. Here, a node to which the gate of the transistor 41, the other of the source or the drain of the transistor 42, and one electrode of the capacitor 51 are connected is referred to as a node N. For other configurations of the memory cell 21 shown in FIG. 3B, the description of the memory cell 21 shown in FIG. 1C can be referred to.

[0141] 3B can be used for data writing, data retention, and data reading in the same manner as the memory cell 21 shown in Fig. 1C. During the above series of operations, a constant potential, i.e., GND (ground potential) or a low potential, is always applied to the wiring 36, just like the wiring 35.

[0142] FIG. 3C is a modified example of the memory cell 21 shown in FIG. 3B, and differs from the memory cell 21 shown in FIG. 3B in that a transistor 44 is included.

[0143] 3C , one of the source and the drain of the transistor 44 is connected to the wiring 35. The other of the source and the drain of the transistor 44 is connected to the other electrode of the capacitor 51. The gate of the transistor 44 is connected to the gate of the transistor 41 and one electrode of the capacitor 51. For other configurations of the memory cell 21 shown in FIG. 3C , the description of the memory cell 21 shown in FIG. 3B can be referred to.

[0144] The memory cell 21 shown in Fig. 3C can be used for data writing, data retention, and data reading in the same manner as the memory cell 21 shown in Fig. 3B. During the above series of operations, the same constant potential as that of the wiring 35, i.e., GND (ground potential) or a low potential, is always applied to the wiring 36.

[0145] 3C shows an example in which the transistor 44 does not have a back gate, but this is not limiting. The transistor 44 may have a back gate. For the connection destination of the back gate of the transistor 44, see the description of the connection destination of the back gates of the transistors 41 and 42.

[0146] 2B and 3B are 3Tr1C type memory cells each including three transistors and one capacitor. Also, the memory cell 21 shown in Fig. 3C is a 4Tr1C type memory cell including four transistors and one capacitor. Each transistor in these memory cells may be an OS transistor or a Si transistor.

[0147] Note that a memory cell 21 in which OS transistors are used as each transistor in the memory cell 21 illustrated in FIGS. 2B, 3B, and 3C is also referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0148] As described above, an OS transistor has an extremely low off-state current. Therefore, by using an OS transistor as the transistor 42 included in each of the memory cells 21 illustrated in FIGS. 1C , 2A , 2B , 3B , and 3C according to one embodiment of the present invention, charge accumulated in the node N can be held for a long period of time. Furthermore, since the transistor 42 has a back gate, the off-state current can be smaller than that of a transistor without a back gate. Therefore, charge accumulated in the node N can be held for a longer period of time. Since data written to the memory cell 21 can be held for a long period of time, the frequency of refresh operations (rewriting data to the memory cell 21) can be reduced. Therefore, the power consumption of the semiconductor device 10 can be reduced.

[0149] 4A is a plan view showing a structural example of a portion of a semiconductor device 10 that is a semiconductor device of one embodiment of the present invention. FIG. 4A includes a structural example of the memory cell 21 shown in FIG. 1C. In FIG. 4A, some elements such as insulating layers are omitted for clarity. Some elements will also be omitted in the plan views shown later. FIG. 4B is a cross-sectional view taken along dashed dotted line A1-A2 shown in FIG. 4A, and FIG. 4C is a cross-sectional view taken along dashed dotted line A3-A4 shown in FIG. 4A.

[0150] A semiconductor device of one embodiment of the present invention includes an insulating layer 101 over a substrate (not shown) and a memory cell 21 over the insulating layer 101. The memory cell 21 includes a transistor 43, a transistor 41 over the transistor 43, and a transistor 42 over the transistor 41.

[0151] In addition, the semiconductor device of one embodiment of the present invention includes an insulating layer 103c_1 over the insulating layer 101, an insulating layer 103c_2 over the insulating layer 103c_1, an insulating layer 107c over the transistor 43 and over the insulating layer 103c_2, an insulating layer 103c_3 over the insulating layer 107c, the transistor 41 over the insulating layer 103c_3, the insulating layer 103a_1, and the insulating layer 103a_2 over the insulating layer 103a_1, and the transistor 41 over the insulating layer 103c_3. The insulating layer 107a is provided over the transistor 41, the insulating layer 103a_1, and the insulating layer 103a_2, the insulating layer 131 is provided over the insulating layer 107a, the transistor 42, the insulating layer 103b_1, and the insulating layer 103b_2 are provided over the transistor 41 and the insulating layer 131, and the insulating layer 103b_1 and the insulating layer 103b_2 are provided over the transistor 42, the insulating layer 103b_1, and the insulating layer 103b_2. Here, the insulating layer 101, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103a_1, the insulating layer 103a_2, the insulating layer 131, the insulating layer 103b_1, and the insulating layer 103b_2 each function as an interlayer insulating layer and are preferably planarized. Note that the insulating layer functioning as an interlayer insulating layer does not necessarily have to be planarized.

[0152] The transistor 43 includes a conductive layer 111c, a conductive layer 111a, a semiconductor layer 113c, an insulating layer 105c, and a conductive layer 115c.

[0153] A part of the conductive layer 111c functions as one of the source electrode and the drain electrode of the transistor 43, and functions as a wiring 33R. A part of the conductive layer 111a functions as the other of the source electrode and the drain electrode of the transistor 43. A part of the insulating layer 105c functions as a gate insulating layer of the transistor 43. A part of the conductive layer 115c functions as a gate electrode of the transistor 43, and functions as a wiring 31R. The conductive layer 111c functioning as the wiring 33R has a region extending in the Y direction. The conductive layer 115c functioning as the wiring 31R has a region extending in the X direction.

[0154] A conductive layer 111c is provided over the insulating layer 101. An insulating layer 103c_1 is provided over the insulating layer 101 and the conductive layer 111c. A conductive layer 115c is provided over the insulating layer 103c_1. An insulating layer 103c_2 is provided over the insulating layer 103c_1 and the conductive layer 115c. The insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 have an opening 121c that reaches the conductive layer 111c. FIG. 4A shows an example in which the shape of the opening 121c is circular in a plan view. By making the top surface shape of the opening 121c circular, processing accuracy in forming the opening 121c can be improved, and the opening 121c can be formed with a fine size. Note that the top surface shape of the opening 121c may be, for example, an ellipse, a rectangle, or another polygon (including a polygon with rounded corners).

[0155] The insulating layer 105c, which functions as a gate insulating layer of the transistor 43, is provided in the opening 121c so as to have a region in contact with part of the top surface of the conductive layer 111c, the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, and the side surface of the insulating layer 103c_2.

[0156] The semiconductor layer 113c covers the opening 121c via the insulating layer 105c and has a region located inside the opening 121c. The upper end of the insulating layer 105c has a curved shape. The semiconductor layer 113c has a region in contact with the top surface of the insulating layer 103c_2, a region in contact with the curved portion of the insulating layer 105c, a region in contact with the side surface of the insulating layer 105c, and a region in contact with the top surface of the conductive layer 111c. The semiconductor layer 113c has a shape that conforms to the top surface of the insulating layer 103c_2, the curved portion of the insulating layer 105c, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. As a result, the semiconductor layer 113c has a recess at a position overlapping the opening 121c. A layer 114 is provided to fill the recess. The layer 114 has a function of filling the recess and planarizing the top surface. It should be noted that even if the recesses are present, if they do not affect the coverage of the upper layer to be formed later, or if the recesses themselves are not formed, there is no need to provide layer 114.

[0157] 4B and 4C, the semiconductor layer 113c has a single-layer structure; however, one embodiment of the present invention is not limited to this. The semiconductor layer 113c may have a stacked structure of two or more layers.

[0158] The insulating layer 107c is provided to cover the side surfaces of the semiconductor layer 113c at the end portions thereof and the top surface of the insulating layer 103c_2. The insulating layer 107c has a function of suppressing diffusion of impurities into the transistor 43, for example, a function of suppressing diffusion into the semiconductor layer 113c. The insulating layer 103c_3 is provided over the insulating layer 107c. It is preferable that the top surfaces of the semiconductor layer 113c, the insulating layer 107c, and the insulating layer 103c_3 relative to the substrate surface (surfaces in contact with the bottom surface of the conductive layer 111a) are at approximately the same height relative to the substrate surface. This allows the surface on which an upper layer (e.g., the conductive layer 111a) to be formed later to be formed to be flat, thereby improving the coverage of the upper layer. In addition, when the film thickness of the insulating layer 107c and the film thickness of the semiconductor layer 113c are approximately equal (i.e., when the height of the upper surface of the insulating layer 107c and the height of the top surface of the semiconductor layer 113c are approximately the same), it is not necessary to provide the insulating layer 103c_3.

[0159] The conductive layer 111a functioning as the other of the source electrode and the drain electrode of the transistor 43 is provided in contact with the top surface of the semiconductor layer 113c, the top surface of the layer 114, the top surface of the insulating layer 107c, and the top surface of the insulating layer 103c_3, each of which is relative to the substrate surface. The conductive layer 111a is provided to have a region overlapping with the conductive layer 111c functioning as one of the source electrode and the drain electrode of the transistor 43.

[0160] It is preferable that the end of the conductive layer 111a be substantially aligned with the end of the semiconductor layer 113c or be located outside the end of the semiconductor layer 113c, thereby increasing the contact area between the conductive layer 111a and the semiconductor layer 113c and reducing the contact resistance between the conductive layer 111a and the semiconductor layer 113c.

[0161] In the transistor 43, a source electrode, a drain electrode, and a gate electrode are provided at different heights with respect to the substrate surface and overlap each other. The gate electrode is sandwiched between the source electrode and the drain electrode. Therefore, in the transistor 43, the channel length direction corresponds to the direction along the side surface of the insulating layer 105c in a cross-sectional view, and a drain current flows in this direction.

[0162] When the transistor 43 has the above-described structure, the channel length of the transistor 43 can be controlled by adjusting the film thicknesses of layers (the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2) located between the source electrode and the drain electrode in a cross-sectional view. Therefore, the channel length of the transistor 43 can be made smaller than the resolution limit of an exposure device. Furthermore, the area occupied by the transistor in a plan view can be made smaller than that of a transistor having a structure in which the source electrode and the drain electrode are provided on the same plane.

[0163] In addition, in the transistor 43, the gate electrode (conductive layer 115c) is provided to surround the semiconductor layer 113c and the insulating layer 105c located in the opening 121c in a plan view. Therefore, the entire region of the semiconductor layer 113c in the opening 121c that faces the conductive layer 115c with the insulating layer 105c interposed therebetween can be used as a channel formation region of the transistor 43. In this case, the channel width direction of the transistor 43 is parallel to the XY plane, and the channel width of the transistor 43 corresponds to the perimeter length of the opening 121c in FIG. 4A .

[0164] The transistor 41 includes a conductive layer 111a, a conductive layer 112a, a semiconductor layer 113a, an insulating layer 105a, a conductive layer 115a, an insulating layer 116a, and a conductive layer 117a.

[0165] A part of the conductive layer 111a functions as one of the source electrode and the drain electrode of the transistor 41. A part of the conductive layer 112a functions as the other of the source electrode and the drain electrode of the transistor 41 and functions as a wiring 35. A part of the insulating layer 105a functions as a gate insulating layer (first gate insulating layer) of the transistor 41. A part of the conductive layer 115a functions as a gate electrode (first gate electrode) of the transistor 41. A part of the insulating layer 116a functions as a back gate insulating layer (second gate insulating layer) of the transistor 41. A part of the conductive layer 117a functions as a back gate electrode (second gate electrode) of the transistor 41. The conductive layer 117a has a region extending in the X direction. The conductive layer 112a functioning as the wiring 35 has a region extending in the Y direction.

[0166] 4A to 4C , the conductive layer 111a also functions as the other of the source electrode and the drain electrode of the transistor 43. Therefore, in the semiconductor device illustrated in FIG. 4A to FIG. 4C , the conductive layer 111a functions as the other of the source electrode and the drain electrode of the transistor 43 and also functions as one of the source electrode and the drain electrode of the transistor 41.

[0167] A conductive layer 111a is provided over the semiconductor layer 113c, the layer 114, the insulating layer 107c, and the insulating layer 103c_3. An insulating layer 103a_1 is provided over the insulating layer 103c_3 and the conductive layer 111a. A conductive layer 117a is provided over the insulating layer 103a_1. An insulating layer 103a_2 is provided over the insulating layer 103a_1 and the conductive layer 117a. A conductive layer 112a is provided over the insulating layer 103a_2. The conductive layer 111a and the conductive layer 112a overlap with each other in regions with the insulating layer 103a_1, the conductive layer 117a, and the insulating layer 103a_2 interposed therebetween. The insulating layer 103a_1, the conductive layer 117a, the insulating layer 103a_2, and the conductive layer 112a each have an opening 121a that reaches the conductive layer 111a. Note that in Figures 4A and 4B, an example is shown in which the side end of the conductive layer 111a is located outside the side end of the conductive layer 112a that does not face the opening 121a in the X direction, i.e., the side end of the conductive layer 112a that does not face the opening 121a overlaps with the conductive layer 111a, but the side end of the conductive layer 111a does not overlap with the conductive layer 112a. However, one embodiment of the present invention is not limited to this example. For example, the side end of the conductive layer 111a may be located inside the side end of the conductive layer 112a that does not face the opening 121a.

[0168] 4A shows an example in which the shape of the opening 121a is circular in a plan view. By making the top surface shape of the opening 121a circular, the processing accuracy when forming the opening 121a can be improved, and the opening 121a can be formed with a fine size. Note that the top surface shape of the opening 121a may also be polygonal, such as elliptical or rectangular.

[0169] The insulating layer 116a, which functions as a back-gate insulating layer of the transistor 41, is provided in the opening 121a so as to have a region in contact with part of the top surface of the conductive layer 111a, the side surface of the insulating layer 103a_1, the side surface of the conductive layer 117a, and the side surface of the insulating layer 103a_2.

[0170] The semiconductor layer 113a covers the opening 121a via the insulating layer 116a and has a region located inside the opening 121a. The upper end of the insulating layer 116a has a curved shape. The semiconductor layer 113a has a region in contact with the upper surface of the conductive layer 112a, a region in contact with the curved portion of the insulating layer 116a, a region in contact with the side surface of the insulating layer 116a, and a region in contact with the upper surface of the conductive layer 111a. The semiconductor layer 113a has a shape that follows the upper surface of the conductive layer 112a, the curved portion of the insulating layer 116a, the side surface of the insulating layer 116a, and the upper surface of the conductive layer 111a. As a result, the semiconductor layer 113a has a recess at a position overlapping the opening 121a.

[0171] The semiconductor layer 113a preferably covers the side edge of the conductive layer 112a on the opening 121a side. For example, FIGS. 4B and 4C show a configuration in which the side edge of the semiconductor layer 113a is located on the conductive layer 112a. It can also be said that the lower edge of the semiconductor layer 113a contacts the upper surface of the conductive layer 112a. Note that FIGS. 4A to 4C show an example in which the side edge of the semiconductor layer 113a is located inside the side edge of the conductive layer 112a that does not face the opening 121a, i.e., the entire semiconductor layer 113a overlaps with the conductive layer 112a or the opening 121a. Also, FIGS. 4A to 4C show an example in which the side edge of the semiconductor layer 113a is located inside the side edge of the conductive layer 111a, i.e., the entire semiconductor layer 113a overlaps with the conductive layer 111a.

[0172] In this specification, the upper end portion refers to the uppermost part of the side end portion, and the lower end portion refers to the lowermost part of the side end portion. In other words, the upper end portion and the lower end portion are each a part of the side end portion.

[0173] 4B and 4C, the semiconductor layer 113a has a single-layer structure; however, one embodiment of the present invention is not limited to this. The semiconductor layer 113a may have a stacked structure of two or more layers.

[0174] An insulating layer 108a is provided in contact with the side surface of the conductive layer 112a that does not face the opening 121a. The upper end of the insulating layer 108a has a curved shape. The insulating layer 108a is an insulating layer made of the same material as the insulating layer 116a. The insulating layer 108a is a portion of the insulating film that will become the insulating layer 116a that remains when the insulating layer 116a is formed. Note that FIG. 4B and other figures show an example in which the insulating layer 108a is provided on the side surface of the conductive layer 112a that does not face the opening 121a, but this is not limited to this. Depending on the film thickness of the conductive layer 112a, the angle between the side surface of the conductive layer 112a that does not face the opening 121a and the insulating layer 103a_2, the processing conditions of the insulating layer 116a, and the like, a configuration without the insulating layer 108a may also be used.

[0175] The insulating layer 105a, which functions as a gate insulating layer of the transistor 41, is provided to cover the opening 121a and to have a region located inside the opening 121a. The insulating layer 105a is provided over the semiconductor layer 113a, the conductive layer 112a, the insulating layer 108a, and the insulating layer 103a_2. The insulating layer 105a has a region in contact with the top surface of the semiconductor layer 113a, a region in contact with the side surface of the semiconductor layer 113a, a region in contact with the top surface of the conductive layer 112a, a region in contact with the curved portion of the insulating layer 108a, a region in contact with the side surface of the insulating layer 108a, and a region in contact with the top surface of the insulating layer 103a_2. The insulating layer 105a has a shape that follows the top surface of the semiconductor layer 113a, the side surface of the semiconductor layer 113a, the top surface of the conductive layer 112a, the curved portion of the insulating layer 108a, the side surface of the insulating layer 108a, and the top surface of the insulating layer 103a_2. As a result, the insulating layer 105a has a recess at a position overlapping the opening 121a.

[0176] The conductive layer 115a functioning as the gate electrode of the transistor 41 is provided over the insulating layer 105a and has a region in contact with the top surface of the insulating layer 105a. The conductive layer 115a has a region overlapping with the semiconductor layer 113a with the insulating layer 105a interposed therebetween. Here, the semiconductor layer 113a can be configured to cover the side surface and bottom surface of the conductive layer 115a within the opening 121a with the insulating layer 105a interposed therebetween. For example, within the opening 121a, the insulating layer 105a has a region in contact with the side surface of the semiconductor layer 113a, a region in contact with the top surface of the recess of the semiconductor layer 113a, a region in contact with the side surface of the conductive layer 115a, and a region in contact with the bottom surface of the conductive layer 115a.

[0177] 4B and 4C is a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside an opening formed in an interlayer insulating layer. In other words, the transistor 41 is a transistor in which the semiconductor layer is provided to surround the gate electrode (first gate electrode) through the gate insulating layer (first gate insulating layer) in a plan view. This allows the channel length direction of the transistor 41 to be aligned along the side surfaces of the insulating layer 103a_1, the conductive layer 117a, and the insulating layer 103a_2 in the opening 121a in a cross-sectional view. Therefore, the channel length is not affected by the performance of an exposure tool used to manufacture the transistor 41, and the channel length can be made smaller than the resolution limit of the exposure tool. Therefore, the transistor 41 can be miniaturized. For example, Figure 4A shows an example in which the entire opening 121a has an area overlapping with the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a, but a part of the opening 121a does not have to overlap with at least one of the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a.

[0178] The transistor 41 also includes a back gate electrode (conductive layer 117a) that surrounds the semiconductor layer 113a and the insulating layer 116a located in the opening 121a in a plan view. Therefore, the entire region of the semiconductor layer 113a in the opening 121a that faces the conductive layer 117a with the insulating layer 116a interposed therebetween can be used as a channel formation region (also referred to as a second channel formation region or a back channel formation region) of the transistor 41.

[0179] As described above, the transistor 41 of one embodiment of the present invention has two gate electrodes sandwiching a semiconductor layer. This allows the influence of a gate electric field on carriers in the semiconductor layer to be stronger than in the case where only one gate electrode is provided. Therefore, a larger on-state current and a smaller off-state current can be obtained than in the case where only one gate electrode is provided. Furthermore, the potential of the semiconductor layer can be fixed by the electric field from the back gate electrode, thereby providing stable transistor characteristics with little variation.

[0180] As shown in Figures 4B and 4C, a portion of the insulating layer 105a is located outside the opening 121a, that is, on the conductive layer 112a and the insulating layer 103a_2. In this case, the insulating layer 105a preferably covers the side edges of the semiconductor layer 113a. This can prevent a short circuit between the conductive layer 115a and the semiconductor layer 113a. In addition, the insulating layer 105a preferably covers the side edges of the conductive layer 112a. This can prevent a short circuit between the conductive layer 115a and the conductive layer 112a.

[0181] 4B, 4C, etc., a portion of the conductive layer 115a is located outside the opening 121a, i.e., on the conductive layer 112a. While FIGS. 4B, 4C, etc. show an example in which the side edge of the conductive layer 115a is located inside the side edge of the semiconductor layer 113a, this is not a limitation. The side edge of the conductive layer 115a may also be located outside the side edge of the semiconductor layer 113a.

[0182] An insulating layer 107a is provided in contact with the upper surface of the insulating layer 105a and the side surface of the conductive layer 115a. An insulating layer 131 is provided on the insulating layer 107a. The upper surface of the conductive layer 115a, the uppermost surface of the insulating layer 107a, and the upper surface of the insulating layer 131 are all at approximately the same height relative to the substrate surface.

[0183] The insulating layer 107a has a function of suppressing diffusion of impurities into the transistor 41, for example, into the semiconductor layer 113a. As described above, the insulating layer 131 functions as an interlayer insulating layer.

[0184] The transistor 42 includes a conductive layer 111b, a conductive layer 112b, a semiconductor layer 113b, an insulating layer 105b, a conductive layer 115b, an insulating layer 116b, and a conductive layer 117b.

[0185] A part of the conductive layer 111b functions as one of the source electrode and the drain electrode of the transistor 42. A part of the conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 42 and functions as a wiring 33W. A part of the insulating layer 105b functions as a gate insulating layer (first gate insulating layer) of the transistor 42. A part of the conductive layer 115b functions as a gate electrode (first gate electrode) of the transistor 42 and functions as a wiring 31W. A part of the insulating layer 116b functions as a back gate insulating layer (second gate insulating layer) of the transistor 42. A part of the conductive layer 117b functions as a back gate electrode (second gate electrode) of the transistor 42. The conductive layer 112b functioning as the wiring 33W has a region extending in the Y direction. The conductive layer 115b functioning as the wiring 31W has a region extending in the X direction. The conductive layer 117b has a region extending in the X direction.

[0186] 4A to 4C , the conductive layer 111b also functions as the other of the source electrode and the drain electrode of the transistor 41. Therefore, in the semiconductor device illustrated in FIG. 4A to FIG. 4C , the conductive layer 111b functions as the other of the source electrode and the drain electrode of the transistor 41 and also functions as one of the source electrode and the drain electrode of the transistor 42.

[0187] A conductive layer 111b is provided over the conductive layer 115a, the insulating layer 107a, and the insulating layer 131. The conductive layer 111b has at least a region in contact with the top surface of the conductive layer 115a. An insulating layer 103b_1 is provided over the insulating layer 131 and the conductive layer 111b. A conductive layer 117b is provided over the insulating layer 103b_1. An insulating layer 103b_2 is provided over the insulating layer 103b_1 and the conductive layer 117b. A conductive layer 112b is provided over the insulating layer 103b_2. The conductive layer 111b and the conductive layer 112b have regions where they overlap with each other with the insulating layer 103b_1, the conductive layer 117b, and the insulating layer 103b_2 interposed therebetween.

[0188] The insulating layer 103b_1, the conductive layer 117b, the insulating layer 103b_2, and the conductive layer 112b have an opening 121b that reaches the conductive layer 111b. In FIG. 4A, the opening 121b has a circular shape in a plan view. Note that the opening 121b can have the same shape as the opening 121a.

[0189] An insulating layer 108b is provided in contact with the side surface of the conductive layer 112b that does not face the opening 121b.

[0190] The structure of the transistor 42 can be similar to that of the aforementioned transistor 41. For the description of the structure of the transistor 42, the description of the structure of the transistor 41 can be referred to by replacing the transistor 41, the insulating layer 103a_1, the insulating layer 103a_2, the insulating layer 105a, the conductive layer 111a, the conductive layer 112a, the semiconductor layer 113a, the conductive layer 115a, the insulating layer 116a, the conductive layer 117a, and the insulating layer 108a with the transistor 42, the insulating layer 103b_1, the insulating layer 103b_2, the insulating layer 105b, the conductive layer 111b, the conductive layer 112b, the semiconductor layer 113b, the conductive layer 115b, the insulating layer 116b, the conductive layer 117b, and the insulating layer 108b, respectively, and making appropriate necessary changes.

[0191] In this specification and the like, the insulating layer 103a_1, the insulating layer 103a_2, the insulating layer 103b_1, the insulating layer 103b_2, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103c_3, and the like may be collectively referred to as the insulating layer 103. The insulating layer 105a, the insulating layer 105b, and the insulating layer 105c may be collectively referred to as the insulating layer 105. The insulating layer 107a, the insulating layer 107b, and the insulating layer 107c may be collectively referred to as the insulating layer 107. The conductive layer 111a, the conductive layer 111b, and the conductive layer 111c may be collectively referred to as the conductive layer 111. The conductive layer 112a and the conductive layer 112b may be collectively referred to as the conductive layer 112. The semiconductor layer 113a, the semiconductor layer 113b, and the semiconductor layer 113c may be collectively referred to as the semiconductor layer 113. The conductive layers 115a, 115b, and 115c may be collectively referred to as conductive layers 115. The insulating layers 116a and 116b may be collectively referred to as insulating layers 116. The conductive layers 117a and 117b may be collectively referred to as conductive layers 117. The insulating layers 108a and 108b may be collectively referred to as insulating layers 108. The openings 121a, 121b, and 121c may be collectively referred to as openings 121.

[0192] An insulating layer 107b is provided over the conductive layer 115b and the insulating layer 105b. The insulating layer 107b can be provided to cover the top surface and side surfaces of the conductive layer 115b. The insulating layer 107b has a function of suppressing diffusion of impurities into the transistor 42, for example, a function of suppressing diffusion into the semiconductor layer 113b.

[0193] As described above, in a semiconductor device according to one embodiment of the present invention, the transistor 43, the transistor 41, and the transistor 42 are stacked in this order. The transistor 43 has a source electrode, a drain electrode, and a gate electrode that overlap with each other at different heights relative to a substrate surface. The gate insulating layer and the semiconductor layer are provided so that the channel length direction is aligned along the height direction. The transistors 41 and 42 each have a semiconductor layer, a gate insulating layer, and a gate electrode in an opening formed in an interlayer insulating layer. One of the source electrode and the drain electrode is provided under the opening, and the other of the source electrode and the drain electrode is provided on the interlayer insulating layer. This reduces the area occupied by the memory cell 21 in a plan view. Therefore, the memory cell can be miniaturized and highly integrated. Therefore, one embodiment of the present invention can provide a semiconductor device that enables miniaturization and high integration.

[0194] In the semiconductor device of one embodiment of the present invention, the transistor 41 and the transistor 42 each have a backgate electrode. This allows an electric field to be applied to carriers in the semiconductor layer from both the gate electrode and the backgate electrode, thereby enabling a larger on-state current and a smaller off-state current than in a semiconductor device without a backgate electrode. This improves the speed at which data is written to the memory cell 21 and extends the data retention time. This reduces the frequency of refresh operations, thereby reducing power consumption. Furthermore, the potential of the semiconductor layer can be fixed by the electric field from the backgate electrode, thereby providing stable transistor characteristics.

[0195] Here, in the cross-sectional views shown in Figures 4B and 4C, the boundaries of each layer may not be clearly visible. For example, the boundary between two insulating layers that contact each other may not be clearly visible. Also, the boundary between two conductive layers that contact each other may not be clearly visible. Furthermore, the boundary between two semiconductor layers that contact each other may not be clearly visible.

[0196] 66A to 66C show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configuration examples shown in FIGS. 4A to 4C . Fig. 66A is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 66B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 66A , and Fig. 66C is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 66A .

[0197] The semiconductor device 10 shown in Figures 66A to 66C differs from the semiconductor device 10 shown in Figures 4A to 4C in that the transistor 42 does not have a back gate electrode and a back gate insulating layer. The circuit configuration of the semiconductor device 10 corresponds to the configuration shown in Figure 61B. Therefore, the same effects as those described with reference to Figure 61B can be achieved. Furthermore, since the transistor 42 does not have a back gate electrode and a back gate insulating layer, the number of manufacturing steps can be reduced compared to the semiconductor device 10 shown in Figures 4A to 4C. Note that the insulating layer 103b in the semiconductor device 10 shown in Figures 66A to 66C can be formed using the same material and by the same method as the insulating layers 103b_1 and 103b_2 in the semiconductor device 10 shown in Figures 4A to 4C.

[0198] 67A to 67C show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configuration examples shown in FIGS. 4A to 4C . Fig. 67A is a plan view showing a configuration example of a portion of the semiconductor device 10. Fig. 67B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 67A , and Fig. 67C is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 67A .

[0199] The semiconductor device 10 shown in Figures 67A to 67C differs from the semiconductor device 10 shown in Figures 4A to 4C in that the transistor 41 does not have a back gate electrode and a back gate insulating layer. The semiconductor device 10 has a circuit configuration equivalent to that shown in Figure 61A. Therefore, the same effects as those described in Figure 61A can be achieved. Furthermore, since the transistor 41 does not have a back gate electrode and a back gate insulating layer, the number of manufacturing steps can be reduced compared to the semiconductor device 10 shown in Figures 4A to 4C. The insulating layer 103a in the semiconductor device 10 shown in Figures 67A to 67C can be formed using the same material and by the same method as the insulating layers 103a_1 and 103a_2 in the semiconductor device 10 shown in Figures 4A to 4C.

[0200] 5A to 5C show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configuration examples shown in FIGS. 4A to 4C . Fig. 5A is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 5B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 5A , and Fig. 5C is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 5A .

[0201] The semiconductor device 10 shown in FIGS. 5A to 5C differs from the semiconductor device 10 shown in FIGS. 4A to 4C in the configuration of the transistor 43.

[0202] A transistor 43 included in the semiconductor device 10 illustrated in FIGS. 5A to 5C includes a conductive layer 111c, a conductive layer 111a, a semiconductor layer 113c, an insulating layer 105c, and a conductive layer 115c.

[0203] A part of the conductive layer 111c functions as one of the source electrode and the drain electrode of the transistor 43, and functions as a wiring 33R. A part of the conductive layer 111a functions as the other of the source electrode and the drain electrode of the transistor 43. A part of the insulating layer 105c functions as a gate insulating layer of the transistor 43. A part of the conductive layer 115c functions as a gate electrode of the transistor 43, and functions as a wiring 31R. The conductive layer 111c functioning as the wiring 33R has a region extending in the Y direction. The conductive layer 115c functioning as the wiring 31R has a region extending in the X direction.

[0204] A conductive layer 111c is provided on the insulating layer 101. An insulating layer 105c is provided on the insulating layer 101 and the conductive layer 111c. A conductive layer 115c is provided on the insulating layer 105c. An insulating layer 103c is provided on the insulating layer 105c and the conductive layer 115c. As shown in FIGS. 5A to 5C , the semiconductor layer 113c is provided in a columnar shape on the conductive layer 111c. Note that although FIG. 5A shows an example in which the shape of the semiconductor layer 113c is circular in a plan view, this is not limiting. The top surface shape of the semiconductor layer 113c may be, for example, an ellipse or a polygon such as a rectangle.

[0205] The insulating layer 105c functioning as a gate insulating layer of the transistor 43 has a region in contact with the side surfaces of the semiconductor layer 113c, the side surfaces and bottom surfaces of the conductive layer 115c, the top surface and side surfaces of the conductive layer 111c, the side surfaces and bottom surfaces of the insulating layer 103c, and the top surface of the insulating layer 101. The semiconductor layer 113c and the conductive layer 115c are provided opposite to each other with the insulating layer 105c interposed therebetween in a cross-sectional view.

[0206] The conductive layer 115c, which functions as the gate electrode of the transistor 43, is provided to cover the pillar-shaped semiconductor layer 113c with the insulating layer 105c interposed therebetween. With this configuration, a gate electric field (an electric field from the conductive layer 115c) can be applied to the semiconductor layer 113c from any direction in the XY plane.

[0207] The insulating layer 103c is provided to have a region in contact with the side surface of the conductive layer 115c, the top surface of the conductive layer 115c, the top surface of the insulating layer 105c, and the side surface of the insulating layer 105c.

[0208] The upper surface of the semiconductor layer 113c, the uppermost surface of the insulating layer 105c, and the upper surface of the insulating layer 103c are at approximately the same height relative to the substrate surface.

[0209] The conductive layer 111a functioning as the other of the source electrode and the drain electrode of the transistor 43 is provided in contact with the top surface of the semiconductor layer 113c, the top surface of the insulating layer 105c, and the top surface of the insulating layer 103c, each of which is relative to the substrate surface. The conductive layer 111a is provided to have a region overlapping with the conductive layer 111c functioning as one of the source electrode and the drain electrode of the transistor 43.

[0210] It is preferable that the end of the conductive layer 111a be substantially aligned with the end of the semiconductor layer 113c or be located outside the end of the semiconductor layer 113c, thereby increasing the contact area between the conductive layer 111a and the semiconductor layer 113c and reducing the contact resistance between the conductive layer 111a and the semiconductor layer 113c.

[0211] 4A to 4C , the transistor 43 shown in Figures 5A to 5C has a source electrode, a drain electrode, and a gate electrode that are provided at different heights and overlap with each other with respect to the substrate surface. The gate electrode is sandwiched between the source electrode and the drain electrode. Therefore, in the transistor 43, the channel length direction corresponds to the direction along the side surface of the insulating layer 105c in a cross-sectional view, and a drain current flows in this direction.

[0212] When the transistor 43 has the above-described structure, the channel length of the transistor 43 can be controlled by adjusting the film thickness of the semiconductor layer 113c located between the source electrode and the drain electrode in a cross-sectional view. Therefore, the channel length of the transistor 43 can be made smaller than the limit resolution of the exposure device. Furthermore, the area occupied by the transistor in a plan view can be made smaller than that of a transistor having a structure in which the source electrode and the drain electrode are provided on the same plane.

[0213] 5A to 5C , the gate electrode (conductive layer 115c) is provided to surround the semiconductor layer 113c in a plan view. Therefore, the entire region of the semiconductor layer 113c that faces the conductive layer 115c with the insulating layer 105c interposed therebetween can be used as the channel formation region of the transistor 43. In this case, the channel width direction of the transistor 43 is parallel to the XY plane, and the channel width of the transistor 43 corresponds to the perimeter of the semiconductor layer 113c in FIG. 5A .

[0214] 4A to 4C has a structure in which the semiconductor layer 113c is provided so as to cover an opening in an insulating layer, whereas the transistor 43 shown in Figures 5A to 5C has a structure in which the semiconductor layer 113c is provided in a pillar shape. Therefore, the transistor 43 having the structure shown in Figures 5A to 5C can be said to be a FIN transistor. As described above, the transistor 43 included in the semiconductor device 10 of one embodiment of the present invention can have various structures.

[0215] In the semiconductor device 10 shown in Figures 5A to 5C, for differences other than those described above (such as the configurations of the transistors 41 and 42), the contents described for the semiconductor device 10 shown in Figures 4A to 4C can be referred to.

[0216] 6A is an enlarged view of the transistor 42 shown in FIG. 4C and its vicinity. FIG. 6B is a cross-sectional view of the transistor shown in FIG. 6A taken along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112. The structures shown in FIGS. 6A and 6B can be applied not only to the transistor 42 but also to the transistor 41.

[0217] As shown in FIG. 6A, the semiconductor layer 113 has a region 113i, and regions 113na and 113nb that are provided so as to sandwich the region 113i.

[0218] The region 113na is in contact with the conductive layer 111 of the semiconductor layer 113. At least a part of the region 113na functions as one of the source region and the drain region of the transistor. The region 113nb is in contact with the conductive layer 112 of the semiconductor layer 113. At least a part of the region 113nb functions as the other of the source region and the drain region of the transistor.

[0219] The region 113i is a region between the region 113na and the region 113nb in the semiconductor layer 113. At least a part of the region 113i functions as a channel formation region of the transistor. That is, the channel formation region of the transistor can be said to be located in a region of the semiconductor layer 113 that faces the conductive layer 115 between the conductive layer 111 and the conductive layer 112, with the insulating layer 105 interposed therebetween.

[0220] The transistor 42 also includes a conductive layer 117 that functions as a back gate electrode. Therefore, a region of the semiconductor layer 113 that faces the conductive layer 117 with the insulating layer 116 interposed therebetween can also function as a back channel formation region.

[0221] The channel length of a transistor is the distance between the source region and the drain region. In other words, it can be said that the channel length of a transistor is determined by the thickness of the insulating layer 103 and the like on the conductive layer 111. In Figure 6A, the channel length L of the transistor is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L corresponds to the distance along the insulating layer 116 between the edge of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the edge of the region where the semiconductor layer 113 and the conductive layer 112 contact each other.

[0222] In a planar transistor, for example, the channel length is set by the exposure limit of photolithography. However, in the present invention, the channel length can be set by the film thickness of the insulating layer 103 or the like. Therefore, the channel length of the transistor can be made into an extremely fine structure (e.g., 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 5 nm to 10 nm) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor, thereby improving frequency characteristics. Therefore, the read speed and write speed of the memory cell can be improved, and a semiconductor device with high operating speed can be provided.

[0223] As will be described in detail later, OS transistors have higher resistance to short-channel effects than Si transistors. As described above, for example, transistors with the structures shown in FIGS. 6A and 6B can have shorter channel lengths than planar transistors. For these reasons, when a transistor has the structure shown in FIGS. 6A and 6B, for example, a metal oxide is preferably used for the semiconductor layer 113. Note that the semiconductor layer 113 may be made of a material other than a metal oxide, such as silicon.

[0224] Furthermore, as described above, a channel formation region and one of a source region and a drain region can be formed in the opening 121. This allows the area occupied by the transistor to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. This allows for a high integration of the semiconductor device, thereby increasing the storage capacity per unit area.

[0225] 6B , in the XY plane including the channel formation region of the semiconductor layer 113, the insulating layer 116, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged concentrically. As described above, in the semiconductor layer 113, a region facing the conductive layer 115 across the insulating layer 105 can function as a channel formation region of the transistor. In addition, in the semiconductor layer 113, a region facing the conductive layer 117 across the insulating layer 116 can function as a back channel formation region of the transistor. Therefore, the inner periphery length in a planar view of the semiconductor layer 113 that can function as a channel formation region of the transistor can be defined as the channel width of the transistor. In addition, the outer periphery length in a planar view of the semiconductor layer 113 that can function as a back channel formation region of the transistor can also be defined as the channel width of the transistor. In addition, because the channel formation region and the back channel formation region of the transistor exist within the opening 121, the contour length of the opening 121 in a planar view can also be defined as the channel width of the transistor. 6B, the last definition above is applied to the channel width W of the transistor, which is indicated by a dashed line with a double-headed arrow. Also, in FIGS. 6A and 6B, the maximum width D of the opening 121 is indicated by a dashed line with a double-headed arrow. By increasing the maximum width D of the opening 121, the channel width per unit area can be increased, and the on-current can be increased.

[0226] The maximum width D of the opening 121 is preferably, for example, 5 nm to 100 nm, 10 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm. When the opening 121 is circular in plan view, the maximum width D of the opening 121 corresponds to the diameter of the opening 121, and the channel width W can be calculated as "D × π".

[0227] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor is preferably smaller than at least the channel width W of the transistor. The channel length L of the transistor of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0228] Note that by providing the insulating layer 116, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 concentrically, the distance between the conductive layer 115 and the semiconductor layer 113 and the distance between the conductive layer 117 and the semiconductor layer 113 become approximately uniform. Therefore, a gate electric field (an electric field from the gate electrode and an electric field from the back gate electrode) can be applied to the semiconductor layer 113 approximately uniformly.

[0229] The sidewalls of the opening 121 (the side surfaces of the insulating layer 103, the conductive layer 117, and the conductive layer 112 in the opening 121) are preferably perpendicular to the top surface of the conductive layer 111. This structure allows miniaturization or high integration of the semiconductor device. The sidewalls of the opening 121 may be tapered.

[0230] The components of the transistor included in the memory cell will be described below.

[0231] [Transistor Components] A metal oxide described in the section [Metal Oxide] below can be used as a single layer or a stacked layer for the semiconductor layer 113. Furthermore, a material such as silicon described in the section [Other Semiconductor Materials] below can be used as a single layer or a stacked layer for the semiconductor layer 113.

[0232] When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:3:4 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:2 [atomic ratio] or a composition thereabout, or In:M:Zn = 4:2:3 [atomic ratio] or a composition thereabout can be used as the semiconductor layer 113. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0233] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0234] For example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the metal oxide used in the semiconductor layer 113. Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0235] The metal oxide can be preferably formed by atomic layer deposition (ALD).

[0236] Alternatively, the metal oxide may be formed by sputtering or chemical vapor deposition (CVD).

[0237] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0238] The metal oxide used for the semiconductor layer 113 preferably has crystallinity. Examples of crystalline oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductor, single-crystalline oxide semiconductor, and the like. For the semiconductor layer 113, it is preferable to use a CAAC-OS or an nc-OS, and it is particularly preferable to use a CAAC-OS.

[0239] The CAAC-OS preferably has multiple layered crystalline regions, and the c-axes of the layers are oriented in the normal direction to the surface where the layered crystalline regions are formed. For example, the semiconductor layer 113 preferably has layered crystals that are substantially parallel to the direction along the sidewall of the opening 121, particularly to the side surface of the insulating layer 116. With this structure, the layered crystals of the semiconductor layer 113 are formed substantially parallel to the channel length direction of the transistor, which enables the on-state current of the transistor to be increased.

[0240] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0241] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0242] Furthermore, by using a crystalline oxide such as CAAC-OS for the semiconductor layer 113, it is possible to suppress extraction of oxygen from the semiconductor layer 113 by the source electrode or the drain electrode. Thus, even when heat treatment is performed, oxygen can be suppressed from being extracted from the semiconductor layer 113, and the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0243] The crystallinity of the semiconductor layer 113 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0244] The thickness of the semiconductor layer 113 is preferably, for example, 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 12 nm, or 5 nm to 10 nm.

[0245] 4B, 4C, and 6A show the semiconductor layer 113 as a single layer, but the present invention is not limited to this. The semiconductor layer 113 may have a stacked structure of multiple oxide layers with different chemical compositions. For example, the semiconductor layer 113 may have a structure in which multiple types of oxides selected from the above metal oxides are appropriately stacked.

[0246] The insulating layer 105 functioning as a gate insulating layer and the insulating layer 116 functioning as a back-gate insulating layer can be formed using a single layer or a stack of insulators described in the section [Insulators] below. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 105 and the insulating layer 116. Silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0247] Furthermore, a material having a high relative dielectric constant, so-called a high-k material, which will be described later in the section [Insulator], may be used for the insulating layer 105 and the insulating layer 116. For example, hafnium oxide or aluminum oxide may be used.

[0248] The thickness of the insulating layer 105 and the insulating layer 116 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and further preferably 0.5 nm to 10 nm. The insulating layer 105 and the insulating layer 116 preferably have a region with the above thickness in at least a part thereof.

[0249] The concentrations of impurities such as water and hydrogen in the insulating layer 105 and the insulating layer 116 are preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0250] 4B, 4C, and 6A, the insulating layer 105 and the insulating layer 116 are each shown as a single layer, but the present invention is not limited to this. The insulating layer 105 and the insulating layer 116 may each have a stacked structure.

[0251] The conductive layer 115 functioning as a gate electrode and the conductive layer 117 functioning as a back gate electrode can be formed using a single layer or a stack of conductors described in the section [Conductor] described later. For example, the conductive layer 115 and the conductive layer 117 can be formed using a conductive material with high conductivity, such as tungsten, aluminum, or copper.

[0252] Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, for the conductive layers 115 and 117. Examples of such a conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride), a conductive material containing oxygen (for example, ruthenium oxide), and the like. This can suppress a decrease in the conductivity of the conductive layers 115 and 117. Furthermore, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used for the conductive layers 115 and 117.

[0253] 4B, 4C, and 6A, the conductive layer 115 and the conductive layer 117 are each shown as a single layer, but the present invention is not limited to this. The conductive layer 115 and the conductive layer 117 may each have a stacked structure.

[0254] The conductive layer 111 can be formed using a single layer or a stacked layer of any of the conductors described in the section [Conductor] below. It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 111. For example, titanium nitride, tantalum nitride, or the like can be used. Alternatively, for example, a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride is in contact with the insulating layer 101, the insulating layer 103, the insulating layer 131, or the like, and tantalum nitride is in contact with the semiconductor layer 113. With such a structure, excessive oxidation of the conductive layer 111 by the semiconductor layer 113 can be suppressed. Furthermore, when an oxide insulator is used for the insulating layer 101, the insulating layer 103, the insulating layer 131, or the like, the insulating layer can suppress excessive oxidation of the conductive layer 111. Alternatively, for example, a structure in which tungsten is stacked on titanium nitride may be used for the conductive layer 111.

[0255] Furthermore, since the conductive layer 111 has a region in contact with the semiconductor layer 113, it is preferable to use a conductive material containing oxygen described in the section of [Conductor] described later. By using a conductive material containing oxygen for the conductive layer 111, the conductive layer 111 can maintain conductivity even when it absorbs oxygen. For example, indium tin oxide (also referred to as ITO), indium tin oxide doped with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used as a single layer or a stacked layer.

[0256] 4B, 4C, and 6A show a configuration in which the upper surface of the conductive layer 111 is flat, but the present invention is not limited to this. For example, a configuration in which a recess overlapping the opening 121 is formed on the upper surface of the conductive layer 111 may be used. By forming at least a portion of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 so as to fill the recess, it is possible to easily apply the gate electric field of the conductive layer 115 up to the vicinity of the conductive layer 111 of the semiconductor layer 113.

[0257] A single layer or a stack of conductors described in the section [Conductor] below can be used as the conductive layer 112. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, can be used as the conductive layer 112.

[0258] Like the conductive layers 111, 115, and 117, the conductive layer 112 is preferably formed using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, tantalum nitride, or the like can be used. With such a structure, excessive oxidation of the conductive layer 112 by the semiconductor layer 113 can be suppressed. Similarly to the conductive layers 115 and 117, the conductive layer 112 may be formed using a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

[0259] Alternatively, for example, a structure in which tungsten is stacked on titanium nitride may be used. By stacking tungsten on titanium nitride in this manner, the conductivity of the conductive layer 112 can be improved.

[0260] Furthermore, when the conductive layer 112 has a structure in which a first conductive layer and a second conductive layer are stacked in this order, for example, the first conductive layer may be formed using a conductive material with high conductivity, and the second conductive layer may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen for the second conductive layer whose area in contact with the insulating layer 105 is larger than that of the first conductive layer, it is possible to prevent oxygen in the insulating layer 105 from diffusing into the first conductive layer of the conductive layer 112. For example, tungsten may be used for the first conductive layer of the conductive layer 112, and indium tin oxide to which silicon is added may be used for the second conductive layer of the conductive layer 112.

[0261] When the semiconductor layer 113 and the conductive layer 111 come into contact with each other, a metal compound or oxygen vacancy is formed in the semiconductor layer 113, and the resistance of a region 113na of the semiconductor layer 113 is reduced. When the semiconductor layer 113 comes into contact with the conductive layer 111, the resistance of the semiconductor layer 113 and the conductive layer 111 is reduced, thereby reducing the contact resistance between the semiconductor layer 113 and the conductive layer 111. Similarly, when the semiconductor layer 113 and the conductive layer 112 come into contact with each other, the resistance of a region 113nb of the semiconductor layer 113 is reduced. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

[0262] The insulating layer 101, the insulating layer 103, and the insulating layer 131, which function as interlayer insulating layers, preferably have a low dielectric constant. By using a material with a low dielectric constant as an interlayer insulating layer, parasitic capacitance occurring between wirings can be reduced. As the insulating layer 101, the insulating layer 103, and the insulating layer 131, a single layer or a stacked layer of insulators containing a material with a low dielectric constant, as described in the section [Insulator] below, can be used. In particular, silicon oxide and silicon oxynitride are preferred because of their thermal stability.

[0263] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layer 101, the insulating layer 103, and the insulating layer 131. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0264] The insulating layer 116 and the insulating layer 103 disposed near the channel formation region of the semiconductor layer 113 preferably contain oxygen that is desorbed by heating (hereinafter, sometimes referred to as excess oxygen). By performing heat treatment on the insulating layer 116 and the insulating layer 103 containing excess oxygen, oxygen is supplied from the insulating layer 116 and the insulating layer 103 to the channel formation region of the semiconductor layer 113, and oxygen vacancies in the semiconductor layer 113 and defects in which hydrogen has entered the oxygen vacancies (hereinafter, referred to as V Ｏ This can stabilize the electrical characteristics of the transistor and improve its reliability.

[0265] Alternatively, the insulating layer 116 and the insulating layer 103 may be formed using an insulator having a function of capturing or fixing hydrogen, as described in the section [Insulator] below. With such a structure, hydrogen can be captured or fixed in the semiconductor layer 113, thereby reducing the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, or the like can be used for the insulating layer 116 and the insulating layer 103.

[0266] 4B, 4C, and 6A, the insulating layer 103 is shown as a single layer, but the present invention is not limited to this. The insulating layer 103 may have a multilayer structure.

[0267] For the insulating layer 107, an insulator having a barrier property against hydrogen, as described in the section [Insulator] below, can be preferably used. This can suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 113 through the insulating layer 105. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 107.

[0268] Furthermore, it is preferable to use an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below, for the insulating layer 107. With such a structure, diffusion of hydrogen from above the insulating layer 107 to the semiconductor layer 113 can be suppressed, and further hydrogen in the semiconductor layer 113 can be captured or fixed to reduce the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used for the insulating layer 107. For example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used for the insulating layer 107.

[0269] 4B, 4C, and 6A illustrate the structure in which the insulating layer 107 is formed on the top surface of the transistor, but the present invention is not limited to this. For example, the insulating layer 107 or an insulating layer having a similar function or material to the insulating layer 107 may be formed on the side and bottom surfaces of the transistor, and the transistor may be surrounded by the insulating layer. Alternatively, the insulating layer 107 may be formed on the top, side, and bottom surfaces of the transistor 43, the transistor 41, and the transistor 42, and the transistor 43, the transistor 41, and the transistor 42 may be surrounded by the insulating layer 107. With this structure, impurities (for example, water, hydrogen, etc.) can be prevented from entering the transistor 43, the transistor 41, and the transistor 42.

[0270] 7A to 7C show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configurations described above. Fig. 7A is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 7B is a cross-sectional view taken along dashed line A1-A2 in Fig. 7A, and Fig. 7C is a cross-sectional view taken along dashed line A3-A4 in Fig. 7A.

[0271] The semiconductor device 10 shown in Figures 7A to 7C differs from the semiconductor device 10 shown in Figures 4A to 4C in that a conductive layer functioning as the other of the source electrode and the drain electrode of the transistor 43 and a conductive layer functioning as one of the source electrode and the drain electrode of the transistor 41 are provided independently, and the two conductive layers are connected by a conductive layer functioning as a plug.

[0272] 7A to 7C , the conductive layer 112c functions as the other of the source electrode and the drain electrode. The conductive layer 112c can be formed using any of the materials that can be used for the conductive layer 111 or the conductive layer 112.

[0273] The conductive layer 112c is provided in contact with top surfaces of the semiconductor layer 113c, the layer 114, the insulating layer 107c, and the insulating layer 103c_3 so as to have a region overlapping with the conductive layer 111c. An insulating layer 103c_4 is provided in a region of the insulating layer 103c_3 that does not overlap with the conductive layer 112c. The top surfaces of the conductive layer 112c and the insulating layer 103c_4 are provided so as to be at approximately the same height with respect to the substrate surface.

[0274] An insulating layer 132 is provided over the conductive layer 112c and the insulating layer 103c_4. An opening is provided in the insulating layer 132 in a region overlapping with the conductive layer 112c, and the conductive layer 118 is provided to fill the opening. The upper surfaces of the conductive layer 118 and the insulating layer 132 are preferably at approximately the same height relative to the substrate surface. The upper surface of the conductive layer 112c is in contact with the lower surface of the conductive layer 118. The upper surface of the conductive layer 118 is in contact with the lower surface of the conductive layer 111a. The insulating layer 103c_4 and the insulating layer 132 each function as an interlayer insulating layer. The insulating layer 103c_4 and the insulating layer 132 can be formed using the same materials as those used for the insulating layer 101, the insulating layer 103, and the insulating layer 131. The conductive layer 118 also functions as a plug that connects the conductive layer 112c that functions as the other of the source and drain electrodes of the transistor 43 and the conductive layer 111a that functions as one of the source and drain electrodes of the transistor 41. For the conductive layer 118, for example, the above-described conductive material with high conductivity that can be used for the conductive layer 115 and the conductive layer 117 can be used. In order to prevent the conductive layer 118 from being oxidized by oxygen contained in the insulating layer 132 or the like, a conductive material that is not easily oxidized and that can be used for the conductive layer 111, the conductive layer 112, the conductive layer 115, and the conductive layer 117 or a conductive material that has a function of suppressing oxygen diffusion may be provided in contact with a side surface of the insulating layer 132, and a conductive material with high conductivity may be provided inside the conductive material.

[0275] In the semiconductor device 10 shown in FIGS. 7A to 7C, the contents described in connection with the semiconductor device 10 shown in FIGS. 4A to 4C can be referred to, except for the differences described above.

[0276] 8A to 8C show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configurations described above. Fig. 8A is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 8B is a cross-sectional view taken along dashed line A1-A2 in Fig. 8A, and Fig. 8C is a cross-sectional view taken along dashed line A3-A4 in Fig. 8A.

[0277] The semiconductor device 10 shown in Figures 8A to 8C differs from the semiconductor device 10 shown in Figures 7A to 7C in that a conductive layer (conductive layer 112c) that functions as the other of the source electrode and the drain electrode of the transistor 43 and a conductive layer (conductive layer 111a) that functions as one of the source electrode and the drain electrode of the transistor 41 are directly connected without a plug (i.e., the upper surface of the conductive layer 112c is in contact with the lower surface of the conductive layer 111a).

[0278] Since the semiconductor device 10 shown in FIGS. 8A to 8C has the above-described configuration, the manufacturing process can be simplified compared to the semiconductor device 10 shown in FIGS. 7A to 7C.

[0279] In the semiconductor device 10 shown in FIGS. 8A to 8C, the contents described in connection with the semiconductor device 10 shown in FIGS. 4A to 4C can be referred to for other points other than the differences described above.

[0280] 9A to 9C show a structural example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the previously described structure. Fig. 9A is a plan view showing a structural example of a part of the semiconductor device 10. Fig. 9B is a cross-sectional view taken along dashed line A1-A2 in Fig. 9A , and Fig. 9C is a cross-sectional view taken along dashed line A3-A4 in Fig. 9A .

[0281] The semiconductor device 10 shown in Figures 9A to 9C differs from the semiconductor device 10 shown in Figures 4A to 4C in that it does not include a conductive layer 111a that functions as the other of the source electrode and the drain electrode of the transistor 43 and one of the source electrode and the drain electrode of the transistor 41.

[0282] In the semiconductor device 10 shown in Figures 9A to 9C, the bottom surface of the semiconductor layer 113a of the transistor 41 (the surface on the transistor 43 side) is in direct contact with a portion of the top surface of the semiconductor layer 113c of the transistor 43 and the top surface of the layer 114.

[0283] Since the semiconductor device 10 shown in FIGS. 9A to 9C has the above-described configuration, the manufacturing process can be simplified compared to the semiconductor device 10 shown in FIGS. 4A to 4C.

[0284] In the semiconductor device 10 shown in FIGS. 9A to 9C, the contents described in connection with the semiconductor device 10 shown in FIGS. 4A to 4C can be referred to for the differences other than those described above.

[0285] 10A to 10C show a structural example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the previously described structure. Fig. 10A is a plan view showing a structural example of a part of the semiconductor device 10. Fig. 10B is a cross-sectional view taken along dashed line A1-A2 in Fig. 10A , and Fig. 10C is a cross-sectional view taken along dashed line A3-A4 in Fig. 10A .

[0286] The semiconductor device 10 shown in Figures 10A to 10C differs from the semiconductor device 10 shown in Figures 9A to 9C in that the semiconductor layer 113a of the transistor 41 is formed so as to fill the recess on the semiconductor layer 113c of the transistor 43.

[0287] The semiconductor device 10 shown in Figures 10A to 10C has a configuration in which a semiconductor layer 113a of the transistor 41 is provided in the location where the layer 114 of the transistor 43 of the semiconductor device 10 shown in Figures 9A to 9C was provided.

[0288] Since the semiconductor device 10 shown in FIGS. 10A to 10C has the above-described configuration, the manufacturing process can be simplified compared to the semiconductor device 10 shown in FIGS. 9A to 9C.

[0289] In the semiconductor device 10 shown in FIGS. 10A to 10C, the contents described in connection with the semiconductor device 10 shown in FIGS. 4A to 4C can be referred to for other points other than the differences described above.

[0290] 11A , 13A , and 13B show a structural example of a semiconductor device 10 of one embodiment of the present invention. Fig. 11A is a plan view showing a structural example of a part of the semiconductor device 10. Fig. 13A is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 11A , and Fig. 13B is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 11A .

[0291] 11A, 13A, and 13B includes a capacitor 51 in addition to the configuration of the semiconductor device 10 shown in FIGS. 4A to 4C. The capacitor 51 is provided overlapping the transistor 41, and the transistor 42 is provided overlapping the capacitor 51.

[0292] The capacitor 51 includes a conductive layer 141 , a conductive layer 143 , and an insulating layer 135 .

[0293] The conductive layer 143 functions as one electrode of the capacitor 51. The conductive layer 141 functions as the other electrode of the capacitor 51 and also functions as the wiring 36. The insulating layer 135 functions as a dielectric layer of the capacitor 51. The conductive layer 141, which functions as the wiring 36, has a region extending in the X direction.

[0294] The conductive layer 141 has an opening 123, and an insulating layer 135 and a conductive layer 143 are provided inside the opening 123. Specifically, the insulating layer 135 is provided inside the opening 123 so as to cover the side surface of the conductive layer 141, and the conductive layer 143 is provided inside the insulating layer 135. As a result, the conductive layer 141 is provided so as to cover at least a part of the side surface of the conductive layer 143 via the insulating layer 135. Inside the opening 123, the insulating layer 135 has, for example, a region in contact with the side surface of the conductive layer 141 and a region in contact with the side surface of the conductive layer 143.

[0295] An insulating layer 133 is provided over the conductive layer 141. The conductive layer 141 and the insulating layer 133 can have the same shape in a plan view, and both have openings 123. For example, after a conductive film to be the conductive layer 141 and an insulating film to be the insulating layer 133 are formed in this order, a pattern is formed by photolithography, and the insulating film and the conductive film are processed by etching based on the pattern, whereby the insulating layer 133 and the conductive layer 141 having the openings 123 can be formed.

[0296] FIG. 11A shows an example in which the shape of the opening 123 is quadrangular in plan view. Although FIG. 11A shows the shape of the opening 123 as a square in plan view, the shape of the opening 123 is not limited thereto and may be, for example, a rectangle, a rhombus, or a parallelogram in plan view. Furthermore, the shape of the opening 123 may be, for example, a triangle or a polygon with pentagons or more sides in plan view. Furthermore, in the example shown in FIG. 11A , the top surface shape of the conductive layer 143 is quadrangular, similar to the opening 123, but the conductive layer 143 may have the same shape as the top surface shape that the opening 123 can have. The top surface shapes of the opening 123 and the conductive layer 143 may be different.

[0297] An insulating layer 135 is provided over the insulating layer 133. Specifically, the insulating layer 135 is provided so as to cover the top surface and side surfaces of the insulating layer 133, the side surfaces of the conductive layer 141, and the top surface of the insulating layer 131. An insulating layer 137 is provided over the insulating layer 135.

[0298] An opening 125 is provided in the insulating layer 107a, the insulating layer 131, the insulating layer 135, and the insulating layer 137. The opening 125 is provided to have a region overlapping with the opening 123. A conductive layer 143 is provided inside the opening 125. By providing the conductive layer 143 inside the opening 125 that reaches the conductive layer 115a, for example, the top surface of the conductive layer 115a can be in contact with the bottom surface of the conductive layer 143. This allows the conductive layer 115a, which functions as the gate electrode of the transistor 41, to be connected to the conductive layer 143, which functions as one electrode of the capacitor 51.

[0299] If the insulating layer 133 is not provided on the conductive layer 141, a region where the insulating layer 135 is thin may be formed between the conductive layer 141 and the conductive layer 143 during the process of forming the opening 125. That is, a region where the distance between the conductive layer 141 and the conductive layer 143 is short may be formed. In this case, the conductive layer 141 and the conductive layer 143 may be short-circuited, for example. Therefore, by providing the insulating layer 133 on the conductive layer 141, it is possible to prevent the formation of a region where the distance between the conductive layer 141 and the conductive layer 143 is short. This improves the reliability of the memory cell 21, thereby providing a highly reliable semiconductor device. Furthermore, it is possible to improve the manufacturing yield of the semiconductor device and provide a low-cost semiconductor device. Note that, for example, if a short circuit between the conductive layer 141 and the conductive layer 143 does not occur, the insulating layer 133 does not need to be provided. In this case, the manufacturing process of the semiconductor device can be simplified.

[0300] The height of the top surface of the conductive layer 143 and the height of the top surface of the insulating layer 137 relative to the substrate surface are approximately the same. A conductive layer 111b functioning as one of a source electrode and a drain electrode of the transistor 42 is provided over the conductive layer 143 so as to have a region overlapping with the conductive layer 143.

[0301] The conductive layer 111b has a region in contact with the conductive layer 143. For example, the bottom surface of the conductive layer 111b has a region in contact with the top surface of the conductive layer 143. This allows the conductive layer 111b, which functions as one of the source and drain electrodes of the transistor 42, to be connected to the conductive layer 143, which functions as one electrode of the capacitor 51. As described above, the conductive layer 143 is connected to the conductive layer 115a, which functions as the gate electrode of the transistor 41. As described above, the gate electrode of the transistor 41, one of the source and drain electrodes of the transistor 42, and one electrode of the capacitor 51 can be connected to one another.

[0302] The components of the capacitance of a memory cell will be described below.

[0303] [Capacitor Components] The conductive layers 141 and 143 can be formed using a single layer or a stack of conductors described in the section [Conductor] below. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, can be used for the conductive layers 141 and 143. By using such a conductive material with high conductivity, the conductivity of the conductive layers 141 and 143 can be improved.

[0304] For the conductive layers 141 and 143, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion may be used, either as a single layer or as a stacked layer. For example, titanium nitride, indium tin oxide to which silicon is added, or the like may be used. Alternatively, for example, a structure in which titanium nitride is stacked over tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked over a first titanium nitride and a second titanium nitride is stacked over the tungsten may be used. With such a structure, when an oxide insulator is used for the insulating layer 135, the insulating layer 135 can suppress oxidation of the conductive layers 141 and 143. When an oxide insulator is used for the insulating layer 133, the insulating layer 133 can suppress oxidation of the conductive layer 141. For the conductive layers 141 and 143, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0305] It is preferable to use a material with a high relative dielectric constant, so-called a high-k material, as described in the section [Insulator] below, for the insulating layer 135. By using a high-k material for the insulating layer 135, the insulating layer 135 can be made thick enough to suppress leakage current and the capacitance of the capacitor 51 can be sufficiently ensured.

[0306] Furthermore, the insulating layer 135 is preferably formed by laminating insulators made of high-k materials, and preferably by using a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 135 can be formed by laminating an insulating film in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, the insulating film can be formed by laminating an insulating film in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, the insulating film can be formed by laminating an insulating film in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By laminating an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 51 can be suppressed.

[0307] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 135. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Examples of materials that may have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate, for example, the ratio of the number of hafnium atoms to the number of element J1 is 1:1 or close thereto. Examples of materials that may have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate, for example, the ratio of the number of zirconium atoms to the number of element J2 is 1:1 or close thereto. Furthermore, lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0308] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0309] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0310] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0311] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer 135 can have a layered structure made of multiple materials selected from the materials listed above. Incidentally, for example, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. Therefore, in this specification, a ferroelectric is not only used to refer to a material that exhibits ferroelectricity, but is also referred to as a material capable of exhibiting ferroelectricity or a material that imparts ferroelectricity.

[0312] Metal oxides containing one or both of hafnium and zirconium are preferred because they can exhibit ferroelectricity even in thin films of only a few nanometers. The thickness of the insulating layer 135 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, a thickness of 8 nm to 12 nm is preferred. By using a ferroelectric layer that can be thinned, the capacitor 51 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that, in this specification, a layer of a material that can exhibit ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.

[0313] Furthermore, a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a very small area. ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 nm, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 51 can be reduced.

[0314] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor (hereinafter, sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is also called an FeRAM (Ferroelectric Random Access Memory) or a ferroelectric memory. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor 51, the semiconductor device described in this embodiment functions as a ferroelectric memory.

[0315] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer 135 to manifest ferroelectricity, the insulating layer 135 must contain crystals. In particular, the insulating layer 135 preferably contains crystals having an orthorhombic crystal structure, since this manifests ferroelectricity. The crystal structure of the crystals contained in the insulating layer 135 may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer 135 may also have an amorphous structure. In this case, the insulating layer 135 may have a composite structure having an amorphous structure and a crystalline structure.

[0316] The insulating layer 133 preferably has a low dielectric constant, which can reduce the parasitic capacitance generated between wirings. As the insulating layer 133, a single layer or a stack of insulators containing a material with a low dielectric constant, as described in the section [Insulator] below, can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0317] 13A and 13B, the insulating layer 133 is shown as a single layer, but the present invention is not limited to this. The insulating layer 133 may have a multilayer structure.

[0318] 68A and 68B show a structural example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the structural examples shown in Fig. 11A, 13A, and 13B. Fig. 68A is a cross-sectional view of the semiconductor device 10 of this structural example corresponding to the dashed-dotted line A1-A2 shown in Fig. 11A, and Fig. 68B is a cross-sectional view of the semiconductor device 10 of this structural example corresponding to the dashed-dotted line A3-A4 shown in Fig. 11A.

[0319] 68A and 68B differs from the semiconductor device 10 shown in FIGS. 11A , 13A , and 13B in that the transistor 42 does not have a back gate electrode and a back gate insulating layer. Since the transistor 42 does not have a back gate electrode and a back gate insulating layer, the number of manufacturing steps can be reduced compared to the semiconductor device 10 shown in FIGS. 11A , 13A , and 13B . The insulating layer 103b in the semiconductor device 10 shown in FIGS. 68A and 68B can be formed using the same material and by the same method as the insulating layers 103b_1 and 103b_2 in the semiconductor device 10 shown in FIGS. 13A and 13B .

[0320] 69A and 69B show a structural example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the structural examples shown in Fig. 11A, 13A, and 13B. Fig. 69A is a cross-sectional view of the semiconductor device 10 of this structural example corresponding to the dashed-dotted line A1-A2 shown in Fig. 11A, and Fig. 69B is a cross-sectional view of the semiconductor device 10 of this structural example corresponding to the dashed-dotted line A3-A4 shown in Fig. 11A.

[0321] 69A and 69B differs from the semiconductor device 10 shown in FIGS. 11A , 13A , and 13B in that the transistor 41 does not have a back gate electrode and a back gate insulating layer. Since the transistor 41 does not have a back gate electrode and a back gate insulating layer, the number of manufacturing steps can be reduced compared to the semiconductor device 10 shown in FIGS. 11A , 13A , and 13B . The insulating layer 103 a in the semiconductor device 10 shown in FIGS. 69A and 69B can be formed using the same material and by the same method as the insulating layers 103 a_1 and 103 a_2 in the semiconductor device 10 shown in FIGS. 13A and 13B .

[0322] 11B, 14A, and 14B show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configuration described above. Fig. 11B is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 14A is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 11B, and Fig. 14B is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 11B.

[0323] The semiconductor device 10 shown in Figures 11B, 14A, and 14B has a configuration that combines the semiconductor device 10 shown in Figures 7A to 7C with the semiconductor device 10 shown in Figures 11A, 13A, and 13B. As a result, the semiconductor device 10 shown in Figures 11B, 14A, and 14B can enjoy both the effects obtained by the semiconductor device 10 shown in Figures 7A to 7C and the effects obtained by the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0324] Specifically, the semiconductor device 10 shown in Figures 7A to 7C has a configuration in which a capacitor 51 that the semiconductor device 10 shown in Figures 11A, 13A, and 13B has is provided between the transistor 41 and the transistor 42, in contrast to the configuration of the transistor 43, the transistor 41, and the transistor 42 that the semiconductor device 10 has shown in Figures 11A, 13A, and 13B.

[0325] In the semiconductor device 10 shown in Figures 11B, 14A, and 14B, for points other than those mentioned above, reference can be made to the contents described for the semiconductor device 10 shown in Figures 7A to 7C and the contents described for the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0326] 11C , 15A , and 15B show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configurations described above. Fig. 11C is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 15A is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 11C , and Fig. 15B is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 11C .

[0327] The semiconductor device 10 shown in Figures 11C, 15A, and 15B has a configuration that combines the semiconductor device 10 shown in Figures 8A to 8C with the semiconductor device 10 shown in Figures 11A, 13A, and 13B. As a result, the semiconductor device 10 shown in Figures 11C, 15A, and 15B can enjoy both the effects obtained by the semiconductor device 10 shown in Figures 8A to 8C and the effects obtained by the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0328] Specifically, the semiconductor device 10 shown in Figures 8A to 8C has a configuration in which a capacitor 51 that the semiconductor device 10 shown in Figures 11A, 13A, and 13B has is provided between the transistor 41 and the transistor 42, in contrast to the configuration of the transistor 43, the transistor 41, and the transistor 42 that the semiconductor device 10 has shown in Figures 11A, 13A, and 13B.

[0329] In the semiconductor device 10 shown in Figures 11C, 15A, and 15B, for the points other than those mentioned above, reference can be made to the contents described for the semiconductor device 10 shown in Figures 8A to 8C and the contents described for the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0330] 12A , 16A , and 16B show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configurations described above. Fig. 12A is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 16A is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 12A , and Fig. 16B is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 12A .

[0331] The semiconductor device 10 shown in Figures 12A, 16A, and 16B has a configuration that combines the semiconductor device 10 shown in Figures 9A to 9C and the semiconductor device 10 shown in Figures 11A, 13A, and 13B. As a result, the semiconductor device 10 shown in Figures 12A, 16A, and 16B can enjoy both the effects obtained by the semiconductor device 10 shown in Figures 9A to 9C and the effects obtained by the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0332] Specifically, the semiconductor device 10 shown in Figures 9A to 9C has a configuration in which a capacitor 51 that the semiconductor device 10 shown in Figures 11A, 13A, and 13B has is provided between the transistor 41 and the transistor 42, in contrast to the configuration of the transistor 43, the transistor 41, and the transistor 42 that the semiconductor device 10 has shown in Figures 11A, 13A, and 13B.

[0333] In the semiconductor device 10 shown in Figures 12A, 16A, and 16B, for the points other than those mentioned above, reference can be made to the contents described for the semiconductor device 10 shown in Figures 9A to 9C and the contents described for the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0334] 12B , 17A, and 17B show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configuration described above. Fig. 12B is a plan view showing a configuration example of a part of the semiconductor device 10. Fig. 17A is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 12B , and Fig. 17B is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 12B .

[0335] The semiconductor device 10 shown in Figures 12B, 17A, and 17B has a configuration that combines the semiconductor device 10 shown in Figures 10A to 10C and the semiconductor device 10 shown in Figures 11A, 13A, and 13B. As a result, the semiconductor device 10 shown in Figures 12B, 17A, and 17B can enjoy both the effects obtained by the semiconductor device 10 shown in Figures 10A to 10C and the effects obtained by the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0336] Specifically, the semiconductor device 10 shown in FIGS. 10A to 10C has a configuration in which a capacitor 51 that the semiconductor device 10 shown in FIGS. 11A, 13A, and 13B has is provided between the transistor 41 and the transistor 42, in contrast to the configuration of the transistor 43, the transistor 41, and the transistor 42 that the semiconductor device 10 has shown in FIGS.

[0337] In the semiconductor device 10 shown in Figures 12B, 17A, and 17B, for points other than those mentioned above, reference can be made to the contents described for the semiconductor device 10 shown in Figures 10A to 10C and the contents described for the semiconductor device 10 shown in Figures 11A, 13A, and 13B.

[0338] 12C , 18A , and 18B show a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which is different from the configurations described above. Fig. 12C is a plan view showing a configuration example of a portion of the semiconductor device 10. Fig. 18A is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 12C , and Fig. 18B is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 12C .

[0339] The semiconductor device 10 shown in Figures 12C, 18A, and 18B differs from the semiconductor device 10 shown in Figures 11A, 13A, and 13B in that a conductive layer 112a functioning as the other of the source electrode or drain electrode of the transistor 41 is connected to a conductive layer 141 functioning as the other electrode of the capacitor 51.

[0340] 12C, 18A, and 18B, the upper surface of conductive layer 115a, the uppermost surface of insulating layer 105a, the uppermost surface of semiconductor layer 113a, the upper surface of conductive layer 112a, the uppermost surface of insulating layer 107a, and the upper surface of insulating layer 131 are all at approximately the same height relative to the substrate surface. Meanwhile, the lower surface of conductive layer 143, the lowermost surface of insulating layer 135, and the lower surface of conductive layer 141 are all at approximately the same height relative to the substrate surface. The upper surface of conductive layer 112a and the lower surface of conductive layer 141 are provided so as to have a contact area.

[0341] 12C , 18A, and 18B has the above-described structure, the same potential can be supplied to the conductive layer 112a and the conductive layer 141. As described above, the conductive layer 112a functions as the wiring 35, and the conductive layer 141 functions as the wiring 36. Therefore, by configuring the semiconductor device 10 as described above, the number of wirings can be reduced, and the manufacturing process can be simplified.

[0342] In the semiconductor device 10 shown in Figures 12C, 18A, and 18B, other than the differences described above, the contents described for the semiconductor device 10 shown in Figures 11A, 13A, and 13B can be referred to.

[0343] <Configuration Example 17 of Semiconductor Device> A configuration example of a plurality of memory cells 21 will be described below. Specifically, a configuration example of four rows and four columns of memory cells 21 will be described using a plan view. Note that in the plan view, some reference numerals may be omitted.

[0344] Fig. 20A is a plan view showing an example of a configuration in which the memory cells 21 shown in Fig. 4A are arranged in a matrix. Fig. 20B is a plan view in which the transistors 42 and 43 are omitted from the configuration shown in Fig. 20A.

[0345] As shown in FIGS. 20A and 20B , the conductive layer 111c functioning as the wiring 33R and the conductive layer 112a functioning as the wiring 35 each have a region extending in the Y direction and are shared by the memory cells 21 arranged in the Y direction. That is, the memory cells 21 in the same column share the same conductive layer 111c and conductive layer 112a. This prevents current from flowing from multiple wirings 33R functioning as read bit lines to a single wiring 35 functioning as a power supply line when reading data stored in the memory cells 21. This reduces the current flowing through the wiring 35. According to Ohm's law, the voltage drop ΔV of a wiring is the product of the wiring resistance R and the current I (ΔV = R × I). Therefore, reducing the current flowing through the wiring 35 can prevent a drop in the potential supplied as a power supply potential, particularly in memory cells 21 that are located a long distance from the power supply circuit 15 shown in FIG. 1A . This can prevent, for example, data stored in the memory cells 21 from being incorrectly read. Therefore, it is possible to provide a memory cell and a semiconductor device with high read accuracy.

[0346] 20A , the conductive layers 115b functioning as interconnects 31W each have an area extending in the X direction and are shared by the memory cells 21 arranged in the X direction. That is, the memory cells 21 in the same row share the same conductive layer 115b. The conductive layers 112b functioning as interconnects 33W each have an area extending in the Y direction and are shared by the memory cells 21 arranged in the Y direction. That is, the memory cells 21 in the same column share the same conductive layer 112b.

[0347] 21 and 22 show cross-sectional views of the memory cell 21 arranged in four rows and four columns, the plan view of which is shown in FIG. 20A . FIG. 21 is a cross-sectional view taken along the XZ plane, and FIG. 22 is a cross-sectional view taken along the YZ plane. As shown in the plan view of FIG. 20A and the cross-sectional views of FIGS. 21 and 22 , a semiconductor device according to one embodiment of the present invention can have a configuration in which memory cells 21, each of which has a stack of three transistors whose source electrodes and drain electrodes are provided at different heights relative to a substrate surface, are densely arranged in the XY plane. Therefore, not only can the area occupied by each memory cell in a plan view be reduced, but also a semiconductor device in which multiple memory cells are highly integrated can be realized.

[0348] 55 and the like, the semiconductor device of one embodiment of the present invention may have a structure in which the memory cells 21 are stacked not only in the XY plane but also in the Z direction. With such a structure, the semiconductor device can be further highly integrated.

[0349] 23A and 23B are modifications of the configurations shown in Figures 20A and 20B, respectively, and show an example in which the conductive layer 112a functioning as the wiring 35 is shared by two adjacent columns of memory cells 21. By having multiple columns of memory cells 21 share the conductive layer 112a, the memory cells 21 can be arranged at a high density.

[0350] 24A and 24B are modified examples of the configuration shown in FIGS. 20A and 20B , respectively. The conductive layer 112a, which functions as the power supply wiring 35, has a region extending in the X direction and a region extending in the Y direction. The conductive layer 112a has an opening 121a at the intersection of the region extending in the X direction and the region extending in the Y direction. By shaping the conductive layer 112a in this manner, the wiring resistance of the conductive layer 112a can be reduced compared to the configuration shown in FIGS. 20A and 20B . Meanwhile, in the example shown in FIGS. 24A and 24B , for example, the conductive layers 112a of all memory cells 21 are connected to each other. Therefore, when reading data stored in the memory cells 21, for example, current flows from all the wirings 33R to one conductive layer 112a. In the example shown in FIG. 24B , the conductive layer 112a has an opening 122 surrounded by four memory cells 21.

[0351] 25A and 25B are modifications of the configuration shown in Figures 24A and 24B, respectively, and show an example in which the conductive layer 112a does not have the opening 122. In the examples shown in Figures 25A and 25B, in a memory portion in which memory cells 21 are arranged in a matrix, the conductive layer 112a can have a rectangular shape, and openings 121a can be provided in the rectangular conductive layer 112a.

[0352] 26A and 26B are modifications of the configurations shown in Figures 20A and 20B, respectively, and show an example in which the conductive layer 112a functioning as the wiring 35 has a region extending in the X direction and is shared by the memory cells 21 arranged in the X direction. That is, in the examples shown in Figures 26A and 26B, the memory cells 21 in the same row share the same conductive layer 112a.

[0353] 27A and 27B are modifications of the configurations shown in Figures 26A and 26B, respectively, and show an example in which the conductive layer 112a is shared by two adjacent rows of memory cells 21. By having multiple rows of memory cells 21 share the conductive layer 112a, the memory cells 21 can be arranged at a high density.

[0354] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0355] [Substrate] The substrate on which the transistors 41, 42, 43, and capacitor 51 are formed can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductive substrate, etc. Alternatively, these substrates on which elements are provided may be used.

[0356] [Insulator] Examples of an insulator that can be used for at least one of the insulating layer 103a_1, the insulating layer 103a_2, the insulating layer 103b_1, the insulating layer 103b_2, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103c_3, the insulating layer 105a, the insulating layer 105b, the insulating layer 105c, the insulating layer 107a, the insulating layer 107b, the insulating layer 107c, the insulating layer 108a, the insulating layer 108b, the insulating layer 116a, the insulating layer 116b, the insulating layer 131, the insulating layer 133, the insulating layer 135, and the insulating layer 137 include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like having insulating properties.

[0357] In the following description, the term "insulator" refers to an insulator that can be used for at least one of the insulating layers described above.

[0358] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the insulator that functions as the gate insulating layer allows for lower voltage during transistor operation while maintaining the physical film thickness. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulator. Note that materials with a low dielectric constant also have high dielectric strength.

[0359] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0360] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen. Silicon oxide may be formed using an organic silane such as tetraethoxysilane (TEOS).

[0361] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0362] Furthermore, an insulator such as a gate insulating layer that is in contact with a semiconductor layer or that is provided near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, by providing an insulator having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0363] Examples of insulators having a barrier property against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0364] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0365] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0366] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, crystalline regions may be formed in some parts.

[0367] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, the term "barrier property against oxygen" refers to the property of making it difficult for at least one of oxygen atoms, oxygen molecules, etc. to diffuse.

[0368] [Conductor] The conductor that can be used for at least one of the conductive layers 111a, 111b, 111c, 112a, 112b, 115a, 115b, 115c, 117a, 117b, 141, and 143 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or the like, or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0369] In the following description, the term "conductor" refers to a conductor that can be used for at least one of the above-mentioned conductive layers.

[0370] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, conductive materials containing oxygen are sometimes referred to as oxide conductors.

[0371] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0372] Furthermore, a plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0373] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0374] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0375] [Metal Oxide] Metal oxides that can be used for at least one of the semiconductor layers 113a, 113b, and 113c may have lattice defects. Examples of lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that can cause lattice defects include a discrepancy in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms), impurities, etc.

[0376] The term "metal oxide" used below refers to a metal oxide that can be used in at least one of the above-mentioned semiconductor layers.

[0377] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0378] In a transistor using a metal oxide for a semiconductor layer, oxygen vacancies (V Ｏ) and impurities, the electrical characteristics may be easily changed and the reliability may be deteriorated. Ｏ H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the metal oxide in the channel formation region, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the metal oxide in the channel formation region. In other words, it is preferable that the carrier concentration in the metal oxide in the channel formation region is reduced and the metal oxide is made i-type (intrinsic) or substantially i-type.

[0379] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide, the method for forming the metal oxide film, and the like.

[0380] The structure of metal oxides can be divided into single crystal structures and other structures (non-single crystal structures). Examples of non-single crystal structures include CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures. The a-like structure has a structure between the nc structure and the amorphous structure.

[0381] Furthermore, metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Furthermore, metal oxides having an a-like structure have a higher hydrogen concentration than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0382] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for the semiconductor layer of a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0383] Furthermore, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0384] Here, it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, the crystal preferably has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having such crystals include single-crystal oxide semiconductors and CAAC-OS.

[0385] Furthermore, the c-axis of the crystal is preferably oriented in the normal direction to the surface on which the metal oxide is formed or the film surface, so that the layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface, i.e., the layers extend in the channel length direction.

[0386] For example, the above-described three-layered crystal structure may have the following structure: The first layer has an octahedral oxygen atomic coordination structure with the metal contained in the first layer at the center; The second layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the second layer at the center; The third layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the third layer at the center.

[0387] The crystal structure of the above crystal is, for example, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ There are various types of structures, including modified structures.

[0388] Furthermore, each of the first to third layers is preferably composed of one metal element or multiple metal elements having the same valence and oxygen. The valence of the one or more metal elements constituting the first layer is preferably the same as the valence of the one or more metal elements constituting the second layer. The first layer and the second layer may contain the same metal element. The valence of the one or more metal elements constituting the first layer is preferably different from the valence of the one or more metal elements constituting the third layer.

[0389] The above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases and the electrical characteristics of the transistor can be improved.

[0390] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0391] Examples of metal oxides include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of the usable oxide include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0392] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0393] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0394] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0395] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0396] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0397] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0398] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0399] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms one layer at a time. The ALD method makes it easy to form the metal oxide having the layered crystal structure.

[0400] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0401] The ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS.

[0402] When the ALD method is used as a method for forming a metal oxide film, by adopting a condition in which the substrate temperature is high during film formation and / or by performing an impurity removal process, the amount of carbon and chlorine contained in the film can be reduced compared to when the ALD method is used without applying these conditions.

[0403] For example, it is preferable to perform an impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of a metal oxide film. Furthermore, it is preferable to perform an impurity removal treatment in an oxygen-containing atmosphere after the formation of a metal oxide film. By performing an impurity removal treatment either during or after the formation of a metal oxide film, impurities in the film can be removed. This can prevent impurities (e.g., hydrogen, carbon, nitrogen) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. Furthermore, the crystallinity of the metal oxide can be improved.

[0404] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0405] When performing plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher and 500° C. or lower, 100° C. or higher and 500° C. or lower, 200° C. or higher and 500° C. or lower, 300° C. or higher and 500° C. or lower, 400° C. or higher and 500° C. or lower, or 400° C. or higher and 450° C. or lower. The heat treatment temperature is preferably set to 100° C. or higher and 450° C. or lower, 200° C. or higher and 450° C. or lower, 300° C. or higher and 450° C. or lower, or 400° C. or higher and 450° C. or lower.

[0406] The temperature for the impurity removal treatment is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or a semiconductor device, because the amount of impurities in the metal oxide can be reduced without reducing productivity. For example, the productivity of the semiconductor device can be increased by setting the maximum temperature in the manufacturing process of the semiconductor device of one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

[0407] Here, the microwave treatment refers to, for example, a treatment using a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0408] In the microwave treatment, it is preferable to use, for example, a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0409] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0410] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0411] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less.

[0412] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment may also be carried out in an atmosphere of ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less).

[0413] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２ The impurities can be removed by the reaction of the impurities with the metal atoms and oxygen atoms, and the impurities can be released as O. Furthermore, at the same time as the removal of the impurities, rearrangement of the metal atoms and oxygen atoms occurs, thereby improving the crystallinity. Therefore, it is possible to form a metal oxide with a highly crystalline layered crystal structure, particularly a metal oxide with the above-mentioned CAAC structure.

[0414] Unlike film formation methods in which particles emitted from a target are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as a sputtering method or a CVD method, which have a faster film formation rate. For example, a method can be used in which a first metal oxide film is formed by sputtering, and a second metal oxide film is formed on the first metal oxide by ALD. For example, if the first metal oxide has crystalline portions, the second metal oxide may grow crystals using the crystalline portions as nuclei.

[0415] The ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, for example, the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0416] [Transistor Having Metal Oxide] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer will be referred to as an OS transistor, and a transistor using silicon for a semiconductor layer will be referred to as a Si transistor.

[0417] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. Furthermore, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.

[0418] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ or less, more preferably 1 × 10 １５ cm −３ or less, more preferably 1 × 10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that when the carrier concentration of an oxide semiconductor film is reduced, it is preferable to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0419] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0420] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0421] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0422] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0423] Furthermore, as Si transistors are miniaturized, a short channel effect (also referred to as SCE) occurs. This makes miniaturization of Si transistors difficult. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, OS transistors use an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.

[0424] The short-channel effect is a deterioration in electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0425] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0426] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0427] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ accumulation type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0428] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 10 nm, 5 nm to 7 nm, or 5 nm to 6 nm. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be preferably used as a transistor with a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0429] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0430] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0431] [Impurities in Metal Oxide] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0432] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0433] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen in a semiconductor layer tends to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm３ The following applies.

[0434] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Less than.

[0435] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0436] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0437] [Other Semiconductor Materials] The semiconductor layer 113 can be rephrased as a semiconductor layer including a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0438] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0439] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0440] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0441] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0442] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a semiconductor device with a large on-current can be provided.

[0443] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0444] In this embodiment, a semiconductor device according to one embodiment of the present invention, which has a different structure from the above-described examples, will be described with reference to the drawings. In this embodiment, a display device will be mainly described as an example of the semiconductor device according to one embodiment of the present invention.

[0445] <Structure Example of Display Device> One embodiment of the present invention can also be applied to a display device. FIG. 19A is a block diagram showing a structure example of a display device 70, which is a display device of one embodiment of the present invention. The display device 70 includes a display portion 80, a scan line driver circuit 71, a signal line driver circuit 73, a power supply circuit 75, and a reference potential generation circuit 77. The display portion 80 includes a plurality of pixels 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the display device 70.

[0446] The scanning line driving circuit 71 is connected to the pixels 81 via the wiring 31 (the wiring 31a, the wiring 31b, and the wiring 31c). The wiring 31 extends, for example, in the row direction of the matrix.

[0447] The signal line driving circuit 73 is connected to the pixels 81 via the wiring 33. The wiring 33 extends, for example, in the column direction of the matrix.

[0448] The power supply circuit 75 is connected to the pixels 81 via the wiring 35. The wiring 35 extends, for example, in the row direction of the matrix.

[0449] The reference potential generating circuit 77 is connected to the pixels 81 via the wiring 38. The wiring 38 extends, for example, in the column direction of the matrix.

[0450] The pixel 81 has a display element (also referred to as a display device), and can display an image on the display unit 80 by using the display element. As the display element, for example, a light-emitting element (also referred to as a light-emitting device) can be used, and specifically, an organic EL element can be used. Furthermore, as the display element, a liquid crystal element (also referred to as a liquid crystal device) can be used.

[0451] The scanning line driver circuit 71 has a function of selecting, for example, pixels 81 to which image data is to be written, row by row. Specifically, the scanning line driver circuit 71 can select the pixels 81 to which image data is to be written by outputting a signal to the wiring 31. Here, the scanning line driver circuit 71 can select all the pixels 81 by, for example, outputting the signal to the wiring 31 in the first row, then outputting the signal to the wiring 31 in the second row, and so on, sequentially up to the wiring 31 in the final row. Thus, the signal output by the scanning line driver circuit 71 to the wiring 31 is a scanning signal, and the wiring 31 provided in the display device 70 can be referred to as a scanning line.

[0452] The signal line driver circuit 73 has a function of generating image data. The image data is supplied to the pixels 81 via the wirings 33. For example, the image data can be written to all the pixels 81 included in the row selected by the scanning line driver circuit 71. Here, the image data can be expressed as a signal (image signal). Therefore, the wirings 33 provided in the display device 70 can be called signal lines.

[0453] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 35. The power supply circuit 75 has a function of generating, for example, a high power supply potential (hereinafter also simply referred to as a "high potential" or "VDD") and supplying it to the wiring 35. The power supply circuit 75 may also have a function of generating a low power supply potential (hereinafter also simply referred to as a "low potential" or "VSS"). As described above, the wiring 35 functions as a power supply line.

[0454] The reference potential generating circuit 77 has a function of generating a reference potential and supplying it to the wiring 38. Because the potential of the wiring 38 serves as the reference potential, the wiring 38 can be referred to as a reference potential line. Note that the electrical characteristics of each pixel may be read out to the reference potential generating circuit 77 outside the pixel via the wiring 38. In other words, the reference potential generating circuit 77 may have a function of sensing the electrical characteristics of each pixel. By reading the electrical characteristics of each pixel with the reference potential generating circuit 77, deterioration and variations in elements (transistors, light-emitting elements, etc.) within each pixel may be sensed. The read characteristics may then be fed back to a video signal to correct deterioration and variations in image quality.

[0455] FIG. 19B is a plan view illustrating a configuration example of a pixel 81. The pixel 81 can have multiple subpixels 83. FIG. 19B illustrates an example in which the pixel 81 has subpixels 83R, 83G, and 83B as the subpixels 83. Here, when the pixel 81 has a light-emitting element as a display element, for example, the top surface shape of the subpixels illustrated in FIG. 19B corresponds to the top surface shape of the light-emitting region of the light-emitting element. Note that FIG. 19B illustrates the subpixels 83R, 83G, and 83B as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the subpixels 83R, 83G, and 83B can be determined as appropriate. The aperture ratios of the subpixels 83R, 83G, and 83B may be different from one another, or two or more of them may be the same or approximately the same.

[0456] 19B, a stripe arrangement is applied as an arrangement method of the sub-pixels 83. Note that an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as an arrangement method of the sub-pixels 83.

[0457] The sub-pixels 83R, 83G, and 83B each emit light of a different color. Examples of the sub-pixels 83R, 83G, and 83B include sub-pixels of three colors: red (R), green (G), and blue (B), and sub-pixels of three colors: yellow (Y), cyan (C), and magenta (M). The pixel 81 may also be provided with four or more sub-pixels 83. For example, the pixel 81 may be provided with sub-pixels of four colors: R, G, B, and white (W). As described above, the display device 70 can display a full-color image on the display unit 80 by providing the pixel 81 with a plurality of sub-pixels 83 that emit light of different colors. The pixel 81 may also be provided with sub-pixels of R, G, B, and infrared (IR), for example.

[0458] Note that a sensor may be provided in the display unit 80, for example, a sensor may be provided in the pixel 81. For example, the display unit 80 may have a function as a fingerprint sensor. For example, the display unit 80 may have a function as an optical or ultrasonic fingerprint sensor.

[0459] Fig. 19C is a circuit diagram showing an example of the configuration of a sub-pixel 83 included in the pixel 81 shown in Fig. 19A. The sub-pixel 83 shown in Fig. 19C includes a pixel circuit 90 and a light-emitting element 91.

[0460] The pixel circuit 90 includes a transistor 41, a transistor 42, a transistor 43, a transistor 53, a capacitor 51, and a capacitor 58. In other words, the pixel circuit 90 is a 4Tr2C type pixel circuit.

[0461] In the pixel circuit 90, one of the source and the drain of the transistor 42 is connected to a wiring 33. The other of the source and the drain of the transistor 42 is connected to one electrode of a capacitor 51 and the gate (first gate) of the transistor 41. The gate (first gate) of the transistor 42 is connected to a wiring 31a. One of the source and the drain of the transistor 41 is connected to one of the source and the drain of the transistor 43. The other of the source and the drain of the transistor 43 is connected to a wiring 35. The gate of the transistor 43 is connected to a wiring 31c. One electrode of the capacitor 58 is connected to the other of the source and the drain of the transistor 41, one of the source and the drain of the transistor 53, the other electrode of the capacitor 51, and one electrode of the light-emitting element 91. The other electrode of the capacitor 58 is connected to a wiring 35. The other of the source and the drain of the transistor 53 is connected to a wiring 38. The gate of the transistor 53 is connected to a wiring 31b. The other electrode of the light emitting element 91 is connected to the wiring 37 .

[0462] 19C shows a configuration example in which the transistors 41 and 42 included in the pixel circuit 90 have back gates (second gates) and the transistors 43 and 53 do not have back gates; however, this is not limiting. In one embodiment of the present invention, the transistors 43 and 53 may each have a back gate.

[0463] In addition, although FIG. 19C does not explicitly show the connection destination of the back gates of transistors 41 and 42, as described above, they can be connected to, for example, the source or gate (first gate) of each transistor, or a wiring (wiring 35, wiring 38, etc.) to which a constant potential is supplied.

[0464] The transistor 43 functions as a switch and controls conduction or non-conduction between the wiring 35 and one of the source and the drain of the transistor 41 based on the potential of the wiring 31c.

[0465] By turning on the transistor 43, a current having a magnitude corresponding to the gate potential of the transistor 41 flows, for example, from the wiring 35 to the wiring 37. This causes the light-emitting element 91 to emit light with a luminance corresponding to the gate potential of the transistor 41. On the other hand, by turning off the transistor 43, no current flows through the light-emitting element 91, and therefore the light-emitting element 91 does not emit light.

[0466] As described above, the transistor 41 functions as a driving transistor in the pixel circuit 90. The transistor 41 has a back gate, which allows an electric field to be applied to the semiconductor layer from both the gate and the back gate, thereby enabling a larger on-state current to be obtained than in a case where the transistor 41 does not have a back gate. This allows a display device with high brightness to be realized. Furthermore, the off-state current can be reduced compared to a case where the transistor 41 does not have a back gate, which prevents a problem such as a current flowing through a light-emitting element 91 that is not intended to emit light, causing the light-emitting element to emit light.

[0467] Meanwhile, the transistor 42 functions as a selection transistor in the pixel circuit 90. By providing the back gate, the transistor 42 can obtain a larger on-state current than when the transistor 42 does not have a back gate. This improves the speed at which pixels to be illuminated are selected. Furthermore, because the off-state current can be made smaller than when the transistor 42 does not have a back gate, it is possible to prevent problems such as the transistor 41 being turned on in pixels that are not to be illuminated.

[0468] OS transistors are preferably used as the transistors 41, 42, and 43. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 41 and 42, the display device 70 can be driven at high speed.

[0469] Furthermore, as described above, an OS transistor has an extremely small off-state current. Therefore, by using an OS transistor as the transistor 42, charge stored in the capacitor 51 can be held for a long period of time. This allows image data written to the subpixel 83 to be held for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the subpixel 83). As a result, the power consumption of the display device 70 can be reduced.

[0470] Here, to increase the emission luminance of the light-emitting element 91, it is necessary to increase the current flowing through the light-emitting element 91. To achieve this, it is necessary to increase the source-drain voltage of the transistor 41, which is a driving transistor. Because an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 41, it is possible to increase the current flowing through the light-emitting element 91 and increase the emission luminance of the light-emitting element 91.

[0471] It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting element 91. Examples of the light-emitting material included in the light-emitting element 91 include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (for example, a quantum dot material). Alternatively, an LED such as a micro LED (light-emitting diode) can be used as the light-emitting element 91.

[0472] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0473] Embodiment 3 In this embodiment, an example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0474] <Example of Manufacturing Method of Semiconductor Device> Below, as a method for manufacturing a semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 4A to 4C will be described with reference to FIGS. 28A to 53C.

[0475] (A) in each figure shows a plan view. Also, (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure. Also, (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure. Note that in the plan view of (A) of each figure, some elements have been omitted for clarity.

[0476] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0477] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct-current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0478] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0479] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method does not use plasma, and therefore is a film formation method capable of forming films without causing plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, and therefore produces films with fewer defects.

[0480] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0481] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0482] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0483] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0484] First, a substrate (not shown) is prepared, and an insulating layer 101 is formed on the substrate (FIGS. 28A to 28C). The insulating material described above can be used as appropriate for the insulating layer 101. The insulating layer 101 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0485] Next, a conductive layer 111c is formed over the insulating layer 101 (FIGS. 28A to 28C). For example, a conductive film to be the conductive layer 111c is formed and then processed to form the conductive layer 111c. For the conductive film to be the conductive layer 111c, any of the conductive materials applicable to the conductive layer 111 described above can be used as appropriate.

[0486] The conductive film that becomes the conductive layer 111c can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a stacked film in which tungsten and titanium nitride are deposited in this order can be formed as the conductive film that becomes the conductive layer 111c by a CVD method. After the conductive film that becomes the conductive layer 111c is formed, for example, a pattern is formed by lithography, and the conductive film is processed based on the pattern by a dry etching method, a wet etching method, or the like, to form the conductive layer 111c. Here, processing the conductive film by a dry etching method is preferable because it enables fine processing.

[0487] In the lithography method, first, the resist is exposed to light through a mask, and then the exposed area is removed or left using a developer to form a resist mask, thereby forming a pattern.

[0488] For example, a resist mask is formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV light, or the like. Also, a liquid immersion technique may be used in which exposure is performed by filling a liquid (e.g., water) between the substrate and the projection lens. Also, an electron beam or an ion beam may be used instead of the light described above. Note that, when an electron beam or an ion beam is used, a mask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0489] Next, etching is performed through the resist mask, whereby the conductive layer, the semiconductor layer, the insulating layer, or the like can be processed into a desired shape.

[0490] When dry etching is performed as the etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, a C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, NF ３ Gas, CHF ３ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, CCl ４ Gas, or BBr ３ A gas such as a silicon dioxide gas can be used alone or in combination of two or more gases. Furthermore, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the etching gas as appropriate. The etching conditions can be appropriately set depending on the target to be etched.

[0491] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0492] Next, an insulating layer 103c_1 functioning as an interlayer insulating layer is formed over the insulating layer 101 and the conductive layer 111c (FIGS. 29A to 29C). The insulating layer 103c_1 can be formed using any of the above-described insulating materials as appropriate. The insulating layer 103c_1 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. For example, a silicon oxide film is formed as the insulating layer 103c_1 by a sputtering method. Note that the insulating layer 103c_1 preferably has a top surface that is planarized by chemical mechanical polishing (CMP) treatment after the formation. By performing planarization treatment on the insulating layer 103c_1, a conductive layer 115c that functions as a wiring can be suitably formed in a later step. Alternatively, after aluminum oxide is formed on the insulating layer 103c_1 by, for example, sputtering, CMP treatment may be performed until the insulating layer 103c_1 is reached. By performing the CMP treatment, the surface of the insulating layer 103c_1 can be planarized and smoothed. By disposing the aluminum oxide on the insulating layer 103c_1 and performing the CMP treatment, it becomes easy to detect the end point of the CMP treatment.

[0493] Note that CMP treatment may not be performed in some cases. In this case, the top surface of the insulating layer 103c_1 has a convex curved shape. By not performing planarization treatment, manufacturing costs can be reduced and production yields can be increased.

[0494] Next, a conductive layer 115c is formed over the insulating layer 103c_1 (FIGS. 30A to 30C). For example, a conductive film to be the conductive layer 115c is formed and then processed to form the conductive layer 115c. The conductive film to be the conductive layer 115c can be formed using any of the above-described conductive materials applicable to the conductive layer 115 as appropriate. The conductive film to be the conductive layer 115c can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate.

[0495] After forming the conductive film to be the conductive layer 115c, for example, a pattern is formed by lithography, and the conductive film is processed based on the pattern by dry etching, wet etching, or the like, to form the conductive layer 115c. Here, processing the conductive film by dry etching is preferable because fine processing can be performed.

[0496] Next, an insulating layer 103c_2 functioning as an interlayer insulating layer is formed over the insulating layer 103c_1 and the conductive layer 115c (FIGS. 31A to 31C). The insulating layer 103c_2 can be formed using the same material and method as the insulating layer 103c_1. Note that the insulating layer 103c_2 is preferably subjected to CMP treatment after deposition to planarize its top surface.

[0497] Next, a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 are processed to form an opening 121c that reaches the conductive layer 111c (FIGS. 32A to 32C). The opening 121c can be formed by, for example, lithography and etching.

[0498] Here, the sidewalls of the opening 121c (the side surfaces of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 in the opening 121c) are preferably perpendicular to the top surface of the conductive layer 111c. Such a structure enables miniaturization or high integration of the semiconductor device. The sidewalls of the opening 121c may also be tapered. Tapering the sidewalls of the opening 121c improves coverage with a metal oxide film or the like that becomes the semiconductor layer 113c (described later), thereby reducing defects such as voids.

[0499] The maximum width of the opening 121c (or the diameter when the opening 121c is circular in plan view) is preferably very small, for example, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 5 nm to 20 nm.

[0500] Because the opening 121c has a large aspect ratio, it is preferable to process part of the insulating layer 103c_2, part of the conductive layer 115c, and part of the insulating layer 103c_1 by anisotropic etching. Dry etching is particularly preferable because it is suitable for microfabrication. Different processing conditions may be used for each layer. Depending on the processing conditions for part of the insulating layer 103c_2, part of the conductive layer 115c, and part of the insulating layer 103c_1, the inclination of the side surface of the insulating layer 103c_2 in the opening 121c, the inclination of the side surface of the conductive layer 115c in the opening 121c, and the inclination of the side surface of the insulating layer 103c_1 in the opening 121c may differ.

[0501] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C. Note that the heat treatment is performed in, for example, a nitrogen gas or inert gas atmosphere. The heat treatment may also be performed under reduced pressure. By performing the above heat treatment, impurities such as water contained in the insulating layer 103c_1, the insulating layer 103c_2, and the like can be reduced before the formation of a metal oxide film that becomes the semiconductor layer 113c, which will be described later.

[0502] The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, for example, moisture can be prevented from being introduced into the insulating layers 103c_1 and 103c_2 as much as possible.

[0503] Next, an insulating film 105C, which will later become the insulating layer 105c, is formed in contact with the top surface of the insulating layer 103c_2, the side surfaces of the insulating layer 103c_2, the side surfaces of the conductive layer 115c, the side surfaces of the insulating layer 103c_1, and the top surface of the conductive layer 111c ( FIGS. 33A to 33C ). The insulating film 105C can be formed using any of the above-described insulating materials as appropriate. The insulating film 105C can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. Here, the insulating film 105C is preferably formed in contact with the bottom and sidewalls of the opening 121c, which has a large aspect ratio. Therefore, a film formation method with good coverage is preferably used for forming the insulating film 105C, and more preferably a CVD method, an ALD method, or the like. For example, silicon oxide is formed as the insulating film 105C by an ALD method.

[0504] When the sidewall of the opening 121c has a tapered shape, the method for forming the insulating film 105C is not limited to the CVD method or the ALD method, and for example, sputtering may be used.

[0505] Next, the insulating film 105C is processed to expose the top surface of the insulating layer 103c_2 and the top surface of the conductive layer 111c, and an insulating layer 105c is formed in contact with the side surfaces of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 (FIGS. 34A to 34C).

[0506] The insulating film 105C is preferably processed by anisotropic etching. By using anisotropic etching to process the insulating film 105C, it is possible to selectively remove a region of the insulating film 105C located in the opening 121c with a large aspect ratio that is in contact with the top surface of the insulating layer 103c_2 and a region that is in contact with the bottom of the opening 121c (the top surface of the conductive layer 111c). This allows the insulating layer 105c that is in contact with the sidewall of the opening 121c to be formed with high accuracy.

[0507] Next, a metal oxide film 113C, which will later become the semiconductor layer 113c, is formed in contact with the top surface of the conductive layer 111c, the side surface of the i...

Claims

a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; the first transistor, the second transistor, and the third transistor are stacked in this order; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a seventh insulating layer, and a first semiconductor layer; the first insulating layer, the third conductive layer, and the second insulating layer are laminated in this order on the first conductive layer; a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer; the seventh insulating layer is provided in contact with a side wall of the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer in the first opening, a side surface of the seventh insulating layer in the first opening, and an upper surface of the second insulating layer; the second conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an eighth insulating layer, a ninth insulating layer, and a second semiconductor layer; the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer are stacked in this order on the second conductive layer; a second opening reaching the second conductive layer is provided in the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer; the eighth insulating layer is provided in contact with a side wall of the second opening, the second semiconductor layer is provided in contact with an upper surface of the second conductive layer in the second opening, a side surface of the eighth insulating layer in the second opening, and an upper surface of the fourth conductive layer; the ninth insulating layer is provided in contact with an upper surface of the second semiconductor layer, a side surface of the second semiconductor layer, an upper surface of the fourth conductive layer, and an upper surface of the fourth insulating layer; the sixth conductive layer is provided on and in contact with the ninth insulating layer so as to fill the second opening; the third transistor has a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a tenth insulating layer, an eleventh insulating layer, and a third semiconductor layer; the seventh conductive layer is provided in contact with an upper surface of the sixth conductive layer, the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer are stacked in this order on the seventh conductive layer; a third opening reaching the seventh conductive layer is provided in the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer; the tenth insulating layer is provided in contact with a side wall of the third opening, the third semiconductor layer is provided in contact with an upper surface of the seventh conductive layer in the third opening, a side surface of the tenth insulating layer in the third opening, and an upper surface of the eighth conductive layer; the eleventh insulating layer is provided in contact with an upper surface of the third semiconductor layer, a side surface of the third semiconductor layer, an upper surface of the eighth conductive layer, and an upper surface of the sixth insulating layer; the tenth conductive layer is provided on and in contact with the eleventh insulating layer so as to fill the third opening; Semiconductor device. 　 In claim 1, At least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer comprises a metal oxide; The metal oxide has two or three selected from indium, an element M, and zinc; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony; Semiconductor device. 　 In claim 1 or 2, the second conductive layer includes an eleventh conductive layer and a twelfth conductive layer; the eleventh conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the twelfth conductive layer is provided in contact with an upper surface of the eleventh conductive layer so as to have an area overlapping with the first conductive layer; The second semiconductor layer is provided in contact with an upper surface of the twelfth conductive layer. Semiconductor device. 　 In claim 1 or 2, the second conductive layer includes an eleventh conductive layer, a twelfth conductive layer, and a thirteenth conductive layer; the eleventh conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the thirteenth conductive layer is provided in contact with an upper surface of the eleventh conductive layer, the twelfth conductive layer is provided in contact with an upper surface of the thirteenth conductive layer so as to have an area overlapping with the first conductive layer; The second semiconductor layer is provided in contact with an upper surface of the twelfth conductive layer. Semiconductor device. 　 In claim 1 or 2, a capacitance is provided between the second transistor and the third transistor; the first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order; the capacitor includes a fourteenth conductive layer, a fifteenth conductive layer, and a twelfth insulating layer; the twelfth insulating layer has a region in contact with a side surface of the fourteenth conductive layer, the fifteenth conductive layer covers at least a part of a side surface of the fourteenth conductive layer via the twelfth insulating layer; the fourteenth conductive layer is provided in contact with an upper surface of the sixth conductive layer, The seventh conductive layer is provided in contact with an upper surface of the fourteenth conductive layer. Semiconductor device. 　 a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; the first transistor, the second transistor, and the third transistor are stacked in this order; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a seventh insulating layer, and a first semiconductor layer; the first insulating layer, the third conductive layer, and the second insulating layer are laminated in this order on the first conductive layer; a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer; the seventh insulating layer is provided in contact with a side wall of the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer in the first opening, a side surface of the seventh insulating layer in the first opening, and an upper surface of the second insulating layer; the second conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the third conductive layer is provided to surround the first semiconductor layer with the seventh insulating layer interposed therebetween in a plan view, the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an eighth insulating layer, a ninth insulating layer, and a second semiconductor layer; the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer are stacked in this order on the second conductive layer; a second opening reaching the second conductive layer is provided in the third insulating layer, the fifth conductive layer, the fourth insulating layer, and the fourth conductive layer; the eighth insulating layer is provided in contact with a side wall of the second opening, the second semiconductor layer is in contact with an upper surface of the second conductive layer in the second opening, a side surface of the eighth insulating layer in the second opening, and an upper surface of the fourth conductive layer; the ninth insulating layer is provided in contact with an upper surface of the second semiconductor layer, a side surface of the second semiconductor layer, an upper surface of the fourth conductive layer, and an upper surface of the fourth insulating layer; the sixth conductive layer is provided on and in contact with the ninth insulating layer so as to fill the second opening; the fifth conductive layer is provided to surround the second semiconductor layer via the eighth insulating layer in a plan view, the second semiconductor layer is provided to surround the sixth conductive layer with the ninth insulating layer interposed therebetween in a plan view, the third transistor has a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a tenth insulating layer, an eleventh insulating layer, and a third semiconductor layer; the seventh conductive layer is provided in contact with an upper surface of the sixth conductive layer, the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer are stacked in this order on the seventh conductive layer; a third opening reaching the seventh conductive layer is provided in the fifth insulating layer, the ninth conductive layer, the sixth insulating layer, and the eighth conductive layer; the tenth insulating layer is provided in contact with a side wall of the third opening, the third semiconductor layer is in contact with an upper surface of the seventh conductive layer in the third opening, a side surface of the tenth insulating layer in the third opening, and an upper surface of the eighth conductive layer; the eleventh insulating layer is provided in contact with an upper surface of the third semiconductor layer, a side surface of the third semiconductor layer, an upper surface of the eighth conductive layer, and an upper surface of the sixth insulating layer; the tenth conductive layer is provided on and in contact with the eleventh insulating layer so as to fill the third opening; the ninth conductive layer is provided to surround the third semiconductor layer via the tenth insulating layer in a plan view, the third semiconductor layer is provided to surround the tenth conductive layer via the eleventh insulating layer in a plan view; Semiconductor device. 　 In claim 6, At least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer comprises a metal oxide; The metal oxide has two or three selected from indium, an element M, and zinc; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony; Semiconductor device. 　 In claim 6 or 7, the second conductive layer includes an eleventh conductive layer and a twelfth conductive layer; the eleventh conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the twelfth conductive layer is provided in contact with an upper surface of the eleventh conductive layer so as to have an area overlapping with the first conductive layer; The second semiconductor layer is provided in contact with an upper surface of the twelfth conductive layer. Semiconductor device. 　 In claim 6 or 7, the second conductive layer includes an eleventh conductive layer, a twelfth conductive layer, and a thirteenth conductive layer; the eleventh conductive layer is provided in contact with an upper surface of the first semiconductor layer so as to have a region overlapping with the first conductive layer; the thirteenth conductive layer is provided in contact with an upper surface of the eleventh conductive layer, the twelfth conductive layer is provided in contact with an upper surface of the thirteenth conductive layer so as to have an area overlapping with the first conductive layer; The second semiconductor layer is provided in contact with an upper surface of the twelfth conductive layer. Semiconductor device. 　 In claim 6 or 7, a capacitance is provided between the second transistor and the third transistor; the first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order; the capacitor includes a fourteenth conductive layer, a fifteenth conductive layer, and a twelfth insulating layer; the twelfth insulating layer has a region in contact with a side surface of the fourteenth conductive layer, the fifteenth conductive layer covers at least a part of a side surface of the fourteenth conductive layer via the twelfth insulating layer; the fourteenth conductive layer is provided in contact with an upper surface of the sixth conductive layer, The seventh conductive layer is provided in contact with an upper surface of the fourteenth conductive layer. Semiconductor device. 　 forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and on the second conductive layer; processing the first insulating layer, the second conductive layer, and the second insulating layer to form a first opening reaching the first conductive layer; forming a third insulating layer in contact with a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and a side surface of the second insulating layer in the first opening; forming a first semiconductor layer in contact with an upper surface of the first conductive layer in the first opening, a side surface of the third insulating layer in the first opening, and an upper surface of the second insulating layer; forming a third conductive layer in contact with an upper surface of the first semiconductor layer; forming a fourth insulating layer on the third conductive layer and on the second insulating layer; forming a fourth conductive layer on the fourth insulating layer; forming a fifth insulating layer on the fourth insulating layer and on the fourth conductive layer; forming a fifth conductive layer on the fifth insulating layer; processing the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, and the fifth conductive layer to form a second opening reaching the third conductive layer; forming a sixth insulating layer in contact with a side surface of the fourth insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, a side surface of the fifth insulating layer in the second opening, and a side surface of the fifth conductive layer in the second opening; forming a second semiconductor layer in contact with an upper surface of the third conductive layer in the second opening, a side surface of the sixth insulating layer in the second opening, and an upper surface of the fifth conductive layer; forming a seventh insulating layer on the second semiconductor layer, the fifth conductive layer, and the fifth insulating layer; forming a sixth conductive layer on the seventh insulating layer, the sixth conductive layer having a region overlapping with the second semiconductor layer; forming an eighth insulating layer on the seventh insulating layer and on the sixth conductive layer; processing an upper surface of the eighth insulating layer and an upper surface of the sixth conductive layer to make their heights with respect to a substrate surface approximately equal; forming a seventh conductive layer in contact with an upper surface of the sixth conductive layer; forming a ninth insulating layer on the eighth insulating layer and on the seventh conductive layer; forming an eighth conductive layer on the ninth insulating layer; forming a tenth insulating layer on the ninth insulating layer and the eighth conductive layer; forming a ninth conductive layer on the tenth insulating layer; processing the ninth insulating layer, the eighth conductive layer, the tenth insulating layer, and the ninth conductive layer to form a third opening reaching the seventh conductive layer; forming an eleventh insulating layer in contact with a side surface of the ninth insulating layer in the third opening, a side surface of the eighth conductive layer in the third opening, a side surface of the tenth insulating layer in the third opening, and a side surface of the ninth conductive layer in the third opening; forming a third semiconductor layer in contact with an upper surface of the seventh conductive layer in the third opening, a side surface of the eleventh insulating layer in the third opening, and an upper surface of the ninth conductive layer; forming a twelfth insulating layer on the third semiconductor layer, on the ninth conductive layer, and on the tenth insulating layer; forming a tenth conductive layer on the twelfth insulating layer, the tenth conductive layer having a region overlapping with the third semiconductor layer; A method for manufacturing a semiconductor device.

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