Semiconductor device

Abstract

The present invention provides a semiconductor device with reduced power consumption. The semiconductor device has a first circuit that generates a first potential and a second circuit that includes a first transistor and a second transistor, each of which is a vertical transistor, wherein after the first potential is supplied to the back gate of the first transistor via the source and drain of the second transistor, the back gate of the first transistor is put into a floating state by turning off the second transistor.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and driving methods or manufacturing methods thereof.

[0003] In recent years, development of semiconductor devices using transistors has progressed. In semiconductor devices using transistors, controlling the threshold voltage of the transistor is important. For example, if a transistor becomes a normally-on type, problems such as malfunction during operation or high power consumption during non-operation may occur.

[0004] As an example of a method for controlling the threshold voltage of a transistor, a method is known in which the threshold voltage of the transistor is shifted by supplying a power supply potential to the back gate of the transistor (for example, Patent Document 1).

[0005] JP 2006-165808 A

[0006] However, the threshold voltage control method disclosed in Patent Document 1 requires a constant supply of a power supply potential to the back gate of the transistor, making it difficult to reduce power consumption. Furthermore, with the trend toward smaller and lighter electronic devices, semiconductor devices with smaller occupancy areas are in demand.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with a small area.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0008] It should be noted that the problems associated with one embodiment of the present invention are not limited to the above problems. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. It should be noted that the problems associated with one embodiment of the present invention do not necessarily solve all of the above and other problems. One embodiment of the present invention solves at least one of the above and other problems.

[0009] (1) One embodiment of the present invention is a semiconductor device that includes a plurality of transistors, a first transistor, and a circuit that generates a first potential. In the cross-sectional view in the channel width direction, the length of a semiconductor layer of the first transistor in a direction perpendicular to a surface on which the first transistor is formed is longer than its width. After the first potential is supplied to the back gates of the plurality of transistors via the source and the drain of the first transistor, the back gates of the plurality of transistors are brought into a floating state by turning off the second transistor.

[0010] In the method (1), the gate of the first transistor preferably has a plurality of regions overlapping with the semiconductor layer. In a cross-sectional view in the channel width direction, the length of the semiconductor layer in a direction perpendicular to the surface on which the semiconductor layer is formed is preferably from two to ten times the width of the semiconductor layer. The semiconductor layer preferably contains an oxide semiconductor.

[0011] (2) Another embodiment of the present invention includes a first circuit having a function of generating a first potential, a second circuit including a first transistor and a second transistor, a first conductive layer functioning as one of a source and a drain of the first transistor, a second conductive layer provided above the first conductive layer and functioning as a gate of the first transistor, a third conductive layer provided above the second conductive layer and functioning as the other of the source and the drain of the first transistor, a first semiconductor layer including a first channel formation region of the first transistor, a fourth conductive layer including a region located above the third conductive layer, a region functioning as a back gate of the first transistor, and a region functioning as one of the source and the drain of the second transistor, a fifth conductive layer provided above the fourth conductive layer and functioning as the other of the source and the drain of the second transistor, and a fifth conductive layer provided above the fourth conductive layer and functioning as the other of the source and the drain of the second transistor. and a sixth conductive layer including a region located above the fifth conductive layer and a region functioning as a gate of the second transistor, wherein the first semiconductor layer has a region electrically connected to the first conductive layer, a region along a side surface of the second conductive layer, and a region electrically connected to the third conductive layer, the second semiconductor layer has a region electrically connected to the fourth conductive layer and a region electrically connected to the fifth conductive layer, the fourth conductive layer has a region along the first channel formation region, and the sixth conductive layer has a region along the second channel formation region, and the semiconductor device has a function of turning off the second transistor and putting the back gate of the first transistor into an electrically floating state after a first potential is supplied to the back gate of the first transistor via the source and drain of the second transistor.

[0012] In (2), the first channel formation region and the second channel formation region preferably have regions that overlap each other in a planar view, and the first conductive layer, the fourth conductive layer, and the sixth conductive layer preferably have regions that overlap each other in a planar view.

[0013] The first semiconductor layer preferably includes an oxide semiconductor, the second semiconductor layer preferably includes an oxide semiconductor, and the first circuit has a function of supplying a first potential to each of the plurality of second circuits, for example.

[0014] (3) Another aspect of the present invention is a semiconductor device including a first transistor and a second transistor, the semiconductor device including: a first conductive layer functioning as one of a source or a drain of the first transistor; a second conductive layer functioning as a back gate of the first transistor and also as one of the source or the drain of the second transistor; a third conductive layer functioning as the other of the source or the drain of the first transistor; a fourth conductive layer functioning as the other of the source or the drain of the second transistor; a fifth conductive layer functioning as a gate of the first transistor; a sixth conductive layer functioning as a gate of the second transistor; a first semiconductor layer including a channel formation region of the first transistor; a second semiconductor layer including a channel formation region of the second transistor; a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is provided on the first conductive layer, and the second conductive layer is The first semiconductor layer is provided on the first insulating layer, the second insulating layer is provided on the second conductive layer, the third conductive layer and the fourth conductive layer are provided on the second insulating layer, and the third insulating layer is provided on the third conductive layer and the fourth conductive layer, the first semiconductor layer has a region in contact with the first conductive layer, a region along a side surface of the first insulating layer, a region along a side surface of the second conductive layer, a region along a side surface of the second insulating layer, and a region in contact with the third conductive layer, and the second semiconductor layer has a region in contact with the second conductive layer and a region along the second insulating layer. The semiconductor device has a region that runs along the side of the edge layer and a region that contacts the fourth conductive layer, the fifth conductive layer has a region that runs along the side of the first insulating layer via the third insulating layer and the first semiconductor layer, a region that runs along the side of the second conductive layer via the third insulating layer and the first semiconductor layer, and a region that runs along the side of the second insulating layer via the third insulating layer and the first semiconductor layer.The sixth conductive layer has a region that runs along the side of the second insulating layer via the third insulating layer and the second semiconductor layer.

[0015] In (3), the first semiconductor layer preferably includes an oxide semiconductor, the second semiconductor layer preferably includes an oxide semiconductor, and the channel length of the second transistor is preferably shorter than the channel length of the first transistor.

[0016] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a small area can be provided. Furthermore, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0017] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0018] FIGS. 1A and 1B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 2A is a timing chart illustrating the operation of the semiconductor device. FIGS. 2B to 2E are diagrams illustrating electrical characteristics of a transistor. FIGS. 3A to 3D are circuit diagrams illustrating the operation of the semiconductor device. FIGS. 4A and 4B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 5A is a plan view illustrating an example of a transistor. FIGS. 5B to 5E are cross-sectional views illustrating an example of a transistor. FIG. 6 is a cross-sectional view illustrating an example of a transistor. FIG. 7A is a plan view illustrating an example of a transistor. FIGS. 7B to 7D are cross-sectional views illustrating an example of a transistor. FIG. 8A is a schematic perspective view illustrating an example of a semiconductor device. FIG. 8B is a plan view illustrating an example of a semiconductor device. FIG. 8C is a cross-sectional view illustrating an example of a semiconductor device. FIG. 9 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 10A is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 10B is a schematic perspective view illustrating an example of a semiconductor device. FIG. 11A is a plan view illustrating an example of a semiconductor device. FIGS. 11B to 11D are cross-sectional views illustrating an example of a semiconductor device. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIG. 12B is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 13A to 13D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 14A to 14D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 15A is a plan view illustrating an example of a transistor. FIG. 15B is a schematic perspective view illustrating an example of a transistor. FIGS. 15C to 15E are cross-sectional views illustrating an example of a transistor. FIGS. 16A and 16B are cross-sectional views illustrating an example of a transistor. FIG. 17A is a plan view illustrating an example of a transistor. FIG. 17B is a schematic perspective view illustrating an example of a transistor. FIGS. 17C to 17E are cross-sectional views illustrating an example of a transistor. FIG. 18 is a cross-sectional view illustrating an example of a transistor. FIG. 19A is a plan view illustrating an example of a transistor. FIG. 19B is a schematic perspective view illustrating an example of a transistor. FIGS. 19C to 19E are cross-sectional views illustrating an example of a transistor. FIG. 20A is a diagram illustrating an example of a shift register.20B and 20C are diagrams illustrating an example of a signal output circuit. FIG. 21 is a diagram illustrating an example of a signal output circuit. FIG. 22 is a diagram illustrating an example of a signal output circuit. FIGS. 23A to 23D are diagrams illustrating an example of a functional circuit. FIGS. 24A and 24B are diagrams illustrating an example of a potential generating circuit. FIGS. 25A and 25B are diagrams illustrating an example of a potential generating circuit. FIGS. 26A and 26B are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 27A to 27H are diagrams illustrating an example of the circuit configuration of a memory cell. FIG. 28 is a cross-sectional view showing an example of a semiconductor device. FIGS. 29A to 29J are diagrams illustrating an example of an electronic device. FIG. 30 is a diagram illustrating an example of an electronic device.

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0020] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0021] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings.

[0022] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0023] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0024] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0025] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0026] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not mean that insulating layer A and electrode B are necessarily in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0027] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0029] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0030] In this specification, "source" refers to a source region, a source electrode, or a source wiring. A source region refers to a region of a semiconductor layer whose resistivity is equal to or lower than a certain value. A source electrode refers to a conductive layer including a portion connected to a source region. A source wiring refers to a conductive layer for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0031] In this specification, "drain" refers to a drain region, a drain electrode, or a drain wiring. A drain region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. A drain electrode refers to a conductive layer including a portion connected to the drain region. A drain wiring refers to a conductive layer for electrically connecting a drain electrode of a transistor to another electrode or another wiring.

[0032] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode refers to an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage. The gate wiring refers to a conductive layer that electrically connects the gate electrode of a transistor to another electrode or another wiring.

[0033] In this specification, when it is explicitly stated that X and Y are connected, this includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, this is not limited to a predetermined connection relationship, for example, a connection relationship shown in a diagram or text, but also includes connection relationships other than those shown in a diagram or text.

[0034] An example of a case where X and Y are electrically connected is when one or more elements (e.g., switches, transistors, inductors, resistors, etc.) that enable the electrical connection between X and Y are connected between X and Y.

[0035] An example of a case where X and Y are functionally connected is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or amount of current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) are connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0036] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0037] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0038] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0039] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0040] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0041] Unless otherwise specified, the transistors described in this specification are enhancement-mode (normally-off) n-channel field-effect transistors. Therefore, the threshold voltage is assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0042] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS.

[0043] In addition, in drawings and the like, to clearly indicate the potential of a wiring, electrode, or the like, an "H" indicating a potential H or an "L" indicating a potential L may be added adjacent to the wiring, electrode, or the like. A wiring, electrode, or the like in which a potential change has occurred may be surrounded by "H" or "L." When a transistor is in an off state, an "x" symbol may be added over the transistor. An arrow may also be added to indicate the direction of current flow.

[0044] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," and "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 10%.

[0045] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0046] Generally, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other with an insulator interposed therebetween, a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween.

[0047] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0048] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term is not used in this specification, an ordinal number may be used in the claims to avoid confusion between components. Furthermore, even if a term is used in this specification with an ordinal number, a different ordinal number may be used in the claims. Furthermore, even if a term is used in this specification with an ordinal number, the ordinal number may be omitted in the claims, etc.

[0049] Embodiment 1 A semiconductor device which is one embodiment of the present invention will be described with reference to the drawings.

[0050] The semiconductor device 500 shown in FIG. 1A includes a functional circuit 100 including n transistors 130 (n is an integer of 1 or more), a potential supply circuit 120 including n transistors 140, a potential generation circuit 101, and a control signal output circuit 102.

[0051] 1A shows an example in which n holding circuits 150 are configured using n transistors 130 included in the functional circuit 100 and n transistors 140 included in the potential supply circuit 120.

[0052] Various circuits having specific functions can be applied as the functional circuit 100. Examples of the functional circuit 100 include driver circuits such as gate drivers and source drivers, arithmetic circuits, and integrated circuits.

[0053] The potential generating circuit 101 has a function of generating a potential Vbg using VDD and VSS supplied to the potential generating circuit 101. FIG. 1A shows a configuration example in which VDD is supplied to the potential generating circuit 101 via a switch 105. When the switch 105 is turned on, VDD is supplied to the potential generating circuit 101. When the switch 105 is turned off, VDD is no longer supplied to the potential generating circuit 101, and the operation of the potential generating circuit 101 stops. The potential generating circuit 101 can be configured using, for example, a charge pump, an inverting converter, a Cuk converter, or the like. The control signal output circuit 102 has a function of outputting a signal that controls the on / off state of the transistor 140. Note that the potential generating circuit 101 and the control signal output circuit 102 can be included in the functional circuit 100. Furthermore, the control signal output circuit 102 can have a function of outputting a plurality of signals.

[0054] It is also possible to configure the potential generating circuit 101 so that VSS is supplied to the potential generating circuit 101 via the switch 105. It is also possible to configure the potential generating circuit 101 so that VDD is supplied to the potential generating circuit 101 via the switch 105, and VSS is supplied to the potential generating circuit 101 via another switch.

[0055] 1A, the first holding circuit 150 is indicated as holding circuit 150[1], the second holding circuit 150 is indicated as holding circuit 150[2], the n-1th holding circuit 150 is indicated as holding circuit 150[n-1], and the nth holding circuit 150 is indicated as holding circuit 150[n]. The transistors 130 and 140 included in the holding circuit 150[1] are indicated as transistors 130[1] and 140[1], respectively. The transistors 130 and 140 included in the holding circuit 150[2] are indicated as transistors 130[2] and 140[2], respectively. The transistors 130 and 140 included in the holding circuit 150[n-1] are indicated as transistors 130[n-1] and 140[n-1], respectively. The transistor 130 and the transistor 140 included in the holding circuit 150[n] are denoted as a transistor 130[n] and a transistor 140[n], respectively.

[0056] The transistor 130 has a back gate. One of the source and the drain of the transistor 140 is connected to the back gate of the transistor 130. Therefore, one of the source and the drain of the transistor 140[1] is connected to the back gate of the transistor 130[1]. The other of the source and the drain of the transistor 140[1] is connected to the output of the potential generating circuit 101 via a wiring 111. The gate of the transistor 140[1] is connected to the output of the control signal output circuit 102 via a wiring 112.

[0057] 1A, a region where the back gate of the transistor 130 and one of the source and drain of the transistor 140 are connected is shown as a node SN. As described above, the node SN included in the holding circuit 150[1] is shown as a node SN[1] in FIG.

[0058] Here, the gate and back gate of a transistor will be described. The gate and back gate of a transistor are arranged to sandwich a channel formation region of a semiconductor layer. Both the gate and the back gate are formed of a conductive layer or a semiconductor layer with low resistivity. The back gate can function similarly to the gate. When the gate is used to control the on / off state of a transistor, the potential of the back gate is preferably set to the same potential as the gate, GND, or any other potential. For example, when a transistor is turned on, supplying a potential H to both the gate and the back gate can increase the on-state current compared to supplying a potential H to only one of them. Furthermore, changing the potential of the back gate independently of the gate can change the threshold voltage of the transistor. Furthermore, since the gate and the back gate are formed of a conductive layer or a semiconductor layer with low resistivity, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (especially an electric field shielding function against static electricity, etc.). By providing a back gate in addition to the gate, characteristic variations between transistors can be reduced.

[0059] The on / off state of the transistor 140 is controlled in accordance with a signal input to the gate from the control signal output circuit 102. When the transistor 140 is turned on, the output of the potential generating circuit 101 and the back gate of the transistor 130 are brought into a conductive state. Therefore, the potential Vbg is supplied to the node SN. When the transistor 140 is turned off, the output of the potential generating circuit 101 and the back gate of the transistor 130 are brought into a non-conductive state.

[0060] Next, a method for driving the semiconductor device 500 shown in FIG. 1A will be described with reference to FIGS. 2A to 2E and 3A to 3D. FIG. 2A is a timing chart illustrating the method for driving the semiconductor device 500. FIGS. 2B and 2D are circuit symbols for the transistor 130. FIGS. 2C and 2E are diagrams illustrating the Id-Vg characteristics of the transistor 130. The horizontal axis of FIGS. 2C and 2E represents the potential difference (gate voltage Vg) between the gate and source of the transistor 130, and the vertical axis represents the current (drain current Id) flowing between the drain and source according to Vg, expressed in logarithm. FIGS. 3A to 3D are circuit diagrams illustrating the method for driving the semiconductor device 500. In addition, in FIGS. 2A, 2B, 2D, and 3A to 3D, a positive potential Vbg is indicated as "+Vbg," and a negative potential Vbg is indicated as "-Vbg."

[0061] In this specification, a positive potential is a potential higher than a reference potential, and a negative potential is a potential lower than the reference potential. That is, the reference potential is set to 0V in this specification.

[0062] 2C and 2E, the Id-Vg characteristics 131 indicated by the dashed lines are Id-Vg characteristics when a reference potential is supplied to the back gate of the transistor 130.

[0063] First, a case where a positive potential is supplied to the node SN as the potential Vbg will be described. In a period T1, the switch 105 is turned on (ON), and the potential Vbg is generated by the potential generation circuit 101. The potential Vbg is also supplied from the potential generation circuit 101 to the wiring 111. Here, a positive potential (+Vbg) is supplied as the potential Vbg. A potential H is also supplied from the control signal output circuit 102 to the wiring 112. Since the wiring 112 is connected to the gate of the transistor 140, the transistor 140 is turned on, and the potential Vbg is supplied from the wiring 111 to the node SN via the source and drain of the transistor 140. Therefore, +Vbg is supplied to the back gate of the transistor 130 as the potential Vbg (see FIG. 3A).

[0064] When +Vbg is supplied as the potential Vbg to the back gate of the transistor 130 (see FIG. 2B), the Id-Vg characteristics of the transistor 130 shift in the negative direction as shown by the solid line in FIG. 2C. That is, the threshold voltage of the transistor 130 shifts in the negative direction. The negative shift of the threshold voltage allows a high on-state current to be obtained even with the same Vg as before the shift. Note that the amount of shift in the threshold voltage can be controlled by the absolute value of the potential Vbg.

[0065] In the period T2, the potential L is supplied to the wiring 112. Then, the transistor 140 is turned off, the node SN is brought into a floating state (electrically floating state), and the potential of the node SN is held. After that, the switch 105 is turned off to stop the power supply to the potential generation circuit 101. Therefore, the supply of the potential Vbg to the wiring 111 is stopped (see FIG. 3B ). The semiconductor device according to one embodiment of the present invention does not need to constantly supply a potential to the node SN, and therefore the operation of the potential generation circuit 101 can be stopped in the period T2. Therefore, the power consumption of the semiconductor device can be reduced.

[0066] Depending on the electrical characteristics of the transistor 140, the potential of the node SN may gradually change. In such a case, the potential Vbg can be resupplied (also referred to as "recharge") to the node SN in the period T3. Note that recharging may be performed at regular intervals as needed. Recharging at regular intervals can improve the reliability of the semiconductor device.

[0067] Furthermore, by using a transistor with low off-state current as the transistor 140, the recharge interval can be lengthened, thereby reducing the power consumption of the semiconductor device.

[0068] Next, a case where a negative potential (−Vbg) is supplied to the node SN as the potential Vbg will be described. In the period T4, the switch 105 is turned on, and the potential Vbg is generated by the potential generation circuit 101. The potential Vbg is supplied from the potential generation circuit 101 to the wiring 111. Here, −Vbg is supplied as the potential Vbg. A potential H is supplied from the control signal output circuit 102 to the wiring 112. Since the wiring 112 is connected to the gate of the transistor 140, the transistor 140 is turned on, and the potential Vbg is supplied from the wiring 111 to the node SN through the source and drain of the transistor 140. Therefore, −Vbg is supplied as the potential Vbg to the back gate of the transistor 130 (see FIG. 3C ).

[0069] When −Vbg is supplied as the potential Vbg to the back gate of the transistor 130 (see FIG. 2D ), the Id-Vg characteristics of the transistor 130 shift in the positive direction, as shown by the solid line in FIG. 2E . That is, the threshold voltage of the transistor 130 shifts in the positive direction. The positive shift of the threshold voltage allows the transistor 130 to be more reliably off even with the same Vg as before the shift.

[0070] In the period T5, the potential L is supplied to the wiring 112. Then, the transistor 140 is turned off, the node SN is brought into a floating state, and the potential of the node SN is held (see FIG. 3D ). By holding the potential of the node SN, the operation of the potential generating circuit 101 can be stopped after the transistor 140 is turned off. In other words, there is no need to constantly supply a potential to the node SN, which leads to reduced power consumption of the semiconductor device.

[0071] In addition, similarly to the period T3, the node SN can be recharged to the potential Vbg in the period T6.

[0072] This completes the description of the example of the method for driving the semiconductor device shown in FIG. 1A.

[0073] In a semiconductor device according to one embodiment of the present invention, the transistor 140 controls power supply from the potential generating circuit 101 to the back gate of the transistor 130. With this configuration, the potential of the back gate of the transistor 130 can be held when the transistor 140 is off, and the operation of the potential generating circuit 101 can be stopped intermittently. Therefore, the power consumption of the semiconductor device can be reduced.

[0074] A transistor with a small off-state current is used as the transistor 140. For example, the drain current (also referred to as "cutoff current") when Vg is 0 V is preferably smaller than the cutoff current of the transistor 130. For example, by making the ratio of the channel length L to the channel width W (also referred to as the L / W ratio) of the transistor 140 larger than the L / W ratio of the transistor 130, the cutoff current of the transistor 140 can be smaller than the cutoff current of the transistor 130.

[0075] 1B , a transistor having a back gate can be used as the transistor 140. By using a transistor having a back gate as the transistor 140 and connecting the gate and the back gate, the on-state current of the transistor 140 can be increased. Therefore, the rate at which the potential Vbg is supplied to the node SN can be increased.

[0076] 4A, by connecting a plurality of potential generating circuits 101 to the wiring 111 via switches, a plurality of different potentials can be supplied to the node SN of the holding circuit 150. In the semiconductor device 510 shown in FIG. 4A, an example is shown in which the potential generating circuit 101A is connected to the wiring 111 via a switch 103A, and the potential generating circuit 101B is connected to the wiring 111 via a switch 103B.

[0077] 4A shows an example in which VDD is supplied to the potential generating circuit 101A via a switch 105A and VDD is supplied to the potential generating circuit 101B via a switch 105B. Note that it is also possible to control the supply of VDD to the potential generating circuit 101A and the potential generating circuit 101B by a single switch 105.

[0078] By turning on the switch 103A and turning off the switch 103B, the output of the potential generator circuit 101A can be supplied to the wiring 111. By turning on the switch 103B and turning off the switch 103A, the output of the potential generator circuit 101B can be supplied to the wiring 111. Note that the number of potential generator circuits 101 and switches 103 connected to the wiring 111 is not limited to one or two. The number of switches 103 may be determined according to the number of potential generator circuits 101. By providing a plurality of potential generator circuits 101 connected to the wiring 111, a plurality of threshold voltages of the transistor 130 can be set.

[0079] 4B , it is preferable to divide the functional circuit 100 into a plurality of regions 160, and provide the potential generating circuit 101, the control signal output circuit 102, the wirings 111, and the wirings 112 for each region 160. By providing the potential generating circuit 101 for each region 160, the threshold voltage of the transistor 130 can be made different for each region 160. Therefore, an optimal threshold voltage can be set for each region 160.

[0080] 4B shows an example in which the other of the source and the drain of the transistor 140 included in the first holding circuit 150 is connected to the potential generation circuit 101[1] through a wiring 111[1], and the gate is connected to the control signal output circuit 102[1] through a wiring 112[1]. Also, FIG. 4B shows an example in which the other of the source and the drain of the transistor 140 included in the i-th (i is an integer of 2 to n) holding circuit 150 is connected to the potential generation circuit 101[2] through a wiring 111[2], and the gate is connected to the control signal output circuit 102[2] through a wiring 112[2]. When the control signal output circuit 102 has a function of outputting a plurality of signals, one of the control signal output circuit 102[1] or the control signal output circuit 102[2] can be omitted.

[0081] In Figure 4B, the i-th holding circuit 150 is shown as holding circuit 150[i], the transistor 130 included in holding circuit 150[i] is shown as transistor 130[i], the transistor 140 included in holding circuit 150[i] is shown as transistor 140[i], and the node SN included in holding circuit 150[i] is shown as node SN[i].

[0082] The potential generating circuit 101[1] is supplied with VDD via the switch 105[1]. The potential generating circuit 101[2] is supplied with VDD via the switch 105[2]. The potential generating circuits 101[1] and 101[2] are supplied with VSS.

[0083] <Structure Example of Transistor> A structure example of a transistor 200 that can be used as the transistor 130 and the transistor 140 will be described with reference to FIGS. 5A to 5E and 6 .

[0084] FIG. 5A is a plan view of the transistor 200. FIGS. 5B and 6 are cross-sectional views taken along the dashed-dotted line A1-A2 in FIG. 5A. FIG. 6 is an enlarged view of FIG. 5B, illustrating an example of the configuration of each layer in more detail. FIG. 5C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 5A. FIG. 5D is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIGS. 5B and 5C. FIG. 5D can also be considered a cross-sectional view of the XY plane including the insulating layer 280a. FIG. 5E is a cross-sectional view taken along the dashed-dotted line A7-A8 in FIGS. 5B and 5C. FIG. 5E can also be considered a cross-sectional view of the XY plane including the conductive layer 255. Note that some elements are omitted in the plan view of FIG. 5A for clarity. Some elements may also be omitted in the subsequent plan views.

[0085] 5A to 5E and 6 includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, and an insulating layer 280b over the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0086] The transistor 200 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 255 on the insulating layer 280a, a conductive layer 240a on the insulating layer 280b, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, a conductive layer 265a on the insulating layer 250, and a conductive layer 265b on the conductive layer 265a.

[0087] In this specification, the conductive layers 220a and 220b may be collectively referred to as the conductive layers 220. The conductive layers 240a and 240b may be collectively referred to as the conductive layers 240. The conductive layers 265a and 265b may be collectively referred to as the conductive layers 265.

[0088] In the transistor 200, the semiconductor layer 230 functions as a semiconductor layer including a channel formation region, the conductive layer 265 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer. The conductive layer 265 also functions as a gate wiring.

[0089] When the conductive layer 265 is used as a gate electrode, the conductive layer 255 functions as a back gate electrode. In this case, the insulating layer 250 functions as a gate insulating layer, and the insulating layer 235 functions as a back gate insulating layer. Note that when the conductive layer 265 is used as a back gate electrode, the conductive layer 255 functions as a gate electrode.

[0090] The transistor 200 has a structure in which the channel formation region is electrically surrounded by the electric field of the conductive layer 255 that can function as a gate electrode, and therefore can be said to have a type of GAA (Gate All Around) structure.

[0091] The semiconductor layer 230 has a region overlapping with the conductive layer 255 with the insulating layer 235 interposed therebetween and a region overlapping with the conductive layer 265 with the insulating layer 250 interposed therebetween. At least one of these regions functions as a channel formation region of the transistor 200. One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0092] As shown in FIGS. 5B and 5C, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0093] The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 220b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 220b. Specifically, the conductive layer 220b has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. 5B and the like, the side surface of the first recess is aligned with the side surface of the insulating layer 235 on the semiconductor layer 230 side, and the side surface of the second recess is aligned with the side surface of the insulating layer 280a or the like on the opening 290 side. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0094] The opening 290 overlaps with the recess of the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220b, and the side surfaces of the opening 290 include the side surfaces of the recess of the conductive layer 220b, the side surfaces of the insulating layer 280a, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 280b, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b.

[0095] The opening 290 includes an opening in the insulating layer 280a, an opening in the conductive layer 255, an opening in the insulating layer 280b, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, the opening in the region where the insulating layer 280a overlaps with the conductive layer 220a is part of the opening 290, the opening in the region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the insulating layer 280b overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and the opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the opening 290 in plan view may differ depending on the layer. When the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0096] At least some of the components of the transistor 200 are disposed within the opening 290. Specifically, the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265 are each disposed such that at least a portion of each is located within the opening 290.

[0097] The insulating layer 235 has a region located between the semiconductor layer 230 and the conductive layer 255. The semiconductor layer 230 has a region in contact with the insulating layer 235 within the opening 290.

[0098] 5B and other drawings, insulating layer 235 has a region in contact with the bottom surface of the second recess of conductive layer 220 and a region in contact with the side surface of the second recess of conductive layer 220. Furthermore, insulating layer 235 has, within opening 290, a region in contact with the side surface of insulating layer 280a, a region in contact with the side surface of conductive layer 255, a region in contact with the side surface of insulating layer 280b, a region in contact with the side surface of conductive layer 240a, and a region in contact with the side surface of conductive layer 240b. Semiconductor layer 230 has a region in contact with the bottom surface of the first recess of conductive layer 220, a region in contact with the side surface of the first recess of conductive layer 220, a region in contact with insulating layer 235, and a region in contact with the top surface of conductive layer 240b. The insulating layer 250 has a region located inside the semiconductor layer 230 within the opening 290 , and the conductive layer 265 a has a region located inside the insulating layer 250 within the opening 290 .

[0099] The insulating layer 235 is provided along at least a portion of the side surface of the opening 290. Furthermore, the portions of the semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290. Specifically, the semiconductor layer 230 is provided so as to cover the bottom and side surfaces of the opening 290, and the insulating layer 250 is provided so as to cover the semiconductor layer 230. Then, the conductive layer 265a is provided so as to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 290.

[0100] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 has a region located inside the opening 290. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 265 inside the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller. Figures 5B and 5C show an example in which the conductive layer 265 has a two-layer structure, in which part of the conductive layer 265a is provided inside the opening 290, and the conductive layer 265b over the conductive layer 265a is provided so as to overlap with the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, both the conductive layer 265a and the conductive layer 265b may be located inside the opening 290.

[0101] By providing a recess in the conductive layer 220b at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 265a in the opening 290 can be lower than the height of the top surface of the conductive layer 220b that is in contact with the insulating layer 280a, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided can be used as the reference.

[0102] 6 , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220b that contacts the insulating layer 280a is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the contact area between the side surface of the conductive layer 220b and the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220b and the semiconductor layer 230. This prevents a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220b and the semiconductor layer 230. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 within the opening 290.

[0103] 6, the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 265a, and more preferably, is greater than the shortest distance Tb. This allows an electric field from the conductive layer 265a to be applied to the entire region between the source and drain regions of the semiconductor layer 230. That is, an electric field from the conductive layer 265a is applied to the entire channel formation region of the semiconductor layer 230, thereby increasing the on-state current of the transistor 200. This improves the electrical characteristics of the transistor 200. Furthermore, a gate electric field is more likely to be applied to the region of the semiconductor layer 230 in contact with the conductive layer 220b, further increasing the on-state current of the transistor 200. Whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. The shortest distance Tb can be determined based on the bottom surface of the conductive layer 265a within the opening 290.

[0104] The semiconductor layer 230 contacts the bottom and side surfaces of the recessed portion of the conductive layer 220b and the top surface of the conductive layer 240b. The recessed portion of the conductive layer 220b increases the area where the semiconductor layer 230 contacts the conductive layer 220b. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0105] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 230, a conductive material containing oxygen is preferably used for the conductive layer 220b, which can reduce contact resistance between the semiconductor layer 230, which is an oxide semiconductor, and the conductive layer 220b.

[0106] Since a conductive material containing oxygen has low contact resistance with an oxide semiconductor, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is preferably used for a layer in the stacked structure that has the largest contact area with the semiconductor layer 230, which is an oxide semiconductor. For this reason, for example, a conductive material containing oxygen is preferably used for the conductive layer 220b and the conductive layer 240b.

[0107] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that is closest to a channel formation region, the on-state current of a transistor including an oxide semiconductor for the semiconductor layer 230 can be increased. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0108] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an "oxide conductor").

[0109] 5B shows a configuration in which the ends of the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 can be manufactured in the same process using the same mask. Therefore, the number of masks required to manufacture a semiconductor device can be reduced. Note that any one of the ends of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b may be located inside or outside the other in the X or Y direction.

[0110] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. Furthermore, it is preferable that the conductive layer 240 is not located inside the opening 290 of the insulating layer 280b or the like. That is, it is preferable that the conductive layer 240 does not have a region in contact with the side surface of the insulating layer 280b within the opening 290. With this configuration, the opening 290 can be formed simultaneously in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a. Furthermore, if the side surfaces of the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a are aligned within the opening 290, the film thickness distribution of the insulating layer 235, the semiconductor layer 230, and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the insulating layer 235, the semiconductor layer 230, and the like from being separated by a step or the like between the conductive layer 240 and the insulating layer 280b.

[0111] 5B and 5C show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 are flush (or may be said to be aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280b in the opening 290 may differ from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280b in the opening 290. This configuration improves the coverage of the semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 and reduces defects such as voids. Furthermore, when the insulating layer 280a and the insulating layer 280b each have a stacked structure, the inclination of the side surface of each layer may differ within the opening 290. Similarly, when the conductive layer 240 has a stacked structure, the inclination of the side surface of each layer within the opening 290 may differ.

[0112] An oxide semiconductor is preferably used for the semiconductor layer 230 in which a channel is formed. In this specification, a transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed is also referred to as an "OS transistor." An oxide semiconductor has a band gap of 2 eV or more and therefore has an extremely small off-state current. Therefore, by using an OS transistor as the transistor 140, data written to the node SN can be held for a long period of time.

[0113] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, their off-state current hardly increases even in high-temperature environments. Specifically, their off-state current hardly increases even in temperatures ranging from room temperature to 200° C. Furthermore, their on-state current is unlikely to decrease even in high-temperature environments. Furthermore, OS transistors have a high withstand voltage between the source and drain. Therefore, semiconductor devices using OS transistors operate stably and exhibit high reliability even in high-temperature environments.

[0114] Furthermore, the electrical characteristics of an OS transistor are less susceptible to change due to radiation such as cosmic rays. That is, soft errors due to radiation are less likely to occur and the OS transistor has high reliability. By using an OS transistor as the transistor 140, a highly reliable semiconductor device can be achieved.

[0115] On the other hand, in an OS transistor, oxygen vacancies (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0116] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0117] As described above, the semiconductor layer 230 is provided inside the opening 290. The semiconductor layer 230 has a region connected to the conductive layer 220 and a region connected to the conductive layer 240. The transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located on the bottom and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located on the top, and thus current flows vertically. In other words, a channel is formed along the side surface of the opening 290. Therefore, the semiconductor layer 230 of the transistor 200 has a region along the side surface of the insulating layer 280b, a region along the side surface of the conductive layer 255, and a region along the side surface of the insulating layer 280a.

[0118] That is, the transistor 200 is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. The source region and the drain region of the transistor 200 are arranged at different heights. In other words, the source region and the drain region of the transistor 200 are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0119] A vertical transistor can occupy a smaller area than a conventional transistor (e.g., a planar transistor) in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, by using a vertical channel transistor, the area occupied by a semiconductor device can be reduced. By using a vertical channel transistor in a semiconductor device, the area of ​​the semiconductor device can be reduced and high integration can be achieved.

[0120] The positional relationship of each layer in the opening 290 will be described with reference to Figures 5D and 5E. The insulating layer 235 is in contact with the outer surface of the semiconductor layer 230. The conductive layer 255 surrounds the entire periphery of the semiconductor layer 230 via the insulating layer 235. The insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The semiconductor layer 230 surrounds the entire periphery of the conductive layer 265a via the insulating layer 250. Therefore, the channel formation region of the transistor 200 can be formed over the entire outer surface of the semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235). Note that Figure 5E can also be considered a cross-sectional view in the XY plane including the channel formation region of the semiconductor layer 230.

[0121] The channel length of a transistor can be regarded as the distance between the source region and the drain region. That is, the channel length of the transistor 200 can be determined by the thicknesses of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, and the like over the conductive layer 220. That is, the channel formation region of the semiconductor layer 230 can be said to have a region overlapping with the side surface of the insulating layer 280a, a region overlapping with the side surface of the conductive layer 255, and a region overlapping with the side surface of the insulating layer 280b.

[0122] Since the transistor 200 includes the conductive layer 255 that functions as a back gate, the threshold voltage of the transistor 200 can be controlled by the potential applied to the conductive layer 255. In this case, a portion of the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween is most susceptible to the influence of the conductive layer 255. Therefore, in FIG. 6 , the semiconductor layer 230 is shown divided into three regions: a region 230n+, a region 230n−, and a region 230i. The region 230i corresponds to the portion of the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween.

[0123] The region 230n+ is formed in the semiconductor layer 230 in a region in contact with the conductive layer 240b or the conductive layer 220b and in the vicinity thereof, and can be called a source region or a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0124] The region 230i is a region in the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 265a with the insulating layer 250 interposed therebetween. The region 230i functions as a channel formation region. The channel formation region is preferably controlled to be i-type (intrinsic) or substantially i-type by a potential applied to the conductive layer 255.

[0125] The region 230n- is preferably a region having a higher resistance than the region 230n+ and a lower resistance than the region 230i. However, if there is a high-resistance region between the region 230i and the region 230n+, the on-current of the transistor 200 may decrease. By making the region 230n- a relatively low-resistance region, the on-current of the transistor 200 may be increased. Note that the region 230n- may also function as a channel formation region.

[0126] As described above, when the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be referred to as length L1. On the other hand, since the region 230n- has a lower resistance than the region 230i, the channel formation region of the transistor 200 can also be regarded as the region 230i that is controlled by the conductive layer 255 to become a high-resistance region. In this case, the channel length of the transistor 200 can be regarded as length L0 of the region 230i, which is shorter than length L1. In this case, length L0 can also be referred to as the effective channel length of the transistor 200.

[0127] When the resistance of the region 230n− is low and the effective channel length of the transistor is short, the transistor tends to have normally-on characteristics. On the other hand, the transistor of one embodiment of the present invention has a back gate. By supplying a potential equal to or lower than the source potential or a potential equal to or lower than 0 V (preferably a negative potential) to the back gate, the threshold voltage of the transistor can be shifted in the positive direction, thereby making the transistor normally-off. As a result, the transistor of one embodiment of the present invention can have both a large on-state current and normally-off characteristics.

[0128] In the transistor of one embodiment of the present invention, one of the conductive layer 255 and the conductive layer 265 is used as a gate, and the other is used as a back gate. Note that by using the conductive layer 265, which has a wider region facing the semiconductor layer 230 than the conductive layer 255, as the gate, a gate electric field can be applied to the semiconductor layer 230 more efficiently, which can improve the electrical characteristics of the transistor in some cases.

[0129] In a planar transistor, the channel length is limited by the exposure limit of photolithography. However, in a vertical transistor, the channel length can be set by the film thickness of the insulating layer 280a and the insulating layer 280b. Therefore, the channel length of the transistor 200 can be made into a very fine structure (e.g., 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor 200, thereby improving frequency characteristics. Since the channel length of a vertical transistor can be easily reduced, it is easy to reduce the on-state current (increase the on-state resistance). By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0130] As shown in FIG. 5D , the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are concentrically arranged. Therefore, the side surface of the central conductive layer 265a faces the side surface of the semiconductor layer 230 via the insulating layer 250. That is, in a plan view, the entire periphery of the semiconductor layer 230 forms a channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the outer periphery of the semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view). FIGS. 5B to 5E show the width D of the opening 290, and FIG. 5E shows the channel width W of the transistor 200. Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0131] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 255 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 255, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b on the opening 290 side may be used as the width D. Furthermore, the width of the opening 290 at the highest position in the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths can be used as the width D.

[0132] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided within the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π."

[0133] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0134] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. As a result, the distance between the conductive layer 255 and the semiconductor layer 230 and the distance between the conductive layer 265a and the semiconductor layer 230 are approximately uniform, and therefore, a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0135] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 5A and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0136] 7A to 7D show a structural example of a transistor 201, which is a variation of the transistor 200. Like the transistor 201 shown in FIGS. 7A to 7D , a structure without the conductive layer 255 functioning as a gate or a back gate is also possible. FIG. 7A is a plan view of the transistor 201. FIGS. 7B and 6 are cross-sectional views taken along the line A1-A2 indicated by the dashed-dotted line in FIG. 7A . FIG. 6 is an enlarged view of FIG. 7B , illustrating a structural example of each layer in more detail. FIG. 7C is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in FIG. 7A . FIG. 7D is a cross-sectional view taken along the line A5-A6 indicated by the dashed-dotted line in FIGS. 7B and 7C . FIG. 7D can also be considered a cross-sectional view of the XY plane including the insulating layer 280a.

[0137] Furthermore, since the conductive layer 255 is not provided in the transistor 201, the formation of the insulating layer 235 is also unnecessary. By not providing the conductive layer 255 and the insulating layer 235, productivity of the transistor 201 can be increased. Furthermore, since the conductive layer 255 is not provided in the transistor 201, the insulating layer 280a and the insulating layer 280b can be formed as a single insulating layer. This can increase productivity of the transistor 201.

[0138] <Constituent Materials of Semiconductor Device> Materials that can be used for semiconductor devices such as transistors, memory cells, memory strings, and memory devices according to one embodiment of the present invention are described below. Note that each layer included in a semiconductor device according to one embodiment of the present invention may have a single-layer structure or a stacked-layer structure. FIGS. 5B, 5C, 7B, and 7C show examples in which the conductive layer 220a has a single-layer structure. FIG. 6 shows an example in which the conductive layer 220a has a stacked-layer structure.

[0139] [Semiconductor Layer 230] As described above, the semiconductor layer 230 has a channel formation region. The semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 can have a stacked structure of two or more layers.

[0140] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0141] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 230, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer 230, the off-state current of the transistor can be reduced. Since an OS transistor has a small off-state current, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, since the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0142] For an oxide semiconductor that can be used for a semiconductor layer of a transistor of one embodiment of the present invention, refer to the description in Embodiment 3. Detailed description thereof will be omitted here.

[0143] It should be noted that the semiconductor device of this embodiment can also be applied to transistors using other semiconductor materials in the channel formation region. Examples of such other semiconductor materials include semiconductors made of simple elements and compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0144] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0145] The semiconductor layer of a transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0146] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0147] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 235, insulating layer 250, insulating layer 280a, insulating layer 280b, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In addition, an organic insulating film can also be used for the insulating layers of a semiconductor device.

[0148] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0149] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 235 and insulating layer 250, enables lower voltages during transistor operation while maintaining the physical film thickness. It also enables thinner equivalent oxide thickness (EOT) for the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer that functions as an interlayer film can reduce parasitic capacitance between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0150] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0151] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having voids. These silicon oxides may contain nitrogen.

[0152] Furthermore, materials that can have ferroelectricity can be used for the insulating layer 235, the insulating layer 250, etc. Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide doped with element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide doped with element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). The ratio of the number of zirconium atoms to the number of element J2 atoms can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ It is also possible to use piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0153] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0154] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0155] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, can also be used.

[0156] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0157] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0158] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0159] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystalline structure is preferred because it exhibits ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal systems. Furthermore, the insulating layer may have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0160] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0161] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0162] Specifically, examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0163] Furthermore, an insulating layer provided in contact with or near an oxide semiconductor layer, such as the insulating layer 235 or the insulating layer 250, is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers in which a region containing excess oxygen is easily formed include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0164] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0165] In addition, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230.

[0166] Furthermore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 provided on the outer side of the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the semiconductor layer 230 can be suppressed.

[0167] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0168] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, OH − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0169] For example, it is preferable to use a silicon nitride film as the insulating layer 210 .

[0170] When an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 280a and the insulating layer 280b each preferably have the above-mentioned barrier insulating layer against hydrogen. The insulating layer 280a and the insulating layer 280b are provided so as to surround the semiconductor layer 230. The insulating layer 280a and the insulating layer 280b provided on the outer side of the semiconductor layer 230 have barrier properties against hydrogen, thereby suppressing diffusion of hydrogen into the semiconductor layer 230. For example, the insulating layer 280a and the insulating layer 280b each preferably have one or both of an aluminum oxide film and a silicon nitride film.

[0171] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280 a and the insulating layer 280 b, oxygen can be extracted from the semiconductor layer 230, and the formation of an excessive amount of oxygen vacancies in the semiconductor layer 230 can be suppressed.

[0172] When an oxide semiconductor is used for the semiconductor layer 230, using silicon nitride for the insulating layers 280a and 280b can prevent excess oxygen from being supplied to the semiconductor layer 230. Therefore, excess oxygen can be prevented from being contained in the channel formation region of the semiconductor layer 230, which can improve the reliability of the transistor 200.

[0173] The insulating layer 280a and the insulating layer 280b preferably include the above-described oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.

[0174] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentrations in the insulating layers 280a and 280b can be reduced. By depositing at least some of the layers that make up the insulating layers 280a and 280b in this manner, oxygen can be supplied from the insulating layers 280a and 280b to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0175] When an oxide semiconductor is used for the semiconductor layer 230, the concentrations of impurities such as water and hydrogen in the insulating layers 280a and 280b are preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230.

[0176] Note that the thicknesses of the insulating layers 280a and 280b on the conductive layer 220 affect the channel length of the transistor 200, and therefore the thicknesses of the insulating layers 280a and 280b are appropriately set in accordance with the design value of the channel length of the transistor 200.

[0177] For example, the insulating layers 280a and 280b preferably have a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film. Alternatively, the insulating layers 280a and 280b preferably have a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order. For example, the insulating layers 280a and 280b preferably have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order.

[0178] When an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0179] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with amorphous structures have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, adding silicon to these oxides can achieve an amorphous structure. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some areas.

[0180] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0181] When an oxide semiconductor is used for the semiconductor layer 230 and the gate insulating layer has a stacked structure, a layer in contact with the semiconductor layer 230 preferably has a function of capturing and fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the semiconductor layer 230. In addition, the layer preferably has an amorphous structure.

[0182] By making the layer amorphous, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 250 uniform, and it is possible to reduce portions with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer 250. It is also possible to make the film thickness distribution of the film provided on the insulating layer 250 uniform.

[0183] Furthermore, by suppressing the formation of grain boundaries in the layer, leakage current due to defect levels in the grain boundaries can be reduced, and the insulating layer 250 can function as an insulating film with a small leakage current.

[0184] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It is also possible to reduce the EOT of the gate insulating layer.

[0185] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0186] Furthermore, when an oxide semiconductor is used for the semiconductor layer 230, the above-described barrier insulating layer against hydrogen is preferably used for the insulating layer 250. By using a barrier insulating layer against hydrogen for the insulating layer 250, it is possible to suppress diffusion of impurities contained in the conductive layer 265 into the semiconductor layer 230. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Furthermore, the insulating layer 250 preferably has an insulating layer with a heat-stable structure, such as silicon oxide or silicon oxynitride.

[0187] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0188] Furthermore, the insulating layer 250 preferably has an insulating layer with a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0189] Furthermore, the insulating layer 250 preferably has an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0190] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0191] The use of a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 that is in contact with the conductive layer 265 can suppress oxidation of the conductive layer 265. Furthermore, when an oxide semiconductor is used for the semiconductor layer 230, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 265 and forming oxygen vacancies in the semiconductor layer 230.

[0192] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon.

[0193] The layer of the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280b. The layer has oxygen barrier properties, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0194] Each layer constituting the insulating layer 250 is preferably a thin film. For example, by setting the thickness of each insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0195] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0196] When an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a three-layer structure in which, from the semiconductor layer 230 side, a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having barrier properties against hydrogen and oxygen are stacked in this order. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant for the first insulating layer. The first insulating layer is a layer in contact with the semiconductor layer 230. Using an oxide for the first insulating layer can supply oxygen to the semiconductor layer 230. Furthermore, providing the third insulating layer can suppress diffusion of oxygen contained in the first insulating layer into the conductive layer 265, thereby suppressing oxidation of the conductive layer 265. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 230 can be suppressed.

[0197] When an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a four-layer structure in which, from the semiconductor layer 230 side, a fourth insulating layer having a barrier property against oxygen, a first insulating layer including a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. The first to third insulating layers can have the same structure as the layers used in the three-layer structure described above. The fourth insulating layer is in contact with the semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, making it suitable for the fourth insulating layer in contact with the semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0198] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0199] Furthermore, it is preferable to use a three-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the semiconductor layer 230 side as the insulating layer 250. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0200] Note that it is preferable to use an insulating layer having the above-mentioned function of capturing or fixing hydrogen as the insulating layer 210. This allows hydrogen in the semiconductor layer 230 to diffuse into the insulating layer 210 via the conductive layers 220a and 220b, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. For example, the insulating layer 210 can have a two-layer structure of a silicon nitride film and a hafnium silicate film on the silicon nitride film.

[0201] The insulating layer 235 can also be called a sidewall, a sidewall insulating layer, a side surface protection layer, or the like.

[0202] When an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 235 preferably includes an insulating layer having a region containing oxygen that is released by heating, thereby enabling oxygen to be supplied from the insulating layer 235 to the semiconductor layer 230. For example, the insulating layer 235 is preferably made of silicon oxide or silicon oxynitride.

[0203] The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0204] Furthermore, the insulating layer 235 may be made of the above-mentioned material that can have ferroelectricity.

[0205] For example, the insulating layer 235 can have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, it is preferable to provide a silicon oxide film on the semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side. This allows oxygen to be efficiently supplied to the semiconductor layer 230 and prevents impurities such as hydrogen from diffusing into the semiconductor layer 230. Alternatively, it is also possible to provide a silicon nitride film on the semiconductor layer 230 side and a silicon oxide film on the conductive layer 255 side.

[0206] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 265, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. It is also possible to use semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0207] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0208] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0209] In addition, it is possible to use a plurality of stacked conductive layers formed from the above-mentioned materials. For example, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. In addition, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. In addition, it is possible to use a stacked structure by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0210] When a metal oxide is used for the channel formation region of a transistor, a conductive layer that functions as a gate electrode, such as the conductive layer 255 or the conductive layer 265, preferably has a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0211] When an oxide semiconductor is used for the semiconductor layer 230, the conductive layer 220 and the conductive layer 240 are each conductive layers in contact with the semiconductor layer 230. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0212] By using a conductive material containing oxygen for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0213] 6 shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. In this case, for example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 220a1, a highly conductive material as the conductive layer 220a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220b. Specifically, for example, it is preferable to use titanium nitride as the conductive layer 220a1, tungsten as the conductive layer 220a2, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) as the conductive layer 220b. In this case, the titanium nitride is in contact with the insulating layer 210, and the oxide conductor is in contact with the semiconductor layer 230, which is an oxide semiconductor. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 230, and therefore the current path between the source and drain can be shortened, thereby increasing the on-state current of the transistor. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, the insulating layer 210 can prevent the conductive layer 220 from being excessively oxidized. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0214] 6 shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240b and a material having higher conductivity than the conductive layer 240b for the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 240b and tungsten for the conductive layer 240a. It is also possible to use ruthenium, titanium nitride, tantalum nitride, or the like for the conductive layer 240a.

[0215] Of the conductive layer 240, the layer that is mainly in contact with the semiconductor layer 230 is the conductive layer 240b. When an oxide semiconductor is used for the semiconductor layer 230, it is preferable to use an oxide conductor for the conductive layer 240b, since the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, it is preferable to use a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240, since the conductivity of the conductive layer 240 can be increased.

[0216] Note that a conductive material containing oxygen can be used for the conductive layer 240a, and a material having higher conductivity than that of the conductive layer 240a can be used for the conductive layer 240b. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-current of the transistor can be increased.

[0217] The conductive layer 255 and the conductive layer 265 are preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 255 and the conductive layer 265 are preferably made of a conductive material that is resistant to oxidation, a conductive material that has a function of suppressing oxygen diffusion, or the like. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride, tantalum nitride, etc.) and a conductive material containing oxygen (e.g., ruthenium oxide, etc.). This can suppress a decrease in the conductivity of the conductive layer 255 and the conductive layer 265.

[0218] The conductive layer 265 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive layer 265 can be made of a conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.). Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon can be used. Nitrogen-containing indium gallium zinc oxide can also be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0219] 6 shows an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b over the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0220] The conductive layer 265 may also have a stacked structure of three or more layers, for example, a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0221] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten can be used.

[0222] The conductive layer 255 is preferably made of, for example, tungsten or tantalum nitride.

[0223] [Substrate] When a semiconductor device is provided on a substrate, there are no significant limitations on the material used for the substrate. The material can be determined depending on the purpose, taking into consideration factors such as whether the substrate is light-transmitting or not, and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). It is also possible to use semiconductor substrates, flexible substrates, resin substrates, and the like.

[0224] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0225] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are also substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0226] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0227] By using the above materials for the substrate, a lightweight semiconductor device can be provided.Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided.Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to breakage can be provided.

[0228] Alternatively, it is also possible to use a substrate provided with elements such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0229] Next, a configuration example in which a transistor 200 or a transistor 201 is applied to the holding circuit 150 included in the functional circuit 100 will be described. The holding circuit 150 is also a type of semiconductor device. Fig. 8A shows a schematic perspective view of the holding circuit 150. Fig. 8B is a schematic plan view of the holding circuit 150 shown in Fig. 8A as viewed from the Z direction. Fig. 8C is a cross-sectional view taken along the line B1-B2 indicated by the dashed dotted line in Fig. 8A.

[0230] 8A to 8C show an example in which a transistor 200 is used as the transistor 130 and a transistor 201 is used as the transistor 140. By configuring the holding circuit 150 using vertical transistors, it is possible to reduce the area occupied by the holding circuit 150. Furthermore, by providing the transistor 130 and the transistor 140 so that they overlap, it is possible to further reduce the area occupied by the holding circuit 150.

[0231] 8A to 8C, "AB" and "BL" are added to the reference symbols shown in Figures 5A to 5E, 6, and 7A to 7D to facilitate comparison with the configurations of transistors 200 and 201. Specifically, "AB" is added to the reference symbols of transistor 140 and parts mainly related to transistor 140, and "BL" is added to the reference symbols of transistor 130 and parts mainly related to transistor 130.

[0232] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 130, and the conductive layer 240BL functions as the other of the source electrode and the drain electrode of the transistor 130. The conductive layer 265BL functions as a back gate electrode of the transistor 130, and the conductive layer 255 functions as a gate electrode of the transistor 130. Thus, the insulating layer 250BL functions as a back gate insulating layer of the transistor 130, and the insulating layer 235 functions as a gate insulating layer of the transistor 130. The semiconductor layer 230BL functions as a semiconductor layer including a channel formation region of the transistor 130.

[0233] The conductive layer 240AB functions as the other of the source electrode and the drain electrode of the transistor 140. The conductive layer 265AB functions as the gate electrode of the transistor 130. Thus, the insulating layer 250AB functions as a gate insulating layer of the transistor 140. The semiconductor layer 230AB functions as a semiconductor layer including a channel formation region of the transistor 140.

[0234] The conductive layer 265BL functions not only as a backgate electrode of the transistor 130 but also as one of a source electrode and a drain electrode of the transistor 140. Thus, the conductive layer 265BL functions as a node SN.

[0235] The conductive layer 265BL serves as both the back gate electrode of the transistor 130 and one of the source electrode and drain electrode of the transistor 140, thereby reducing the number of conductive layers included in the holding circuit 150. This reduces the manufacturing cost of a semiconductor device including the holding circuit 150, thereby improving the productivity of the semiconductor device. Furthermore, since the conductive layer 265BL also functions as the node SN, the overlapping of the transistor 130 and the transistor 140 reduces the parasitic capacitance of the node SN. The reduction in the parasitic capacitance of the node SN reduces the time required to supply the potential Vbg to the node SN without increasing the size of the transistor 140. This allows the operating speed of the holding circuit 150 to be increased without increasing power consumption.

[0236] Furthermore, by providing the transistor 130 and the transistor 140 overlapping with each other, the area occupied by the holding circuit 150 can be reduced. Figure 9 shows an example of a cross-sectional configuration corresponding to the functional circuit 100 and the potential supply circuit 120 shown in Figure 1A. By providing the transistor 130 and the transistor 140 overlapping with each other, there may be a region where the channel formation region of the semiconductor layer 230BL and the channel formation region of the semiconductor layer 230AB highly overlap each other. There may also be a region where the conductive layer 220, the conductive layer 265BL, and the conductive layer 265AB overlap each other.

[0237] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0238] (Embodiment 2) In this embodiment, a semiconductor device 550 having a different configuration from the semiconductor device 500, the semiconductor device 510, and the semiconductor device 520 described in the above embodiment will be described. Note that the semiconductor device 550 is a modified example of the semiconductor device 500. Therefore, for matters not described in this embodiment, the descriptions of the other embodiments can be referred to.

[0239] 10A , the back gates of all of the n transistors 130 can be connected to one of the source and the drain of one transistor 140. The configuration of the semiconductor device 550 shown in FIG. 10A eliminates the need to route the wirings 111 and 112, thereby reducing the area occupied by the semiconductor device.

[0240] 10A , it is necessary to increase the on-state current of the transistor 140 in order to supply a potential to the back gates of all of the n transistors 130. The on-state current of the transistor 140 can be increased by shortening the channel length of the transistor, increasing the channel width, or both.

[0241] 11A to 11D show a configuration example of a transistor 202 suitable for the transistor 140 of the semiconductor device 550. Note that the transistor 202 is a modified example of the transistor 200. FIG. 11A is a plan view of the transistor 201. FIG. 11B is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in FIG. 11A. FIG. 11C is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in FIG. 11A. FIG. 11D is a cross-sectional view taken along the line A5-A6 indicated by the dashed-dotted line in FIG. 11C. FIG. 11D can also be considered a cross-sectional view of the XY plane including the insulating layer 280b. Note that to avoid repetition, differences between the transistor 202 and the transistor 200 will be mainly described.

[0242] The transistor 202 has an opening 291 that penetrates the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b and reaches the conductive layer 255. In the transistor 202, a recess is provided in the conductive layer 255. Specifically, the conductive layer 255 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When forming the opening 291, the second recess is provided in the conductive layer 255, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 255. Therefore, in FIG. 11B and other figures, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280b and other layers facing the opening 291.

[0243] The opening 291 overlaps the recess of the conductive layer 255. Here, the bottom of the opening 291 includes the bottom surface of the recess of the conductive layer 255, and the sidewall of the opening 291 includes the side surface of the recess of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0244] The opening 291 corresponds to the opening 290 of the transistor 200. The opening 291 includes an opening in the insulating layer 280b, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, the opening in the region where the insulating layer 280b overlaps with the conductive layer 255 is part of the opening 291, the opening in the region where the conductive layer 240a overlaps with the conductive layer 255 is another part of the opening 291, and the opening in the region where the conductive layer 240b overlaps with the conductive layer 255 is another part of the opening 291. Note that the shape and size of the opening 291 in a plan view may differ depending on the layer. Furthermore, when the top surface shape of the opening 291 is circular, the openings in each layer may or may not be concentric.

[0245] At least some of the components of the transistor 201 are disposed in the opening 291. Specifically, the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265 are disposed so that at least some of them are located in the opening 291.

[0246] The insulating layer 235 has a region located between the semiconductor layer 230 and the conductive layer 255. The semiconductor layer 230 has a region in contact with the insulating layer 235 within the opening 290.

[0247] 11B and other drawings, insulating layer 235 has a region in contact with the bottom surface of the second recess of conductive layer 255 and a region in contact with the side surface of the second recess of conductive layer 255. Furthermore, insulating layer 235 has a region in contact with the side surface of insulating layer 280b, a region in contact with the side surface of conductive layer 240a, and a region in contact with the side surface of conductive layer 240b within opening 291. Semiconductor layer 230 has a region in contact with the bottom surface of the first recess of conductive layer 255, a region in contact with the side surface of the first recess of conductive layer 255, a region in contact with insulating layer 235, and a region in contact with the top surface of conductive layer 240b. Insulating layer 250 has a region located inside semiconductor layer 230 within opening 291, and conductive layer 265a has a region located inside insulating layer 250 within opening 291.

[0248] The channel length L1 of the transistor 202 is determined by the thickness of the insulating layer 280b. That is, it can be said that the channel formation region of the semiconductor layer 230 included in the transistor 202 has a region overlapping with the side surface of the insulating layer 280b. The transistor 202 does not have a backgate. Furthermore, in the transistor 202, the conductive layer 255 functions as one of the source electrode and the drain electrode. Since the transistor 202 does not have a backgate, the insulating layer 235 does not need to be provided, similar to the transistor 201.

[0249] 10B, 12A, and 12B show configuration examples in which the transistor 200 is used as the transistor 130 and the transistor 202 is used as the transistor 140 of the semiconductor device 550 shown in Fig. 10A. Note that Fig. 10B, 12A, and 12B show the connection relationship between the transistor 130[1], the transistor 130[2], and the transistor 140 in the configuration of the semiconductor device 550.

[0250] 10B is a perspective view showing a configuration example of the semiconductor device 550. FIG. 12A is a plan view showing a configuration example of the semiconductor device 550. FIG. 12B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 12A. A part of the conductive layer 255 functions as a back gate electrode of the transistor 130, and another part of the conductive layer 255 functions as one of a source electrode and a drain electrode of the transistor 140.

[0251] The transistor 200 used as the transistor 130 and the transistor 202 used as the transistor 140 have openings 290 (see FIG. 5B ) and 291 (see FIG. 11B ) formed in different steps, but other components can be formed simultaneously in the same step. That is, transistors having different channel lengths and / or channel widths can be formed substantially simultaneously.

[0252] Specifically, the channel length of the transistor 140 can be made shorter than that of the transistor 130. By shortening the channel length of the transistor 140, the on-state current of the transistor 140 increases, and the node SN can be set to a target potential in a short time. Therefore, the operation speed of the semiconductor device 550 can be increased. Furthermore, the reliability of the semiconductor device 550 can be improved.

[0253] Furthermore, the channel width of the transistor 140 can be made longer than the channel width of the transistor 130. Increasing the channel width of the transistor 140 provides the same effect as shortening the channel length of the transistor 140. By shortening the channel length of the transistor 140 and increasing the channel width of the transistor 140, the operating speed and reliability of the semiconductor device 550 can be further improved.

[0254] Furthermore, the transistor 200 and the transistor 202 according to one embodiment of the present invention can be formed substantially simultaneously. Furthermore, the number of layers, such as insulating layers and conductive layers, included in the transistor 202 is smaller than the number of layers included in the transistor 200. Therefore, the transistors 200 and 202, which have the same number of stacked layers as the transistor 200 but different transistor sizes, can be formed. Therefore, a semiconductor device including the transistor 200 and the transistor 202 according to one embodiment of the present invention has high productivity.

[0255] Furthermore, by sharing the conductive layer 255 between the transistors 200 and 202, the connection distance between the transistors 200 and 202 can be shortened. Therefore, the wiring resistance and parasitic capacitance from the transistor 200 to the transistor 202 are reduced, leading to reduced power consumption. In addition, the occupied area is reduced, leading to increased integration of the transistors.

[0256] 12A and 12B show a case where the conductive layer 255 having a region functioning as one of the source electrode or drain electrode of the transistor 140 of the semiconductor device 550 has a region extending along the X direction. Also, in FIG. 12A and 12B, a conductive layer 220 (here, the conductive layer 220[1] and the conductive layer 220[2]) having a region functioning as one of the source electrode or drain electrode of the transistor 130 of the semiconductor device 550 has a region extending along the Y direction.

[0257] 12A and 12B show a case where the conductive layer 265 (here, the conductive layer 265[0]) having a region functioning as the gate electrode of the transistor 140 of the semiconductor device 550 has a region extending along the X direction. Also, FIG. 12A and 12B show a case where the conductive layer 265 (here, the conductive layer 265[1] and the conductive layer 265[2]) having a region functioning as the gate electrode of the transistor 130 of the semiconductor device 550 has a region extending along the Y direction.

[0258] 12A and 12B show a case where a conductive layer 240 (here, conductive layer 240[0]) having a region functioning as the other of the source electrode or drain electrode of the transistor 140 of the semiconductor device 550, and a conductive layer 240 (here, conductive layer 240[1] and conductive layer 240[2]) having a region functioning as the other of the source electrode or drain electrode of the transistor 130 of the semiconductor device 550 have regions extending along the Y direction.

[0259] As described above, the conductive layer 255 has a region that functions as one of the source electrode and the drain electrode of the transistor 140. Therefore, when the channel width of the transistor 130 in the semiconductor device 550 is smaller than the channel width of the transistor 140, the width WB of the conductive layer 220 can be made smaller than the width WA of the conductive layer 255. Therefore, the area occupied by the semiconductor device 550 can be reduced.

[0260] Similarly, the width WD of the conductive layer 240 having a region functioning as the other of the source electrode and the drain electrode of the transistor 130 can be made smaller than the width WC of the conductive layer 240 having a region functioning as the other of the source electrode and the drain electrode of the transistor 140. Thus, the area occupied by the semiconductor device 550 can be reduced.

[0261] Similarly, the width WF of the conductive layer 265 having a region functioning as the gate electrode of the transistor 130 can be made smaller than the width WE of the conductive layer 265 having a region functioning as the gate electrode of the transistor 140. Thus, the area occupied by the semiconductor device 550 can be reduced.

[0262] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0263] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0264] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0265] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0266] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0267] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0268] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0269] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO). Examples of the usable oxide include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0270] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0271] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0272] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements may enhance the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0273] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0274] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0275] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0276] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0277] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0278] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0279] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0280] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0281] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs one or both of a high substrate temperature condition during film formation and an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0282] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0283] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0284] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0285] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0286] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0287] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0288] [Method for Manufacturing Oxide Semiconductor Layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming a semiconductor layer 230a on the layer 229, which is a surface to be formed, by an ALD method, forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a, which is an oxide semiconductor layer, by a sputtering method, and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b, by an ALD method. Furthermore, after forming the semiconductor layer 230, which is an oxide semiconductor layer, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process.

[0289] The layer 229 corresponds to the insulating layer 235, the insulating layer 280, or the like described in the above embodiments. The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide of the semiconductor layer 230.

[0290] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 13A to 13D and 14A to 14D.

[0291] When a metal oxide film is formed by sputtering, damage caused by energy imparted to the substrate by sputtering particles or the like onto the surface on which the film is to be formed can cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, as described below, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0292] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 13A), and then a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 13B).

[0293] In the method for forming an oxide semiconductor layer of one embodiment of the present invention, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to a surface on which the semiconductor layer 230a is formed. This suppresses alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, thereby enabling the semiconductor layer 230 to have higher crystallinity.

[0294] By using the above configuration, the thickness of the alloyed region can be reduced, or made so thin that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 13A and 13B show an example in which no alloyed region is formed between the layer 229 and the semiconductor layer 230a.

[0295] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0296] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0297] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0298] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0299] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0300] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, "near the surface to be formed" refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the surface to be formed of the semiconductor layer 230.

[0301] The CAAC structure near the formation surface can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0302] When the semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 13A , the semiconductor layer 230a may have a region having lower crystallinity than the semiconductor layer 230b.

[0303] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0304] When the semiconductor layer 230b is formed by sputtering, a mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, due to energy imparted to the substrate by sputtering particles or the like during the formation of the semiconductor layer 230b, minute crystalline regions may be formed in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, and at least a portion of the semiconductor layer 230a may be crystallized.

[0305] In forming the semiconductor layer 230b by a sputtering method, it is preferable to heat the substrate. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it is possible to form a metal oxide with high crystallinity in some cases.

[0306] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by ALD (FIG. 13C). For the formation of the semiconductor layer 230c by ALD, the method for forming the semiconductor layer 230a can be referred to.

[0307] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially using the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. Furthermore, it is preferable that the region having the CAAC structure is formed over the entire semiconductor layer 230c.

[0308] Next, a heat treatment step may be performed. This heat treatment step may increase the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. Furthermore, if the region is formed only below the semiconductor layer 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward (FIG. 13D). That is, by performing this heat treatment, a region having the CAAC structure may be formed throughout the entire semiconductor layer 230c.

[0309] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted into CAAC by this heat treatment process ( FIG. 13D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b, which acts as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0310] Furthermore, because the CAAC is formed from the top to the bottom of the semiconductor layer 230a, the CAAC can be formed up to the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0311] 13A to 13D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 13A to 13D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide according to one embodiment of the present invention. As shown in FIGS. 13A to 13D , the semiconductor layers 230a and 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during the formation of the semiconductor layer 230b or after the formation of the semiconductor layer 230c. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during the formation of the semiconductor layer 230c or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect of increasing the crystallinity.

[0312] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the semiconductor layer 230a and the semiconductor layer 230c here) can be increased by using the semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the semiconductor layer 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 14A to 14D illustrate a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c, the present invention is not limited thereto. For example, the structure including the semiconductor layer 230a and the semiconductor layer 230b can also be an AG CAAC.

[0313] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. Fig. 14A shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0314] Furthermore, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Fig. 14B shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Fig. 14C shows a state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized. Fig. 14D shows a state in which the vicinity of the interface of the semiconductor layer 230a with the layer 229 and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0315] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0316] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the semiconductor layer 230, the boundaries between the stacked semiconductor layers 230a, 230b, and 230c may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, a TEM or the like.

[0317] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0318] Furthermore, it is preferable that the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. In this case, for example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0319] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or 230c is small, the crystal structure of the semiconductor layer 230a or 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0320] [Composition of Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, a sputtering method. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the semiconductor layer 230b preferably contains an element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn = 1:1:1 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:1.2 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:0.5 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:2 atomic ratio or a composition thereabout, an In:M:Zn = 4:2:3 atomic ratio or a composition thereabout, an In:M:Zn = 1:3:2 atomic ratio or a composition thereabout, or an In:M:Zn = 1:3:4 atomic ratio or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0321] The semiconductor layer 230b may be configured without the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. It may also be configured with a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0322] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0323] The semiconductor layers 230a and 230c may also be configured without the element M. For example, they may be made of In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. The semiconductor layers 230a and 230c may also be configured with a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, an In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0324] Increasing the zinc content of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby facilitating the formation of CAAC.

[0325] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0326] Alternatively, for example, a metal oxide having a higher Ga content than the semiconductor layer 230b can be used for the semiconductor layer 230a and the semiconductor layer 230c. For example, it is preferable to use a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout for the semiconductor layer 230a and the semiconductor layer 230c, respectively. Increasing the Ga content may result in the band gaps of the semiconductor layer 230a and the semiconductor layer 230c being larger than those of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field-effect mobility.

[0327] In the oxide semiconductor layer of one embodiment of the present invention, even when the semiconductor layers 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the semiconductor layer 230a and the semiconductor layer 230c and the semiconductor layer 230b.

[0328] In particular, even when the semiconductor layers 230 a and 230 c have a high In content, the semiconductor layers can have suitable crystallinity for use as semiconductor layers of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0329] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0330] The semiconductor layers 230a and 230c preferably use a metal oxide having the same composition as that of the semiconductor layer 230b.

[0331] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0332] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed using a combination of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0333] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0334] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0335] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0336] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0337] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0338] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0339] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0340] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0341] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region, starting from the top of the layer 229. Each region is a layer-like region.

[0342] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0343] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0344] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0345] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0346] Embodiment 4 In this embodiment, a structural example of a transistor that can be used as a transistor according to one embodiment of the present invention will be described.

[0347] <Configuration Example of Transistor> A configuration example of a transistor will be described with reference to FIGS. 15 to 19 . FIG. 15A is a plan view of a transistor 600. It is also a schematic perspective view of the transistor 600. Also, FIGS. 15C to 15E are cross-sectional views of the transistor 600. Here, FIG. 15C is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 15A , which is also a cross-sectional view of the transistor 600 in the channel width direction (Y direction). FIG. 15D is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 15A , which is also a cross-sectional view of the transistor 600 in the channel width direction. Also, FIG. 15E is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 15A , which is also a cross-sectional view of the transistor 600 in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the plan view of FIG. 15A and the perspective schematic view of FIG. 15B. Also, FIG. 16A shows an enlarged view of the vicinity of the conductive layer 260 in FIG. 15E. Also, FIG. 16B shows an enlarged view of the vicinity of the semiconductor layer 230 in FIG. 15C.

[0348] The transistor 600 according to this embodiment includes an insulating layer 215 over a substrate (not shown), an insulating layer 216 over the insulating layer 215, an insulating layer 221 over the insulating layer 216, an insulating layer 222 over the insulating layer 221, a semiconductor layer 230 over the insulating layer 222, conductive layers 242a and 242b over the semiconductor layer 230 and the insulating layer 222, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 (conductive layer 260a and conductive layer 260b) over the insulating layer 250. Note that in this specification, the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.

[0349] An insulating layer 275 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that penetrates the insulating layer 280 and the insulating layer 275 and reaches the semiconductor layer 230. In a plan view, the first opening has a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. Therefore, in a plan view, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. The conductive layer 260 also functions as wiring. The insulating layer 250 has a region in contact with the semiconductor layer 230 within the first opening. Furthermore, an insulating layer 282 is provided on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 283 is provided on the insulating layer 282.

[0350] Furthermore, insulating layer 241a is provided in contact with the inner wall of the second opening, which penetrates insulating layers 283, 282, 280, and 275 to reach conductive layer 242a, and conductive layer 245a is provided in contact with insulating layer 241a. Conductive layer 245a has a region in contact with conductive layer 242a at the bottom of the first opening.

[0351] Furthermore, insulating layer 241b is provided in contact with the inner wall of the third opening, which penetrates insulating layers 283, 282, 280, and 275 to reach conductive layer 242b, and conductive layer 245b is provided in contact with insulating layer 241b. Conductive layer 245b has a region in contact with conductive layer 242b at the bottom of the second opening.

[0352] In this specification, the conductive layers 245a and 245b may be collectively referred to as conductive layers 245. The insulating layers 241a and 241b may be collectively referred to as insulating layers 241.

[0353] The semiconductor layer 230 includes a channel formation region of the transistor 600. The conductive layer 260 has a region that functions as a gate electrode of the transistor 600. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 600. In the transistor 600, a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region. A region of the conductive layer 260 that overlaps with the semiconductor layer 230 functions as a gate electrode. A region of the insulating layer 250 where the insulating layer 250 and the semiconductor layer 230 overlap and where the insulating layer 250 and the conductive layer 260 overlap functions as a gate insulating layer.

[0354] The conductive layer 242a has a region functioning as one of a source electrode and a drain electrode of the transistor 600. The conductive layer 245a functions as a plug connected to the conductive layer 242a. The conductive layer 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 600. The conductive layer 245b functions as a plug connected to the conductive layer 242b.

[0355] The semiconductor layer 230 is formed on the insulating layer 222. As shown in FIG. 16B , the semiconductor layer 230 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. Therefore, the semiconductor layer 230 can also be said to have a fin-like shape. A transistor whose semiconductor layer is fin-shaped is also called a "fin transistor," "fin transistor," or "fin transistor."

[0356] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel formation region is defined as length Lx, and the maximum length of the semiconductor layer 230 in the channel formation region in a direction perpendicular to the surface on which the semiconductor layer 230 is formed (for example, the upper surface of the insulating layer 222) is defined as length H. The ratio of length H to length Lx is referred to as the aspect ratio of the semiconductor layer 230.

[0357] The length Lx can also be considered to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be considered to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be read as "height H."

[0358] The aspect ratio of the semiconductor layer 230 is preferably as large as possible without causing the semiconductor layer 230 to collapse during the manufacturing process of the transistor 600. The aspect ratio of the semiconductor layer 230 can be greater than 1 and less than 400, greater than or equal to 2 and less than or equal to 100, greater than or equal to 5 and less than or equal to 40, or greater than or equal to 10 and less than or equal to 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 can be greater than 1 and less than or equal to 400 times, greater than or equal to 2 and less than or equal to 100 times, greater than or equal to 5 and less than or equal to 40 times, or greater than or equal to 10 and less than or equal to 20 times the length Lx of the semiconductor layer 230. For example, the height H can be greater than or equal to 2 and less than or equal to 10 times the length Lx. For example, the length Lx can be greater than or equal to 5 nm and less than or equal to 100 nm, greater than or equal to 5 nm and less than or equal to 50 nm, or greater than or equal to 10 nm and less than or equal to 30 nm. For example, the height H can be 50 nm or more and 2000 nm or less, or 100 nm or more and 1000 nm or less. For example, the height H can be 50 nm or more and 100 nm or less.

[0359] 16B , in a cross-sectional view in the channel width direction, the angle θ between the formation surface of the semiconductor layer 230 on the insulating layer 222 and the side surface of the semiconductor layer 230 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0360] The insulating layer 250, the conductive layer 260, and the conductive layer 242 are provided to cover the semiconductor layer 230 having such an aspect ratio. In the transistor 600, as shown in FIG. 16B , the insulating layer 250 and a portion of the conductive layer 260 are provided so as to sandwich the semiconductor layer 230 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided facing each other with the insulating layer 250 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 each function as a channel formation region. Therefore, compared to when the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 600 is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0361] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 600 can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 600. This allows for miniaturization or high integration of the semiconductor device.

[0362] Furthermore, as shown in FIG. 16B and other figures, it is preferable that the upper portion of the semiconductor layer 230 has a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in FIG. 16B and other figures, a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 230, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 230.

[0363] When an oxide semiconductor is used as the semiconductor layer 230, as shown in FIGS. 16A and 16B, the configuration including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in the third embodiment can be applied.

[0364] 16A and 16B , when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0365] Examples of insulating layers having the function of capturing or fixing hydrogen include metal oxides having an amorphous structure. For example, metal oxides such as magnesium oxide and oxides containing one or both of aluminum and hafnium are preferably used for the insulating layer 250a and the insulating layer 250c. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0366] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 250a and the insulating layer 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 250a and the insulating layer 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the EOT of the insulating layer that functions as the gate insulating layer.

[0367] For the insulating layer 250a and the insulating layer 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0368] In this embodiment, an aluminum oxide film is used as the insulating layer 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 250a in contact with the semiconductor layer 230, hydrogen contained in the semiconductor layer 230 and the like can be more effectively captured and fixed to the insulating layer 250a.

[0369] In this embodiment, hafnium oxide is used as the insulating layer 250 c. By providing the insulating layer 250 c between the insulating layer 250 b and the insulating layer 250 d, hydrogen contained in the insulating layer 250 b and the like can be more effectively captured and fixed.

[0370] Next, the insulating layer 250b is preferably an insulating layer that is stable to heat, such as silicon oxide, silicon oxynitride, etc. The silicon oxide film used as the insulating layer 250b is preferably formed by using a PEALD method.

[0371] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, it is preferable to provide a barrier insulating layer against oxygen near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 275.

[0372] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer.

[0373] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium, and oxides containing hafnium and silicon. For example, the insulating layer 250 a, the insulating layer 250 c, the insulating layer 250 d, and the insulating layer 275 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layer against oxygen.

[0374] The insulating layer 250a preferably has a barrier property against oxygen. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 600.

[0375] The insulating layer 250a is provided in contact with the top surface and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 222. The insulating layer 250a has a barrier property against oxygen, which can suppress oxygen from being released from the channel formation region of the semiconductor layer 230 when heat treatment or the like is performed. Therefore, oxygen vacancies can be reduced in the semiconductor layer 230.

[0376] Furthermore, by providing the insulating layer 250a, an excessive amount of oxygen can be prevented from being supplied from the insulating layer 280 to the semiconductor layer 230, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, it is possible to prevent the source and drain regions from being excessively oxidized, thereby preventing a decrease in the on-state current or the field-effect mobility of the transistor 600.

[0377] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and is therefore suitable for the insulating layer 250a.

[0378] The insulating layer 250d also preferably has a barrier property against oxygen. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0379] Furthermore, the insulating layer 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0380] The insulating layer 275 also preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 275 is provided in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 222. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242. Therefore, it is possible to prevent the conductive layer 242 from being oxidized by the oxygen contained in the insulating layer 280 and its resistivity from increasing. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 is an insulating layer containing at least nitrogen and silicon.

[0381] In order to suppress a decrease in the hydrogen concentrations in the source and drain regions in the semiconductor layer 230, it is preferable to provide a barrier insulating layer against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulating layer against hydrogen is, for example, the insulating layer 275.

[0382] Examples of the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 275 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layers against hydrogen.

[0383] By providing the insulating layer 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0384] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 600 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0385] The insulating layers 250a to 250d function as part of a gate insulating layer. The insulating layers 250a to 250d, together with the conductive layer 260, are provided in an opening formed in the insulating layer 280. To miniaturize the transistor 600, the insulating layers 250a to 250d are preferably thin. The thicknesses of the insulating layers 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above thickness at least in part.

[0386] The thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0387] In order to thin the film thicknesses of the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by using the ALD method. Furthermore, it is preferable to form the insulating layers 250a to 250d by using the ALD method in order to provide the insulating layers 250a to 250d in openings in the insulating layer 280, etc. By forming the insulating layers 250 by using the ALD method, it is possible to form the insulating layer 250 with good coverage on the side surfaces of the first openings formed in the insulating layer 280, the side edges of the conductive layer 242a, the side edges of the conductive layer 242b, and the like.

[0388] Although the insulating layer 250 has been described above as having a four-layer structure of the insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the transistor 600 can be simplified and the productivity of a semiconductor device including the transistor 600 can be improved.

[0389] As shown in FIG. 15A , the shape of the semiconductor layer 230 in a planar view is preferably a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding. That is, it is preferable that the semiconductor layer 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This can prevent the semiconductor layer 230 from collapsing during the transistor fabrication process when the aspect ratio of the semiconductor layer 230 is increased. Note that the semiconductor layer 230 shown in FIG. 15A can also be described as having a shape with an opening in the center. In FIG. 15A , the shape of the semiconductor layer 230 in a planar view is line-symmetrical about the A1-A2 axis, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in a planar view may be asymmetrical.

[0390] 15A is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. As shown in Fig. 15A, the semiconductor layer 230 preferably overlaps with the conductive layer 260 at two or more locations in a plan view. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. In other words, it is preferable that the semiconductor layer 230 and the conductive layer 260 have two or more regions where they overlap with each other.

[0391] With this structure, as shown in FIG. 15B , a plurality of fin-shaped semiconductor layers 230 are formed in a cross section in the channel width direction. Each of the plurality of fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 600 functions as a multi-channel transistor. Therefore, the channel width of the transistor 600 can be further increased, thereby increasing the on-state current. Therefore, the operating speed of a semiconductor device including the transistor 600 can be increased.

[0392] Although the above description has been given of a configuration in which two circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 230 are provided is also possible. It is also possible to combine circumferential semiconductor layers 230 to form a semiconductor layer 230 having a shape with a plurality of openings. It is also possible to use a semiconductor layer 230 that is shaped like a lattice in plan view.

[0393] As shown in FIGS. 17A to 17E , the transistor 600 can include an insulating layer 224 below the semiconductor layer 230. The planar shape of the insulating layer 224 (when viewed from the Z direction) is similar to that of the semiconductor layer 230, and the insulating layer 224 overlaps with the semiconductor layer 230 in plan view. The lower surface of the insulating layer 224 is in contact with the insulating layer 222, the side surface of the insulating layer 224 is in contact with the insulating layer 250 and the conductive layer 242a, and the upper surface of the insulating layer 224 is in contact with the lower surface of the semiconductor layer 230. The insulating layer 224 may be made of an insulating material that can be used for the insulating layer 250b. For example, silicon oxide can be used for the insulating layer 224. Here, FIGS. 17A to 17E correspond to FIGS. 15A to 15E . FIG. 18 corresponds to FIG. 16B . Regarding the configurations relating to FIGS. 17A to 17E and 18 that are not explained below, the explanations relating to FIGS. 15A to 15E and 16B above can be referred to.

[0394] 18 , it is preferable that the thickness t2 of the insulating layer 250 at the bottom of the first opening be thinner than the thickness t1 (the length of the insulating layer 224 in the direction perpendicular to the surface on which it is formed) of the insulating layer 224. With this configuration, the lower surface of the conductive layer 260 (conductive layer 260 a) located in the first opening can be positioned lower than the lower surface of the semiconductor layer 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0395] By positioning the lower surface of the conductive layer 260 below the lower surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230. In other words, within the opening of the insulating layer 280 or the like, the entire semiconductor layer 230 is electrically surrounded by the electric field of the conductive layer 260, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistors, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 600 can be improved.

[0396] Furthermore, as described above, the semiconductor layer 230 functions as a channel formation region from the top to the bottom, whereby the channel width can be increased, thereby improving the on-state current, transconductance, frequency characteristics, and the like of the transistor 600.

[0397] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, four, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0398] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a GAA structure or a lateral gate all around (LGAA) structure. By forming the transistor 600 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250 functioning as a gate insulating layer can be the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230 has a CAAC structure and a fin-like structure. With this structure, the current path flowing through the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material. Furthermore, by using such an oxide semiconductor, a device having two-dimensional conduction can be fabricated.

[0399] 19A to 19E, the transistor 600 may have a conductive layer 205 below an insulating layer 221. Note that FIGS. 19A to 19E correspond to FIGS. 15A to 15E. Regarding the configurations in FIGS. 19A to 19E that are not described below, the above description of FIGS. 15A to 15E can be used as a reference.

[0400] The conductive layer 205 has a region that functions as a gate electrode, similar to the conductive layer 260. The conductive layer 260 may be referred to as a first gate electrode (upper gate electrode) of the transistor 600, and the conductive layer 205 may be referred to as a second gate electrode (lower gate electrode) of the transistor 600. When the conductive layer 260 is referred to as a gate electrode of the transistor 600, the conductive layer 205 may be referred to as a backgate electrode of the transistor 600.

[0401] When the transistor 600 includes the conductive layer 205 under the insulating layer 221, each of the insulating layer 222 and the insulating layer 221 has a region that functions as a gate insulating layer, similar to the insulating layer 250. Specifically, a region of each of the insulating layer 222 and the insulating layer 221 that overlaps with the conductive layer 205 functions as a gate insulating layer. The insulating layer 250 may be referred to as a first gate insulating layer (upper gate insulating layer), and the insulating layer 222 and the insulating layer 221 may be referred to as a second gate insulating layer (lower gate insulating layer).

[0402] In the transistor 600, the conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. In Figures 19C and 19E, the conductive layer 205 is provided inside a fourth opening that penetrates the insulating layer 216 and reaches the insulating layer 215. In addition, the fourth opening has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. Therefore, in a plan view, the conductive layer 205 provided inside the fourth opening also has a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also functions as wiring.

[0403] 19C and 19E , the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the bottom and sidewalls of the fourth opening. Here, the height of the upper surface of the conductive layer 205 is the same as or approximately the same as the height of the upper surface of the insulating layer 216.

[0404] Here, the conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0405] By using a conductive material that has the function of reducing hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductive layer 205a, it is possible to suppress oxidation of the conductive layer 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0406] The conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0407] As described above, the conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 600 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 600 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0408] The electrical resistivity of the conductive layer 205 is designed taking into consideration the potential applied to the conductive layer 205, and the film thickness of the conductive layer 205 is set to match the electrical resistivity. The film thickness of the insulating layer 216 is approximately the same as that of the conductive layer 205. Here, it is preferable to make the film thicknesses of the conductive layer 205 and the insulating layer 216 thin within the range permitted by the design of the conductive layer 205. By making the film thickness of the insulating layer 216 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 216 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0409] Although the above describes a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited to this, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, the stacked structure of the conductive layer 205a and the conductive layer 205b may further include a conductive layer made of the same material as the conductive layer 205a on the conductive layer 205b. In this case, it is preferable to form the conductive layer so that the top surface of the conductive layer 205b is lower than the top of the conductive layer 205a and so as to fill the recess formed by the conductive layer 205a and the conductive layer 205b.

[0410] In addition to the materials disclosed in this embodiment, the materials for conductive layers shown in other embodiments can be used as materials for conductive layer 205, conductive layer 242, conductive layer 245, and conductive layer 260. In addition to the materials disclosed in this embodiment, the materials for insulating layer shown in other embodiments can be used as materials for insulating layer 215, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 241, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, and insulating layer 283.

[0411] The transistor 600 described in this embodiment can be used as a transistor included in the semiconductor device 500, the semiconductor device 510, the semiconductor device 520, and the semiconductor device 550. The on-state current can be increased without increasing the occupied area. The transistor 600 is particularly suitable for the transistor 140 of the semiconductor device 550 because the on-state current can be increased without increasing the occupied area.

[0412] The transistor 600 can be used as the switch 105. The transistor 600 can be used as a transistor included in the potential generating circuit 101. The transistor 600 can be used as a transistor included in the control signal output circuit 102.

[0413] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0414] Embodiment 5 In this embodiment, an example of a circuit configuration of a functional circuit 100 will be described.

[0415] <Shift Register> An example of the functional circuit 100 is a shift register 300. The shift register 300 shown in Fig. 20A has m (m is an integer equal to or greater than 1) signal output circuits 310. In this specification and the like, the first-stage (first) signal output circuit 310 may be referred to as signal output circuit 310[1], and the m-th stage (m-th) signal output circuit 310 may be referred to as signal output circuit 310[m].

[0416] Furthermore, the jth stage (j is an integer between 1 and m) signal output circuit 310 may be referred to as signal output circuit 310[j]. Note that an arbitrary stage number is represented as j+α, and when α is positive, j+α does not exceed m. Also, an arbitrary stage number is represented as j-α, and when α is positive, j-α does not fall below 1.

[0417] The shift register 300 also has two signal output circuits 310 (signal output circuit 310[m+1] and signal output circuit 310[m+2]) which are dummy circuits.

[0418] The terminals and input / output signals of the signal output circuit 310 may also be referred to in the same manner as above. For example, the signal OUT of the signal output circuit 310[j] may be referred to as the signal OUT[j].

[0419] The shift register 300 also includes wirings 301 to 304 to which four signals CLK (signals CLK_1 to CLK_4) that are clock signals are supplied, and wirings 305 to 308 to which four signals PWC (signals PWC_1 to PWC_4) are supplied. The signal CLK_1 is supplied to the wiring 301, the signal CLK_2 is supplied to the wiring 302, the signal CLK_3 is supplied to the wiring 303, and the signal CLK_4 is supplied to the wiring 304. The signal PWC_1 is supplied to the wiring 305, the signal PWC_2 is supplied to the wiring 306, the signal PWC_3 is supplied to the wiring 307, and the signal PWC_4 is supplied to the wiring 308.

[0420] The signal output circuit 310 has terminals 311 to 318 (see FIG. 20B ). The terminals 311, 312, and 313 are each electrically connected to different wirings among the wirings 301 to 304. For example, in FIG. 20A , in the first-stage signal output circuit 310[1], the terminal 311 is electrically connected to the wiring 301, the terminal 312 is electrically connected to the wiring 302, and the terminal 313 is electrically connected to the wiring 303. That is, a signal CLK_1 is supplied to the terminal 311, a signal CLK_2 is supplied to the terminal 312, and a signal CLK_3 is supplied to the terminal 313.

[0421] In addition, in the second-stage signal output circuit 310[2], a terminal 311 is electrically connected to the wiring 302, a terminal 312 is electrically connected to the wiring 303, and a terminal 313 is electrically connected to the wiring 304. That is, a signal CLK_2 is supplied to the terminal 311, a signal CLK_3 is supplied to the terminal 312, and a signal CLK_4 is supplied to the terminal 313.

[0422] That is, a signal CLK_k is supplied to a terminal 311[j] of a signal output circuit 310[j] (see FIG. 20C ). Here, k is an integer between 1 and 4, and when j is 4 or less, k is equal to j, and when j is 5 or more, k is equal to j−4×g, where g is the quotient obtained by dividing j by 4.

[0423] Furthermore, a signal CLK_k+1 is supplied to a terminal 312[j] of a signal output circuit 310[j], where k is an integer between 1 and 4, and when k+1 is 5, k is set to 1. When j is 3 or less, k is equal to j, and when j is 4 or more, k is equal to j-4×g.

[0424] Furthermore, a signal CLK_k+2 is supplied to a terminal 313[j] of a signal output circuit 310[j]. Here, k+1 is an integer between 1 and 4, and when k+2 is 5, k+2 is set to 1, and when k+2 is 6, k+2 is set to 2. When j is 2 or less, k is equal to j, and when j is 3 or more, k is equal to j-4×g.

[0425] Furthermore, terminal 314[j] is electrically connected to terminal 317[j+1] (not shown) of the next-stage signal output circuit 310[j+1] (not shown). Therefore, terminal 317[j] is electrically connected to terminal 314[j-1]. For example, terminal 314 of signal output circuit 310[1] is electrically connected to terminal 317 of signal output circuit 310[2].

[0426] Furthermore, terminal 315[j] is electrically connected to terminal 314[j+2] (not shown) of signal output circuit 310[j+2] (not shown) two stages later. For example, terminal 315 of signal output circuit 310[1] is electrically connected to terminal 314 of signal output circuit 310[3], and terminal 315 of signal output circuit 310[2] is electrically connected to terminal 314 of signal output circuit 310[4]. Therefore, terminal 315 of signal output circuit 310[m-1] is electrically connected to terminal 314 of signal output circuit 310[m+1], and terminal 315 of signal output circuit 310[m] is electrically connected to terminal 314 of signal output circuit 310[m+2]. Note that signal output circuit 310[m+1] and signal output circuit 310[m+2] do not necessarily have terminal 315.

[0427] Furthermore, the terminal 318[j] is electrically connected to any of the wirings 305 to 308. For example, the terminal 318 of the signal output circuit 310[1] is electrically connected to the wiring 305, and the terminal 318 of the signal output circuit 310[2] is electrically connected to the wiring 306. In other words, a signal PWC_k is supplied to the terminal 318[j] of the signal output circuit 310[j]. Here, k is an integer greater than or equal to 1 and less than or equal to 4. When j is 4 or less, k is equal to j, and when j is 5 or more, k is equal to j-4×g.

[0428] Furthermore, a signal OUT[j] is output from a terminal 316[j]. For example, a signal OUT[1] is output from a terminal 316 of a signal output circuit 310[1]. Furthermore, a signal OUT[m] is output from a terminal 316 of a signal output circuit 310[m] in the mth stage. Note that "A signal OUT[j] is output from a terminal 316[j]" can be read as "A signal OUT[j] is supplied to a terminal 316[j]."

[0429] Furthermore, a signal SROUT[j] is supplied to the terminal 314[j]. In other words, the signal SROUT[j] is output from the terminal 314[j]. For example, the signal SROUT[1] is output from the terminal 314 of the signal output circuit 310[1]. Furthermore, the signal SROUT[m] is output from the terminal 314 of the m-th stage signal output circuit 310[m]. Note that "The signal SROUT[j] is output from the terminal 314[j]" can be read as "The signal SROUT[j] is supplied to the terminal 314[j]."

[0430] 21 shows a circuit configuration example of the signal output circuit 310. The signal output circuit 310 includes transistors 10[1] to 10

[11] , transistors 12[1] to 12[4], and capacitors 20[1] to 20[3].

[0431] The gate of the transistor 10[1] is electrically connected to the terminal 317 and the gate of the transistor 10[6]. The source of the transistor 10[1] is electrically connected to the drain of the transistor 10[2], and the drain of the transistor 10[1] is electrically connected to a wiring 331. The gate of the transistor 10[2] is electrically connected to one terminal of the capacitor 20[1]. The source of the transistor 10[2] is electrically connected to the other terminal of the capacitor 20[1], the source of the transistor 10[6], and a wiring 332.

[0432] The gate of the transistor 10[3] is electrically connected to the terminal 313, the drain of the transistor 10[3] is electrically connected to the wiring 331, and the source of the transistor 10[3] is electrically connected to the drain of the transistor 10[4]. The gate of the transistor 10[4] is electrically connected to the terminal 312, and the drain of the transistor 10[4] is electrically connected to the source of the transistor 10[3]. The source of the transistor 10[4] is electrically connected to the gates of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] and one terminal of the capacitor 20[1].

[0433] In this specification and the like, a region where the gates of the transistors 10[2], 10[9], and 10

[11] , the source of the transistor 10[4], and one terminal of the capacitor 20[1] are electrically connected is referred to as a node ND[1]. The capacitor 20[1] has a function of suppressing a potential fluctuation of the node ND[1] when the node ND[1] is in a floating state and maintaining the potential of the node ND[1].

[0434] The gate of the transistor 10[5] is electrically connected to the terminal 315, and the drain of the transistor 10[5] is electrically connected to the wiring 331. The source of the transistor 10[5] is electrically connected to the gate of the transistor 10[2], the gate of the transistor 10[9], the gate of the transistor 10

[11] , and the drain of the transistor 10[6].

[0435] The gate of the transistor 10[7] is electrically connected to the wiring 331, and one of the source and drain of the transistor 10[7] is electrically connected to the source of the transistor 10[1] and the drain of the transistor 10[2]. The other of the source and drain of the transistor 10[7] is electrically connected to the gate of the transistor 10[8], one terminal of the capacitor 20[2], the gate of the transistor 10

[10] , and one terminal of the capacitor 20[3].

[0436] In this specification, a region where the source or drain of the transistor 10[7], the source of the transistor 10[1], and the drain of the transistor 10[2] are electrically connected is referred to as a node ND[2]. In this specification, a region where the source or drain of the transistor 10[7], the gate of the transistor 10[8], one terminal of the capacitor 20[2], the gate of the transistor 10

[10] , and one terminal of the capacitor 20[3] are electrically connected is referred to as a node ND[3].

[0437] The other of the source or the drain or one of the drains of the transistor 10[8] is electrically connected to the terminal 311. The other of the source or the drain of the transistor 10[8] is electrically connected to the other terminal of the capacitor 20[2], the terminal 314, and the drain of the transistor 10[9]. The other of the source or the drain of the transistor 10

[10] is electrically connected to the terminal 318. The other of the source or the drain of the transistor 10

[10] is electrically connected to the other terminal of the capacitor 20[3], the terminal 316, and the drain of the transistor 10

[11] .

[0438] The source of the transistor 10[9] and the source of the transistor 10

[11] are electrically connected to the wiring 332.

[0439] The drain of the transistor 10[1], the drain of the transistor 10[3], the drain of the transistor 10[5], and the gate of the transistor 10[7] can be electrically connected to different wirings. The source of the transistor 10[2], the source of the transistor 10[6], the source of the transistor 10[9], the source of the transistor 10

[11] , and the other terminal of the capacitor 20[1] can be electrically connected to different wirings.

[0440] A signal RIN is supplied to a terminal 315, a signal LIN is supplied to a terminal 317, a signal SROUT is supplied to a terminal 314, and a signal OUT is supplied to a terminal 316. In addition, in a signal output circuit 310[1] that is the first-stage signal output circuit 310, a signal CLK_1 is supplied to a terminal 311, a signal CLK_2 is supplied to a terminal 312, a signal CLK_3 is supplied to a terminal 313, and a signal PWC_1 is supplied to a terminal 318.

[0441] Furthermore, terminal 314 of signal output circuit 310[1] is electrically connected to terminal 317 of signal output circuit 310[2]. That is, terminal 314[j] of signal output circuit 310[j] is connected to terminal 317[j+1] of signal output circuit 310[j+1]. Therefore, signal SROUT[j] is supplied to terminal 317[j+1] as signal LIN[j+1].

[0442] In addition, in the signal output circuit 310[2], which is the second-stage signal output circuit 310, the signal CLK_2 is supplied to the terminal 311, the signal CLK_3 is supplied to the terminal 312, the signal CLK_4 is supplied to the terminal 313, and the signal PWC_2 is supplied to the terminal 318.

[0443] Furthermore, transistors having back gates are used as transistors 10[2], 10[6], 10[9], and 10

[11] . The back gate of transistor 10[2] is connected to one of the source and drain of transistor 12[1]. The back gate of transistor 10[6] is connected to one of the source and drain of transistor 12[2]. The back gate of transistor 10[9] is connected to one of the source and drain of transistor 12[3]. The back gate of transistor 10

[11] is connected to one of the source and drain of transistor 12[4].

[0444] The gates of the transistors 12[1] to 12[4] are connected to the terminal 321. The other of the source and the drain of each of the transistors 12[1] to 12[4] is connected to the potential generating circuit 101 via a wiring 334.

[0445] In the signal output circuit 310, the holding circuit 150[1] includes transistors 10[2] and 12[1], the holding circuit 150[2] includes transistors 10[6] and 12[2], the holding circuit 150[3] includes transistors 10[9] and 12[3], and the holding circuit 150[4] includes transistors 10

[11] and 12[4]. That is, transistors 10[2], 10[6], 10[9], and 10

[11] correspond to the transistor 130. Transistors 12[1] to 12[4] correspond to the transistors 140. A signal SEL is supplied to the terminal 321 from the control signal output circuit 102 (not shown in FIG. 21).

[0446] Here, the reliability of a transistor will be explained. One of the indicators for evaluating the reliability of a transistor is a gate bias temperature stress (GBTS) test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these tests, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a positive bias temperature stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a negative bias temperature stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0447] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on, so the amount of change in threshold voltage in the PBTS test is one important item to note as an index of transistor reliability. In a p-type transistor, a negative potential is applied to the gate when the transistor is turned on, so the amount of change in threshold voltage in the NBTS test is one important item to note as an index of transistor reliability. The smaller the amount of change in threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0448] When VDD is used as the potential H and VSS is used as the potential L, the potential H is held at the node ND[1] of the signal output circuit 310 for a long period of time during the operation of the shift register 300. Therefore, PBTS is applied to the transistors 10[2], 10[9], and 10

[11] for a long period of time. Also, NBTS is applied to the transistor 10[6] for a long period of time. By using transistors with back gates for the transistors 10[2], 10[6], 10[9], and 10

[11] , degradation of transistor characteristics due to NBTS and PBTS is suppressed.

[0449] Furthermore, even if the threshold voltage of the transistor changes negatively (becomes normally on) due to degradation of the transistor characteristics, the transistor can be reliably turned off by supplying a potential lower than the potential L to the back gate. This reliably maintains the potential of the node ND[1]. This stabilizes the operation of the signal output circuit 310, thereby improving the reliability of the semiconductor device including the signal output circuit 310.

[0450] Furthermore, when the operating speed of the shift register 300 is slow (the driving frequency is low), the period during which the nodes ND[1] and the like are in a floating state becomes longer. Even under such circumstances, the potential of the nodes ND[1] and the like can be reliably maintained by supplying a potential lower than the potential L to the back gate. This stabilizes the operation of the signal output circuit 310, thereby improving the reliability of the shift register 300 including the signal output circuit 310. Furthermore, the reliability of the semiconductor device including the signal output circuit 310 can be improved.

[0451] Furthermore, the signal output circuit 310 described in this embodiment includes a holding circuit 150. Therefore, the potentials supplied to the back gates of transistors 10[2], 10[6], 10[9], and 10

[11] can be held by turning off transistors 12[1] to 12[4]. That is, since there is no need to continuously supply a potential to the back gates of transistors 10[2], 10[6], 10[9], and 10

[11] , the power consumption of the shift register 300 including the signal output circuit 310 is reduced. Furthermore, the power consumption of a semiconductor device including the signal output circuit 310 is reduced.

[0452] Transistors 10[2], 10[6], 10[9], and 10

[11] correspond to the transistor 130 of the semiconductor device 500 shown in Figure 1A. Transistors 12[1] to 12[4] correspond to the transistor 140 of the semiconductor device 500 shown in Figure 1A.

[0453] 22 shows a circuit configuration example of a signal output circuit 310a, which is a modified example of the signal output circuit 310. In the signal output circuit 310a, the other of the source and the drain of each of the transistors 12[1] to 12[4] is connected to the potential generating circuit 101[1] via a wiring 334. A signal from the control signal output circuit 102 (not shown in FIG. 22) is supplied to the terminal 321 as the signal SEL[1].

[0454] The signal output circuit 310a includes transistors having back gates as transistors 10[1], 10[3], 10[4], 10[5], 10[7], 10[8], and 10

[10] . In addition to the circuit configuration of the signal output circuit 310, the signal output circuit 310a also includes transistors 12[5] and 12[6].

[0455] The back gates of transistors 10[1], 10[3], 10[4], 10[5], and 10[7] are connected to one of the source and drain of transistor 12[5]. The other of the source and drain of transistor 12[5] is connected to the potential generating circuit 101[2]. The gate of transistor 12[5] is connected to terminal 322. A signal SEL[2] is supplied to terminal 322 from the control signal output circuit 102.

[0456] By turning on the transistor 12[5], the potential generated by the potential generating circuit 101[2] is supplied to the back gates of the transistors 10[1], 10[3], 10[4], 10[5], and 10[7]. By turning off the transistor 10[5], the potentials of the back gates of the transistors 10[1], 10[3], 10[4], 10[5], and 10[7] are maintained. This means that there is no need to continuously supply a potential to the back gates of the transistors 10[1], 10[3], 10[4], 10[5], and 10[7], which reduces the power consumption of the shift register 300 including the signal output circuit 310a. This also reduces the power consumption of the semiconductor device including the signal output circuit 310a.

[0457] Transistor 12[5] corresponds to transistor 140 of the semiconductor device 550 shown in Figure 10A. Transistors 10[1], 10[3], 10[4], 10[5], and 10[7] correspond to transistor 130 of the semiconductor device 550 shown in Figure 10A.

[0458] The back gates of the transistors 10[8] and 10

[10] are connected to one of the source and drain of the transistor 12[6]. The other of the source and drain of the transistor 12[6] is connected to the potential generating circuit 101[3]. The gate of the transistor 12[6] is connected to the terminal 323. The signal SEL[3] is supplied to the terminal 323 from the control signal output circuit 102.

[0459] By turning on the transistor 12[6], the potential generated by the potential generating circuit 101[2] is supplied to the back gates of the transistors 10[8] and 10

[10] . By turning off the transistor 12[6], the potentials of the back gates of the transistors 10[8] and 10

[10] are maintained. This means that there is no need to continuously supply a potential to the back gates of the transistors 10[8] and 10

[10] , which reduces the power consumption of the shift register 300 including the signal output circuit 310a. This also reduces the power consumption of the semiconductor device including the signal output circuit 310a.

[0460] The transistor 12[6] corresponds to the transistor 140 of the semiconductor device 550 shown in Figure 10A. The transistors 10[8] and 10

[10] correspond to the transistor 130 of the semiconductor device 550 shown in Figure 10A.

[0461] By appropriately combining the configuration of the semiconductor device 500 and the configuration of the semiconductor device 550, the degree of freedom in designing the semiconductor device can be increased.

[0462] <Logic Circuit> An LSI (integrated circuit) is another example of the functional circuit 100. Fig. 23A shows an example of a NOT gate circuit (also called an "inverter circuit") as a logic circuit 320 included in the LSI.

[0463] 23A has one input terminal (terminal TIN) and one output terminal (terminal TOUT). The logic circuit 320 also has transistors Tr1 and Tr2. VDD is supplied to one of the source or drain and the gate of transistor Tr1, and the other of the source or drain is connected to one of the source or drain of transistor Tr2 and the terminal TOUT. VSS is supplied to transistor Tr2, and the gate is connected to the terminal TIN.

[0464] The transistors Tr1 and Tr2 each have a back gate and correspond to the transistor 130 described in the above embodiment. A potential Vbg is supplied to the back gate of the transistor Tr1 via a transistor 140, and a potential Vbg is supplied to the back gate of the transistor Tr2 via another transistor 140.

[0465] Furthermore, if the distance between transistors Tr1 and Tr2 is short and the charge supply capability of transistor 140 is sufficient for the two transistors, it is also possible to supply potential Vbg to the back gates of both transistors via one transistor 140, as shown in FIG. 23B.

[0466] The on / off state of the transistor 140 is controlled in accordance with a pulse signal from the control signal output circuit 102, and controls conduction between the potential generating circuit 101 and the back gates of the transistors Tr1 and Tr2. By controlling the potential of the back gates of the transistors Tr1 and Tr2, for example, the transistors Tr1 and Tr2 can be driven as normally-off transistors even if they are normally-on transistors. Note that although an example in which the logic circuit 320 is an inverter is shown in FIG. 23B , the present invention is not limited to this, and other logic circuits can be used.

[0467] <Sensor Circuit> Another example of the functional circuit 100 is a sensor circuit 340. The sensor circuit 340 shown in Fig. 23C includes a sensor element 345, a transistor Tr3, and a transistor Tr4. The transistor Tr3 functions as a selection transistor, and the transistor Tr4 functions as an amplification transistor.

[0468] For example, an optical sensor element or a temperature sensor element can be used as the sensor element 345. In the sensor circuit 340, the potential of the source or drain of the transistor Tr4 becomes the potential of the output signal.

[0469] The back gate of transistor Tr3 is connected to transistor 140. The transistor 140 is turned on or off to control conduction or non-conduction between the potential generating circuit 101 and the back gate of transistor Tr3. By supplying a potential Vbg to the back gate of transistor Tr3 and controlling the potential of the back gate, for example, transistor Tr3 can be operated as a normally-off transistor even if it is a normally-on transistor. Transistor Tr3 has a function of controlling conduction or non-conduction between the sensor element 345 and the gate of transistor Tr4.

[0470] 23D includes a light-emitting element 351, a transistor Tr5, a transistor Tr6, and a capacitor 352.

[0471] The light-emitting element 351 has a function of emitting light with a brightness corresponding to the amount of current flowing through the light-emitting element 351. The amount of current flowing through the light-emitting element 351 is determined by the drain current of the transistor Tr6. The drain current of the transistor Tr6 is controlled by a video signal supplied to the gate of the transistor Tr6. The video signal is supplied to the gate of the transistor Tr6 via the source and drain of the transistor Tr5. The capacitance element 352 has a function of holding the video signal supplied to the gate of the transistor Tr6.

[0472] The transistor Tr5 has a back gate, and the back gate is connected to the potential generating circuit 101 via the source and drain of the transistor 140. When the transistor 140 is turned on or off, conduction or non-conduction between the potential generating circuit 101 and the back gate of the transistor Tr5 is controlled. By supplying a potential Vbg to the back gate of the transistor Tr5 and controlling the potential of the back gate, for example, the transistor Tr5 can be operated as a normally-off transistor even if it is a normally-on transistor.

[0473] Note that the transistor Tr6 can be provided with a back gate and connected to the potential generating circuit 101 via the transistor 140 .

[0474] 23A to 23D, various circuit configurations can be used as the functional circuit 100. The circuit configurations that can be used for the functional circuit 100 are not limited to these, and a storage device, a processor, etc. can also be used.

[0475] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0476] Embodiment 6 This embodiment describes a circuit configuration example of the potential generating circuit 101. Circuit configuration examples of the potential generating circuit 101 are shown in FIGS.

[0477] 24A includes diodes 361a_1 to 361a_n, capacitors 362a_1 to 362a_n, and a capacitor 363a. Note that in FIG. 24A, n is 4 or more, for example.

[0478] VDD is supplied to the cathode of the diode 361a_1. The cathode of a diode 361a_k (k is an integer of 2 or greater) is connected to the anode of a diode 361a_k-1.

[0479] The clock signal C_CLK is input to one of a pair of electrodes of the capacitors 362a_f (f is an integer of 1 to n) whose f is an odd number. The inverted clock signal C_CLKB, which is an inverted signal of the clock signal C_CLK, is input to one of a pair of electrodes of the capacitors 362a_f whose f is an even number.

[0480] Furthermore, the other of the pair of electrodes of the capacitor 362a_f is connected to the anode of the diode 361a_f.

[0481] One of a pair of electrodes of the capacitor 363a is supplied with VSS, and the other is connected to the anode of the diode 361a_n.

[0482] 24A, the clock signal C_CLK and the inverted clock signal C_CLKB alternate between high and low levels, thereby lowering the voltages of the capacitors 362a_1 to 362a_n. Furthermore, the voltage of the capacitor 362a_k becomes lower than the voltage of the capacitor 362a_k-1. This allows a negative potential Vbg to be output as the signal OUT.

[0483] 24B includes transistors 371a_1 to 371a_3, capacitors 372a_1 to 372a_3, transistors 373a_1 to 373a_3, transistors 374a_1 to 374a_3, a transistor 375a, and a capacitor 376a. Note that the potential generation circuit 101 illustrated in FIG. 24B generates a power supply potential that is three times the input VDD, but is not limited to this. When VSS is used as a reference potential, the potential generation circuit 101 generates a potential that is three times lower than the reference potential by the potential difference between VSS and VDD, but is not limited to this.

[0484] VDD is supplied to one of the source and drain of a transistor 371a_i (i is an integer of 1 to 3). Furthermore, a clock signal C_CLK is input to the gate of the transistor 371a_i.

[0485] One of a pair of electrodes of the capacitor 372a_i is connected to the other of the source and drain of the transistor 371a_i.

[0486] VSS is supplied to one of the source and drain of the transistor 373a_1, and the other is connected to one of the pair of electrodes of the capacitor 372a_1. Furthermore, an inverted clock signal C_CLKB is input to the gate of the transistor 373a_1.

[0487] One of a source and a drain of the transistor 373a_j is connected to the other of the pair of electrodes of the capacitor 372a_j-1, and the other of the source and drain is connected to one of the pair of electrodes of the capacitor 372a_j. Further, an inverted clock signal C_CLKB is input to a gate of the transistor 373a_j.

[0488] VSS is supplied to one of the source and the drain of the transistor 374a_i, and the other is connected to the other of the pair of electrodes of the capacitor 372a_i.

[0489] One of the source and the drain of the transistor 375a is connected to the other of the pair of electrodes of the capacitor 372a_3. Further, an inverted clock signal C_CLKB is input to the gate of the transistor 375a.

[0490] VDD is supplied to one of a pair of electrodes of the capacitor 376a, and the other electrode is connected to the other of the source and drain of the transistor 375a.

[0491] 24B, the clock signal C_CLK and the inverted clock signal C_CLKB alternately change between high and low levels, thereby lowering the voltages of the capacitors 372a_1 to 372a_3. This allows a negative potential Vbg to be output as the signal OUT.

[0492] 25A includes diodes 361b_1 to 361b_n, capacitors 362b_1 to 362b_n, and a capacitor 363b. Note that in FIG. 25A, n is 4 or more, for example.

[0493] VDD is supplied to the anode of the diode 361b_1.

[0494] The anode of the diode 361b_k is electrically connected to the cathode of the diode 361b_k-1.

[0495] The clock signal C_CLK is input to one of a pair of electrodes of the capacitor 362b_f where f is an odd number.

[0496] An inverted clock signal C_CLKB, which is an inverted signal of the clock signal C_CLK, is input to one of a pair of electrodes of the capacitor 362b_f, where f is an even number.

[0497] Furthermore, the other of the pair of electrodes of the capacitor 362b_f is electrically connected to the cathode of the diode 361b_f.

[0498] VSS is applied to one of a pair of electrodes of the capacitor 363b, and the other electrode is electrically connected to the cathode of the diode 361b_n.

[0499] 25A, the clock signal C_CLK and the inverted clock signal C_CLKB alternate between high and low levels, thereby boosting the voltages of the capacitors 362b_1 to 362b_n. Furthermore, the voltage of the capacitor 362b_k becomes higher than the voltage of the capacitor 362b_k-1. This allows a positive potential Vbg to be output as the signal OUT.

[0500] 25B includes transistors 371b_1 to 371b_3, capacitors 372b_1 to 372b_3, transistors 373b_1 to 373b_3, transistors 374b_1 to 374b_3, a transistor 375b, and a capacitor 376b. Note that the potential generation circuit 101 illustrated in FIG. 25B will be described as generating a potential that is three times higher than the reference potential by the potential difference between VSS and VDD when VSS is used as the reference potential, but is not limited to this.

[0501] VSS is supplied to one of the source and drain of the transistor 371b_i. Furthermore, a clock signal C_CLK is input to the gate of the transistor 371b_i.

[0502] One of a pair of electrodes of the capacitor 372b_i is electrically connected to the other of the source and the drain of the transistor 371b_i.

[0503] VDD is supplied to one of the source and drain of the transistor 373b_1, and the other is electrically connected to one of the pair of electrodes of the capacitor 372b_1. Furthermore, an inverted clock signal C_CLKB is input to the gate of the transistor 373b_1.

[0504] One of a source and a drain of a transistor 373b_j (j is an integer greater than or equal to 2 and less than or equal to 3) is electrically connected to the other of a pair of electrodes of the capacitor 372b_j-1, and the other of the source and drain is electrically connected to one of a pair of electrodes of the capacitor 372b_j. Furthermore, an inverted clock signal C_CLKB is input to a gate of the transistor 373b_j.

[0505] VDD is supplied to one of a source and a drain of the transistor 374b_i, and the other is electrically connected to the other of the pair of electrodes of the capacitor 372b_i.

[0506] One of the source and the drain of the transistor 375b is electrically connected to the other of the pair of electrodes of the capacitor 372b_3. Further, an inverted clock signal C_CLKB is input to the gate of the transistor 375b.

[0507] One of a pair of electrodes of the capacitor 376b is supplied with VSS, and the other electrode is electrically connected to the other of the source and drain of the transistor 375b.

[0508] 25B, the clock signal C_CLK and the inverted clock signal C_CLKB alternately change between high and low levels, thereby boosting the voltages of the capacitors 372b_1 to 372b_3. As a result, a positive potential Vbg can be output as the signal OUT.

[0509] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0510] Embodiment 7 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0511] Fig. 26A is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 26A has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 26A shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0512] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a potential generating circuit 928.

[0513] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits and signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0514] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0515] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. The control circuit 912 also generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0516] The potential generating circuit 928 has a function of generating a potential. The signal WAKE has a function of controlling the input of the signal CLK to the potential generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the potential generating circuit 928, and the potential generating circuit 928 generates a potential. The potential generating circuit 928 corresponds to the potential generating circuit 101.

[0517] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0518] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0519] For example, a signal output circuit 310 including a semiconductor device according to one embodiment of the present invention can be used for the row driver 923 and the column driver 924. Thus, the driver circuit 910 corresponds to the functional circuit 100. Furthermore, the memory cell 950 can be provided with a transistor 140 that functions as the potential supply circuit 120. Thus, the memory cell 950 corresponds to the functional circuit 100.

[0520] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0521] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply potential of the semiconductor device 900 is VDD, and the low power supply potential is GND. VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 26A, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0522] The driver circuit 910 and the memory array 920 of the semiconductor device 900 can be provided on the same plane. Alternatively, as shown in FIG. 26B , the driver circuit 910 can be provided in the element layer 50, and an element layer 40 having a memory array 920 can be provided on the element layer 50. By providing the driver circuit 910 and the memory array 920 so that they overlap, the signal propagation distance can be shortened. A single-crystal semiconductor substrate, an SOI substrate, or the like can be used as the element layer 50. By separately forming the element layer 50 including the driver circuit 910 and the element layer 40 including the memory array 920, the operation of the driver circuit 910 included in the element layer 50 can be confirmed before forming the element layer 40 on the element layer 50. Therefore, only non-defective element layers 50 can be used, thereby improving the manufacturing yield of the semiconductor device 900.

[0523] 27A to 27H, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0524] In the following, when two components are described as being connected, this includes cases where the two components are in contact with each other and cases where the two components are electrically connected via a circuit element (transistor, switch, diode, resistor, etc.) or a conductive layer. Electrical connection means that a state in which a current can flow between the two components. Note that a case in which two components are connected via a switch or transistor is also included in the term electrical connection, because a state in which a current can flow when these are in an on state is also included in the term electrical connection.

[0525] 27A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0526] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied. Alternatively, the front gate and the back gate may be connected to each other.

[0527] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0528] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0529] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0530] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 27B can be used. The memory cell 952 is an example in which the memory cell 952 does not include the capacitor CA and the wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0531] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0532] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be extremely small. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, the extremely small leakage current allows multilevel data and analog data to be held in the memory cell 951 and the memory cell 952.

[0533] 27C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0534] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0535] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0536] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0537] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB.

[0538] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 27D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0539] 27E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 27F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0540] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0541] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell and eliminates the need for refreshing the memory cell. Furthermore, since the leakage current is extremely low, multilevel data and analog data can be held in the memory cells 953, 954, 955, and 956.

[0542] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 in which an OS transistor is used as the transistor M2 are one embodiment of an NOSRAM.

[0543] It is possible to use a Si transistor as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0544] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0545] 27G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0546] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0547] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0548] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0549] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (and the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (and the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (and the gate of the transistor M5).

[0550] Note that at least the transistor M4 is preferably an OS transistor.

[0551] Note that Si transistors can also be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0552] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0553] 27H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 27H is a memory cell of an SRAM capable of backing up data.

[0554] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0555] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0556] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0557] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0558] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0559] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0560] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0561] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0562] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0563] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potentials held in the memory cells can be read from the potentials of the wirings BIL and BILB.

[0564] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells and eliminates the need for refreshing the memory cells.

[0565] It is also possible to use Si transistors as the transistors MS1 to MS4.

[0566] The transistors M1, M2, M4, M9, and M10 each have a function of retaining written data. By using transistors M1, M2, M4, M9, and M10 each having a back gate, supplying a potential Vbg to the back gate and controlling the potential of the back gate, even a normally-on transistor can be operated as a normally-off transistor. Thus, the memory array 920 corresponds to the functional circuit 100. The transistors M1, M2, M4, M9, and M10 correspond to the transistor 130 described in the above embodiment.

[0567] 28 shows an example of a stacked structure of a semiconductor device 900, which is one type of semiconductor device. The semiconductor device 900 shown in Fig. 28 includes an element layer 40 including a memory array 920 above an element layer 50 including a driver circuit 910. Fig. 28 shows, as an example, a transistor 130 functioning as the transistor M1, the transistor M2, the transistor M4, the transistor M9, or the transistor M10, and a transistor 140 functioning as the potential supply circuit 120.

[0568] To avoid repetition of the description, the description of the transistor 130 and the transistor 140 will be omitted here.

[0569] 28 illustrates a transistor 400 as an example of a transistor included in the driver circuit 910. The transistor 400 is provided over a substrate 371 and includes a conductive layer 376 functioning as a gate, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of part of the substrate 371, and low-resistance regions 374a and 374b functioning as source and drain regions. The transistor 400 can be either a p-channel transistor or an n-channel transistor. The substrate 371 can be, for example, a single crystal silicon substrate.

[0570] Here, in the transistor 400 shown in FIG. 28 , a semiconductor region 373 (a part of a substrate 371) where a channel is formed has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 with an insulating layer 375 interposed therebetween. A material for adjusting the work function can also be used for the conductive layer 376. Such a transistor 400 is also called a Fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It is also possible to have an insulating layer in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, it is also possible to form a semiconductor film having a convex shape by processing an SOI substrate.

[0571] Note that the transistor 400 illustrated in FIG. 28 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0572] The element layer 50 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0573] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are embedded in the insulating layers 390 and 391. A conductive layer 395 and the like are embedded in the insulating layers 393 and 394. The conductive layers 392 and 395 function as contact plugs or wirings.

[0574] The insulating layer serving as an interlayer film preferably also serves as a planarizing film that covers the uneven shape below it. For example, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve the planarity.

[0575] A wiring layer can also be provided over the insulating layer 394 and the conductive layer 395. For example, in FIG. 28 , an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 386 is formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 functions as a contact plug or a wiring. For example, the transistor 130 is connected to the transistor 400 through the conductive layer 386.

[0576] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0577] Embodiment 8 In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described.

[0578] A semiconductor device according to one embodiment of the present invention can be used in various electronic components. For example, the semiconductor device can be applied to caches and registers of microprocessors such as CPUs, digital signal processors (DSPs), and graphics processing units (GPUs). Note that the microprocessor may be implemented by a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA).

[0579] Therefore, the semiconductor device according to one embodiment of the present invention can be applied to, for example, various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). The semiconductor device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer...

Claims

A plurality of transistors; a first transistor; a circuit having a function of generating a first potential; the semiconductor layer of the first transistor has a length in a direction perpendicular to a surface on which the first transistor is formed that is longer than a width in a cross-sectional view in a channel width direction; The semiconductor device has a function of putting the back gates of the plurality of transistors into a floating state by turning off the first transistor after the first potential is supplied to the back gates of the plurality of transistors via the source and drain of the first transistor. 　 In claim 1, The semiconductor device comprises a gate of the first transistor having a plurality of regions overlapping the semiconductor layer. 　 In claim 1, A semiconductor device, wherein, in a cross-sectional view in a channel width direction, the length of the semiconductor layer in a direction perpendicular to a surface on which the semiconductor layer is formed is between two and ten times the width of the semiconductor layer. 　 In any one of claims 1 to 3, The semiconductor device, wherein the semiconductor layer includes an oxide semiconductor. 　 a first circuit having a function of generating a first potential; a second circuit including a first transistor and a second transistor; a first conductive layer functioning as one of a source or a drain of the first transistor; a second conductive layer provided above the first conductive layer and functioning as a gate of the first transistor; a third conductive layer provided above the second conductive layer and functioning as the other of the source and the drain of the first transistor; a first semiconductor layer including a first channel formation region of the first transistor; a fourth conductive layer including a region located above the third conductive layer, a region functioning as a back gate of the first transistor, and a region functioning as one of a source and a drain of the second transistor; a fifth conductive layer provided above the fourth conductive layer and functioning as the other of the source and the drain of the second transistor; a second semiconductor layer including a second channel formation region of the second transistor; a sixth conductive layer including a region located above the fifth conductive layer and a region functioning as a gate of the second transistor; the first semiconductor layer has a region electrically connected to the first conductive layer, a region along a side surface of the second conductive layer, and a region electrically connected to the third conductive layer; the second semiconductor layer has a region electrically connected to the fourth conductive layer and a region electrically connected to the fifth conductive layer, the fourth conductive layer has a region along the first channel forming region, the sixth conductive layer has a region along the second channel forming region, A semiconductor device having a function of putting the back gate of the first transistor into an electrically floating state by turning off the second transistor after the first potential is supplied to the back gate of the first transistor via the source and drain of the second transistor. 　 In claim 5, The first channel formation region and the second channel formation region have regions that overlap each other in a plan view. 　 In claim 5 or 6, The first conductive layer, the fourth conductive layer, and the sixth conductive layer have regions that overlap each other in a plan view. 　 In claim 5 or 6, The second semiconductor layer is a semiconductor device including an oxide semiconductor. 　 In claim 8, The first semiconductor layer of the semiconductor device includes an oxide semiconductor. 　 In claim 5, A plurality of the second circuits are provided, The first circuit has a function of supplying a first potential to each of the second circuits. 　 A semiconductor device having a first transistor and a second transistor, a first conductive layer functioning as one of a source or a drain of the first transistor; a second conductive layer that functions as a back gate of the first transistor and as one of a source and a drain of the second transistor; a third conductive layer functioning as the other of the source and the drain of the first transistor; a fourth conductive layer functioning as the other of the source and the drain of the second transistor; a fifth conductive layer that functions as a gate of the first transistor; a sixth conductive layer that functions as a gate of the second transistor; a first semiconductor layer including a channel formation region of the first transistor; a second semiconductor layer including a channel formation region of the second transistor; A first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer is disposed on the first conductive layer; the second conductive layer is disposed on the first insulating layer; the second insulating layer is disposed on the second conductive layer; the third conductive layer and the fourth conductive layer are provided on the second insulating layer; the third insulating layer is provided on the third conductive layer and the fourth conductive layer; the first semiconductor layer has a region in contact with the first conductive layer, a region along a side surface of the first insulating layer, a region along a side surface of the second conductive layer, a region along a side surface of the second insulating layer, and a region in contact with the third conductive layer; the second semiconductor layer has a region in contact with the second conductive layer, a region along a side surface of the second insulating layer, and a region in contact with the fourth conductive layer; the fifth conductive layer has a region along a side surface of the first insulating layer via the third insulating layer and the first semiconductor layer, a region along a side surface of the second conductive layer via the third insulating layer and the first semiconductor layer, and a region along a side surface of the second insulating layer via the third insulating layer and the first semiconductor layer, The sixth conductive layer has a region along a side surface of the second insulating layer via the third insulating layer and the second semiconductor layer. 　 In claim 11, The second semiconductor layer is a semiconductor device including an oxide semiconductor. 　 In claim 11 or 12, The first semiconductor layer of the semiconductor device includes an oxide semiconductor. 　 In claim 11 or 12, The channel length of the second transistor is shorter than the channel length of the first transistor.

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