Method for manufacturing semiconductor device, and semiconductor device

Abstract

Disclosed is a method for manufacturing a semiconductor device. This method for manufacturing a semiconductor device comprises: a step for preparing a first semiconductor substrate which has a first substrate body, a first electrode disposed on the first substrate body, and a first insulating layer disposed around the first electrode on the first substrate body; a step for preparing a second semiconductor substrate which has a second substrate body, a second electrode disposed on the second substrate body, and a second insulating layer disposed around the second electrode on the second substrate body; a step for processing a first surface of the first semiconductor substrate on the side opposite to the first substrate body such that the first electrode recesses relative to the first insulating layer; a step for processing a second surface of the second semiconductor substrate on the side opposite to the second substrate body such that the second electrode protrudes relative to the second insulating layer; and a step for joining the first electrode of the first semiconductor substrate and the second electrode of the second semiconductor substrate and joining the first insulating layer of the first semiconductor substrate and the second insulating layer of the second semiconductor substrate.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] Patent Literature 1 discloses a hybrid bonding method, a three-dimensional semiconductor packaging technology. This bonding method bonds multiple semiconductor chips formed by dicing a second semiconductor substrate having terminal electrodes and an insulating film onto a first semiconductor substrate having terminal electrodes and an insulating film. In this bonding method, the surfaces of the first and second semiconductor substrates are first polished using a chemical mechanical polishing (CMP) method so that the surfaces of the terminal electrodes of both the first and second semiconductor substrates are slightly lower than the surfaces of the insulating film. Next, the second semiconductor substrate is diced into multiple semiconductor chips. Next, the multiple semiconductor chips are aligned with the first semiconductor substrate, and the insulating film of each of the multiple semiconductor chips is bonded to the insulating film of the first semiconductor substrate. Next, at least one of a predetermined amount of heat and pressure is applied to the first semiconductor substrate and the multiple semiconductor chips to bond the terminal electrodes of the first semiconductor substrate to the terminal electrodes of the multiple semiconductor chips.

[0003] Japanese Patent Application Laid-Open No. 2021-197430

[0004] In the bonding method described in Patent Document 1, the surfaces of the terminal electrodes on both the first semiconductor substrate and the second semiconductor substrate are positioned slightly lower than the surfaces of the insulating films, so when a predetermined amount of heat or pressure is applied to bond the terminal electrodes of the first semiconductor substrate to the terminal electrodes of the multiple semiconductor chips, large stresses are generated in the insulating films of the first semiconductor substrate and the multiple semiconductor chips, which results in large residual stress in the insulating films of the manufactured semiconductor devices, making them prone to low reliability.

[0005] Furthermore, since the surfaces of the terminal electrodes on both the first and second semiconductor substrates are slightly lower than the surface of the insulating film, it is difficult to align the multiple semiconductor chips with the first semiconductor substrate.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can improve the reliability of an insulating layer, and a semiconductor device with a highly reliable insulating layer.

[0007] The present disclosure relates to a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a first semiconductor substrate having a first substrate body, a first electrode disposed on the first substrate body, and a first insulating layer disposed on the first substrate body around the first electrode; preparing a second semiconductor substrate having a second substrate body, a second electrode disposed on the second substrate body, and a second insulating layer disposed on the second substrate body around the second electrode; processing a first surface of the first semiconductor substrate opposite the first substrate body so that the first electrode is recessed with respect to the first insulating layer; processing a second surface of the second semiconductor substrate opposite the second substrate body so that the second electrode protrudes with respect to the second insulating layer; and bonding the first electrode of the first semiconductor substrate to the second electrode of the second semiconductor substrate and bonding the first insulating layer of the first semiconductor substrate to the second insulating layer of the second semiconductor substrate.

[0008] In this semiconductor device manufacturing method, the first surface of the first semiconductor substrate is processed so that the first electrode is recessed relative to the first insulating layer, thereby forming a recessed portion on the first surface of the first semiconductor substrate, where the first electrode is recessed relative to the first insulating layer. Furthermore, the second surface of the second semiconductor substrate is processed so that the second electrode protrudes relative to the second insulating layer, thereby forming a protruding portion on the second surface of the second semiconductor substrate, where the second electrode protrudes relative to the second insulating layer. Therefore, when the first semiconductor substrate and the second semiconductor substrate are superimposed, the protruding portion on the second surface of the second semiconductor substrate can be fitted into the recessed portion on the first surface of the first semiconductor substrate. This reduces the amount of expansion or contraction (expansion or contraction) of the first insulating layer and the second insulating layer when the first semiconductor substrate and the second semiconductor substrate are bonded, compared to when both the first electrode and the second electrode are recessed or protruded relative to the first insulating layer and the second insulating layer, thereby mitigating stresses generated in the first insulating layer and the second insulating layer. This allows for the manufacture of a semiconductor device with highly reliable first insulating layer and second insulating layer. Furthermore, by fitting the convex portion formed on the second surface of the second semiconductor substrate into the concave portion formed on the first surface of the first semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate can be easily aligned.

[0009] In the method for manufacturing a semiconductor device, the first electrode and the second electrode may be made of copper. In this method for manufacturing a semiconductor device, since the first electrode and the second electrode are made of copper, a semiconductor device with excellent conductivity can be manufactured.

[0010] In the method for manufacturing a semiconductor device described above, the first surface may be polished using a CMP method in the step of processing the first surface. In this method for manufacturing a semiconductor device, polishing the first surface using a CMP method makes it possible to easily recess the first electrode with respect to the first insulating layer.

[0011] In the method for manufacturing a semiconductor device described above, the second surface may be polished using a CMP method in the step of processing the second surface. In this method for manufacturing a semiconductor device, polishing the second surface using a CMP method makes it easy to make the second electrode protrude from the second insulating layer.

[0012] In the method for manufacturing a semiconductor device, the bonding step may include a step of activating the first surface and the second surface, which facilitates bonding the first electrode and the second electrode and also facilitates bonding the first insulating layer and the second insulating layer.

[0013] In the above-described method for manufacturing a semiconductor device, the bonding step may include a step of aligning the first semiconductor substrate and the second semiconductor substrate by fitting a protrusion formed on the second surface, where the second electrode protrudes from the second insulating layer, into a recess formed on the first surface, where the first electrode is recessed from the first insulating layer. In this method for manufacturing a semiconductor device, fitting the protrusion formed on the second surface into the recess formed on the first surface facilitates alignment of the first semiconductor substrate and the second semiconductor substrate.

[0014] In the above-described method for manufacturing a semiconductor device, the first insulating layer may be formed of an inorganic insulating material. In this method for manufacturing a semiconductor device, even if foreign matter such as particles is present on the first insulating layer or the second insulating layer, the first insulating layer can trap the foreign matter, thereby firmly bonding the first insulating layer and the second insulating layer.

[0015] In the above-described method for manufacturing a semiconductor device, the first insulating layer may be formed of an organic insulating material. In this method for manufacturing a semiconductor device, since the first insulating layer is formed of an organic insulating material, the first insulating layer and the second insulating layer can be bonded even at low temperatures. This can improve the reliability of the semiconductor device.

[0016] In the above-described method for manufacturing a semiconductor device, the second insulating layer may be formed of an inorganic insulating material. In this method for manufacturing a semiconductor device, even if foreign matter such as particles is present on the first insulating layer or the second insulating layer, the second insulating layer can trap the foreign matter, thereby firmly bonding the first insulating layer and the second insulating layer.

[0017] In the above-described method for manufacturing a semiconductor device, the second insulating layer may be formed of an organic insulating material. In this method for manufacturing a semiconductor device, since the second insulating layer is formed of an organic insulating material, the first insulating layer and the second insulating layer can be bonded even at low temperatures. This can improve the reliability of the semiconductor device.

[0018] In the above-described method for manufacturing a semiconductor device, the first semiconductor substrate may be a semiconductor wafer, or may be a semiconductor chip obtained by dividing the semiconductor wafer.

[0019] In the above-described method for manufacturing a semiconductor device, the second semiconductor substrate may be a semiconductor wafer, or may be a semiconductor chip obtained by dividing the semiconductor wafer.

[0020] In the above-described method for manufacturing a semiconductor device, in the bonding step, the first semiconductor substrate may be disposed above the second semiconductor substrate, or the second semiconductor substrate may be disposed above the first semiconductor substrate.

[0021] Another aspect of the present disclosure relates to a semiconductor device including: a first semiconductor substrate having a first substrate body, a first electrode disposed on the first substrate body, and a first insulating layer disposed around the first electrode on the first substrate body; and a second semiconductor substrate having a second substrate body, a second electrode disposed on the second substrate body, and a second insulating layer disposed around the second electrode on the second substrate body, wherein the first electrode of the first semiconductor substrate and the second electrode of the second semiconductor substrate are bonded together, and the first insulating layer of the first semiconductor substrate and the second insulating layer of the second semiconductor substrate are bonded together, and a first bonding surface between the first electrode and the second electrode is located closer to the first substrate body than a second bonding surface between the first insulating layer and the second insulating layer.

[0022] In this semiconductor device, the first bonding surface between the first electrode and the second electrode is located closer to the first substrate body than the second bonding surface between the first insulating layer and the second insulating layer. That is, this semiconductor device is manufactured by bonding the first semiconductor substrate and the second semiconductor substrate together by fitting a protrusion 25 of the second semiconductor substrate, where the second electrode protrudes from the second insulating layer, into a recess of the first semiconductor substrate, where the first electrode is recessed from the first insulating layer. This means that stresses generated in the first insulating layer and the second insulating layer when the first semiconductor substrate and the second semiconductor substrate are bonded are alleviated. This results in high reliability for the first insulating layer and the second insulating layer.

[0023] In the semiconductor device described above, the shear strength of the first insulating layer and the second insulating layer may be 25 MPa or more and 35 MPa or less. In this semiconductor device, the shear strength of the first insulating layer and the second insulating layer is 25 MPa or more and 35 MPa or less, so the reliability of the first insulating layer and the second insulating layer is high. Note that, by manufacturing a semiconductor device using the above-described method, the shear strength of the first insulating layer and the second insulating layer can be 25 MPa or more and 35 MPa or less.

[0024] Another aspect of the present disclosure relates to a semiconductor device including a first substrate body, a first electrode disposed on the first substrate body, a second substrate body, a second electrode disposed on the second substrate body and joined to the first electrode, and an insulating layer disposed around the first electrode and the second electrode between the first substrate body and the second substrate body, the insulating layer having a shear strength of 25 MPa or more and 35 MPa or less.

[0025] In this semiconductor device, the insulating layer has a shear strength of 25 MPa or more and 35 MPa or less, which results in high reliability of the insulating layer. Note that, by manufacturing a semiconductor device using the above-described method, the shear strength of the insulating layer can be made 25 MPa or more and 35 MPa or less.

[0026] According to one aspect of the present disclosure, the reliability of the insulating layer can be improved.

[0027] FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present disclosure. FIGS. 2(a), 2(b), and 2(c) are schematic cross-sectional views sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1. FIGS. 3(a), 3(b), and 3(c) are schematic cross-sectional views sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 4 is a schematic cross-sectional view schematically showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 5 is a schematic cross-sectional view schematically showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 6 is a schematic cross-sectional view schematically showing another method of manufacturing the semiconductor device shown in FIG. 1. FIG. 7 is a schematic cross-sectional view schematically showing another method of manufacturing the semiconductor device shown in FIG. 1.

[0028] Hereinafter, several embodiments of the present disclosure will be described in detail, with reference to the drawings as necessary. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, these are intended for explanatory purposes and do not necessarily mean that these relative positions will always be the same. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0029] As used herein, the term "layer" encompasses not only structures with shapes formed over the entire surface when viewed in a plan view, but also structures with shapes formed only on a portion of the surface. Furthermore, as used herein, the term "process" refers not only to an independent process, but also to processes that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. Furthermore, numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described in stages in this specification, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages. Furthermore, in the numerical ranges described in this specification, the upper or lower limit value of the numerical range may be replaced with the value shown in the examples.

[0030] (Configuration of Semiconductor Device) FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor device manufactured by a manufacturing method according to this embodiment. As shown in FIG. 1, the semiconductor device 1 includes a first semiconductor substrate 10 and a second semiconductor substrate 20 bonded to the first semiconductor substrate 10. Each of the first semiconductor substrate 10 and the second semiconductor substrate 20 is a semiconductor chip such as an LSI (Large Scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor, or a semiconductor wafer provided with multiple semiconductor elements that constitute functional circuits corresponding to the semiconductor chip. The semiconductor chips are obtained by dividing the semiconductor wafer into individual pieces by cutting means such as dicing. Examples of methods that can be used to divide the semiconductor wafer into individual pieces include plasma dicing, stealth dicing, and laser dicing.

[0031] The semiconductor device 1 can have a W2W (Wafer to Wafer), C2C (Chip to Chip), or C2W (Chip to Wafer) structure depending on the combination of the first semiconductor substrate 10 and the second semiconductor substrate 20 with a semiconductor wafer and a semiconductor chip. That is, when both the first semiconductor substrate 10 and the second semiconductor substrate 20 are semiconductor wafers, the semiconductor device 1 has a W2W structure. When both the first semiconductor substrate 10 and the second semiconductor substrate 20 are semiconductor chips, the semiconductor device 1 has a C2C structure. When the first semiconductor substrate 10 is a semiconductor wafer and the second semiconductor substrate 20 is a semiconductor chip, or when the first semiconductor substrate 10 is a semiconductor chip and the second semiconductor substrate 20 is a semiconductor wafer, the semiconductor device 1 has a C2W structure.

[0032] The first semiconductor substrate 10 includes a first substrate body 11, a plurality of first electrodes 12 arranged on the first substrate body 11, and a first insulating layer 13 arranged around the first electrodes 12 on the first substrate body 11. The second semiconductor substrate 20 includes a second substrate body 21, a plurality of second electrodes 22 arranged on the second substrate body 21, and a second insulating layer 23 arranged around the second electrodes 22 on the second substrate body 21. In the semiconductor device 1, the plurality of first electrodes 12 of the first semiconductor substrate 10 and the plurality of second electrodes 22 of the second semiconductor substrate 20 are directly bonded to each other. Also, in the semiconductor device 1, the first insulating layer 13 of the first semiconductor substrate 10 and the second insulating layer 23 of the second semiconductor substrate 20 are directly bonded to each other. An insulating layer consisting of the first insulating layer 13 and the second insulating layer 23 is arranged around the plurality of first electrodes 12 and the plurality of second electrodes 22 between the first substrate body 11 and the second substrate body 21. The bonding surface between the plurality of first electrodes 12 of the first semiconductor substrate 10 and the plurality of second electrodes 22 of the second semiconductor substrate 20 is referred to as a first bonding surface 31. The bonding surface between the first insulating layer 13 of the first semiconductor substrate 10 and the second insulating layer 23 of the second semiconductor substrate 20 is referred to as a second bonding surface 32.

[0033] A semiconductor element (not shown) is provided on the first substrate body 11. A semiconductor element (not shown) is provided on the second substrate body 21.

[0034] The multiple first electrodes 12 are electrodes that are electrically connected to semiconductor elements provided on the first substrate body 11 and that penetrate the first insulating layer 13. The multiple first electrodes 12 are formed of a conductive metal such as copper (Cu). The multiple second electrodes 22 are electrodes that are electrically connected to semiconductor elements provided on the second substrate body 21 and that penetrate the second insulating layer 23. Like the multiple first electrodes 12, the multiple second electrodes 22 are formed of a conductive metal such as copper (Cu).

[0035] The first insulating layer 13 is an insulating layer provided on the first substrate body 11. The first insulating layer 13 is made of an inorganic insulating material or an organic insulating material. The second insulating layer 23 is an insulating layer provided on the second substrate body 21. Like the first insulating layer 13, the second insulating layer 23 is made of an inorganic insulating material or an organic insulating material.

[0036] The inorganic insulating material forming the first insulating layer 13 and the second insulating layer 23 is, for example, silicon dioxide (SiO ２ ), silicon nitride (SiN), or silicon oxynitride (SiON). When the first insulating layer 13 and the second insulating layer 23 are formed of inorganic insulating materials, the inorganic insulating material forming the first insulating layer 13 and the inorganic insulating material forming the second insulating layer 23 may be the same or different.

[0037] The organic insulating material forming the first insulating layer 13 and the second insulating layer 23 may be, for example, polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), a PBO precursor, polydimethylsiloxane (PDMS), an epoxy resin, a phenolic resin, or a silicone resin. The organic insulating material forming the first insulating layer 13 and the second insulating layer 23 may include a photosensitive resin or a thermosetting resin. The organic insulating material forming the first insulating layer 13 and the second insulating layer 23 may be, for example, silicon oxide (SiO ２ The organic insulating material has a lower elastic modulus than inorganic materials such as polyethylene terephthalate (PE), ...

[0038] (Method of Manufacturing Semiconductor Device) Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 2 to 5. FIGS. 2(a), 2(b), and 2(c) are schematic cross-sectional views sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1. FIGS. 3(a), 3(b), and 3(c) are schematic cross-sectional views sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 4 is a schematic cross-sectional view sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 5 is a schematic cross-sectional view sequentially showing a method of manufacturing the semiconductor device shown in FIG. 1.

[0039] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (d): (a) preparing (providing) a first semiconductor substrate 10 (see FIG. 2); (b) preparing (providing) a second semiconductor substrate 20 (see FIG. 3); (c) processing a first surface 14 of the first semiconductor substrate 10 opposite to the first substrate body 11 (see FIG. 2); (d) processing a second surface 24 of the second semiconductor substrate 20 opposite to the second substrate body 21 (see FIG. 2); and (e) bonding the first semiconductor substrate 10 and the second semiconductor substrate 20 (see FIGS. 2 to 5).

[0040] [Step (a)] Step (a) is a step of preparing a first semiconductor substrate 10 having a first substrate body 11, a plurality of first electrodes 12 arranged on the first substrate body 11, and a first insulating layer 13 arranged around the plurality of first electrodes 12 on the first substrate body 11. In step (a), first, the plurality of first electrodes 12 are formed on the first substrate body 11. The plurality of first electrodes 12 are formed of a conductive metal such as copper (Cu). After the formation of the plurality of first electrodes 12 is completed, as shown in FIG. 2( a), a first insulating layer 13 is formed on the first substrate body 11 to cover the plurality of first electrodes 12 with the first insulating layer 13. The first insulating layer 13 may be formed of, for example, silicon dioxide (SiO ２ ), silicon nitride (SiN), or silicon oxynitride (SiON), or an inorganic insulating material, or an organic insulating material, such as polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), a PBO precursor, polydimethylsiloxane (PDMS), an epoxy resin, a phenolic resin, or a silicone resin.

[0041] [Step (b)] Step (b) is a step of preparing a second semiconductor substrate 20 having a second substrate body 21, a plurality of second electrodes 22 arranged on the second substrate body 21, and a second insulating layer 23 arranged around the plurality of second electrodes 22 on the second substrate body 21. In step (b), first, the plurality of second electrodes 22 are formed on the second substrate body 21. The plurality of second electrodes 22 are formed of a conductive metal such as copper (Cu). After the formation of the second electrodes 22 is completed, as shown in FIG. 3( a), the second insulating layer 23 is formed on the second substrate body 21 to cover the plurality of second electrodes 22 with the second insulating layer 23. The second insulating layer 23 may be formed of, for example, silicon dioxide (SiO ２ ), silicon nitride (SiN), or silicon oxynitride (SiON), or an inorganic insulating material, or an organic insulating material, such as polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), a PBO precursor, polydimethylsiloxane (PDMS), an epoxy resin, a phenolic resin, or a silicone resin.

[0042] [Step (c)] Step (c) is a step of processing the first surface 14 of the first semiconductor substrate 10 opposite the first substrate body 11 so that the multiple first electrodes 12 are recessed relative to the first insulating layer 13. The first surface 14 is the surface of the first semiconductor substrate 10 that faces the multiple first electrodes 12 and the first insulating layer 13 relative to the first substrate body 11. The processing of the first surface 14 is performed, for example, by polishing the first surface 14 using a chemical mechanical polishing (CMP) method. At this time, the first surface 14 can be polished so that the multiple first electrodes 12 are recessed relative to the first insulating layer 13 by, for example, adjusting the components of the slurry used to polish the first surface 14, adjusting the polishing torque of the first surface 14, or optimizing the polishing pad used to polish the first surface 14. By processing the first surface 14, multiple recesses 15 are formed in the first surface 14 of the first semiconductor substrate 10, where the multiple first electrodes 12 are recessed relative to the first insulating layer 13.

[0043] [Step (d)] Step (d) is a step of processing the second surface 24 of the second semiconductor substrate 20 opposite the second substrate body 21 so that the multiple second electrodes 22 protrude from the second insulating layer 23. The second surface 24 is the surface of the second semiconductor substrate 20 facing the multiple second electrodes 22 and the second insulating layer 23 relative to the second substrate body 21. The processing of the second surface 24 is performed, for example, by polishing the second surface 24 using a CMP method. At this time, the second surface 24 can be polished so that the multiple second electrodes 22 protrude from the second insulating layer 23 by, for example, adjusting the components of the slurry used to polish the second surface 24, adjusting the polishing torque of the second surface 24, or optimizing the polishing pad used to polish the second surface 24. By processing the second surface 24, multiple protrusions 25 are formed on the second surface 24 of the second semiconductor substrate 20, where the multiple second electrodes 22 protrude from the second insulating layer 23.

[0044] [Step (e)] Step (e) is a step of bonding a plurality of first electrodes 12 of the first semiconductor substrate 10 to a plurality of second electrodes 22 of the second semiconductor substrate 20, and bonding a first insulating layer 13 of the first semiconductor substrate 10 to a second insulating layer 23 of the second semiconductor substrate 20.

[0045] 2(c) and 3(c), the step (e) first involves activating the first surface 14 and the second surface 24. In this step, the first surface 14 and the second surface 24 are activated by, for example, ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, plasma treatment, or the like. Activating the first surface 14 and the second surface 24 removes foreign matter such as particles from the first surface 14 and the second surface 24.

[0046] After the activation of the first surface 14 and the second surface 24 is completed, a step of aligning the first semiconductor substrate 10 with the second semiconductor substrate 20 is performed, as shown in FIG. 4 . In this step, the first semiconductor substrate 10 is placed on the bottom side, and the inverted second semiconductor substrate 20 is placed on the top side. That is, the second semiconductor substrate 20 is inverted and placed above the first semiconductor substrate 10. Then, as shown in FIGS. 4 and 5 , in this state, the protrusions 25 formed on the second surface 24 of the second semiconductor substrate 20 are fitted into the recesses 15 formed on the first surface 14 of the first semiconductor substrate 10, thereby aligning the first semiconductor substrate 10 with the second semiconductor substrate 20. That is, the multiple first electrodes 12 of the first semiconductor substrate 10 are aligned with the multiple second electrodes 22 of the second semiconductor substrate 20.

[0047] 5 , the first electrodes 12 of the first semiconductor substrate 10 are bonded to the second electrodes 22 of the second semiconductor substrate 20, and the first insulating layer 13 of the first semiconductor substrate 10 is bonded to the second insulating layer 23 of the second semiconductor substrate 20. The bonding of the first electrodes 12 to the second electrodes 22 and the bonding of the first insulating layer 13 to the second insulating layer 23 are performed by, for example, applying a predetermined amount of heat or pressure, or both, to the first semiconductor substrate 10 and the second semiconductor substrate 20.

[0048] When the first insulating layer 13 is formed from an inorganic insulating material and the second insulating layer 23 is formed from an organic insulating material, the heating temperature of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 50°C or higher and 350°C or lower, and the pressurizing pressure of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 0.1 MPa or higher and 5.0 MPa or lower.

[0049] When the first insulating layer 13 is formed from an organic insulating material and the second insulating layer 23 is formed from an inorganic insulating material, the heating temperature of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 50°C or higher and 350°C or lower, and the pressurizing pressure of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 0.1 MPa or higher and 5.0 MPa or lower.

[0050] When both the first insulating layer 13 and the second insulating layer 23 are formed from inorganic insulating materials, the heating temperature of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 50°C or higher and 350°C or lower, and the pressurizing pressure of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 0.1 MPa or higher and 5.0 MPa or lower.

[0051] When both the first insulating layer 13 and the second insulating layer 23 are formed from organic insulating materials, the heating temperature of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 50°C or higher and 350°C or lower, and the pressurizing pressure of the first semiconductor substrate 10 and the second semiconductor substrate 20 can be, for example, 0.1 MPa or higher and 5.0 MPa or lower.

[0052] This bonding process bonds the plurality of first electrodes 12 to the plurality of second electrodes 22, and also bonds the first insulating layer 13 to the second insulating layer 23. When the bonding of the first semiconductor substrate 10 and the second semiconductor substrate 20 is completed, the semiconductor device 1 is obtained. If at least one of the first semiconductor substrate 10 and the second semiconductor substrate 20 is a semiconductor wafer, the obtained semiconductor device 1 can be diced into individual pieces by cutting means such as dicing, thereby obtaining individual semiconductor devices. Examples of methods that can be used to diced the semiconductor device 1 include plasma dicing, stealth dicing, and laser dicing.

[0053] In the semiconductor device 1 manufactured in this manner, a first bonding surface 31, which is a bonding surface between the plurality of first electrodes 12 and the plurality of second electrodes 22, is located closer to the first substrate body 11 than a second bonding surface 32, which is a bonding surface between the first insulating layer 13 and the second insulating layer 23. Note that when the first insulating layer 13 is formed of an inorganic insulating material and the second insulating layer 23 is formed of an organic insulating material, when the first insulating layer 13 is formed of an organic insulating material and the second insulating layer 23 is formed of an inorganic insulating material, or when both the first insulating layer 13 and the second insulating layer 23 are formed of inorganic insulating materials, an interface between the first insulating layer 13 and the second insulating layer 23 is formed at the second bonding surface 32. On the other hand, when both the first insulating layer 13 and the second insulating layer 23 are formed of organic insulating materials, an interface between the first insulating layer 13 and the second insulating layer 23 may not be formed at the second bonding surface 32, and there may be no boundary between the first insulating layer 13 and the second insulating layer 23.

[0054] Furthermore, in the semiconductor device 1 manufactured in this manner, the shear strength of the first insulating layer 13 and the second insulating layer 23 is 25 MPa or more and 35 MPa or less. That is, the shear strength of the insulating layer disposed around the first electrode 12 and the second electrode 22 between the first substrate body 11 and the second substrate body 21 is 25 MPa or more and 35 MPa or less. The shear strength of the first insulating layer 13 and the second insulating layer 23 (shear strength of the insulating layer) is measured using a universal bond tester (Royce 650, manufactured by Royce Instruments) after the first insulating layer 13 and the second insulating layer 23 (insulating layer) are exposed to an environment specified by JEDEC (MSL3: Moisture Sensitivity Level 3, 30°C, 60% RH, 192 hours) to absorb moisture.

[0055] As described above, in the method for manufacturing a semiconductor device according to this embodiment, the first surface 14 of the first semiconductor substrate 10 is processed so that the plurality of first electrodes 12 are recessed relative to the first insulating layer 13, and therefore, a plurality of recesses 15 formed by the plurality of first electrodes 12 recessed relative to the first insulating layer 13 are formed on the first surface 14 of the first semiconductor substrate 10. Furthermore, the second surface 24 of the second semiconductor substrate 20 is processed so that the plurality of second electrodes 22 protrude relative to the second insulating layer 23, and therefore, a plurality of protrusions 25 formed by the plurality of second electrodes 22 protruding relative to the second insulating layer 23 are formed on the second surface 24 of the second semiconductor substrate 20. Therefore, when the first semiconductor substrate 10 and the second semiconductor substrate 20 are superimposed on each other, the plurality of protrusions 25 formed on the second surface 24 of the second semiconductor substrate 20 can be fitted into the plurality of recesses 15 formed on the first surface 14 of the first semiconductor substrate 10. As a result, when the first semiconductor substrate 10 and the second semiconductor substrate 20 are bonded together, the amount of expansion or contraction (amount of extension or contraction) of the first insulating layer 13 and the second insulating layer 23 is smaller than when both the multiple first electrodes and the multiple second electrodes are recessed or protruded relative to the first insulating layer and the second insulating layer, and stress generated in the first insulating layer 13 and the second insulating layer 23 is alleviated. This makes it possible to manufacture a semiconductor device 1 with highly reliable first insulating layer 13 and second insulating layer 23. Furthermore, by fitting the multiple protrusions 25 formed on the second surface 24 of the second semiconductor substrate 20 into the multiple recesses 15 formed on the first surface 14 of the first semiconductor substrate 10, the first semiconductor substrate 10 and the second semiconductor substrate 20 can be easily aligned.

[0056] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the multiple first electrodes 12 and the multiple second electrodes 22 are formed from copper, so that a semiconductor device 1 with excellent conductivity can be manufactured.

[0057] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the first surface 14 is polished using the CMP method, whereby the first electrodes 12 can be easily recessed into the first insulating layer 13 .

[0058] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the second surface 24 is polished using the CMP method, whereby the plurality of second electrodes 22 can be easily made to protrude from the second insulating layer 23 .

[0059] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, by activating the first surface 14 and the second surface 24, it is possible to easily bond a plurality of first electrodes 12 and a plurality of second electrodes 22, and it is also possible to easily bond the first insulating layer 13 and the second insulating layer 23.

[0060] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, the first semiconductor substrate 10 and the second semiconductor substrate 20 can be easily aligned by fitting a plurality of protrusions 25 formed on the second surface 24 into a plurality of recesses 15 formed on the first surface 14.

[0061] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, since the first insulating layer 13 is formed from an inorganic insulating material, even if foreign matter such as particles is present on the first insulating layer 13 or the second insulating layer 23, the first insulating layer 13 can bite into (trap) the foreign matter, thereby firmly bonding the first insulating layer 13 and the second insulating layer 23.

[0062] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the first insulating layer 13 is made of an organic insulating material, so that the first insulating layer 13 and the second insulating layer 23 can be bonded together without high temperatures, thereby improving the reliability of the semiconductor device 1.

[0063] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, since the second insulating layer 23 is formed from an inorganic insulating material, even if foreign matter such as particles is present on the first insulating layer 13 or the second insulating layer 23, the second insulating layer 23 can bite into (trap) the foreign matter, thereby firmly bonding the first insulating layer 13 and the second insulating layer 23.

[0064] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the second insulating layer 23 is made of an organic insulating material, so that the first insulating layer 13 and the second insulating layer 23 can be bonded together without high temperatures, thereby improving the reliability of the semiconductor device 1.

[0065] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, the first semiconductor substrate 10 is a semiconductor wafer or a semiconductor chip, and the second semiconductor substrate 20 is a semiconductor wafer or a semiconductor chip, so that the variations of the semiconductor device 1 and the variations of the manufacturing method of the semiconductor device 1 can be increased.

[0066] In the semiconductor device 1 according to this embodiment, the first bonding surface 31 between the plurality of first electrodes 12 and the plurality of second electrodes 22 is located closer to the first substrate body 11 than the second bonding surface 32 between the first insulating layer 13 and the second insulating layer 23. In other words, the semiconductor device 1 is manufactured by fitting the plurality of protrusions 25 of the second semiconductor substrate 20, where the plurality of second electrodes 22 protrude from the second insulating layer 23, into the plurality of recesses 15 of the first semiconductor substrate 10, where the plurality of first electrodes 12 are recessed from the first insulating layer 13. This means that the stress generated in the first insulating layer 13 and the second insulating layer 23 when the first semiconductor substrate 10 and the second semiconductor substrate 20 are bonded together is alleviated. This results in high reliability for the first insulating layer 13 and the second insulating layer 23.

[0067] Furthermore, in the semiconductor device 1 according to this embodiment, the shear strength of the first insulating layer 13 and the second insulating layer 23 is 25 MPa or more and 35 MPa or less, which results in high reliability of the first insulating layer 13 and the second insulating layer 23. In other words, the shear strength of the insulating layer is 25 MPa or more and 35 MPa or less, which results in high reliability of the insulating layer.

[0068] Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

[0069] For example, in the above embodiment, the first semiconductor substrate 10 is described as being disposed above the second semiconductor substrate 20 in the bonding step (e). However, as shown in FIGS. 6 and 7 , the second semiconductor substrate 20 may be disposed above the first semiconductor substrate 10. FIGS. 6 and 7 are schematic cross-sectional views illustrating another method for manufacturing the semiconductor device shown in FIG. 1 . After activation of the first surface 14 and the second surface 24 is completed, the second semiconductor substrate 20 may be disposed on the bottom side, and the inverted first semiconductor substrate 10 may be disposed on the top side, as shown in FIG. 6 . That is, the first semiconductor substrate 10 may be inverted and disposed above the second semiconductor substrate 20. Then, as shown in FIGS. 6 and 7 , in this state, the first semiconductor substrate 10 and the second semiconductor substrate 20 may be aligned by fitting a plurality of protrusions 25 formed on the second surface 24 of the second semiconductor substrate 20 into a plurality of recesses 15 formed on the first surface 14 of the first semiconductor substrate 10.

[0070] In this way, by placing the first semiconductor substrate 10 above the second semiconductor substrate 20, or by placing the second semiconductor substrate 20 above the first semiconductor substrate 10, the variety of manufacturing methods for the semiconductor device 1 can be increased.

[0071] 1...semiconductor device, 10...first semiconductor substrate, 11...first substrate body, 12...first electrode, 13...first insulating layer (insulating layer), 14...first surface, 15...recess, 20...second semiconductor substrate, 21...second substrate body, 22...second electrode, 23...second insulating layer (insulating layer), 24...second surface, 25...convex portion, 31...first bonding surface, 32...second bonding surface

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor substrate having a first substrate body, a first electrode disposed on the first substrate body, and a first insulating layer disposed around the first electrode on the first substrate body; preparing a second semiconductor substrate having a second substrate body, a second electrode disposed on the second substrate body, and a second insulating layer disposed around the second electrode on the second substrate body; processing a first surface of the first semiconductor substrate opposite the first substrate body so that the first electrode is recessed with respect to the first insulating layer; processing a second surface of the second semiconductor substrate opposite the second substrate body so that the second electrode protrudes with respect to the second insulating layer; and bonding the first electrode of the first semiconductor substrate to the second electrode of the second semiconductor substrate, and bonding the first insulating layer of the first semiconductor substrate to the second insulating layer of the second semiconductor substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first electrode and the second electrode are made of copper.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the step of processing the first surface, the first surface is polished by using a CMP method.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the step of processing the second surface, the second surface is polished by using a CMP method.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the bonding step includes a step of activating the first surface and the second surface.

6. A method for manufacturing a semiconductor device as claimed in any one of claims 1 to 5, wherein the bonding step includes a step of aligning the first semiconductor substrate and the second semiconductor substrate by fitting a protrusion, formed on the second surface and formed by the second electrode protruding from the second insulating layer, into a recess, formed on the first surface and formed by the first electrode being recessed from the first insulating layer.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first insulating layer is made of an inorganic insulating material.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first insulating layer is made of an organic insulating material.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the second insulating layer is made of an inorganic insulating material.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the second insulating layer is made of an organic insulating material.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the first semiconductor substrate is a semiconductor wafer.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the first semiconductor substrate is a semiconductor chip formed by dicing a semiconductor wafer.

13. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the second semiconductor substrate is a semiconductor wafer.

14. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the second semiconductor substrate is a semiconductor chip formed by dicing a semiconductor wafer.

15. The method for manufacturing a semiconductor device according to claim 1, wherein in the bonding step, the first semiconductor substrate is disposed above the second semiconductor substrate.

16. The method for manufacturing a semiconductor device according to claim 1, wherein in the bonding step, the second semiconductor substrate is disposed above the first semiconductor substrate.

17. A semiconductor device comprising: a first semiconductor substrate having a first substrate body, a first electrode disposed on the first substrate body, and a first insulating layer disposed around the first electrode on the first substrate body; and a second semiconductor substrate having a second substrate body, a second electrode disposed on the second substrate body, and a second insulating layer disposed around the second electrode on the second substrate body, wherein the first electrode of the first semiconductor substrate and the second electrode of the second semiconductor substrate are bonded together, and the first insulating layer of the first semiconductor substrate and the second insulating layer of the second semiconductor substrate are bonded together, and a first bonding surface between the first electrode and the second electrode is located closer to the first substrate body than a second bonding surface between the first insulating layer and the second insulating layer.

18. The semiconductor device according to claim 17, wherein the shear strength of the first insulating layer and the second insulating layer is 25 MPa or more and 35 MPa or less.

19. A semiconductor device comprising: a first substrate body; a first electrode arranged on the first substrate body; a second substrate body; a second electrode arranged on the second substrate body and joined to the first electrode; and an insulating layer arranged around the first electrode and the second electrode between the first substrate body and the second substrate body, wherein the shear strength of the insulating layer is 25 MPa or more and 35 MPa or less.

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