Semiconductor substrate, semiconductor device, power conversion device, and method for manufacturing semiconductor device

Abstract

The present invention comprises: a semiconductor element; and a mounting substrate on which the semiconductor element is mounted. The mounting substrate has a mounting position identification part for causing a mounting position of the semiconductor element to be identified by image processing.

Description

Semiconductor substrate, semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The present invention relates to a semiconductor substrate, a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.

[0002] For example, Patent Document 1 discloses a power module having external connection terminals and a manufacturing method thereof. The power module disclosed in Patent Document 1 has a case provided with an identification mark that is used when placing bonding wires.

[0003] Patent No. 4236826

[0004] Incidentally, a semiconductor device such as the power module disclosed in Patent Document 1 includes a semiconductor substrate having a semiconductor chip (semiconductor element). The semiconductor substrate further includes a mounting substrate on which the semiconductor element is mounted. For example, when manufacturing such a semiconductor device, the mounting substrate is placed on a base member, and the semiconductor element is further placed on the mounting substrate. These mounting substrates and semiconductor elements are bonded by a reflow process. Accurate positioning of the semiconductor element relative to the mounting substrate is required. For this reason, a jig is attached to the mounting substrate, and the semiconductor element is positioned using marks on the jig as a guide. However, using a jig requires securing space within the semiconductor device for the jig, making it difficult to miniaturize the semiconductor device. Furthermore, using a jig requires removing the jig after the reflow process, complicating the manufacturing process. For example, the resin case of the semiconductor device may be slightly deformed due to heating during the reflow process. In such a case, it may become impossible to remove the jig from the resin case once it has been placed within the semiconductor device.

[0005] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a semiconductor substrate, a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device that enable accurate placement of semiconductor elements without using a jig.

[0006] The present invention employs the following configuration as a means for solving the above problems.

[0007] A first aspect of the present invention is a semiconductor substrate comprising a semiconductor element and a mounting substrate on which the semiconductor element is mounted, the mounting substrate having a mounting position identification section for identifying the mounting position of the semiconductor element by image processing.

[0008] A second aspect of the present invention is a semiconductor device comprising the semiconductor substrate of the first aspect, a base member on which the semiconductor substrate is mounted, and a case fixed to the base member and having an opening for accommodating the semiconductor substrate.

[0009] A third aspect of the present invention is a power conversion device that includes the semiconductor device of the second aspect and performs power conversion using the semiconductor device.

[0010] A fourth aspect of the present invention is a method for manufacturing a semiconductor device, comprising a mounting board placement step of placing a mounting board on which a semiconductor element is mounted onto a base member, a case placement step of placing a case enclosing the mounting board onto the base member, and a semiconductor element placement step of placing the semiconductor element on the mounting board, wherein in the semiconductor element placement step, the mounting position of the semiconductor element is identified by image processing based on a mounting position identification unit provided on the mounting board, and the semiconductor element is placed on the mounting board based on the identification result.

[0011] The present invention can identify the mounting position of a semiconductor element by image processing based on a mounting position identification portion provided on the mounting board, and therefore can accurately position the semiconductor element on the mounting board without using a jig.

[0012] FIG. 1 is a circuit diagram showing a schematic electrical configuration of a power conversion device according to an embodiment of this embodiment. FIG. 2 is an exploded perspective view showing a schematic structural configuration of a power conversion device according to an embodiment of this embodiment. FIG. 3 is a schematic exploded perspective view of a power module provided in an intelligent power module of a power conversion device according to an embodiment of this embodiment. FIG. 4 is a schematic enlarged sectional view including one power device of a power module according to an embodiment of this embodiment. FIG. 5 is a schematic enlarged plan view including one power device of a power module according to an embodiment of this embodiment. FIG. 6 is a plan view of a power device according to an embodiment of this embodiment. FIG. 7 is a perspective view of a mounting substrate provided on a power device according to an embodiment of this embodiment. FIG. 8 is a flowchart showing a part of a manufacturing process of a power module according to an embodiment of this embodiment.

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a semiconductor substrate, a semiconductor device, a power converter, and a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

[0014] 1 is a circuit diagram showing a schematic electrical configuration of a power conversion device 1 of this embodiment. The power conversion device 1 of this embodiment is mounted on a vehicle such as an electric automobile and is provided between a motor M and a battery B. The power conversion device 1 of this embodiment performs power conversion between the motor M and the battery B. For example, the power conversion device 1 of this embodiment converts DC power supplied from the battery B into three-phase AC power and supplies it to the motor M. The power conversion device 1 also converts regenerative power (AC power) from the motor M into DC power and supplies it to the battery B.

[0015] As shown in FIG. 1 , the power conversion device 1 of this embodiment has a power conversion circuit H. As described above, the power conversion circuit H converts DC power into AC power. The power conversion circuit H also converts AC power into DC power. The power conversion circuit H includes a capacitor C and an inverter circuit E. The power conversion device 1 may also include, for example, a step-up / step-down converter or a DC / DC converter (not shown). If the vehicle has multiple motors M, the power conversion device 1 may also include multiple inverter circuits E.

[0016] The power conversion device 1 of this embodiment also includes a conductive line BU through which power is conducted. For example, the power conversion device 1 of this embodiment includes a conductive line BU that connects the inverter circuit E and the battery B, and a conductive line BU that connects the inverter circuit E and the motor M.

[0017] As shown in FIG. 1 , the inverter circuit E includes three legs R corresponding to the respective phases of the motor M. Each leg R includes an upper arm HA and a lower arm LA. The upper arm HA is connected to the positive electrode side of a battery B via a conductive line BU. The lower arm LA is connected to the negative electrode side of the battery B via a conductive line BU. The upper arm HA and the lower arm LA are connected in series. An output terminal that connects the legs R and the motor M is connected between the upper arm HA and the lower arm LA.

[0018] 1, the power conversion device 1 of this embodiment includes power devices 20 (semiconductor substrates) corresponding to each leg R. That is, in this embodiment, the power conversion device 1 includes three power devices 20. Each power device 20 includes a power transistor corresponding to the upper arm HA and a power transistor corresponding to the lower arm. That is, in this embodiment, each power device 20 includes two power transistors. Each of these power transistors is formed using a plurality of semiconductor elements.

[0019] Fig. 2 is an exploded perspective view showing a schematic structural configuration of the power conversion device 1 of this embodiment. As shown in Fig. 2, the power conversion device 1 of this embodiment includes an inverter case 2, an intelligent power module 3, and a capacitor unit 4. The power conversion device 1 may also include other components, such as a reactor unit forming a step-up / step-down circuit and a DC-DC converter unit forming a DC-DC converter. When multiple inverter circuits E are included, the power conversion device 1 may also include multiple intelligent power modules 3. The power conversion device 1 may also include a step-up / step-down circuit unit separate from the intelligent power module 3.

[0020] The inverter case 2 is a case that houses the intelligent power module 3, the capacitor unit 4, etc., and includes a center plate 2a and a case cover 2b. The center plate 2a and the case cover 2b are formed as separate parts that can be detached from each other. Note that FIG. 2 illustrates a state in which the case cover 2b is separated above the center plate 2a. However, the installation posture of the power conversion device 1 is not particularly limited. In other words, the power conversion device 1 may be mounted on a vehicle so that the case cover 2b is located to the side of the center plate 2a.

[0021] The central plate 2a has a bottom wall to which the intelligent power modules 3 and the capacitor units 4 are fixed, and side walls that surround the intelligent power modules 3 and the capacitor units 4. In other words, the central plate 2a is formed in the shape of a container that is open on the case cover 2b side. Such central plate 2a is provided with water channels as necessary, and is formed to be able to guide the coolant that cools the intelligent power modules 3 and the capacitor units 4.

[0022] The case cover 2b is fixed to the center plate 2a and covers the intelligent power modules 3 and the capacitor units 4. That is, the intelligent power modules 3 and the capacitor units 4 are exposed when the case cover 2b is detached from the center plate 2a.

[0023] Such an inverter case 2 is fixed to, for example, a housing (not shown) that covers the motor M or a gear case that houses a gear that transmits power generated by the motor M to the outside. In such a case, for example, the center plate 2a is fastened to the motor housing or the gear case using a bolt (not shown) or the like. Note that if the housing that covers the motor M has a space for accommodating the power conversion device 1, the case cover 2b may be omitted.

[0024] The inverter case 2 also holds bus bars that form part or all of the conductive line BU (see Figure 1) that connects the battery B to the intelligent power module 3 and the capacitor unit 4, and the conductive line BU (see Figure 1) that connects the intelligent power module 3 to the motor M.

[0025] The intelligent power module 3 includes a power module 3a (semiconductor device) and a substrate unit 3b. The power module 3a is a module provided with a plurality of power devices 20 (described later). In other words, the power module 3a forms an inverter circuit E with the plurality of power devices 20.

[0026] The board unit 3b is stacked on the power module 3a. This board unit 3b includes, for example, a gate driver board and an ECU (Electronic Control Unit) board. The gate driver board is a board provided with a gate driver that generates a drive signal for the inverter circuit E formed by the power module 3a. The ECU board is a board provided with an ECU that controls the gate driver board.

[0027] The capacitor unit 4 is a unit that houses a capacitor element therein. The capacitor unit 4 is connected to the power module 3a. The capacitor unit 4 forms the capacitor C shown in FIG. 1.

[0028] 3 is a schematic exploded perspective view of a power module 3a included in the intelligent power module 3. As shown in this figure, the power module 3a includes a module case 10 (case), the above-described power device 20 (semiconductor substrate), a heat sink 30 (base member), and a lead frame 40.

[0029] The module case 10 is a resin case that houses the power devices 20 and the like. The module case 10 has an opening 11 for each power device 20 to house the power device 20.

[0030] 4 is a schematic cross-sectional view of the power module 3a with one power device 20 enlarged. As shown in FIG. 4, the module case 10 is fixed onto the heat sink 30 via an adhesive 50. The module case 10 is fixed to the surface 30a of the heat sink 30 so as to surround each power device 20.

[0031] The power conversion device 1 of this embodiment also includes a bus bar 60 molded in the module case 10. In this embodiment, the power conversion device 1 of this embodiment includes a bus bar 60 (hereinafter referred to as a bus bar 61) that conducts power between the battery B and the power device 20, and a bus bar 60 (hereinafter referred to as a bus bar 62) that conducts power between the power device 20 and the motor M.

[0032] The bus bar 61 is molded into the module case 10 with a connection terminal 61a on the battery B side and a portion where the lead frame 40 is joined exposed from the module case 10. The connection terminal 61a is connected to the capacitor unit 4 and a power supply terminal (not shown), and is connected to the battery B via the power supply terminal.

[0033] The bus bar 62 is molded into the module case 10 with a connection terminal 62a on the motor M side and a portion where the lead frame 40 is joined exposed from the module case 10. The connection terminal 62a is connected to the motor M.

[0034] As shown in Fig. 4, the power conversion device 1 of this embodiment also includes a control terminal 70 molded into the module case 10. As shown in Fig. 4, the control terminal 70 is molded into the module case 10 in an L-shaped bent state. One end of the control terminal 70 protrudes upward from the module case 10. This one end of the control terminal 70 is inserted into a through-hole provided in the board unit 3b and connected to the board unit 3b. The other end of the control terminal 70 is arranged so as to be exposed upward at the opening 11.

[0035] 5 is a schematic plan view of the power module 3a in which one power device 20 is enlarged. As shown in this figure, a plurality of control terminals 70 are provided for one semiconductor element 22, which will be described later. A bonding wire 80 is connected to each of these control terminals 70, connecting the semiconductor element 22 and the control terminal 70. In other words, the power conversion device 1 of this embodiment includes a plurality of bonding wires 80, connecting the semiconductor element 22 and the control terminal 70. As shown in FIG. 4, the inside of the opening 11 is sealed with a sealing material 90.

[0036] 5, the module case 10 has a control terminal identification hole 12. The control terminal identification hole 12 is a hole for identifying the positions of the control terminals 70 by image processing during the manufacture of the power module 3a. In other words, the module case 10 has the control terminal identification hole 12 for identifying the positions of the control terminals 70 connected to the semiconductor elements 22 via bonding wires 80 by image processing.

[0037] The control terminal identification holes 12 are provided so as to sandwich the other ends of the plurality of control terminals 70. In other words, two control terminal identification holes 12 forming a pair are arranged so as to sandwich the other ends of the plurality of control terminals 70. The module case 10 has two pairs of control terminal identification holes 12, each consisting of two control terminal identification holes 12, for one opening 11 (i.e., one power device 20).

[0038] Each control terminal identification hole 12 is a hole that penetrates the module case 10 in the vertical direction. These control terminal identification holes 12 are portions that generate contrast that allows the control terminal identification holes 12 to be extracted from image data acquired by an imaging device used for image processing. Note that any control terminal identification portion that can be identified by image processing does not have to be the control terminal identification hole 12. For example, a depression that does not penetrate the module case 10, a protrusion that protrudes from the module case 10, or the like may be used as the control terminal identification portion.

[0039] 5, the module case 10 has a lead frame positioning portion 13 that positions the lead frame 40. The lead frame positioning portion 13 is formed as a recess that is provided so as to be connected to the opening 11. The lead frame positioning portion 13 is formed in a shape that can accommodate a portion of the lead frame 40. By arranging the lead frame 40 so that it is accommodated in this lead frame positioning portion 13, the lead frame 40 is accurately positioned.

[0040] 4 , each power device 20 includes a mounting substrate 21 and a semiconductor element 22. The mounting substrate 21 is a substrate on which the semiconductor element 22 is mounted. The mounting substrate 21 includes a sheet-like insulating substrate 23, a front conductor layer 24 (first conductor layer) provided on the front surface (one surface) of the insulating substrate 23, and a back conductor layer 25 (second conductor layer) provided on the back surface (the other surface) of the insulating substrate 23.

[0041] The insulating substrate 23 is formed of an insulating material such as ceramics and is formed in a sheet shape. A front conductor layer 24 is formed on the surface of the insulating substrate 23 (the surface on the semiconductor element 22 side). This front conductor layer 24 is a metal layer that is electrically connected to the semiconductor element 22 and forms part of the conductive circuit. In other words, the front conductor layer 24 is a conductor layer on which the semiconductor element 22 is mounted.

[0042] 6 is a plan view of the power device 20. As shown in this figure, two semiconductor elements 22 are mounted on the front-side conductor layer 24. The front-side conductor layer 24 is divided into sections for each semiconductor element 22. The portion of the front-side conductor layer 24 on which one semiconductor element 22 is mounted is referred to as the first portion 24a, and the portion of the front-side conductor layer 24 on which the other semiconductor element 22 is mounted is referred to as the second portion 24b. The first portion 24a and the second portion 24b are provided on the insulating substrate 23 and spaced apart from each other.

[0043] 7 is a perspective view of the mounting board 21. As shown in this figure, the first portion 24a is provided with a recess 24c for accommodating the semiconductor element 22. A mounting position R1 for one of the semiconductor elements 22 is provided on the bottom surface of the recess 24c. The second portion 24b is provided with a recess 24d for accommodating the semiconductor element 22. A mounting position R2 for the other semiconductor element 22 is provided on the bottom surface of the recess 24d.

[0044] For example, the depth of the recesses 24c and 24d is greater than the thickness of the semiconductor element 22. In this embodiment, the recesses 24c and 24d are formed in a rectangular shape. Also, a lead frame bonding portion 24e (lead frame bonding position) for bonding the lead frame 40 is formed in the second portion 24b so as to be recessed.

[0045] Furthermore, in the power device 20 of this embodiment, the mounting substrate 21 includes mounting position identification holes 26 for identifying the mounting positions of the semiconductor elements 22 through image processing. As shown in FIGS. 6 and 7 , four mounting position identification holes 26 are provided for one power device 20. Each mounting position identification hole 26 is provided in the top-side conductor layer 24. Each mounting position identification hole 26 is a hole that penetrates the top-side conductor layer 24 in the vertical direction. These mounting position identification holes 26 are used to generate contrast that allows the mounting position identification holes 26 to be extracted from the image data acquired by the imaging device used for image processing. Note that any mounting position identification feature that can be identified through image processing does not have to be a mounting position identification hole 26. For example, a recess that does not penetrate the top-side conductor layer 24 or a protrusion that protrudes from the top-side conductor layer 24 may be used as the mounting position identification feature.

[0046] In this embodiment, two of the four mounting position identification holes 26 are arranged to sandwich mounting position R1 between them. The two mounting position identification holes 26 that sandwich mounting position R1 between them form one mounting position identification hole pair 27. The remaining two mounting position identification holes 26 are arranged to sandwich mounting position R2 between them. The two mounting position identification holes 26 that sandwich mounting position R2 between them also form one mounting position identification hole pair 27. That is, in this embodiment, the mounting board 21 is provided with mounting position identification hole pairs 27 consisting of multiple mounting position identification holes 26 that are arranged to sandwich mounting position R1 between them. In addition, in this embodiment, the mounting board 21 is provided with mounting position identification hole pairs 27 consisting of multiple mounting position identification holes 26 that are arranged to sandwich mounting position R2 between them. In this way, in this embodiment, a mounting position identification hole pair 27 is provided for each of mounting position R1 and mounting position R2.

[0047] Furthermore, the two mounting position identification holes 26 included in one mounting position identification hole pair 27 are arranged so as to straddle a mounting substrate bonding electrode 22a (see FIG. 4 ) of the semiconductor element 22, which will be described later, when viewed from the stacking direction of the mounting substrate 21 and the semiconductor element 22. In other words, the mounting substrate bonding electrode 22a is arranged so as to overlap with a straight line connecting these two mounting position identification holes 26.

[0048] Furthermore, the two mounting position identification holes 26 included in one mounting position identification hole pair 27 are arranged so as to straddle a lead frame bonding electrode 22b (see FIG. 4 ) described later of the semiconductor element 22 when viewed from the stacking direction of the mounting substrate 21 and the semiconductor element 22. In other words, the lead frame bonding electrode 22b is arranged so as to overlap the straight line connecting these two mounting position identification holes 26.

[0049] Furthermore, in this embodiment, two of the four mounting position identification holes 26 are arranged to sandwich the lead frame joint 24e for joining the lead frame 40 between them when viewed from the stacking direction of the mounting substrate 21 and the semiconductor element 22. Therefore, these two mounting position identification holes 26 can be used to identify the position of the lead frame joint 24e by image processing.

[0050] Returning to FIG. 4 , a back-side conductor layer 25 is formed on the other surface of the insulating substrate 23 (the surface opposite the semiconductor element 22). This back-side conductor layer 25 forms part of a heat transfer path that transfers heat conducted from the semiconductor element 22 and the like to the heat sink 30. The surface of this back-side conductor layer 25 opposite the insulating substrate 23 is the mounting surface when the power device 20 is mounted on the heat sink 30. This mounting surface is bonded to the heat sink 30 via solder 100, as shown in FIG. 4 . Note that in this embodiment, the mounting substrate 21 includes the back-side conductor layer 25. However, the mounting substrate 21 does not necessarily need to include the back-side conductor layer 25. In this case, the insulating substrate 23 is bonded to the heat sink 30.

[0051] The semiconductor element 22 is mounted on the front conductor layer 24, for example. The number of semiconductor elements 22 mounted on the front conductor layer 24 is not limited. Such semiconductor elements 22 can be formed using a silicon (Si) semiconductor. Alternatively, the semiconductor element 22 can be formed using a wide-gap semiconductor such as a silicon carbide (SiC) semiconductor or a gallium nitride (GaN) semiconductor.

[0052] As described above, the semiconductor element 22 includes a mounting substrate bonding electrode 22a provided on the front conductor layer 24 side. The mounting substrate bonding electrode 22a is bonded to the front conductor layer 24 via solder 100. In this embodiment, the mounting substrate bonding electrode 22a is formed in a rectangular shape. As described above, the semiconductor element 22 also includes a lead frame bonding electrode 22b provided on the lead frame 40 side. The lead frame bonding electrode 22b is bonded to the lead frame 40 via solder 100.

[0053] Each power device 20 is housed in the opening 11 of the module case 10 while being placed on a heat sink 30. The heat sink 30 supports the module case 10 and the power devices 20. The heat sink 30 also absorbs heat from the power devices 20 to cool them. The heat sink 30 is fixed to the central plate 2a so that the bottom surface thereof is exposed to a flow path provided in the central plate 2a, for example. The heat sink 30 may also have a plurality of fins formed on the bottom surface.

[0054] The lead frame 40 is joined to the power device 20 and the bus bar 60. The lead frame 40 is joined to the lead frame joining electrodes 22b of the semiconductor element 22 via solder 100. The lead frame 40 is also joined to the bus bar 60 via solder 100. Furthermore, the end of the bus bar 60 joined to the lead frame joining electrodes 22b of the semiconductor element 22 mounted at the mounting position R1 is joined to the lead frame joining portion 24e via solder 100.

[0055] 8 is a flowchart showing a part of the manufacturing process of the power module 3a of this embodiment. As shown in this figure, the manufacturing process of the power module 3a of this embodiment includes a mounting substrate arrangement step S1, a case arrangement step S2, a semiconductor element arrangement step S3, a lead frame arrangement step S4, a reflow step S5, and a wire bonding step S6, which are performed in this order.

[0056] The mounting board placement step S1 is a step of placing the mounting board 21 on the surface 30a of the heat sink 30 via sheet solder. Note that the sheet solder may be melted before the case placement step S2 to bond the mounting board 21 to the heat sink 30 in advance.

[0057] The case placement step S2 is a step of placing the module case 10 that surrounds the mounting substrate 21 relative to the heat sink 30. In the case placement step S2, the module case 10 is adhered to the heat sink 30 via an adhesive 50.

[0058] The semiconductor element placement process S3 is a process of placing the semiconductor element 22 on the mounting board 21. In the semiconductor element placement process S3, imaging data including the mounting board 21 is captured, and the positions of mounting positions R1 and R2 are identified by image processing using the imaging data. Specifically, the positions of the mounting position identification holes 26 are extracted from the imaging data, and the positions of mounting positions R1 and R2 are determined. For example, the position of mounting position R1 is determined based on the position of one mounting position identification hole pair 27. Furthermore, the position of mounting position R2 is determined based on the position of the other mounting position identification hole pair 27.

[0059] Next, sheet solder is placed at each of the mounting positions R1 and R2. At this time, the sheet solder may be placed based on the positions of the mounting positions R1 and R2 obtained based on the image processing results.

[0060] Next, the semiconductor element 22 is placed at the mounting position R1 and the mounting position R2 based on the identification result. Here, the semiconductor element 22 is placed based on the positions of the mounting position R1 and the mounting position R2 determined based on the image processing result.

[0061] The lead frame placement step S4 is a step of placing the lead frame 40. Here, the lead frame 40 is placed so as to be in contact with the semiconductor element 22, the bus bar 60, and the lead frame joint portion 24e via sheet solder, bar solder, or the like.

[0062] The reflow process S5 is a process in which the sheet solder or the like is melted by heating and then hardened, thereby joining the mounting substrate 21, the semiconductor element 22, the heat sink 30, and the lead frame 40 to one another.

[0063] The wire bonding process S6 is a process of connecting the control terminals 70 and the semiconductor element 22 via bonding wires 80. Here, the positions of the control terminal identification holes 12 are extracted by image processing, and the positions of the control terminals 70 are identified based on the positions of the control terminal identification holes 12. Furthermore, based on this identification result, bonding wires 80 are formed so as to connect the control terminals 70 and the semiconductor element 22.

[0064] Thereafter, the power module 3a of this embodiment is manufactured by performing necessary operations such as forming the sealing material 90. Furthermore, the power conversion device 1 is manufactured using such a power module 3a.

[0065] The power device 20 of this embodiment as described above includes a semiconductor element 22 and a mounting substrate 21. The semiconductor element 22 is mounted on the mounting substrate 21. The mounting substrate 21 also has a mounting position identification hole 26 for identifying the mounting positions (mounting positions R1 and R2) of the semiconductor element 22 by image processing.

[0066] In the power device 20 of this embodiment, the mounting positions (mounting positions R1 and R2) of the semiconductor element 22 can be determined by image processing based on the mounting position identification holes 26 provided in the mounting substrate 21. Therefore, in the power device 20 of this embodiment, the semiconductor element 22 can be accurately positioned on the mounting substrate 21 without using a jig.

[0067] Furthermore, in the power device 20 of this embodiment, the mounting substrate 21 includes an insulating substrate 23, a top-side conductor layer 24, and a bottom-side conductor layer 25. The insulating substrate 23 is formed in a sheet shape. The top-side conductor layer 24 is provided on one surface (front surface) of the insulating substrate 23, and the semiconductor element 22 is mounted on the top-side conductor layer 24. The bottom-side conductor layer 25 is provided on the other surface (back surface) of the insulating substrate 23. Furthermore, the mounting position identification hole 26 is provided in the top-side conductor layer 24.

[0068] In the power device 20 of this embodiment, a mounting position identification hole 26 is formed in the front conductor layer 24 on which the semiconductor element 22 is mounted. This allows the mounting position identification hole 26 to be located near the mounting positions (mounting positions R1 and R2). This reduces the error when calculating the mounting positions (mounting positions R1 and R2) based on the positions of the mounting position identification hole 26 compared to when the mounting position identification hole 26 is located in the insulating substrate 23 or the like. Therefore, the power device 20 of this embodiment has high placement accuracy for the semiconductor element 22.

[0069] In the power device 20 of this embodiment, the mounting substrate 21 includes a mounting position identification hole pair 27. The mounting position identification hole pair 27 is made up of a plurality of mounting position identification holes 26 arranged with the mounting positions (mounting position R1 and mounting position R2) sandwiched between them.

[0070] In the power device 20 of this embodiment, the mounting positions (mounting positions R1 and R2) can be calculated based on the multiple mounting position identification holes 26. Furthermore, since the mounting positions (mounting positions R1 and R2) are located between the multiple mounting position identification holes 26, they are close to any of the mounting position identification holes 26. Therefore, in the power device 20 of this embodiment, calculation errors in the mounting positions (mounting positions R1 and R2) can be reduced, and the placement accuracy of the semiconductor element 22 is high.

[0071] In the power device 20 of this embodiment, a plurality of semiconductor elements 22 are mounted on the mounting substrate 21. A pair of mounting position identification holes 27 is provided for each mounting position (mounting position R1 and mounting position R2) of each semiconductor element 22.

[0072] In the power device 20 of this embodiment, the mounting position identification holes 26 are provided near each mounting position (mounting position R1 and mounting position R2). Therefore, the power device 20 of this embodiment has high placement accuracy for each of the multiple semiconductor elements 22.

[0073] In the power device 20 of this embodiment, the semiconductor element 22 has mounting substrate bonding electrodes 22a bonded to the mounting substrate 21. The two mounting position identification holes 26 included in one mounting position identification hole pair 27 are arranged so that the mounting substrate bonding electrodes 22a overlap with a straight line connecting the two mounting position identification holes 26 when viewed from the stacking direction of the semiconductor element 22 and the mounting substrate 21.

[0074] If one of the mounting position identification holes 26 is formed at a position slightly different from the design position, the straight line will be tilted relative to its original orientation. As a result, the position of the semiconductor element 22, which is positioned based on the position of the mounting position identification hole 26, will be displaced from its original position. In this case, if the distance from the straight line to the center position of the mounting board bonding electrodes 22a is long, the amount of displacement of the semiconductor element 22 relative to the inclination of the straight line will be greater than if the distance is short. In contrast, in the power device 20 of this embodiment, the mounting position identification hole 26 is positioned so as to overlap the straight line connecting the mounting board bonding electrodes 22a. Therefore, in the power device 20 of this embodiment, even if the position of one of the mounting position identification holes 26 is formed at a position slightly different from the design position, the amount of displacement of the semiconductor element 22 relative to its original position can be kept small.

[0075] The two mounting position identification holes 26 may also be positioned so that the line connecting them overlaps the center of the mounting board bonding electrode 22 a. In this case, even if one of the mounting position identification holes 26 is formed in a position slightly different from the designed position, the amount of displacement of the semiconductor element 22 from its original position can be minimized.

[0076] In the power device 20 of this embodiment, the semiconductor element 22 has a lead frame bonding electrode 22b that is provided on the surface opposite to the mounting substrate bonding electrode 22a that is bonded to the mounting substrate 21 and that is bonded to the lead frame 40. The two mounting position identification holes 26 included in one mounting position identification hole pair 27 are arranged so that the lead frame bonding electrodes 22b overlap on a straight line that connects them when viewed from the stacking direction of the semiconductor element 22 and the mounting substrate 21.

[0077] In the power device 20 of this embodiment, even if one of the mounting position identification holes 26 is formed in a position slightly different from the designed position, the position of the lead frame bonding electrode 22b can be prevented from being significantly displaced from its original position. The two mounting position identification holes 26 may be arranged so that the line connecting them overlaps the center position of the lead frame bonding electrode 22b.

[0078] In the power device 20 of this embodiment, the front conductor layer 24 has a lead frame bonding portion 24e to which an end of the lead frame 40 bonded to the semiconductor element 22 is bonded. A plurality of mounting position identification holes 26 are provided so as to sandwich the lead frame bonding portion 24e between them.

[0079] When image processing is performed on the power device 20 of this embodiment, the positions of the lead frame joints 24e can be accurately determined using the mounting position identification holes 26. Therefore, the power device 20 of this embodiment has the lead frame 40 accurately positioned. Furthermore, sheet solder may be placed on the lead frame joints 24e based on the positions of the lead frame joints 24e determined by image processing.

[0080] In the power device 20 of this embodiment, the top conductor layer 24 has recesses (recesses 24c and 24d) on the bottom surface where mounting positions are provided, so that the power device 20 of this embodiment can prevent the semiconductor element 22 from moving significantly during the reflow process S5.

[0081] In the power device 20 of this embodiment, the mounting position identification hole 26 is a hole provided in the front conductor layer 24. By providing the mounting position identification hole 26, the power device 20 of this embodiment can reduce the amount of material used and the weight.

[0082] The power module 3a of this embodiment includes the above-described power device 20, a heat sink 30, and a module case 10. A semiconductor substrate is mounted on the heat sink 30. The module case 10 is fixed to the heat sink 30 and has an opening 11 that houses the power device 20.

[0083] The power module 3a of this embodiment includes the power device 20. Therefore, the semiconductor element 22 can be accurately positioned on the mounting substrate 21 without using a jig.

[0084] The power module 3a of this embodiment also includes a lead frame 40 joined to the power device 20. The module case 10 has a lead frame positioning portion 13 that positions the lead frame 40.

[0085] In the power module 3 a of this embodiment, the position of the lead frame 40 can be held by the module case 10. Therefore, the lead frame 40 can be prevented from moving during the reflow process S5 or the like without using a jig.

[0086] Furthermore, in the power module 3a of this embodiment, the module case 10 includes a control terminal identification hole 12. The control terminal identification hole 12 is a portion for identifying the position of the control terminal 70 connected to the semiconductor element 22 via the bonding wire 80 by image processing.

[0087] In the power module 3a of this embodiment, the module case 10 is provided with a control terminal identification hole 12 in addition to the mounting position identification hole 26 provided in the power device 20. This allows the control terminal identification hole 12 to be positioned close to the control terminal 70. This makes it possible to accurately identify the position of the control terminal 70 by image processing.

[0088] The power conversion device 1 of this embodiment also includes a power module 3 a, and performs power conversion using the power module 3 a. The power conversion device 1 of this embodiment also includes a power device 20. This allows the semiconductor element 22 to be accurately positioned on the mounting substrate 21 without using a jig.

[0089] Furthermore, the manufacturing method of the power device 20 of this embodiment includes a mounting substrate placement step S1, a case placement step S2, and a semiconductor element placement step S3. The mounting substrate placement step S1 is a step of placing the mounting substrate 21, on which the semiconductor element 22 is mounted, relative to the heat sink 30. The case placement step S2 is a step of placing the module case 10 that surrounds the mounting substrate 21 relative to the heat sink 30. The semiconductor element placement step is a step of placing the semiconductor element 22 on the mounting substrate 21. Furthermore, in the manufacturing method of the power device 20 of this embodiment, in the semiconductor element placement step S3, the mounting position of the semiconductor element 22 is identified by image processing based on the mounting position identification hole 26 provided in the mounting substrate 21, and the semiconductor element 22 is placed on the mounting substrate 21 based on the identification result.

[0090] The manufacturing method for the power module 3a of this embodiment makes it possible to determine the mounting positions (mounting positions R1 and R2) of the semiconductor element 22 by image processing based on the mounting position identification holes 26 provided in the mounting substrate 21. Therefore, the manufacturing method for the power module 3a of this embodiment makes it possible to accurately position the semiconductor element 22 on the mounting substrate 21 without using a jig.

[0091] While the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to the above-described embodiments. The shapes and combinations of the components shown in the above-described embodiments are merely examples, and various modifications can be made based on design requirements, etc., without departing from the spirit of the present invention.

[0092] For example, in the above embodiment, the mounting position identification hole 26 and the control terminal identification hole 12 are circular holes. However, the present invention is not limited to this. Either or both of the mounting position identification hole 26 and the control terminal identification hole 12 may have a shape other than circular. For example, the shape of the mounting position identification hole 26 may be different for each mounting position identification hole pair 27. This makes it possible to identify each mounting position by image processing when multiple mounting positions are provided.

[0093] The above embodiment can also be described as follows, for example:

[0094] (Supplementary Note 1) A semiconductor substrate comprising: a semiconductor element; and a mounting substrate on which the semiconductor element is mounted, wherein the mounting substrate comprises a mounting position identification unit for identifying the mounting position of the semiconductor element by image processing.

[0095] (Supplementary Note 2) The semiconductor substrate according to Supplementary Note 1, wherein the mounting substrate is provided with a pair of mounting position identification parts, each of the mounting position identification parts being arranged with the mounting position sandwiched between them.

[0096] (Supplementary Note 3) The semiconductor substrate according to Supplementary Note 2, wherein the mounting substrate has a plurality of the semiconductor elements mounted thereon, and the mounting position identification portion pair is provided for each of the mounting positions of the semiconductor elements.

[0097] (Supplementary Note 4) The semiconductor substrate according to Supplementary Note 2 or 3, characterized in that the semiconductor element has a mounting substrate bonding electrode bonded to the mounting substrate, and the two mounting position identification parts included in one mounting position identification part pair are arranged so as to overlap on a straight line connecting the mounting substrate bonding electrodes when viewed from the stacking direction of the semiconductor element and the mounting substrate.

[0098] (Appendix 5) The semiconductor substrate according to any one of Appendices 2 to 4, characterized in that the semiconductor element has a lead frame bonding electrode that is provided on a surface opposite to a mounting substrate bonding electrode that is bonded to the mounting substrate and that is bonded to a lead frame, and the two mounting position identification parts included in one mounting position identification part pair are arranged so as to overlap on a straight line connecting the lead frame bonding electrodes to each other when viewed from the stacking direction of the semiconductor element and the mounting substrate.

[0099] (Appendix 6) The semiconductor substrate according to any one of Appendices 1 to 5, characterized in that the mounting substrate comprises: a sheet-like insulating base material; and a first conductor layer provided on one side of the insulating base material and on which the semiconductor element is mounted, and the mounting position identification portion is provided on the first conductor layer.

[0100] (Appendix 7) The semiconductor substrate according to appendix 6, characterized in that the first conductor layer has a lead frame bonding position where an end of a lead frame bonded to the semiconductor element is bonded, and the mounting position identification portion is provided in plurality so as to sandwich the lead frame bonding position between each other.

[0101] (Supplementary Note 8) The semiconductor substrate according to Supplementary Note 6 or 7, wherein the first conductor layer has a recess in a bottom surface where the mounting position is provided.

[0102] (Supplementary Note 9) The semiconductor substrate according to any one of Supplementary Notes 6 to 8, wherein the mounting position identification portion is a hole provided in the first conductor layer.

[0103] (Supplementary Note 10) A semiconductor device comprising: a semiconductor substrate according to any one of Supplementary Notes 1 to 9; a base member on which the semiconductor substrate is mounted; and a case fixed to the base member and having an opening for accommodating the semiconductor substrate.

[0104] (Supplementary Note 11) The semiconductor device according to Supplementary Note 10, further comprising: a lead frame joined to the semiconductor substrate; and the case having a lead frame positioning portion for positioning the lead frame.

[0105] (Supplementary Note 12) The semiconductor device according to Supplementary Note 10 or 11, wherein the case includes a control terminal identification portion for identifying the positions of control terminals connected to the semiconductor element via wires by image processing.

[0106] (Supplementary Note 13) A power conversion device comprising the semiconductor device according to any one of Supplementary Notes 10 to 12, and performing power conversion using the semiconductor device.

[0107] (Appendix 14) A method for manufacturing a semiconductor device, comprising: a mounting board placement step of placing a mounting board on which a semiconductor element is mounted, on a base member; a case placement step of placing a case that encloses the mounting board on the base member; and a semiconductor element placement step of placing the semiconductor element on the mounting board, wherein in the semiconductor element placement step, a mounting position of the semiconductor element is identified by image processing based on a mounting position identification unit provided on the mounting board, and the semiconductor element is placed on the mounting board based on the identification result.

[0108] REFERENCE SIGNS LIST 1 Power conversion device 2 Inverter case 3 Intelligent power module 3a Power module 3b Substrate unit 4 Capacitor unit 10 Module case (case) 11 Opening 12 Control terminal identification hole (control terminal identification portion) 13 Lead frame positioning portion 20 Power device (semiconductor substrate) 21 Mounting substrate 22 Semiconductor element 22a Mounting substrate bonding electrode 22b Lead frame bonding electrode 23 Insulating base material 24 Front conductor layer (first conductor layer) 24a First portion 24b Second portion 24c Recess 24d Recess 24e Lead frame bonding portion 25 Back conductor layer (second conductor layer) 26 Mounting position identification hole (mounting position identification portion) 27 Mounting position identification hole pair (mounting position identification portion pair) 30 Heat sink (base member) 30a Surface 40 Lead frame 50 Adhesive 60 Bus bar 70 Control terminal 80 Bonding wire (wire) 90 Sealing material 100 Solder R1 Mounting position R2 Mounting position

Claims

1. A semiconductor substrate comprising: a semiconductor element; and a mounting substrate on which the semiconductor element is mounted, the mounting substrate having a mounting position identification portion for identifying the mounting position of the semiconductor element through image processing.

2. The semiconductor substrate according to claim 1, wherein said mounting substrate is provided with a pair of mounting position identification parts, each of said mounting position identification parts being arranged with said mounting position therebetween.

3. The semiconductor substrate according to claim 2, wherein a plurality of the semiconductor elements are mounted on the mounting substrate, and the pair of mounting position identification portions is provided for each of the mounting positions of the semiconductor elements.

4. The semiconductor substrate according to claim 2, characterized in that the semiconductor element has a mounting substrate bonding electrode bonded to the mounting substrate, and the two mounting position identification parts included in one mounting position identification part pair are arranged so as to overlap a straight line connecting the mounting substrate bonding electrodes with each other when viewed from the stacking direction of the semiconductor element and the mounting substrate.

5. The semiconductor substrate according to claim 2, characterized in that the semiconductor element has a lead frame bonding electrode that is provided on the surface opposite to the mounting board bonding electrode that is bonded to the mounting board and is bonded to the lead frame, and the two mounting position identification parts included in one mounting position identification part pair are arranged so as to overlap a straight line connecting the lead frame bonding electrodes with each other when viewed from the stacking direction of the semiconductor element and the mounting board.

6. The semiconductor substrate according to any one of claims 1 to 5, characterized in that the mounting board comprises a sheet-like insulating base material, and a first conductor layer provided on one side of the insulating base material and on which the semiconductor element is mounted, and the mounting position identification portion is provided on the first conductor layer.

7. The semiconductor substrate according to claim 6, characterized in that the first conductor layer has a lead frame bonding position to which an end of a lead frame bonded to the semiconductor element is bonded, and the mounting position identification portion is provided in a plurality of positions so as to sandwich the lead frame bonding positions between each other.

8. The semiconductor substrate according to claim 6, wherein said first conductor layer has a recess in a bottom surface thereof in which said mounting position is provided.

9. The semiconductor substrate according to claim 6, wherein said mounting position identifying portion is a hole provided in said first conductor layer.

10. A semiconductor device comprising: a semiconductor substrate according to any one of claims 1 to 5; a base member on which the semiconductor substrate is mounted; and a case fixed to the base member and having an opening for accommodating the semiconductor substrate.

11. The semiconductor device according to claim 10, further comprising a lead frame joined to said semiconductor substrate, said case having a lead frame positioning portion for positioning said lead frame.

12. The semiconductor device according to claim 10, wherein the case is provided with a control terminal identification section for identifying the positions of control terminals connected to the semiconductor element via wires by image processing.

13. A power conversion device comprising the semiconductor device according to claim 10, and performing power conversion using said semiconductor device.

14. A method for manufacturing a semiconductor device, comprising: a mounting board placement step of placing a mounting board on which a semiconductor element is mounted, on a base member; a case placement step of placing a case enclosing the mounting board on the base member; and a semiconductor element placement step of placing the semiconductor element on the mounting board, wherein in the semiconductor element placement step, the mounting position of the semiconductor element is identified by image processing based on a mounting position identification unit provided on the mounting board, and the semiconductor element is placed on the mounting board based on the identification result.

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