Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device in which warpage after a power module substrate and a cooling fin are joined is reduced. The semiconductor device comprises a cooling fin, a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and a plurality of intermediate materials. The first circuit pattern is attached to the cooling fin. The insulating substrate is provided above the first circuit pattern. The second circuit pattern is provided above the insulating substrate. The third circuit pattern is provided above the second circuit pattern. The plurality of intermediate materials are respectively provided between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second circuit pattern and the third circuit pattern.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A power module substrate on which power semiconductor elements are mounted is attached with cooling fins for cooling the power semiconductor elements. Patent Document 1 discloses a power module substrate with a heat sink.

[0003] JP 2013-98423 A

[0004] The power module substrate on which the power semiconductor elements are mounted has a multi-layer structure consisting of an insulating substrate and a circuit pattern, which can cause warping when the power module substrate is joined to the cooling fin.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that reduces warpage after bonding a power module substrate and a cooling fin.

[0006] The semiconductor device according to the present disclosure includes a cooling fin, a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and a plurality of intermediate members. The first circuit pattern is attached to the cooling fin. The insulating substrate is provided above the first circuit pattern. The second circuit pattern is provided above the insulating substrate. The third circuit pattern is provided above the second circuit pattern. The plurality of intermediate members are respectively provided between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second circuit pattern and the third circuit pattern.

[0007] According to the present disclosure, a semiconductor device is provided that reduces warpage after bonding a power module substrate and a cooling fin.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] 1 is a cross-sectional view showing the configuration of a semiconductor device in a first embodiment; FIG. 2 is a cross-sectional view showing the configuration of a member included in the semiconductor device; FIG. 3 is a flowchart showing a method for manufacturing the semiconductor device in the first embodiment; FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device in a first modified example of the first embodiment; FIG. 5 is a cross-sectional view showing the configuration of a member included in the semiconductor device; FIG. 6 is a cross-sectional view showing the configuration of a semiconductor device in a second modified example of the first embodiment; FIG. 7 is a cross-sectional view showing the configuration of a member included in the semiconductor device; FIG. 8 is a cross-sectional view showing the configuration of a semiconductor device in a second embodiment; FIG. 9 is a cross-sectional view showing the configuration of a member included in the semiconductor device;

[0010] <First Embodiment> Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device 101 in a first embodiment. Fig. 2 is a cross-sectional view showing the configuration of components included in the semiconductor device 101. The semiconductor device 101 includes a cooling fin 10, a first circuit pattern 20, an insulating substrate 30, a second circuit pattern 40, a third circuit pattern 50, a plurality of intermediate members 60, and a semiconductor element (not shown). Hereinafter, the structure including the first circuit pattern 20, the insulating substrate 30, the second circuit pattern 40, the third circuit pattern 50, and the plurality of intermediate members 60 will be referred to as a power module substrate.

[0011] The cooling fin 10 includes a plate portion 10A and a fin portion 10B. The fin portion 10B is provided on the underside of the plate portion 10A. The plate portion 10A has an attachment surface on its upper surface. The cooling fin 10 has the function of transferring heat generated by electronic components such as semiconductor devices to the outside. The cooling fin 10 is made of a metal such as copper or aluminum. The cooling fin 10 is also called a heat sink or a radiator.

[0012] The first circuit pattern 20 is attached to the mounting surface of the cooling fin 10 via an intermediate material 60. The first circuit pattern 20 is made of, for example, an Al-Mg-Si alloy. The first circuit pattern 20 is made of, for example, A6063, which is specified in the JIS (Japanese Industrial Standards).

[0013] The insulating substrate 30 is provided above the first circuit pattern 20 via an intermediate material 60. The insulating substrate 30 is made of, for example, ceramic. The ceramic is, for example, SiN.

[0014] The second circuit pattern 40 is provided above the insulating substrate 30 via an intermediate material 60. The second circuit pattern 40 is made of, for example, Al. The purity of the Al is, for example, 99.99% or more (4N).

[0015] The third circuit pattern 50 is provided above the second circuit pattern 40 via an intermediate material 60. The third circuit pattern 50 is formed of, for example, an Al-Mg-Si alloy. The third circuit pattern 50 is formed of, for example, A6063 specified in the JIS standard.

[0016] As described above, the intermediate material 60 is provided between the cooling fin 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50. The thickness of each intermediate material 60 is preferably thinner than the thickness of any of the first circuit pattern 20, the second circuit pattern 40, and the third circuit pattern 50. The intermediate material 60 is, for example, conductive. The intermediate material 60 is, for example, a brazing sheet, which is a clad material in which a brazing material is rolled and integrated onto a core material.

[0017] The semiconductor element is mounted on the third circuit pattern 50 via, for example, a bonding material (not shown). The semiconductor element is also called a semiconductor chip. The semiconductor element is made of, for example, a semiconductor such as Si. The semiconductor element may be made of SiC, GaN, Ga ２ O ３It is preferable that the semiconductor element is formed of a so-called wide bandgap semiconductor such as diamond. The semiconductor element is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, or the like. The semiconductor element includes, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a Schottky barrier diode, or the like. Alternatively, the semiconductor element may include a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a free wheel diode are formed within a single semiconductor substrate.

[0018] The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. The first circuit pattern 20 preferably has a thickness such that the difference in volume between the components above the insulating substrate 30 and the components below the insulating substrate 30 is within 15%. Here, the components below the insulating substrate 30 include only the plate portion 10A of the cooling fin 10, which is predominantly related to the rigidity of the cooling fin 10. The plate portion 10A, which is predominantly related to the rigidity of the cooling fin 10, corresponds to the shaded area A in FIG. 2. In other words, the components below the insulating substrate 30 do not include the fin portion 10B of the cooling fin 10 or the frame portion provided around the outer periphery of the plate portion 10A.

[0019] In such a semiconductor device 101, the rigidity of the members below the insulating substrate 30 is reduced, which reduces warpage after bonding the power module substrate and the cooling fin 10. For example, convex warpage on the cooling fin 10 side, i.e., the lower side, is reduced.

[0020] FIG. 3 is a flowchart showing a method for manufacturing the semiconductor device 101 according to the first embodiment.

[0021] In step S1, the cooling fin 10 is prepared.

[0022] In step S2, the first circuit pattern 20, the insulating substrate 30, the second circuit pattern 40, the third circuit pattern 50, and a plurality of intermediate materials 60 are stacked on the cooling fin 10. At this time, the intermediate materials 60 are respectively arranged between the cooling fin 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50.

[0023] In step S3, the cooling fin 10, the first circuit pattern 20, the insulating substrate 30, the second circuit pattern 40 and the third circuit pattern 50 are joined together by a plurality of intermediate members 60.

[0024] For example, after step S3, the semiconductor element is mounted on the third circuit pattern 50. With the above steps, the semiconductor device 101 of the first embodiment is completed.

[0025] In this manufacturing method, after each component is stacked on the cooling fin 10, the components are bonded together at once using the intermediate material 60. Even if the thickness of the circuit pattern on the upper side of the insulating substrate 30 is different from the thickness of the circuit pattern on the lower side, good bonding is achieved.

[0026] In summary, the semiconductor device 101 in the first embodiment includes a cooling fin 10, a first circuit pattern 20, an insulating substrate 30, a second circuit pattern 40, a third circuit pattern 50, and a plurality of intermediate members 60. The first circuit pattern 20 is attached to the cooling fin 10. The insulating substrate 30 is provided above the first circuit pattern 20. The second circuit pattern 40 is provided above the insulating substrate 30. The third circuit pattern 50 is provided above the second circuit pattern 40. The plurality of intermediate members 60 are provided between the cooling fin 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50, respectively. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50.

[0027] In such a semiconductor device 101, warping after bonding the power module substrate and the cooling fin 10 is reduced.

[0028] (First Modification of First Embodiment) Fig. 4 is a cross-sectional view showing the configuration of a semiconductor device 101A according to a first modification of the first embodiment. Fig. 5 is a cross-sectional view showing the configuration of members included in the semiconductor device 101A.

[0029] In the first modification, the second circuit pattern 40 is thicker than the third circuit pattern 50. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. Even with this configuration, the same effects as those of the first embodiment can be obtained.

[0030] (Modification 2 of Embodiment 1) Fig. 6 is a cross-sectional view showing the configuration of a semiconductor device 101B according to Modification 2 of Embodiment 1. Fig. 7 is a cross-sectional view showing the configuration of members included in the semiconductor device 101B.

[0031] In the second modification, the third circuit pattern 50 is thicker than the second circuit pattern 40. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. Even with this configuration, the same effects as those of the first embodiment can be obtained.

[0032] Second Embodiment In a second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0033] 8 is a cross-sectional view showing the configuration of a semiconductor device 102 according to the second embodiment. FIG. 9 is a cross-sectional view showing the configuration of members included in the semiconductor device 102.

[0034] The semiconductor device 102 includes a first clad material 71 and a second clad material 72. The plurality of intermediate materials 60 include a first intermediate material 61, a second intermediate material 62, a third intermediate material 63, and a fourth intermediate material 64.

[0035] The first clad material 71 includes a first circuit pattern 20, a first intermediate material 61, and a second intermediate material 62. The first circuit pattern 20 is a base material. The first intermediate material 61 is joined to the lower surface of the first circuit pattern 20 as a brazing material. The second intermediate material 62 is joined to the upper surface of the first circuit pattern 20 as a brazing material. The first clad material 71 is a double-sided brazing clad circuit pattern in which brazing material is joined to both surfaces of the first circuit pattern 20.

[0036] The second clad material 72 includes a second circuit pattern 40, a third intermediate material 63, and a fourth intermediate material 64. The second circuit pattern 40 is a base material. The third intermediate material 63 is joined to the lower surface of the second circuit pattern 40 as a brazing material. The fourth intermediate material 64 is joined to the upper surface of the second circuit pattern 40 as a brazing material. The second clad material 72 is a double-sided brazing clad circuit pattern in which brazing material is joined to both surfaces of the second circuit pattern 40. In the manufacturing method, the components shown in FIG. 9 are stacked in step S2 of FIG. 3, and then joined together in step S3.

[0037] Even with this configuration, it is possible to obtain the same effects as in embodiment 1. Furthermore, the number of components constituting the semiconductor device 102 is reduced, and the thermal resistance is also reduced.

[0038] Third Embodiment In a third embodiment, the same components as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0039] 10 is a cross-sectional view showing the configuration of a semiconductor device 103 according to the third embodiment. FIG. 11 is a cross-sectional view showing the configuration of members included in the semiconductor device 103.

[0040] The second circuit pattern 40 and the third circuit pattern 50 are clad materials directly bonded to each other. The second circuit pattern 40 is made of, for example, Al. The purity of the Al is, for example, 99.99% or more (4N). The third circuit pattern 50 is made of, for example, Cu. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. In the manufacturing method, the components shown in FIG. 11 are stacked in step S2 of FIG. 3 and then bonded together in step S3.

[0041] Even with this configuration, it is possible to obtain the same effects as in embodiment 1. Furthermore, the number of components constituting the semiconductor device 103 is reduced, and the thermal resistance is also reduced.

[0042] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0043] In the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0044] 10 Cooling fin, 10A Plate portion, 10B Fin portion, 20 First circuit pattern, 30 Insulating substrate, 40 Second circuit pattern, 50 Third circuit pattern, 60 Intermediate material, 61 First intermediate material, 62 Second intermediate material, 63 Third intermediate material, 64 Fourth intermediate material, 71 First clad material, 72 Second clad material, 101 Semiconductor device, 101A Semiconductor device, 101B Semiconductor device, 102 Semiconductor device, 103 Semiconductor device, A Region.

Claims

1. A semiconductor device comprising: a cooling fin; a first circuit pattern attached to the cooling fin; an insulating substrate provided above the first circuit pattern; a second circuit pattern provided above the insulating substrate; a third circuit pattern provided above the second circuit pattern; and a plurality of intermediate materials provided respectively between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern, wherein the thickness of the first circuit pattern is thinner than at least one of the thicknesses of the second circuit pattern and the third circuit pattern.

2. The semiconductor device according to claim 1, wherein said second circuit pattern is thicker than said third circuit pattern.

3. The semiconductor device according to claim 1, wherein said third circuit pattern is thicker than said second circuit pattern.

4. A semiconductor device as described in any one of claims 1 to 3, further comprising a first clad material and a second clad material, wherein the plurality of intermediate materials include a first intermediate material joined as a brazing material to the underside of the first circuit pattern, a second intermediate material joined as a brazing material to the upper surface of the first circuit pattern, a third intermediate material joined as a brazing material to the underside of the second circuit pattern, and a fourth intermediate material joined as a brazing material to the upper surface of the second circuit pattern, wherein the first clad material includes the first circuit pattern, the first intermediate material, and the second intermediate material, and the second clad material includes the second circuit pattern, the third intermediate material, and the fourth intermediate material.

5. A semiconductor device comprising: a cooling fin; a first circuit pattern attached to the cooling fin; an insulating substrate provided above the first circuit pattern; a second circuit pattern provided above the insulating substrate; a third circuit pattern provided above the second circuit pattern; and a plurality of intermediate materials provided between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, and between the insulating substrate and the second circuit pattern, wherein the thickness of the first circuit pattern is thinner than a thickness of at least one of the second circuit pattern and the third circuit pattern, and the second circuit pattern and the third circuit pattern are clad materials directly bonded to each other.

6. A method for manufacturing a semiconductor device, comprising: a step of preparing a cooling fin; a step of stacking a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and multiple intermediate materials on the cooling fin; and a step of bonding the cooling fin, the first circuit pattern, the insulating substrate, the second circuit pattern, and the third circuit pattern together with the multiple intermediate materials, wherein the multiple intermediate materials are respectively arranged between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern, and a thickness of the first circuit pattern is thinner than a thickness of at least one of the second circuit pattern and the third circuit pattern.

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