Semiconductor device

Abstract

This semiconductor device comprises a first terminal, a second terminal, a third terminal, a fourth terminal, a first lead, a second lead, a semiconductor element, and a sealing resin. A dimension of a first exposed surface of the first lead is larger than a dimension of a first mounting surface of the first terminal. A dimension of a second exposed surface of the second lead is larger than a dimension of a second mounting surface of the second terminal. When viewed in a third direction, which is a direction normal to the bottom surface of the sealing resin, a first end of the first exposed surface and a third end of the second exposed surface are positioned further inward than the peripheral edge of the sealing resin. When viewed in the third direction, a fourth end of the second exposed surface overlaps the peripheral edge of the sealing resin.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] QFN, in which multiple leads are arranged on all four sides, is known as one type of package format for semiconductor devices. Patent Document 1 discloses an example of a QFN semiconductor device. In this semiconductor device, the end faces of the multiple leads that mount a semiconductor element are exposed so as to be flush with the side surfaces of the sealing resin (packaging material in Patent Document 1). Additionally, the back surfaces of the multiple leads are exposed so as to be flush with the bottom surface of the sealing resin. Therefore, compared to QFP, a package format in which multiple leads protrude from the side surfaces of the sealing resin, this semiconductor device has the advantage of being smaller in size while reducing the mounting area of ​​the semiconductor device on a wiring board.

[0003] In the semiconductor device disclosed in Patent Document 1, thermal stress occurs in each of the multiple leads due to heat generated by the semiconductor element. Differences in the shape of each of the multiple leads can cause unevenness in the magnitude of the thermal stress acting on each of the multiple leads. This raises concerns that cracks may occur and propagate in the solder that electrically connects the semiconductor device to the wiring board during use of the semiconductor device.

[0004] Japanese Patent Application Laid-Open No. 2020-77694

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can more uniformly distribute thermal stress acting on each of a plurality of terminals.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a first terminal and a fourth terminal spaced apart from each other in a first direction; a second terminal and a third terminal spaced apart from each other in a second direction perpendicular to the first direction; a semiconductor element electrically connected to at least one of the first terminal, the second terminal, the third terminal, and the fourth terminal; a first lead located adjacent to the first terminal in the second direction and extending in the first direction; a second lead located adjacent to the second terminal in the first direction and extending in the second direction; and a sealing resin covering the semiconductor element. The sealing resin has a bottom surface facing one side in a third direction perpendicular to the first and second directions. The first terminal, the second terminal, the first lead, and the second lead each have a first mounting surface, a second mounting surface, a first exposed surface, and a second exposed surface exposed from the bottom surface. The dimension of the first exposed surface in the first direction is greater than the dimension of the first mounting surface in the first direction. The dimension of the second exposed surface in the second direction is larger than the dimension of the second mounting surface in the second direction. The first exposed surface has a first end and a second end spaced apart from each other in the first direction. The second exposed surface has a third end and a fourth end spaced apart from each other in the second direction. When viewed in the third direction, the first end and the third end are located inward from the periphery of the sealing resin. When viewed in the third direction, the fourth end overlaps the periphery of the sealing resin.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 , seen through a sealing resin. FIG. 3 is a plan view corresponding to FIG. 2 , further seen through a semiconductor element. FIG. 4 is a bottom view of the semiconductor device shown in FIG. 1 . FIG. 5 is a front view of the semiconductor device shown in FIG. 1 . FIG. 6 is a rear view of the semiconductor device shown in FIG. 1 . FIG. 7 is a right side view of the semiconductor device shown in FIG. 1 . FIG. 8 is a left side view of the semiconductor device shown in FIG. 1 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3 . FIG. 10 is a cross-sectional view taken along line X-X in FIG. 3 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3 . FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3 . FIG. 14 is a plan view of a semiconductor device according to a modified example of the first embodiment of the present disclosure, seen through a sealing resin and a semiconductor element. FIG. 15 is a bottom view of the semiconductor device shown in FIG. 14 . FIG. 16 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, with the sealing resin and semiconductor element seen through. FIG. 17 is a bottom view of the semiconductor device shown in FIG. 16 . FIG. 18 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, with the sealing resin and semiconductor element seen through. FIG. 19 is a bottom view of the semiconductor device shown in FIG. 18 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 18 . FIG. 22 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, with the sealing resin and semiconductor element seen through. FIG. 23 is a bottom view of the semiconductor device shown in FIG. 22 . FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 22 . FIG. 25 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure, with the sealing resin and semiconductor element seen through. FIG. 26 is a bottom view of the semiconductor device shown in FIG. 25 . Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 25. Fig. 28 is a plan view of a semiconductor device according to a modified example of the fifth embodiment of the present disclosure, seen through the sealing resin and the semiconductor element. Fig. 29 is a bottom view of the semiconductor device shown in Fig. 28. Fig. 30 is a plan view of a semiconductor device according to a sixth embodiment of the present disclosure, seen through the sealing resin and the semiconductor element. Fig. 31 is a bottom view of the semiconductor device shown in Fig. 30.FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG.

[0009] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0010] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 13. The semiconductor device A10 includes a plurality of first terminals 11, a plurality of second terminals 12, a plurality of third terminals 13, a plurality of fourth terminals 14, a plurality of dummy terminals 19, a first lead 21, a second lead 22, a third lead 23, a semiconductor element 30, and a sealing resin 40. The semiconductor device A10 is packaged in a QFN (Quad For Non-Lead Package) format. For ease of understanding, FIGS. 2 and 3 show the sealing resin 40 in a see-through manner. For ease of understanding, FIG. 3 also shows the semiconductor element 30 in a see-through manner. In FIGS. 2 and 3, the outline of the sealing resin 40 is shown by an imaginary line (double-dashed line). In FIG. 3, the outline of the semiconductor element 30 is also shown by an imaginary line.

[0011] In the description of the semiconductor device A10, for convenience, the direction in which the multiple second terminals 12 are arranged will be referred to as the "first direction x." A direction perpendicular to the first direction x will be referred to as the "second direction y." A direction perpendicular to both the first direction x and the second direction y will be referred to as the "third direction z." The third direction z corresponds to the normal direction to each of the top surface 41 and the bottom surface 42 of the sealing resin 40, which will be described later.

[0012] As shown in Figures 9, 11, and 13, the sealing resin 40 covers a portion of each of the multiple first terminals 11, a portion of each of the multiple second terminals 12, a portion of each of the multiple third terminals 13, and a portion of each of the multiple fourth terminals 14. Furthermore, as shown in Figures 10 and 12, the sealing resin 40 covers a portion of each of the first lead 21, the second lead 22, and the third lead 23, as well as the semiconductor element 30. The sealing resin 40 has electrical insulation properties. An example of a material for the sealing resin 40 is black epoxy resin. When viewed in the third direction z, the sealing resin 40 has a rectangular shape.

[0013] As shown in FIGS. 5 to 8 , the sealing resin 40 has a top surface 41, a bottom surface 42, a first side surface 43, a second side surface 44, a third side surface 45, and a fourth side surface 46. The top surface 41 faces one side in the third direction z. As shown in FIG. 1 , the top surface 41 includes a peripheral edge 401 of the sealing resin 40. The bottom surface 42 faces the opposite side from the top surface 41 in the third direction z. The first side surface 43 faces one side in the first direction x. The second side surface 44 faces one side in the second direction y. The third side surface 45 faces the opposite side from the second side surface 44 in the second direction y. The fourth side surface 46 faces the opposite side from the first side surface 43 in the first direction x.

[0014] As shown in FIGS. 9 to 13 , each of the plurality of first terminals 11, the plurality of second terminals 12, the plurality of third terminals 13, the plurality of fourth terminals 14, the first lead 21, the second lead 22, and the third lead 23 carries a semiconductor element 30. These terminals and leads form a conductive path between the semiconductor element 30 and a wiring board on which the semiconductor device A10 is mounted. These terminals and leads contain copper (Cu). These terminals and leads are obtained from the same lead frame.

[0015] 2 and 3 , the multiple first terminals 11 are located on one side in the first direction x. The multiple first terminals 11 are arranged along the second direction y. In the semiconductor device A10, two of the multiple first terminals 11 that are adjacent to each other in the second direction y are connected to each other.

[0016] As shown in FIGS. 9 and 11 , each of the multiple first terminals 11 has a first mounting surface 111, a first mounting surface 112, a first end surface 113, and a first intermediate surface 114. The first mounting surface 111 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The first mounting surface 111 faces the semiconductor element 30. The first mounting surface 112 faces the opposite side from the first mounting surface 111 in the third direction z. The first mounting surface 112 is exposed from the bottom surface 42 of the sealing resin 40. The first end surface 113 faces one side in the first direction x. The first end surface 113 is exposed from the first side surface 43 of the sealing resin 40. The first intermediate surface 114 is located between the first mounting surface 111 and the first mounting surface 112 in the third direction z. When viewed in the third direction z, the first intermediate surface 114 overlaps the first mounting surface 111. The first intermediate surface 114 is covered with the sealing resin 40.

[0017] 2 and 3, the second terminals 12 are located on one side in the second direction y. The second terminals 12 are arranged along the first direction x.

[0018] As shown in FIG. 13 , each of the multiple second terminals 12 has a second mounting surface 121, a second mounting surface 122, a second end surface 123, and a second intermediate surface 124. The second mounting surface 121 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The second mounting surface 121 faces the semiconductor element 30. The second mounting surface 122 faces the opposite side from the second mounting surface 121 in the third direction z. The second mounting surface 122 is exposed from the bottom surface 42 of the sealing resin 40. The second end surface 123 faces one side in the second direction y. The second end surface 123 is exposed from the second side surface 44 of the sealing resin 40. The second intermediate surface 124 is located between the second mounting surface 121 and the second mounting surface 122 in the third direction z. When viewed in the third direction z, the second intermediate surface 124 overlaps the second mounting surface 121. The second interface surface 124 is covered with a sealing resin 40 .

[0019] 2 and 3, the third terminals 13 are located on the opposite side of the semiconductor element 30 from the second terminals 12 in the second direction y. The third terminals 13 are arranged along the first direction x.

[0020] As shown in FIG. 13 , each of the multiple third terminals 13 has a third mounting surface 131, a third mounting surface 132, a third end surface 133, and a third intermediate surface 134. The third mounting surface 131 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The third mounting surface 131 faces the opposite side from the third mounting surface 131 in the third direction z. The third mounting surface 132 is exposed from the bottom surface 42 of the sealing resin 40. The third end surface 133 faces the opposite side from the side to which the second end surfaces 123 of each of the multiple second terminals 12 face in the second direction y. The third end surface 133 is exposed from the third side surface 45 of the sealing resin 40. The third intermediate surface 134 is located between the third mounting surface 131 and the third mounting surface 132 in the third direction z. When viewed in the third direction z, the third intermediate surface 134 overlaps the third mounting surface 131. The third intermediate surface 134 is covered with the sealing resin 40.

[0021] 2 and 3 , the multiple fourth terminals 14 are located on the opposite side of the multiple first terminals 11 in the first direction x with the semiconductor element 30 as the reference. The multiple fourth terminals 14 are arranged along the second direction y. In the semiconductor device A10, any of the multiple fourth terminals 14 is connected to any of the multiple first terminals 11. Furthermore, any of the multiple fourth terminals 14 is connected to any of the multiple third terminals 13.

[0022] As shown in FIGS. 9 and 11 , each of the multiple fourth terminals 14 has a fourth mounting surface 141, a fourth mounting surface 142, a fourth end surface 143, and a fourth intermediate surface 144. The fourth mounting surface 141 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The fourth mounting surface 141 faces the semiconductor element 30. The fourth mounting surface 142 faces the opposite side from the fourth mounting surface 141 in the third direction z. The fourth mounting surface 142 is exposed from the bottom surface 42 of the sealing resin 40. The fourth end surface 143 faces the opposite side from the side to which the first end surfaces 113 of each of the multiple first terminals 11 face in the first direction x. The fourth end surface 143 is exposed from the fourth side surface 46 of the sealing resin 40. The fourth intermediate surface 144 is located between the fourth mounting surface 141 and the fourth mounting surface 142 in the third direction z. When viewed in the third direction z, the fourth intermediate surface 144 overlaps the fourth mounting surface 141. The fourth intermediate surface 144 is covered with the sealing resin 40.

[0023] As shown in FIGS. 2 to 4 , the first lead 21 is located adjacent to one of the multiple first terminals 11 in the second direction y. The first lead 21 extends in the first direction x. In the semiconductor device A10, the first lead 21 is connected to one of the multiple fourth terminals 14. As shown in FIG. 10 , the first lead 21 has a first main surface 211, a first exposed surface 212, and a first end surface 213. The first main surface 211 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The first main surface 211 faces the semiconductor element 30. The first exposed surface 212 faces the opposite side from the first main surface 211 in the third direction z. The first exposed surface 212 is exposed from the bottom surface 42 of the sealing resin 40. The first end surface 213 faces the same side as the first end surfaces 113 of the multiple first terminals 11 in the first direction x. The first end surface 213 is exposed from the first side surface 43 of the sealing resin 40 .

[0024] As shown in FIG. 4 , the dimension D1 in the first direction x of the first exposed surface 212 of the first lead 21 is larger than the dimension L1 in the first direction x of the first mounting surface 112 of one of the multiple first terminals 11 located adjacent to the first lead 21 in the second direction y. As shown in FIGS. 4 and 10 , the first exposed surface 212 has a first end 212A and a second end 212B that are spaced apart from each other in the first direction x. As viewed in the third direction z, the first end 212A is located inward from the periphery 401 of the sealing resin 40. As viewed in the third direction z, the second end 212B overlaps the periphery 401 of the sealing resin 40. The second end 212B is in contact with the bottom surface 42 of the sealing resin 40. With respect to the first mounting surface 112 of one of the multiple first terminals 11 located adjacent to the first lead 21 in the second direction y, the second end 212B is located closer to the first mounting surface 112 than the first end 212A.

[0025] As shown in FIGS. 2 to 4 , the second lead 22 is located adjacent to one of the multiple second terminals 12 in the first direction x. The second lead 22 extends in the second direction y. As shown in FIG. 12 , the second lead 22 has a second main surface 221, a second exposed surface 222, and a second end surface 223. The second main surface 221 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The second main surface 221 faces the semiconductor element 30. The second exposed surface 222 faces the opposite side from the second main surface 221 in the third direction z. The second exposed surface 222 is exposed from the bottom surface 42 of the sealing resin 40. The second end surface 223 faces the same side as the second end surfaces 123 of each of the multiple second terminals 12 in the second direction y. The second end surface 223 is exposed from the second side surface 44 of the sealing resin 40.

[0026] As shown in FIG. 4 , the dimension D2 in the second direction y of the second exposed surface 222 of the second lead 22 is larger than the dimension L2 in the second direction y of the second mounting surface 122 of any of the multiple second terminals 12 located adjacent to the second lead 22 in the first direction x. As shown in FIGS. 4 and 12 , the second exposed surface 222 has a third end 222A and a fourth end 222B that are spaced apart from each other in the second direction y. As viewed in the third direction z, the third end 222A is located inward from the periphery 401 of the sealing resin 40. As viewed in the third direction z, the fourth end 222B overlaps the periphery 401 of the sealing resin 40. The fourth end 222B is in contact with the bottom surface 42 of the sealing resin 40. With respect to the second mounting surface 122 of any of the multiple second terminals 12 located adjacent to the second lead 22 in the first direction x, the fourth end 222B is located closer to the second mounting surface 122 than the third end 222A.

[0027] As shown in FIGS. 2 to 4 , the third lead 23 is located adjacent to one of the multiple third terminals 13 in the first direction x. The third lead 23 extends in the second direction y. As shown in FIG. 12 , the third lead 23 has a third main surface 231, a third exposed surface 232, and a third end surface 233. The third main surface 231 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The third main surface 231 faces the semiconductor element 30. The third exposed surface 232 faces the opposite side from the third main surface 231 in the third direction z. The third exposed surface 232 is exposed from the bottom surface 42 of the sealing resin 40. The third end surface 233 faces the same side as the third end surfaces 133 of each of the multiple third terminals 13 in the second direction y. The third end surface 233 is exposed from a third side surface 45 of the sealing resin 40.

[0028] As shown in FIG. 4 , the dimension D3 in the second direction y of the third exposed surface 232 of the third lead 23 is larger than the dimension L3 in the second direction y of the third mounting surface 132 of any of the multiple third terminals 13 located adjacent to the third lead 23 in the first direction x. As shown in FIGS. 4 and 12 , the third exposed surface 232 has a fifth end 232A and a sixth end 232B that are spaced apart from each other in the second direction y. As viewed in the third direction z, the fifth end 232A is located inward from the periphery 401 of the sealing resin 40. As viewed in the third direction z, the sixth end 232B overlaps the periphery 401 of the sealing resin 40. The sixth end 232B is in contact with the bottom surface 42 of the sealing resin 40. With respect to the third mounting surface 132 of any of the multiple third terminals 13 located adjacent to the third lead 23 in the first direction x, the sixth end 232B is located closer to the third mounting surface 132 than the fifth end 232A.

[0029] 4 , the dimension D1 of the first exposed surface 212 of the first lead 21 is larger than the dimension D2 of the second exposed surface 222 of the second lead 22. In the semiconductor device A10, the dimension D3 of the third exposed surface 232 of the third lead 23 is equal to the dimension D2 of the second exposed surface 222.

[0030] 4 , in the third direction z, the first center line C1 overlaps the first exposed surface 212 of the first lead 21 and the third exposed surface 232 of the third lead 23. Here, the first center line C1 is a straight line that passes through the center of the second exposed surface 222 of the second lead 22 in the first direction x and extends in the second direction y. The third end 222A of the second exposed surface 222 is located closer to the first exposed surface 212 than the fifth end 232A of the third exposed surface 232.

[0031] 4 , as viewed in the third direction z, the distance between an intersection P of the first center line C1 and the second center line C2 and the center C of the bottom surface 42 of the sealing resin 40 is equal to or less than the dimension L1 of the first mounting surface 112 of any one of the multiple first terminals 11. Here, the second center line C2 is a straight line that passes through the center of the first exposed surface 212 of the first lead 21 in the second direction y and extends in the first direction x. As viewed in the third direction z, the second center line C2 overlaps with the fourth mounting surface 142 of any one of the multiple fourth terminals 14.

[0032] 2 to 4, the multiple dummy terminals 19 are arranged at four corners of the sealing resin 40 when viewed in the third direction z. At least one of the multiple dummy terminals 19 is not electrically connected to the semiconductor element 30. In the semiconductor device A10, any one of the multiple dummy terminals 19 is connected to any one of the multiple fourth terminals 14. The multiple dummy terminals 19 contain copper.

[0033] As shown in FIGS. 3 and 4 , each of the multiple dummy terminals 19 has a dummy exposed surface 191, a first surface 192, a second surface 193, and a third surface 194. The dummy exposed surface 191 faces the opposite side from the top surface 41 of the sealing resin 40 in the third direction z. The dummy exposed surface 191 is exposed from the bottom surface 42 of the sealing resin 40. The dimension of the dummy exposed surface 191 in the first direction x is larger than the dimension of the second mounting surface 122 of each of the multiple second terminals 12 in the first direction x. The dimension of the dummy exposed surface 191 in the second direction y is larger than the dimension of the first mounting surface 112 of each of the multiple first terminals 11 in the second direction y. The first surface 192 faces one side in the first direction x. The first surface 192 is exposed from either the first side surface 43 or the fourth side surface 46 of the sealing resin 40. The second surface 193 faces one side in the second direction y. The second surface 193 is exposed from either the second side surface 44 or the third side surface 45 of the sealing resin 40. The third surface 194 is connected to the first surface 192 and the second surface 193. The third surface 194 is inclined with respect to both the first direction x and the second direction y. The third surface 194 is covered with the sealing resin 40.

[0034] As shown in FIGS. 9 to 13 , the semiconductor element 30 is mounted on a plurality of first terminals 11, a plurality of second terminals 12, a plurality of third terminals 13, a plurality of fourth terminals 14, a first lead 21, a second lead 22, and a third lead 23. The semiconductor element 30 is, for example, an LSI (Large Scale Integration). The semiconductor element 30 has a plurality of electrodes 31. The plurality of electrodes 31 are positioned on sides facing the plurality of first terminals 11, the plurality of second terminals 12, the plurality of third terminals 13, and the plurality of fourth terminals 14 in the third direction z. Each of the plurality of electrodes 31 is conductively bonded to any one of the plurality of first terminals 11, the plurality of second terminals 12, the plurality of third terminals 13, the plurality of fourth terminals 14, the first lead 21, the second lead 22, and the third lead 23 via a bonding layer 39. As a result, the semiconductor element 30 is electrically connected to the plurality of first terminals 11, the plurality of second terminals 12, the plurality of third terminals 13, the plurality of fourth terminals 14, the first lead 21, the second lead 22, and the third lead 23. The bonding layer 39 contains nickel (Ni), laminated tin (Sn), and silver (Ag). In addition, the bonding layer 39 may contain nickel, tin, and antimony (Sb).

[0035] Next, a semiconductor device A11 according to a modified example of the first embodiment of the present disclosure will be described with reference to Fig. 14 and Fig. 15. For ease of understanding, Fig. 14 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In Fig. 14, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0036] As shown in FIG. 15, in the semiconductor device A11, the dimension D2 of the second exposed surface 222 of the second lead 22 is larger than the dimension D3 of the third exposed surface 232 of the third lead 23, compared to the semiconductor device A10.

[0037] Next, the effects of the semiconductor device A10 will be described.

[0038] The semiconductor device A10 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. This configuration reduces the unevenness in the magnitude of thermal stress acting on each of the first terminal 11 and the second terminal 12 due to heat generated from the semiconductor element 30. This suppresses the occurrence of cracks in the solder that conductively joins the wiring board and the semiconductor device A10 when the semiconductor device A10 is in use. Therefore, this configuration makes it possible to more uniformly distribute the thermal stress acting on each of the multiple terminals in the semiconductor device A10.

[0039] The semiconductor device A10 further includes a third lead 23. A dimension D3 of a third exposed surface 232 of the third lead 23 is larger than a dimension L3 of a third mounting surface 132 of the third terminal 13. As viewed in the third direction z, a fifth end 232A of the third exposed surface 232 is located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a sixth end 232B of the third exposed surface 232 overlaps the periphery 401 of the sealing resin 40. This configuration makes it possible to more uniformly distribute thermal stress acting on each of the first terminal 11, the second terminal 12, and the third terminal 13 due to heat generated from the semiconductor element 30.

[0040] In the above case, when viewed in the third direction z, the distance between the intersection P of the first center line C1 and the second center line C2 and the center C of the bottom surface 42 of the sealing resin 40 is equal to or less than the dimension L1 of the first mounting surface 112 of any one of the plurality of first terminals 11 (see FIG. 4 ). By adopting this configuration, the thermal stress acting on each of the first terminal 11, the second terminal 12, and the third terminal 13 can be more effectively uniformed.

[0041] A second end 212B of the first exposed surface 212 of the first lead 21, a fourth end 222B of the second exposed surface 222 of the second lead 22, and a sixth end 232B of the third exposed surface 232 of the third lead 23 are in contact with the bottom surface 42 of the sealing resin 40. By adopting this configuration, the concentration of thermal stress acting on each of the first lead 21, the second lead 22, and the third lead 23 can be reduced.

[0042] The sealing resin 40 has a first side surface 43 facing one side in the first direction x. The first terminal 11 and the first lead 21 are exposed from the first side surface 43. With this configuration, when the semiconductor device A10 is mounted on a wiring board, the volume of solder adhering to each of the first terminal 11 and the first lead 21 increases. This further improves the bonding strength of the semiconductor device A10 to the wiring board.

[0043] The sealing resin 40 has a second side surface 44 facing one side in the second direction y. The second terminals 12 and the second leads 22 are exposed from the second side surface 44. With this configuration, when the semiconductor device A10 is mounted on a wiring board, the volume of solder adhering to each of the second terminals 12 and the second leads 22 increases. This further improves the bonding strength of the semiconductor device A10 to the wiring board.

[0044] When viewed in the third direction z, the semiconductor device A10 further includes a plurality of dummy terminals 19 arranged at four corners of the sealing resin 40. Each of the plurality of dummy terminals 19 has a dummy exposed surface 191 exposed from the bottom surface 42 of the sealing resin 40. With this configuration, when the semiconductor device A10 is mounted on a wiring board, the dummy exposed surface 191 of each of the plurality of dummy terminals 19 is joined to the wiring board, thereby reducing the concentration of thermal stress acting on each of the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14.

[0045] In the above case, the dimension of dummy exposed surface 191 in the first direction x is larger than the dimension of second mounting surface 122 of second terminal 12 in the first direction x. In addition, the dimension of dummy exposed surface 191 in the second direction y is larger than the dimension of first terminal 11 in the second direction y. By adopting this configuration, the concentration of thermal stress acting on each of first terminal 11, second terminal 12, third terminal 13, and fourth terminal 14 can be more effectively reduced.

[0046] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 16 and 17. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 16 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In Figure 16, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0047] The semiconductor device A20 differs from the semiconductor device A10 in that it does not include the third lead 23.

[0048] 16 and 17, the semiconductor device A20 does not include the third lead 23. In the semiconductor device A20, the third lead 23 is replaced with the third terminal 13.

[0049] Next, the effects of the semiconductor device A20 will be described.

[0050] The semiconductor device A20 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. Therefore, with this configuration, even in the semiconductor device A20, it is possible to more uniformly apply thermal stress to each of the multiple terminals. Furthermore, the semiconductor device A20 has the same configuration as the semiconductor device A10, and thus exhibits the same effects as the semiconductor device A10.

[0051] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 18 to 21. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 18 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In FIG. 18, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0052] In the semiconductor device A30, the configurations of the second lead 22 and the third lead 23 are different from those of the semiconductor device A10.

[0053] 18 to 21, the position of the third lead 23 is different from that in the semiconductor device A10. When viewed in the third direction z, the first center line C1 is spaced apart from the third exposed surface 232 of the third lead 23.

[0054] Next, the effects of the semiconductor device A30 will be described.

[0055] The semiconductor device A30 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. Therefore, with this configuration, even in the semiconductor device A30, it is possible to more uniformly apply thermal stress to each of the multiple terminals. Furthermore, the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus exhibits the same effects as the semiconductor device A10.

[0056] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 22 to 24. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 22 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In FIG. 22, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0057] In the semiconductor device A40, the configuration of the first lead 21 is different from that of the semiconductor device A10.

[0058] 23 and 24 , the second end 212B of the first exposed surface 212 of the first lead 21 is located inward from the peripheral edge 401 of the sealing resin 40. The dimension D1 of the first exposed surface 212 is smaller than the dimension D1 in the case of the semiconductor device A10. When viewed in the third direction z, the first center line C1 overlaps the first exposed surface 212.

[0059] Next, the effects of the semiconductor device A40 will be described.

[0060] The semiconductor device A40 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. Therefore, with this configuration, even in the semiconductor device A40, it is possible to more uniformly apply thermal stress to each of the multiple terminals. Furthermore, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus exhibits the same effects as the semiconductor device A10.

[0061] Fifth Embodiment: A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 25 to 27. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 25 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In FIG. 25, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0062] The semiconductor device A50 differs from the semiconductor device A10 in that it further includes a fourth lead 24.

[0063] As shown in FIGS. 25 and 26 , the fourth lead 24 is located adjacent to one of the multiple fourth terminals 14 in the second direction y. The fourth lead 24 extends in the first direction x. In the semiconductor device A50, the fourth lead 24 is connected to the first lead 21. This allows the fourth lead 24 to be electrically connected to the semiconductor element 30 via the first lead 21. The fourth lead 24 has a fourth main surface 241, a fourth exposed surface 242, and a fourth end surface 243. The fourth main surface 241 faces the same side as the top surface 41 of the sealing resin 40 in the third direction z. The fourth main surface 241 faces the semiconductor element 30. The fourth exposed surface 242 faces the opposite side to the fourth main surface 241 in the third direction z. The fourth exposed surface 242 is exposed from the bottom surface 42 of the sealing resin 40. The fourth end surface 243 faces the same side in the first direction x as the fourth end surfaces 143 of the plurality of fourth terminals 14. The fourth end surface 243 is exposed from a fourth side surface 46 of the sealing resin 40.

[0064] 26 , the dimension D4 in the first direction x of the fourth exposed surface 242 of the fourth lead 24 is larger than the dimension L4 in the first direction x of any of the fourth mounting surfaces 142 of the multiple fourth terminals 14 located adjacent to the fourth lead 24 in the second direction y. As shown in FIGS. 26 and 27 , the fourth exposed surface 242 has a seventh end 242A and an eighth end 242B that are spaced apart from each other in the first direction x. As viewed in the third direction z, the seventh end 242A is located inward from the periphery 401 of the sealing resin 40. As viewed in the third direction z, the eighth end 242B overlaps the periphery 401 of the sealing resin 40. The eighth end 242B is in contact with the bottom surface 42 of the sealing resin 40. With respect to the fourth mounting surface 142 of any one of the plurality of fourth terminals 14 located adjacent to the fourth lead 24 in the second direction y, the eighth end 242B is located closer to the fourth mounting surface 142 than the seventh end 242A.

[0065] 26 , when viewed in the third direction z, the first center line C1 is spaced apart from the first exposed surface 212 of the first lead 21 and the fourth exposed surface 242 of the fourth lead 24. When viewed in the third direction z, the second center line C2 overlaps the fourth exposed surface 242 and is spaced apart from the second exposed surface 222 of the second lead 22 and the third exposed surface 232 of the third lead 23. A dimension D4 of the fourth exposed surface 242 is different from the dimension D2 of the first exposed surface 212 of the first lead 21. In the semiconductor device A50, the dimension D4 of the fourth exposed surface 242 is larger than the dimension D1 of the first exposed surface 212.

[0066] Next, a semiconductor device A51 according to a modification of the fifth embodiment of the present disclosure will be described with reference to Fig. 28 and Fig. 29. For ease of understanding, Fig. 28 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In Fig. 28, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0067] 29 , in the semiconductor device A51, when viewed in the third direction z, the first center line C1 overlaps the first exposed surface 212 of the first lead 21 and is spaced apart from the fourth exposed surface 242 of the fourth lead 24. In the semiconductor device A51, the dimension D4 of the fourth exposed surface 242 is smaller than the dimension D1 of the first exposed surface 212.

[0068] Next, the effects of the semiconductor device A50 will be described.

[0069] The semiconductor device A50 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. Therefore, with this configuration, even in the semiconductor device A50, it is possible to more uniformly apply thermal stress to each of the multiple terminals. Furthermore, the semiconductor device A50 has the same configuration as the semiconductor device A10, and thus exhibits the same effects as the semiconductor device A10.

[0070] The semiconductor device A50 further includes a fourth lead 24. A dimension D4 of a fourth exposed surface 242 of the fourth lead 24 is larger than a dimension L4 of a fourth mounting surface 142 of the fourth terminal 14. As viewed in the third direction z, a seventh end 242A of the fourth exposed surface 242 is located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, an eighth end 242B of the fourth exposed surface 242 overlaps the periphery 401 of the sealing resin 40. This configuration makes it possible to more uniformly distribute thermal stress acting on each of the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 due to heat generated from the semiconductor element 30.

[0071] Sixth Embodiment: A semiconductor device A60 according to a sixth embodiment of the present disclosure will be described with reference to FIGS. 30 to 32. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 30 shows a perspective view of the semiconductor element 30 and the sealing resin 40. In FIG. 30, the outlines of the semiconductor element 30 and the sealing resin 40 are shown by imaginary lines.

[0072] In the semiconductor device A60, the configurations of the plurality of first terminals 11 and the plurality of fourth terminals 14 are different from those of the semiconductor device A10.

[0073] 31 and 32 , two of the multiple first terminals 11 each have a first sub-mounting surface 115. The first sub-mounting surface 115 is exposed from the bottom surface 42 of the sealing resin 40. In each of the two first terminals 11, the first sub-mounting surface 115 is located more inward from the bottom surface 42 of the sealing resin 40 than the first mounting surface 112. In each of the two first terminals 11, the dimension of the first sub-mounting surface 115 in the second direction y is smaller than the dimension of the first mounting surface 112 in the second direction y. In each of the two first terminals 11, the first sub-mounting surface 115 is located closer to the first exposed surface 212 of the first lead 21 than the first mounting surface 112.

[0074] 31 and 32 , two of the multiple fourth terminals 14 each have a second sub-mounting surface 145. The second sub-mounting surface 145 is exposed from the bottom surface 42 of the sealing resin 40. In each of the two fourth terminals 14, the second sub-mounting surface 145 is located more inward from the bottom surface 42 of the sealing resin 40 than the fourth mounting surface 142. In each of the two fourth terminals 14, the dimension of the second sub-mounting surface 145 in the second direction y is smaller than the dimension of the fourth mounting surface 142 in the second direction y. In each of the two fourth terminals 14, the second sub-mounting surface 145 is located closer to the first exposed surface 212 of the first lead 21 than the fourth mounting surface 142.

[0075] Next, the effects of the semiconductor device A60 will be described.

[0076] The semiconductor device A60 includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, a first lead 21, a second lead 22, a semiconductor element 30, and a sealing resin 40. A dimension D1 of a first exposed surface 212 of the first lead 21 is larger than a dimension L1 of a first mounting surface 112 of the first terminal 11. A dimension D2 of a second exposed surface 222 of the second lead 22 is larger than a dimension L2 of a second mounting surface 122 of the second terminal 12. As viewed in the third direction z, a first end 212A of the first exposed surface 212 and a third end 222A of the second exposed surface 222 are located inward from a periphery 401 of the sealing resin 40. As viewed in the third direction z, a fourth end 222B of the second exposed surface 222 overlaps the periphery 401 of the sealing resin 40. Therefore, with this configuration, even in the semiconductor device A60, it is possible to more uniformly apply thermal stress to each of the multiple terminals. Furthermore, the semiconductor device A60 has the same configuration as the semiconductor device A10, and thus exhibits the same effects as the semiconductor device A10.

[0077] The first terminal 11 has a first sub-mounting surface 115 exposed from the bottom surface 42 of the sealing resin 40. The first sub-mounting surface 115 is located further inward from the bottom surface 42 than the first mounting surface 112 of the first terminal 11. With this configuration, when one of the multiple electrodes 31 of the semiconductor element 30 is conductively bonded to the first terminal 11, deflection of the first terminal 11 around a direction perpendicular to the third direction z is suppressed. This makes it possible to prevent a decrease in the bonding strength of the semiconductor element 30 to the first terminal 11.

[0078] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0079] The present disclosure includes embodiments described in the following appendices: Appendix 1. a first terminal and a fourth terminal spaced apart from each other in a first direction; a second terminal and a third terminal spaced apart from each other in a second direction perpendicular to the first direction; a semiconductor element conductive to at least one of the first terminal, the second terminal, the third terminal, and the fourth terminal; a first lead located adjacent to the first terminal in the second direction and extending in the first direction; a second lead located adjacent to the second terminal in the first direction and extending in the second direction; and a sealing resin covering the semiconductor element, wherein the sealing resin has a bottom surface facing one side in a third direction perpendicular to the first and second directions, the first terminal, the second terminal, the first lead, and the second lead each have a first mounting surface, a second mounting surface, a first exposed surface, and a second exposed surface exposed from the bottom surface, A semiconductor device in which the first exposed surface has a first end and a second end spaced apart in the first direction, the second exposed surface has a third end and a fourth end spaced apart in the second direction, the first end and the third end being located inward from a periphery of the sealing resin as viewed in the third direction, and the fourth end overlapping the periphery of the sealing resin as viewed in the third direction. Appendix 2. The semiconductor device according to Appendix 1, in which the fourth end is located closer to the second mounting surface than the third end and is in contact with the bottom surface. Appendix 3. The semiconductor device according to Appendix 2, in which a dimension of the first exposed surface in the first direction is larger than a dimension of the second exposed surface in the second direction. Appendix 4. The semiconductor device according to Appendix 3, in which a first center line passing through a center of the second exposed surface in the first direction and extending in the second direction overlaps the first exposed surface as viewed in the third direction. Appendix 5. The semiconductor device according to claim 4, wherein the second end is located closer to the first mounting surface than the first end and is in contact with the bottom surface. 6. The semiconductor device according to claim 4, wherein the second end is located inward from a periphery of the sealing resin when viewed in the third direction.Supplementary Note 7. The semiconductor device according to Supplementary Note 3, wherein, as viewed in the third direction, a first center line that passes through a center of the second exposed surface in the first direction and extends in the second direction is spaced from the first exposed surface.Supplementary Note 8. The semiconductor device according to any one of Supplementary Notes 4 to 7, further comprising a third lead located adjacent to the third terminal in the first direction and extending in the second direction, the third terminal and the third lead each having a third mounting surface and a third exposed surface exposed from the bottom surface, a dimension of the third exposed surface in the second direction being larger than a dimension of the third mounting surface in the second direction, the third exposed surface having a fifth end and a sixth end spaced apart from each other in the second direction, the fifth end being located inward from a periphery of the sealing resin as viewed in the third direction, and the sixth end overlapping a periphery of the sealing resin as viewed in the third direction.Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein the sixth end is located closer to the third mounting surface than the fifth end and is in contact with the bottom surface. Appendix 10. The semiconductor device of Appendix 9, wherein, as viewed in the third direction, the first center line overlaps the third exposed surface. Appendix 11. The semiconductor device of Appendix 10, wherein the third end is located closer to the first exposed surface than the fifth end. Appendix 12. The semiconductor device of Appendix 10, wherein, as viewed in the third direction, a distance between the center of the bottom surface and an intersection of the first center line and a second center line passing through the center of the first exposed surface in the second direction and extending in the first direction is shorter than a dimension of the first mounting surface in the first direction. Appendix 13. The semiconductor device of Appendix 9, wherein, as viewed in the third direction, the first center line is spaced apart from the third exposed surface. Appendix 14. The semiconductor device of Appendix 9, wherein the semiconductor element has a plurality of electrodes located on sides facing the first terminal, the second terminal, the third terminal, and the fourth terminal in the third direction, and any of the plurality of electrodes is conductively connected to any of the first terminal, the second terminal, the third terminal, and the fourth terminal. Appendix 15. The semiconductor device according to Appendix 14, wherein any one of the plurality of electrodes is conductively connected to any one of the first lead, the second lead, and the third lead.Appendix 16. The semiconductor device according to Appendix 15, wherein the sealing resin has a first side surface facing one side in the first direction, and the first terminal and the first lead are exposed from the first side surface. Appendix 17. The semiconductor device according to Appendix 16, wherein the sealing resin has a second side surface facing one side in the second direction, and the second terminal and the second lead are exposed from the second side surface. Appendix 18. The semiconductor device according to Appendix 17, further comprising a plurality of dummy terminals arranged at four corners of the sealing resin when viewed in the third direction, and each of the plurality of dummy terminals has a dummy exposed surface exposed from the bottom surface. Appendix 19. The semiconductor device according to Appendix 18, wherein the dimension in the first direction of the dummy exposed surface is larger than the dimension in the first direction of the second mounting surface, and the dimension in the second direction of the dummy exposed surface is larger than the dimension in the second direction of the first mounting surface. Appendix 20. Supplementary Note 9: The semiconductor device according to Supplementary Note 9, further comprising a fourth lead located adjacent to the fourth terminal in the second direction and extending in the first direction, wherein the fourth terminal and the fourth lead each have a fourth mounting surface and a fourth exposed surface exposed from the bottom surface, wherein a dimension of the fourth exposed surface in the first direction is larger than a dimension of the fourth mounting surface in the first direction, wherein the fourth exposed surface has seventh and eighth ends spaced apart in the first direction, wherein the seventh end is located inward from a periphery of the sealing resin as viewed in the third direction, and wherein the eighth end overlaps the periphery of the sealing resin as viewed in the third direction. Supplementary Note 21: The semiconductor device according to Supplementary Note 20, wherein the eighth end is located closer to the fourth mounting surface than the seventh end and is in contact with the bottom surface. Supplementary Note 22: The semiconductor device according to Supplementary Note 21, wherein a second center line passing through a center of the first exposed surface in the second direction and extending in the first direction overlaps the fourth exposed surface as viewed in the third direction. Appendix 23. The semiconductor device according to Appendix 22, wherein a dimension of the fourth exposed surface in the first direction is different from a dimension of the first exposed surface in the first direction. Appendix 24. The semiconductor device according to Appendix 22, wherein, when viewed in the third direction, the second center line is spaced apart from the second exposed surface and the third exposed surface.Appendix 25. The semiconductor device according to Appendix 9, wherein the first terminal has a first sub-mounting surface exposed from the bottom surface, and the first sub-mounting surface is located more inwardly from the bottom surface than the first mounting surface. Appendix 26. The semiconductor device according to Appendix 25, wherein a dimension of the first sub-mounting surface in the second direction is smaller than a dimension of the first mounting surface in the second direction. Appendix 27. The semiconductor device according to Appendix 26, wherein the first sub-mounting surface is located closer to the first exposed surface than the first mounting surface.

[0080] A10 to A60: semiconductor device 11: first terminal 111: first mounting surface 112: first mounting surface 113: first end surface 114: first intermediate surface 115: first sub-mounting surface 12: second terminal 121: second mounting surface 122: second mounting surface 123: second end surface 124: second intermediate surface 13: third terminal 131: third mounting surface 132: third mounting surface 133: third end surface 134: third intermediate surface 14: fourth terminal 141: fourth mounting surface 142: fourth mounting surface 143: fourth end surface 144: fourth intermediate surface 145: second sub-mounting surface 19: dummy terminal 191: dummy exposed surfaces 192 to 194: first surface to third surface 21: first lead 211: First main surface 212: First exposed surface 212A: First end 212B: Second end 213: First end surface 22: Second lead 221: Second main surface 222: Second exposed surface 222A: Third end 222B: Fourth end 223: Second end surface 23: Third lead 231: Third main surface 232: Third exposed surface 232A: Fifth end 232B: Sixth end 233: Third end surface 24: Fourth lead 241: Fourth main surface 242: Fourth exposed surface 242A: Seventh end 242B: Eighth end 243: Fourth end surface 30: Semiconductor element 31: Electrode 39: Bonding layer 40: Sealing resin 401: Periphery 41: Top surface 42: Bottom surface 43 to 46: First side surface to fourth side surface C1: First center line C2: Second center line x: First direction y: Second direction z: Third direction

Claims

1. A semiconductor device comprising: a first terminal and a fourth terminal spaced apart from each other in a first direction; a second terminal and a third terminal spaced apart from each other in a second direction perpendicular to the first direction; a semiconductor element conductive to at least one of the first terminal, the second terminal, the third terminal, and the fourth terminal; a first lead located adjacent to the first terminal in the second direction and extending in the first direction; a second lead located adjacent to the second terminal in the first direction and extending in the second direction; and a sealing resin covering the semiconductor element, wherein the sealing resin has a bottom surface facing one side of a third direction perpendicular to the first and second directions, the first terminal, the second terminal, the first lead, and the second lead each have a first mounting surface, a second mounting surface, a first exposed surface, and a second exposed surface exposed from the bottom surface, and a dimension of the first exposed surface in the first direction is greater than a dimension of the first mounting surface in the first direction, A semiconductor device, wherein a dimension of the second exposed surface in the second direction is larger than a dimension of the second mounting surface in the second direction, the first exposed surface has a first end and a second end separated from each other in the first direction, the second exposed surface has a third end and a fourth end separated from each other in the second direction, the first end and the third end are located inward from a periphery of the sealing resin as viewed in the third direction, and the fourth end overlaps the periphery of the sealing resin as viewed in the third direction.

2. The semiconductor device according to claim 1, wherein said fourth end is located closer to said second mounting surface than said third end and is in contact with said bottom surface.

3. The semiconductor device according to claim 2, wherein the dimension of said first exposed surface in said first direction is greater than the dimension of said second exposed surface in said second direction.

4. The semiconductor device according to claim 3, wherein, when viewed in the third direction, a first center line passing through the center of the second exposed surface in the first direction and extending in the second direction overlaps with the first exposed surface.

5. The semiconductor device according to claim 4, wherein said second end is located closer to said first mounting surface than said first end and is in contact with said bottom surface.

6. The semiconductor device according to claim 4, wherein the second end is located inward from a periphery of the sealing resin when viewed in the third direction.

7. The semiconductor device according to claim 3, wherein, when viewed in the third direction, a first center line passing through the center of the second exposed surface in the first direction and extending in the second direction is spaced apart from the first exposed surface.

8. The semiconductor device described in any one of claims 4 to 7, further comprising a third lead located adjacent to the third terminal in the first direction and extending in the second direction, the third terminal and the third lead each having a third mounting surface and a third exposed surface exposed from the bottom surface, the dimension of the third exposed surface in the second direction being larger than the dimension of the third mounting surface in the second direction, the third exposed surface having a fifth end and a sixth end separated from each other in the second direction, the fifth end being located inward from the periphery of the sealing resin as viewed in the third direction, and the sixth end overlapping the periphery of the sealing resin as viewed in the third direction.

9. The semiconductor device according to claim 8, wherein the sixth end is located closer to the third mounting surface than the fifth end and is in contact with the bottom surface.

10. The semiconductor device according to claim 9, wherein, when viewed in the third direction, the first center line overlaps the third exposed surface.

11. The semiconductor device according to claim 10, wherein the third end is located closer to the first exposed surface than the fifth end.

12. The semiconductor device described in claim 10, wherein, when viewed in the third direction, the distance between the intersection of the first center line and a second center line passing through the center of the first exposed surface in the second direction and extending in the first direction, and the center of the bottom surface, is shorter than the dimension of the first mounting surface in the first direction.

13. The semiconductor device according to claim 9, wherein, when viewed in the third direction, the first center line is spaced apart from the third exposed surface.

14. The semiconductor device described in claim 9, wherein the semiconductor element has a plurality of electrodes located on the sides facing the first terminal, the second terminal, the third terminal and the fourth terminal in the third direction, and any one of the plurality of electrodes is conductively connected to any one of the first terminal, the second terminal, the third terminal and the fourth terminal.

15. The semiconductor device according to claim 14, wherein any one of the plurality of electrodes is conductively connected to any one of the first lead, the second lead, and the third lead.

16. The semiconductor device according to claim 15, wherein the sealing resin has a first side surface facing one side of the first direction, and the first terminal and the first lead are exposed from the first side surface.

17. The semiconductor device according to claim 16, wherein the sealing resin has a second side surface facing one side of the second direction, and the second terminal and the second lead are exposed from the second side surface.

18. The semiconductor device according to claim 17, further comprising a plurality of dummy terminals arranged at four corners of the sealing resin when viewed in the third direction, each of the plurality of dummy terminals having a dummy exposed surface exposed from the bottom surface.

19. The semiconductor device described in claim 18, wherein the dimension in the first direction of the dummy exposed surface is larger than the dimension in the first direction of the second mounting surface, and the dimension in the second direction of the dummy exposed surface is larger than the dimension in the second direction of the first mounting surface.

Images