Circuit design support device, circuit design method, and program

Abstract

The present disclosure relates to a circuit design support device, a circuit design method, and a program that make it possible to identify a cell that carries out a power reduction measure. Provided is a circuit design support device comprising a processing unit that identifies, on the basis of data obtained from design data of a circuit, one or more cells that influence at least one of the number of output toggles of glitch-generating cells and the number of toggles and power consumption of the entire power reduction target circuit, and presents the identified cells according to the magnitude of the influence. The present disclosure can be applied to, for example, a circuit design support device that designs a logic circuit.

Description

Circuit design support device, circuit design method, and program

[0001] The present disclosure relates to a circuit design support device, a circuit design method, and a program, and more particularly to a circuit design support device, a circuit design method, and a program that are capable of identifying cells for which power reduction measures are to be implemented.

[0002] As a method for reducing power consumption of logic circuits by suppressing glitches in the logic circuit, for example, the methods disclosed in the following documents have been proposed. Patent Documents 1 and 2 propose a method of directly adding a glitch suppression cell to a glitch-generating cell. Non-Patent Document 1 proposes a method of adjusting the delay of other paths to the path with the slowest arrival delay by changing the gate size.

[0003] JP 2018-142235 A International Publication No. 2020 / 129119

[0004] M. Hashimoto, H. Onodera and K. Tamaru, “A practical gate resizing technique considering glitch reduction for low power design,” In Proc. of DAC, pp.446-451, 1999.

[0005] Methods such as changing the gate size of existing logic cells and adding glitch suppression cells, as mentioned above, are not effective enough in reducing power consumption, and a method for identifying cells for which power reduction measures should be implemented was needed.

[0006] The present disclosure has been made in light of such circumstances, and makes it possible to identify cells for which power reduction measures are to be implemented.

[0007] A circuit design support device according to one aspect of the present disclosure is a circuit design support device that includes a processing unit that identifies, based on data obtained from circuit design data, one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire circuit that is a target for power reduction, and presents the identified cells according to the magnitude of their influence.

[0008] A circuit design method according to one aspect of the present disclosure is a circuit design method in which a circuit design support device identifies, based on data obtained from circuit design data, one or more cells that affect the number of output toggles of a glitch-generating cell and at least one of the number of toggles and power consumption of the entire circuit that is a target for power reduction, and presents the identified cells according to the magnitude of their influence.

[0009] A program according to one aspect of the present disclosure causes a computer to function as a processing unit that, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire circuit targeted for power reduction, and presents the identified cells according to the magnitude of their influence.

[0010] In a circuit design support device, a circuit design method, and a program according to one aspect of the present disclosure, one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire circuit targeted for power reduction are identified based on data obtained from the design data of the circuit, and the identified cells are presented according to the magnitude of their influence.

[0011] The circuit design assistance device according to one aspect of the present disclosure may be an independent device or an internal block constituting a single device.

[0012] 1 is a block diagram showing an example of the configuration of an embodiment of a circuit design assistance device to which the present disclosure is applied. FIG. 2 is a flowchart explaining the flow of processing executed by a processor of the circuit design assistance device of FIG. 1. FIG. 3 is a diagram showing an example of calculation of a maximum arrival delay from a FF input pin. FIG. 4 is a diagram showing an example of calculation of a maximum arrival delay from a FF input pin. FIG. 5 is a diagram showing an example of calculation of a maximum arrival delay from a FF input pin. FIG. 6 is a diagram showing an example of calculation of a maximum arrival delay from a FF output pin. FIG. 7 is a diagram showing an example of identification of cell set A. FIG. 8 is a diagram showing an example of identification of cell set A. FIG. 9 is a diagram showing an example of a two-input NAND circuit. FIG. 10 is a diagram showing an example of replacement with a glitch suppression cell. FIG. 11 is a diagram showing an example of insertion of a glitch suppression buffer. FIG. 12 is a diagram showing an example of a case where both replacement with a glitch suppression cell and insertion of a glitch suppression buffer are performed. FIG. 13 is a diagram showing an example of re-encoding. FIG. 14 is a diagram showing an example of drawing a part of a search tree using encoding method 1. FIG. 15 is a flowchart showing an example of a processing flow when a greedy algorithm is used. FIG. 16 is a diagram showing examples of bound operations and branch operations in a branch and bound method. FIG. 17 is a flowchart showing an example of a processing flow when a genetic algorithm is used. FIG. 18 is a flowchart showing an example of a processing flow when a differential evolutionary algorithm is used.

[0013] <Device Configuration> Fig. 1 is a block diagram showing an example configuration of one embodiment of a circuit design assistance device to which the present disclosure is applied. In Fig. 1, the circuit design assistance device 10 is configured by a computer such as a PC (Personal Computer) that designs logic circuits. The circuit design assistance device 10 includes a processor 11, a memory 12, an auxiliary storage device 13, and an input / output interface 14.

[0014] The processor 11 is composed of processing devices (processing units) such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a GPU (Graphics Processing Unit), etc. The processor 11 performs arithmetic processing and controls other hardware. The memory 12 is composed of a volatile storage device such as a RAM (Random Access Memory).

[0015] The auxiliary storage device 13 is configured by a non-volatile storage device such as an HDD (Hard Disk Drive) or an SSD (Solid State Drive). The input / output interface 14 is configured by an interface circuit. To the input / output interface 14, for example, input devices such as a keyboard and a mouse, and output devices such as a display are connected.

[0016] The circuit design assistance device 10 has the hardware configuration described above. In the circuit design assistance device 10, the processor 11 executes a program recorded in the auxiliary storage device 13 to perform processing for assisting circuit design based on data obtained from circuit design data. As shown in FIG. 1 , the processor 11 functionally includes a cell set identification unit 21, a partial cell set identification unit 22, a global optimization unit 23, and a netlist modification unit 24. The operation of each unit of the processor 11 will be described with reference to the flowchart of FIG. 2 .

[0017] <Processing Flow> Figure 2 is a flowchart illustrating the flow of processing executed by the processor 11 of the circuit design assistance device 10 of Figure 1. However, the processing shown in Figure 2 is processing performed after a netlist is generated. For example, RTL (Register Transfer Level) design data is logically synthesized to generate a netlist. The netlist includes component information such as cells and their connection information, and placement and wiring are performed based on the netlist.

[0018] In step S11, the cell set identification unit 21 identifies a cell set A that has timing margins in the countermeasure target circuit. However, the processing of step S11 is not essential, and if the processing of step S11 is skipped and a cell set with timing margins is not identified, all cells are included in cell set A.

[0019] In step S12, the partial cell set identifying unit 22 identifies partial cell set B of cell set A that has a high influence based on the number of output toggles of the glitch-generating cell, the total number of toggles of the entire circuit, and the power consumption of the entire circuit.

[0020] In step S13, the global optimization unit 23 performs global optimization on the partial cell set B as the target of glitch prevention measures, according to each objective, such as reducing the number of output toggles when a glitch occurs, the total number of toggles in the entire circuit, and the power consumption of the entire circuit.

[0021] In step S14, the netlist modification unit 24 modifies the netlist in accordance with the results of the above-described processing. Here, the update may be reflected directly in a layout ECO (Engineering Change Order).

[0022] As described above, the circuit design assistance device 10 identifies cells within the logic cone leading to the glitch-causing cell that affect at least one of the number of output toggles of the glitch-causing cell, the number of toggles (total number of toggles) of the entire power reduction target circuit, and power consumption, and identifies a combination of measures (suppression operations) that will most effectively reduce the number of toggles or power consumption. Each step will be described in detail below.

[0023] <<First Embodiment>>

[0024] <Identifying a Set of Cells with Timing Margins> When identifying a set of cells A with timing margins (S11 in FIG. 2), the following method can be used, for example. That is, the setup timing margin for each cell is calculated by sequentially performing the following steps 1 to 3 for each group of combinational circuits that make up the circuit. Here, a graph is constructed for each combinational circuit, with vertices representing net delays added to the midpoints of each net, and calculations can be performed using the graph with delay weights added to the nodes.

[0025] (Step 1) First, perform a fan-in trace from the FF input pin to which the combinational circuit output is connected, and calculate the minimum setup delay margin for each net. Here, while performing the fan-in trace, calculate the maximum arrival delay to the FF input pin for each net. At this time, the maximum arrival delay is found by calculating the minimum value of "setup constraint - delay from FF input pin."

[0026] 3 to 6 show an example of calculating the minimum setup delay margin for each net by performing a fan-in trace from the FF input pin to which the combinational circuit output is connected. In Figures 3 to 6, alphabets are written at the vertices indicated by white circles, with capital letters representing cell delays and lowercase letters representing net delays. Note that capital letters are also referred to as cell vertices corresponding to cells, and lowercase letters are also referred to as net vertices corresponding to nets between cells. The numbers written at the vertices represent delay values, and the numbers written at the arrows between the vertices represent the maximum arrival delay (Setup) from the FF input pin.

[0027] For example, in Figure 3, cell vertex R and cell vertex Q are FF input pins, and Setup:5 is set for cell vertex R, and Setup:6 is set for cell vertex Q. If we look at the trace from cell vertex R to cell vertex A and from cell vertex Q to cell vertex A, the minimum value of "setup constraint - delay from FF input pin" is selected at cell vertex P, so 3(5) is selected out of 3(5) and 3(6), and at cell vertex A it becomes 5(5).

[0028] In Figure 4, when cell vertex O is an FF input pin and Setup:12 is set to cell vertex O, tracing is performed in the same way as in Figure 3 to find the maximum arrival delay from the FF input pin in each net, and the result is 5(5) at cell vertex A is updated to 13(12), and 9(12) at cell vertex B. In Figures 5 and 6, when cell vertices N and M are FF input pins and Setup:18 is set to cell vertex N and cell vertex M, tracing is performed in the same way as in Figure 3 to find the maximum arrival delay from the FF input pin in each net, and the result is 13(12) at cell vertex A and 9(12) at cell vertex B. Also, as shown in Figure 6, the result is 12(18) at cell vertex C.

[0029] (Step 2) Next, perform a fan-out trace from the FF output pin to which the combinational circuit input is connected, and calculate the maximum delay from the FF output pin in each net. Here, while performing a fan-out trace, calculate the maximum delay from the FF output pin in each net.

[0030] Figure 7 shows an example of calculating the maximum delay from the FF output pin for each net by fanout tracing from the FF output pin connected to the combinational circuit input. In Figure 7, as in Figure 3 and other figures, among the vertices indicated by white circles, the vertices marked with uppercase letters represent cell delays, and the vertices marked with lowercase letters represent net delays. The numbers written on the arrows between vertices are separated by commas (,). The former number represents the maximum delay from the FF output pin, and the latter number represents the maximum arrival delay (Setup) from the FF input pin, as in Figures 3 to 6. In Figure 7, the maximum delay from the FF output pin is added to the numbers written on the arrows between vertices shown in Figure 6 (maximum arrival delay from the FF input pin). Note that the FF output pins described above may also be considered module input pins.

[0031] (Step 3) Next, all cell vertices that satisfy the following (a) to (c) in all input and output nets to the vertices corresponding to the cells are defined as cell set A.

[0032] (a) Maximum delay from FF output pin + Maximum arrival delay to FF input pin < Setup constraint - α (b) Each net for which Maximum delay from FF output pin + Maximum arrival delay to FF input pin ≥ Setup constraint - α can be virtually cut, and all cell vertices whose inputs and outputs have not been cut can be collected to form cell set A. (c) Here, α represents the extra delay value added as a glitch prevention measure.

[0033] 8 and 9 show an example of identification of cell set A. In Fig. 8 and Fig. 9, as in Fig. 3 and the like, among the vertices shown by white circles, vertices with uppercase letters represent cell delays, and vertices with lowercase letters represent net delays. Also, as in Fig. 7, the comma-separated numbers written on the arrows between vertices represent the maximum delay from the FF output pin and the maximum arrival delay (Setup) from the FF input pin.

[0034] Figure 8 shows the case where each net is virtually disconnected, based on (b) above, such that the maximum delay from the FF output pin + the maximum arrival delay to the FF input pin ≥ setup constraint - α. However, for simplicity of explanation, α = 1. Also, in Figure 8, the strikethrough numbers among the comma-separated numbers indicate that each net has been virtually disconnected. For example, in Figure 8, the nets corresponding to net vertices a, b, g, h, i, n, o, q, s, and t are virtually disconnected.

[0035] In Figure 9, the nets that were virtually disconnected in Figure 8 are similarly shown with strikeout lines, and among the capital letter vertices, the vertices with patterns that have not been disconnected from all inputs and outputs are identified as cell set A. For example, in Figure 9, cell vertices B, C, E, F, G, I, and K are identified as cell set A. Therefore, in the examples shown in Figures 3 to 9, A = {B, C, E, F, G, I, K} can be identified as cell set A with timing slack.

[0036] <Identifying a Subset of Cells with High Influence> When identifying a subset of cells A with a high influence on the number of toggles and power consumption (S12 in FIG. 2), the following method can be used, for example: That is, the average causal effect of the cells of cell set A is calculated according to each of the following objectives (d) to (g), and the average causal effect for each objective is sorted in descending order, and the top p% of cells are selected to identify cell set B.

[0037] (d) Number of output toggles of the glitch-generating cell (e) Total number of toggles in the entire circuit (f) Power consumption in the entire circuit (g) Here, the number of toggles (number of toggles) can be obtained by circuit netlist simulation using the input pattern, and power consumption can also be calculated using the simulation results.

[0038] Each cell c i The average causal effect for ∈ A is c iIt is defined as the following formulas (1) to (7) using the average number of toggles and average power consumption values ​​that depend on the input pattern to the target circuit when the output of is fixed to 0 or 1. However, it is also possible to select and use a combination of formulas (5), (6), and (7) or a combination of formulas (5'), (6'), and (7').

[0039]

[0040]

[0041]

[0042]

[0043] Equation (1) is the target glitch generating cell g included in the circuit C for the input pattern x. j Formula (2) is a function that returns the average total number of toggles of the countermeasure target circuit C for the input pattern x. Formula (3) is a function that returns the average power consumption of the countermeasure target circuit C for the input pattern x. Formula (4) is a function that returns the average power consumption of the cell c included in the circuit C. i represents fixing the output of to the Boolean value b.

[0044] Equation (5) is the cell c i ∈ A, the target glitch occurrence cell g j represents the average causal effect of c on the number of output toggles. i ∈ A is the glitch-generating cell g j Equation (6) is limited to cells whose output reaches cell c i ∈ A on the total number of toggles in the entire circuit. i represents the average causal effect of ∈ A on the power consumption of the entire circuit.

[0045] To eliminate input pattern dependency on the target circuit, multiple input patterns may be prepared and the average causal effect calculated for each input pattern may be calculated. For example, for N input patterns {x1, ... , x N} and cell c i For ∈ A, the following equations (8) can be defined respectively.

[0046]

[0047] As described above, the circuit design assistance device 10 is characterized by calculating the average causal effect to identify a cell set that affects at least one of the number of output toggles of a glitch-causing cell and the number of toggles and power consumption of the entire power reduction target circuit. The circuit design assistance device 10 may also identify a cell set with timing slack in the countermeasure target circuit, and then identify a cell set with a high influence from among the cell sets.

[0048] <<Second Embodiment>>

[0049] <Global Optimization According to Objective> When performing global optimization according to each objective (S13 in FIG. 2) with subset cell B as the target of glitch suppression measures, the following method can be used, for example.

[0050] Operations on each cell of cell set B include, for example, glitch suppression operations on the cell and selection of drivability. The glitch suppression operations on the cell can be performed by replacing the cell with a glitch suppression cell, inserting a glitch suppression buffer, or both replacing the cell with a glitch suppression cell and inserting a glitch suppression buffer. Note that the operations on each cell are not limited to these. The drivability can be selected from a finite number of possible drivability options.

[0051] The problem is reduced to finding a combination of a subset and an operation on each cell that minimizes the objective function when possible operations are performed on each cell of possible subsets of cell set B. The objective function can be any of the following equations (9):

[0052]

[0053] In equation (9), circuit C represents a circuit resulting from applying a glitch suppression operation to a subset of cell set B.

[0054] Furthermore, if the implementation of glitch suppression measures results in a timing violation or a value greater than the original value of the optimization target, it is clearly not a solution and must be eliminated. The optimization targets here include the number of output toggles of the glitch-causing cell, the total number of toggles in the entire circuit, and the power consumption of the entire circuit.

[0055] <Encoding Cell Set B into a Vector and Search Tree> From the above, the optimization problem is discrete optimization (discrete-valued optimization). In this disclosure, we describe examples of reduction methods for greedy algorithms, branch-and-bound algorithms, and genetic algorithms, which are suitable for exhaustive search and discrete optimization, and particle swarm optimization (PSO) and differential evolutionary algorithms, which are suitable for continuous optimization (continuous-valued optimization). However, because genetic algorithms involve local optimization, they can also be interpreted as evolutionary algorithms. Note that this does not exclude other reduction methods for these algorithms, or reduction to other methods such as simulated annealing algorithms and artificial bee colony algorithms.

[0056] Examples of operations on each cell of cell set B are shown in Figures 10 to 13. Here, as shown in Figure 10, an example of an operation on cell 51, which is a two-input NAND. Figure 11 shows an example of replacement with a glitch suppression cell. In Figure 11, cell 51 is replaced with glitch suppression cell 52, which is a two-input NAND.

[0057] Fig. 12 is a diagram showing an example of inserting a glitch suppression buffer. In Fig. 12, a glitch suppression buffer 53 is inserted into a two-input NAND cell 51. Fig. 13 is a diagram showing an example in which both replacement with a glitch suppression cell and insertion of a glitch suppression buffer are taken into consideration. In Fig. 13, cell 51 is replaced with a two-input NAND glitch suppression cell 52, and a glitch suppression buffer 53 is inserted into glitch suppression cell 52.

[0058] As described above, glitch suppression operations for cells can be performed by replacing them with glitch suppression cells, by inserting glitch suppression buffers, or by both. However, the operations shown in Figures 11 to 13 are merely examples, and other glitch suppression operations may generally be added.

[0059] Although the drivability is selected from a finite number of possible drivability options, for the sake of simplicity, it is assumed that when both options are used, only the glitch suppression buffer drivability is selected. However, this constraint is not essential and can be eliminated.

[0060] <Encoding Method 1> The following method is used as encoding method 1 to a vector of cell set B. That is, from the definition of the operation on each cell of cell set B, each cell c i Define the encoding for ∈ B. Here, 0 to 3 are assigned as the glitch suppression operation numbers. 0 indicates no operation, 1 indicates replacement with a glitch suppression cell, 2 indicates insertion of a glitch suppression buffer, and 3 indicates both. Also, assign values ​​defined in the cell library as drivability numbers. Here, for the sake of simplicity, the drivability numbers are set to 1, 2, 3, and 4. This allows each cell c i ∈ B can be expressed by concatenating the glitch suppression operation number and the drivability number.

[0061] The vector encoding of cell set B is the encoded cell c i ∈ B can be expressed in descending order of average causal effect. For example, the initial states (01, 02, 01, ..., 03) of the vector representation of cell set B can be arranged. Here, drivability indicates the value of each cell.

[0062] <Encoding Method 2> The following method is used as encoding method 2 for the vector of cell set B. That is, using encoding method 1, the power values ​​for all combinations of operations for each cell type are calculated, and the average value for all cell types is calculated. The average values ​​of the calculated results are then sorted in ascending order, and this order, starting from 0, is re-encoded as discrete values. Figure 14 is a diagram showing an example of re-encoding. In Figure 14, after re-encoding, numbers 0 to 15 are assigned to 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33, 04, 14, 24, and 34.

[0063] When a vector representing a glitch suppression operation for cell set B and a circuit obtained by modifying circuit C with this vector are defined as shown in the following equation 7, the objective function is expressed by the following equation (10).

[0064]

[0065] <Definition of Symbols> In the following description, the initial value of the glitch suppression operation, the drivability at the initial value, the substitution of the glitch suppression operation, etc. will be represented by the symbols shown in the following equation 8.

[0066]

[0067] <1. Discrete Optimization Exhaustive Search> An example of exhaustive search as discrete optimization is as follows. That is, a search tree is constructed using method 1 for encoding cell set B into vectors. FIG. 15 is a diagram showing an example of a portion of a search tree drawn using method 1 for encoding cell set B into vectors. In FIG. 15, the number of elements in set B is three, and the initial vector is (01, 02, 01). In expanding the search tree, nodes that overlap with nodes that have already been generated are not generated. In global optimization, the objective function is calculated for vectors that appear in all nodes of the search tree and do not cause timing violations, and the optimal solution is obtained by finding the vector that gives the minimum value.

[0068] <2. Discrete Optimization Greedy Method> An example of reducing to the greedy method for discrete optimization is as follows. That is, encoding method 1 is adopted, and as an example of a greedy method algorithm, a glitch suppression operation that minimizes the objective function for each cell within a range in which drivability is equal to or less than the original value is performed on each cell, starting with the cell with the highest average causal effect, and the glitch suppression operation that minimizes the objective function is returned. The processing flow when this greedy method algorithm is used can be represented, for example, as shown in the flowchart of FIG. 16.

[0069] <3. Discrete Optimization Branch and Bound Method> An example of discrete optimization reduced to a branch and bound method is as follows: That is, encoding method 1 is adopted, and search, bound operation, and branch operation are performed as an example of a branch and bound method.

[0070] First, in the search, if cell set B belonging to the target circuit does not contain any cells that have not yet undergone the suppression operation, the process ends. On the other hand, if there are any cells that have not yet undergone the suppression operation, the following is performed until there are no more cells that have not yet undergone the suppression operation in cell set B belonging to the target circuit. In other words, one cell that has not yet undergone the suppression operation is selected, and the glitch suppression operation that minimizes the objective function among the applicable glitch suppression operations is performed, and a circuit after the suppression operation is constructed. Then, if the circuit satisfies the timing constraints, the resulting circuit is stored. Here, updated glitch suppression operation vector information is added to each resulting circuit.

[0071] Next, in the limiting operation, the circuit that gives the minimum value of the objective function and the glitch suppression operation vector are found from the obtained result circuit. If the minimum value of the objective function is not improved, the result circuit is discarded and the above search is recursively called. In the branching operation, half of the result circuit group is stored in order from the smallest objective function value. Then, each circuit belonging to the half-stored result circuit group is treated as the target circuit and the above search is recursively called.

[0072] 17 is a diagram showing examples of bounding and branching operations in the branch and bound method. In FIG. 17, result circuits are represented by black circles, and the result circuits within the dashed line P1 are discarded in the bounding operation because they were unable to update the minimum value of the objective function. The result circuits within the dashed line P2 are retained in the branching operation, starting with the smallest one, because they have updated the minimum value of the objective function.

[0073] <4. Discrete Optimization Genetic Algorithm> An example of discrete optimization reduced to a genetic algorithm is as follows. That is, encoding method 1 is adopted, and the elements of the glitch suppression operation vector are expressed as a concatenation of k||d-1 (0 ≦ k ≦ 3, 0 ≦ d-1 ≦ 3), and a vector in which k and d are each expressed in binary is used. Here, as an example of a genetic algorithm, a simple example using the roulette wheel method, one-point crossover, and mutation by bit inversion is shown. Furthermore, as shown in the flowchart in Figure 18, the following steps are performed in order: generation of gene sequence, evaluation of fitness, roulette wheel method (determination of the number of individuals for the next generation), crossover and mutation, generation change, and convergence determination.

[0074] First, in the generation of the gene sequence (S31), the initial value of the glitch suppression operation is set only once at the beginning as shown in the following equation (11), and the relationship in the following equation (12) is obtained.

[0075]

[0076] In addition, 2p (0≦p≦|N / 2|) glitch suppression operation vectors, which are made up of random values ​​within the range of values ​​that the glitch suppression operation can take and have no timing violation, are generated and added.

[0077] Next, in the evaluation of the degree of suitability (S32), a power evaluation is performed by performing an actual load simulation using an input pattern with the glitch transmittance at each cell set to 0% for the initial circuit before the glitch suppression operation is applied. By performing this evaluation, the average total number of toggles, average power consumption, and average number of toggles at a specific logic cell output that should be achieved by optimization are determined according to the optimization objective. The values ​​determined according to the objective are designated as ω minWhen multiple input patterns are used, the average value of the values ​​obtained according to the purpose is set as ω min Let's say.

[0078] The value of the objective function in the glitch suppression operation vector, which is the gene arrangement, is ω min The closer the fit is to the gene sequence, the higher the fit is. For each gene sequence, the following formula (13) is calculated, and the maximum value is found only once at the beginning. max The following formula (14) is calculated as the fitness of each gene sequence. The sum of these is then calculated as the total fitness. Furthermore, the minimum value of the following formula (15) is calculated to obtain f min If it is less than f min The glitch suppression operation vector that gives this is the glitch suppression operation that gives the minimum objective function.

[0079]

[0080] Next, the number of individuals for the next generation is determined by the roulette wheel method (S33). Here, individuals are selected at a rate proportional to the evaluated fitness, and each glitch suppression operation vector is generated in numbers corresponding to this rate.

[0081] Next, in crossover and mutation (S34), element number i is randomly selected for the glitch suppression operation vectors with the first and second evaluated fitnesses, and equations (17) and (18) below are generated from equation (16) below, thereby generating the next two new glitch suppression operation vectors. That is, the i-th element of the first glitch suppression operation vector is replaced with equation (17). Also, the i-th element of the second glitch suppression operation vector is replaced with equation (18). Here, it is confirmed whether the timing constraint is satisfied, and if not, the element number i is updated and crossover is repeated until the timing constraint is satisfied.

[0082]

[0083] For the glitch suppression operation vector with the third highest evaluated fitness, element number j is randomly selected, and one bit in the four-bit string of the following equation (19) is randomly selected and inverted. Here, it is confirmed whether the timing constraint is satisfied, and if not, element number j is updated and the mutation is repeated until the timing constraint is satisfied.

[0084]

[0085] For the glitch suppression operation vectors with the first and second fitness levels, an element number m different from the i used in the above crossover is randomly obtained, and a locally optimal glitch suppression operation vector is obtained using the following equation (20) and generated as a mutation with multiple bits inverted.

[0086]

[0087] At this point, the algorithm checks whether the timing constraint is satisfied. If not, it discards the mutation to element number m and returns it to its original state until the timing constraint is satisfied. Then, it updates the value of element number m and repeats the mutation. This operation can be considered a bit-flip operation, and is therefore a mutation. However, because it yields locally optimal solution candidates, this operation can also be interpreted as an evolutionary algorithm as a whole. Furthermore, in the definitions of (a) food source initialization, (b) gathering bee phase, (c) following bee phase, (d) scouting bee phase, (e) termination condition, and (f) discretionary food source output of the artificial bee colony algorithm, it is possible to define an artificial bee colony algorithm by using the same termination condition as the genetic algorithm in (e), and by using or modifying the local search operation in (b) and (d) in (d).

[0088] Next, in the generation change (S35), 2p-5 vectors are randomly selected from the set of glitch suppression operation vectors generated in step S33, and five newly generated glitch suppression operation vectors are added to them in step S34 to eliminate duplication. Then, the vector values ​​are no longer updated and converge to a certain vector value (S36: Yes), or steps S31 to S35 are repeated for, for example, 10 5 After repeating this process, f mimRepeat this process until no improvement is made twice in a row. mim The glitch suppression operation that minimizes the objective function is returned (S37), and the series of processes ends.

[0089] 5. Discrete Optimization PSO Using Continuous Optimization An example of discrete optimization using continuous optimization reduced to particle swarm optimization (PSO) is as follows: That is, by adopting encoding method 2, the algorithm given by the following formulas (21) to (26) is executed according to the following settings.

[0090]

[0091]

[0092] In the formulas (21) to (26), n=1, . . . , N, and p=1, .

[0093] Here, in addition to the initial value of the glitch suppression operation, P-1 glitch operations consisting of random values ​​within the range of possible values ​​are generated. For each of these P initial values, the process is repeated until the minimum value of the objective function is no longer improved twice in a row. The index variable k represents the number of iterations of the process. The following equation (27) is returned as the solution. For example, it is assumed that the relationships in the following equations (28) and (29) are satisfied. In equation (28), R(a, b) is a function that returns a uniform random value included in the constant-specified interval [a, b].

[0094]

[0095] Here, in the following equation (30), the value of each element of the glitch suppression operation is rounded down to an integer value, and if it is less than 0, it is replaced with 0.

[0096]

[0097] 6. Discrete Optimization Using Continuous Optimization Differential Evolution Algorithm An example of discrete optimization using continuous optimization resulting in a differential evolution algorithm is shown below. That is, encoding method 2 is adopted, but here, for example, a simple example using DE / rand / 1 / bin is shown as an example of a differential evolution algorithm. Also, as shown in the flowchart in Figure 19, the following steps are performed in order: generation of an initial point group, generation of variant points using differences, crossover operation, evaluation, update of glitch suppression operation, update of tentative optimal candidate for glitch suppression operation, and convergence determination.

[0098] First, in generating the initial point group (S51), in addition to the following equation (31) which represents the initial value of the glitch suppression operation, p-1 (p = 1, ..., P) equations (32) below which represent glitch suppression operations consisting of random values ​​within the range of possible values ​​are generated.

[0099]

[0100] Here, it is assumed that the relationship expressed in the following equation (33) holds, and that the relationship expressed in the following equation (34) holds.

[0101]

[0102] Here, in the following equation (35), the value of each element of the glitch suppression operation is rounded down to an integer value, and if it is less than 0, it is replaced with 0.

[0103]

[0104] For example, the initial value may be the value expressed by the following equation (36), and the value may be updated using the following equations (37) and (38).

[0105]

[0106]

[0107] In the formulas (37) and (38), R(a, b) is a function that returns a uniform random value included in the constant-specified interval [a, b].

[0108] Next, in generating a variant point by difference (S52), three different glitch suppression operations other than the p-th glitch suppression operation are randomly selected and expressed by the following equation (39), and using these, a variant point of the p-th glitch suppression operation is generated by the following equation (40). This is repeated for p = 1, ... , P.

[0109]

[0110]

[0111] Next, in the crossover operation (S53), a test point is generated by crossover operation between the glitch suppression operation defined by the following equations (41) and (42) and the variant point.

[0112]

[0113]

[0114] Next, in evaluation (S54), the following equation (43) is calculated, which is the objective function for the p-th glitch suppression operation and test point: This calculation is repeated for p = 1, . . . , P.

[0115]

[0116] Next, in updating the glitch suppression operation (S55), the p-th glitch suppression operation is updated by the following equation (44): This update is repeated for p = 1, . . . , P.

[0117]

[0118] Next, in updating the provisional optimum candidate for the glitch suppression operation (S56), the following equation (45) is obtained.

[0119]

[0120] Furthermore, when the relationship of the following equation (46) is satisfied, the relationships of the following equations (47) and (48) are also established, where k=k+1 in equations (46) to (48).

[0121]

[0122] Then, steps S52 to S56 are repeated for, for example, 10 seconds to see if the value of the objective function converges to a constant value that is the smallest among the values ​​found so far (S57: Yes). 5 After repeating this process, f mim Repeat this process until no improvement is made twice in a row. mim The glitch suppression operation that minimizes the objective function is returned (S58), and the series of processes ends.

[0123] As described above, the circuit design assistance device 10 identifies a cell set that affects the number of output toggles of a glitch-causing cell and at least one of the number of toggles and power consumption of the entire power reduction target circuit by calculating the average causal effect, and performs global optimization to reduce the number of output toggles of a glitch-causing cell and at least one of the number of toggles and power consumption of the entire power reduction target circuit, targeting the identified cell set as the target for glitch prevention measures.

[0124] <<Third Embodiment>>

[0125] Here, as a modified example, an improvement in the efficiency of the calculation of the objective function and the average causal effect will be described. Calculation of the average causal effect requires calculation of the total number of toggles and power consumption of the entire target circuit when the output of each cell in the target cell set B is set to 0 and when it is set to 1, respectively, resulting in a large number of calculations. Furthermore, calculation of the objective function is also performed each time a glitch suppression operation is performed on a sub-cell set of the cell set B using the optimization algorithm, resulting in a large number of calculations. In particular, if the target circuit is all digital circuits on a chip, the calculation costs of the objective function and the average causal effect will be extremely large.

[0126] <1. Improving computational efficiency using belief propagation analysis> Input pattern {x1, ..., x N}, a real load simulation is performed on the target netlist circuit, and power analysis is performed to obtain the average total number of toggles in the entire circuit, the average power consumption, and the average number of toggles at a specific cell output.In addition, the average toggle rate and average glitch rate at the input ports of the target circuit and the output pins of flip-flops (FFs) contained in the target circuit can be obtained according to the input pattern.

[0127] When calculating the objective function or average causal effect, the purpose is to confirm their magnitude relationship, and it is not necessary to obtain accurate values. Therefore, by setting the average toggle rate and average glitch rate at the input ports of the target circuit according to the input pattern and the output pins of the flip-flops (FFs) contained in the target circuit and performing a power analysis based on probability propagation analysis, it is possible to obtain the average toggle rate and average glitch rate for the entire circuit, the average power consumption, and the average toggle rate and average glitch rate at the output of a specific cell faster than with actual load simulation.

[0128] Furthermore, by using the sum of the average toggle rate and average glitch rate for the entire circuit instead of the average total number of toggles for the entire circuit, and by using the sum of the average toggle rate and average glitch rate for a specific cell output instead of the average number of toggles for a specific cell output, the efficiency of the objective function and the calculation of the average causal effect can be improved.

[0129] <2. Improving calculation efficiency by limiting the cells targeted for glitch suppression> Narrowing down the target cell set B by cell type reduces the number of elements in the set, thereby reducing the number of calculations for the average causal effect. Reducing the targets for glitch suppression operations in optimization reduces the solution space and the number of calculations for the objective function. Narrowing down the cell type can be done using methods such as targeting only inverters, or targeting only (one or more) logic cells with a high usage rate among the logic cells in the target circuit.

[0130] <<Fourth Embodiment>>

[0131] Here, as an application example, we will explain the definition of an objective function that takes into account both power consumption and the number of toggles, the calculation of the average causal effect, and its use in optimization. In the above explanation, the following formula (10) was used as the objective function, but optimization targeting both average power consumption and the average total number of toggles was not supported.

[0132]

[0133] In equation (10), the glitch suppression operations are expressed in descending order of average causal effect from the left end, as in the average causal effects shown in equations (5) to (8) above.

[0134] Therefore, by introducing a parameter β∈(0, 1), it becomes possible to calculate the objective function and average causal effect taking into account any two combinations. The following formula (49) shows an example of the configuration of the average causal effect. Also, the following formula (50) shows an example of the configuration of the objective function.

[0135]

[0136]

[0137] Here, when the number of output toggles of a glitch-causing cell is included in the calculation formula, the average total number of toggles, the sum of the average toggle rate and the average glitch rate, the average power consumption, and the combinational logic circuit leading to the glitch-causing cell are calculated as the target circuit. Furthermore, when constructing the formula for the objective function or average causal effect using β, the input patterns are limited to those that are the same.

[0138] <<Fifth Embodiment>>

[0139] Here, as an application example, application to an output cell that requires glitch removal will be described. Examples of circuit structures that require glitch removal include the following four logic cells.

[0140] First, there are logic cells that drive the asynchronous input reset pins or asynchronous input set pins of flip-flops (FFs) or latches. This is because glitches that do not meet the recovery or removal times defined for the clock edge can cause malfunctions. Second, there are logic cells that output enable signals that drive the enable signal input pins of clock gating cells. This is because glitches that do not meet the setup or hold times defined for the enable signal input pins of clock gating cells can cause the flip-flops that are clocked by the gated clock output by the clock gating cells to malfunction or enter a metastable state.

[0141] Third, there are logic cells in which signals from two or more flip-flops with different gated clocks generated from the same source clock are joined together. This is because, if this logic cell is on a multi-cycle path, a flip-flop at a later stage in the multi-cycle path may fetch the output glitch of this logic cell as a normal signal even though the required number of cycles has not elapsed. Fourth, there are logic cells in which signals from two or more flip-flops with different clocks generated from the same source clock are joined together. This is because, if this logic cell is on a multi-cycle path, a flip-flop at a later stage in the multi-cycle path may fetch the output glitch of this logic cell as a normal signal even though the required number of cycles has not elapsed.

[0142] If these logic cells are glitch-generating cells, there is a possibility that the output glitch of the logic cells can be reduced to a range where malfunction can be suppressed by calculating the average causal effect for the glitch-generating cells and performing optimization using the objective function. The average causal effect and the objective function can be any combination of the following formulas (51) to (54).

[0143]

[0144] As described above, the circuit design assistance device 10 can suppress the number of output toggles of a cell that outputs a glitch input for a circuit structure that is characterized by causing a circuit malfunction in response to a glitch input, and can also reduce the number of toggles of the entire logic cone leading to that cell. Thus, it is possible to suppress or mitigate circuit malfunctions caused by glitches.

[0145] <<Sixth Embodiment>>

[0146] Here, as an application example, we will explain how to identify the RTL code modifications required to reduce power consumption. By calculating the average causal effect for a module targeted for power reduction, it becomes possible to identify the cell sets that affect power consumption in order of the degree of impact. For example, by using the function provided by a logic synthesis tool to display the correspondence between the input RTL description and the synthesized netlist, or by using an equivalence verification method to identify the correspondence between the netlist and the RTL description, it becomes possible to identify which parts of the RTL description should be prioritized for power reduction and reducing the number of toggles in the netlist.

[0147] <<Summary>>

[0148] As described above, the present disclosure can identify one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire power reduction target circuit based on data obtained from circuit design data, and present the identified cells according to the magnitude of their influence. More specifically, the identified cells can be listed (e.g., displayed on a display) in order of the magnitude of their influence. This allows the identification of cells for which power reduction measures should be implemented. For example, the priority of which cells in a circuit module with high power consumption should be targeted for power reduction measures can be obtained. Therefore, for example, by using a function provided by a logic synthesis tool that displays the correspondence between the input RTL description and the synthesized netlist, or by using an equivalence verification method to identify the correspondence between the netlist and the RTL description, it is possible to present to the designer which parts of the RTL description should be prioritized as targets for countermeasures.

[0149] Furthermore, the present disclosure can identify a set of cells that affect the number of output toggles of a glitch-causing cell and at least one of the number of toggles and power consumption of the entire power reduction target circuit by calculating the average causal effect, and perform global optimization by targeting the identified set of cells with glitch suppression measures to reduce the number of output toggles of the glitch-causing cell and at least one of the number of toggles and power consumption of the entire power reduction target circuit. That is, the present disclosure does not target only the glitch-causing cell as the direct target of glitch suppression measures, but identifies one or more cells within a logic cone leading to the glitch-causing cell that affect the number of output toggles of the glitch-causing cell, and targets the one or more cells with glitch suppression measures (glitch suppression operations) to identify a combination of suppression operations that most effectively reduces the number of output toggles of the glitch-causing cell. Here, the operations include replacing the glitch-causing cell with a glitch suppression cell, inserting a glitch suppression buffer, and modifying drivability. Furthermore, in the present disclosure, one or more cells that affect the number of toggles or power consumption in the entire circuit targeted for power reduction are identified, and a combination of measures that most effectively reduces the number of toggles or power consumption is identified.

[0150] Furthermore, in the present disclosure, instead of checking for timing violations each time an individual glitch countermeasure is implemented, a set of cells with timing margins can be identified in advance, and from among the set of cells, a set of cells that meets at least one of the following three properties can be identified and a countermeasure implemented: First, the glitch has a strong impact on the increase or decrease in the number of output toggles of the glitch-causing cell; second, the glitch has a strong impact on the increase or decrease in the total number of toggles in the entire circuit; and third, the glitch has a strong impact on the increase or decrease in power consumption in the entire circuit. While measures to reduce power consumption in cells can be taken, such as replacing them with glitch-suppression cells or inserting buffers, these can increase delays and potentially cause timing violations. In the present disclosure, by identifying a set of cells with timing margins in advance, this type of timing violation can be prevented in advance.

[0151] Furthermore, the present disclosure can derive (automatically derive) a combination of glitch suppression operations for a specified cell set that is highly effective in reducing the number of output toggles of glitch-causing cells or the number of toggles or power consumption of the entire power reduction target circuit without causing timing violations within an optimization framework. In other words, it becomes possible to automatically reduce the number of output toggles of glitch-causing cells for a candidate cell set, or the number of toggles or power consumption of the entire power reduction target circuit, without causing timing violations.

[0152] As described above, the present disclosure is characterized in that, first, a cell set with timing margin may be first identified within a countermeasure target circuit, second, a cell set that affects the number of output toggles of a glitch-causing cell, the number of toggles of the entire circuit, and the power consumption of the entire circuit is identified, and third, rather than taking countermeasures directly to the glitch-causing cell or the cells before and after it, global optimization is performed on the identified cell set to reduce the number of output toggles of the glitch-causing cell, the total number of toggles of the entire circuit, and the power consumption of the entire circuit. However, in global optimization, analysis is performed at static timing as the optimization is performed, and an optimal solution without timing violations is searched for, so identifying a cell set with timing margin is not essential.

[0153] The present disclosure, by having such features, can achieve the following effects, for example. That is, it is possible to identify logic cells that have a causal effect on the average total number of toggles, average toggle rate, average glitch rate, and average power consumption of a power reduction target circuit. In particular, it is possible to identify them in a format that includes an order of magnitude of the causal effect. Therefore, it is possible to identify modules in the target circuit that include logic cells with a high power reduction effect and to support prioritizing countermeasures.

[0154] It also makes it possible to identify logic cells that have a causal effect on the average total number of toggles, average toggle rate, and average glitch rate of a specific logic cell. In particular, it is possible to identify them in a format that includes the order of magnitude of the causal effect. Therefore, it is possible to identify logic cells that are highly effective in reducing the number of toggles of the gated clock signal, and it is possible to identify the logic blocks or modules that contain those logic cells and to support prioritizing countermeasures.

[0155] In addition, by replacing logic cells in a circuit targeted for power reduction with glitch suppression cells, by adding glitch suppression buffers, or by automatically changing drivability, it is possible to reduce the average total number of toggles, the average toggle rate, the average glitch rate, and the average power consumption of the circuit targeted for power reduction.By replacing logic cells in a combinational logic circuit leading to a specific logic cell with glitch suppression cells, by adding glitch suppression buffers, or by automatically changing drivability, it is possible to reduce the average total number of toggles, the average toggle rate, the average glitch rate, and the average power consumption of the combinational logic circuit leading to a specific logic cell.

[0156] Furthermore, by replacing logic cells in combinational logic circuits leading to a specific logic cell with glitch suppression cells, adding glitch suppression buffers, and automatically changing drivability, it is possible to reduce the average total number of toggles, average toggle rate, and average glitch rate at the output of a specific logic cell.It is also possible to identify areas to modify the RTL code to reduce power consumption.

[0157] As mentioned above, various power reduction techniques for logic circuits that suppress glitches within the logic circuit have been proposed, including techniques for adjusting the path delay of other paths to match the path with the slowest arrival delay by changing gate sizes and techniques for directly adding glitch suppression cells to glitch-causing cells. In particular, the aforementioned Patent Document 1 proposes a technique for reducing glitches by identifying cells with input delay differences greater than or equal to a certain level as glitch-causing cells, adding glitch removal cells to the glitch-causing cells when the glitch width is less than or equal to a certain level, adjusting the input path delay of the glitch-causing cell when the glitch width is greater than or equal to the certain level, and returning to the state when the glitch width is less than or equal to the certain level. Patent Document 1 also proposes a technique for inserting glitch removal cells before and after the glitch-causing cell to prevent power increase or timing violations as a result of glitch reduction measures.

[0158] These power reduction methods, such as changing the gate size of existing logic cells or adding glitch suppression cells, do not address the following five problems, and therefore do not necessarily achieve power reduction. Even if power reduction is possible, the reduction effect that could be achieved is not achieved.

[0159] The first problem is that there can be multiple glitch-generating cells in a circuit. The second problem is that the number of output toggles of a glitch-generating cell, the number of toggles and power consumption of the entire circuit, and the degree of reduction in these factors can vary depending on which cells are addressed and in what order. The third problem is that it is not easy to identify which cells affect the number of toggles and power consumption of the entire circuit. The fourth problem is that it is not easy to identify which cells affect the number of output toggles of a glitch-generating cell. The fifth problem is that even if the cells to be addressed are identified, as with the second problem, the reduction in the number of toggles and power consumption of the logic cone to a specific cell and the entire circuit can vary depending on which cells are addressed and in what order.

[0160] This disclosure proposes the methods described in the above-described embodiments as solutions to these problems. Specifically, as described above, the present disclosure proposes a method (first method) for identifying cell sets that affect the number of output toggles of glitch-causing cells, the total number of toggles of the entire circuit, and the power consumption of the entire circuit by calculating the average causal effect, and a global optimization method (second method) for reducing the number of output toggles of glitch-causing cells, the total number of toggles of the entire circuit, and the power consumption of the entire circuit, targeting the identified cell sets. Note that, prior to the identification using the first method, a method (third method) for first identifying cell sets with timing slack in the target circuit may be used.

[0161] In particular, the first method enables identifying cell sets that affect power consumption within a module with high power consumption in order of their impact, i.e., their average causal effect. Therefore, for example, by using a logic synthesis tool's function for displaying the correspondence between the input RTL description and the synthesized netlist, or by using an equivalence verification method to identify the correspondence between the netlist and the RTL description, it becomes possible to identify which RTL code should be prioritized for reducing power consumption and the number of netlist toggles. Furthermore, the second method enables reducing the number of output toggles of cells that output glitch inputs in circuit structures that are prone to causing circuit malfunctions when a glitch input is applied, thereby simultaneously reducing the number of toggles in the entire logic cone leading to the cell. In other words, it is possible to prevent or mitigate glitch-induced circuit malfunctions.

[0162] In this disclosure, data obtained from design data of a circuit (target circuit) includes data (netlist) obtained by logical synthesis of the design data of the circuit, data obtained after placement and wiring, etc. The netlist includes component information such as cells and their connection information, and by performing placement and wiring based on the netlist, the cells included in the netlist and their connection information are assigned to transistors, nets (wiring), etc. within the integrated circuit.

[0163] The above-described series of processes can be executed by software or hardware. When the series of processes are executed by software, a program constituting the software is installed in the computer of each device. The program executed by the computer can be provided by being recorded on a removable recording medium such as a package medium. Alternatively, the program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital broadcasting.

[0164] In a computer, a program can be installed in an auxiliary storage device via an input / output interface by inserting a removable recording medium into a drive. Alternatively, the program can be received by a communication device via a wired or wireless transmission medium and installed in the storage device. Alternatively, the program can be pre-installed in the auxiliary storage device.

[0165] In the present disclosure, the processing performed by a computer according to a program does not necessarily have to be performed chronologically in the order described (e.g., the order described as a flowchart). That is, the processing performed by a computer according to a program also includes processing executed in parallel or individually (e.g., parallel processing or object-based processing). Furthermore, the program may be processed by a single computer (processor), or may be distributed among multiple computers (processors). Furthermore, the program may be transferred to and executed on a remote computer. For example, the present disclosure can take the form of cloud computing, in which multiple devices share and jointly process a single function via a network.

[0166] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0167] The present disclosure can also be configured as follows.

[0168] (1) A circuit design support device comprising: a processing unit that, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch-causing cell and the number of toggles and power consumption in an entire power reduction target circuit, and presents the identified cells according to the magnitude of their influence. (2) The circuit design support device described in (1), wherein the processing unit identifies a first set of cells that affect at least one of the number of output toggles of a glitch-causing cell and the number of toggles and power consumption in an entire power reduction target circuit by calculating an average causal effect, and performs global optimization to reduce at least one of the number of output toggles of a glitch-causing cell and the number of toggles and power consumption in the entire power reduction target circuit, with the identified first set of cells as a target of glitch prevention measures. (3) The circuit design support device described in (2), wherein the processing unit identifies a second set of cells in the target circuit that is a set of cells with timing margins, and identifies the first set of cells from the identified second set of cells. (4) The circuit design support device according to (2) or (3), wherein the processing unit derives, within an optimization framework, a combination of glitch suppression operations for the first cell set that is highly effective in reducing the number of output toggles of a glitch-generating cell, or the number of toggles or power consumption of the entire power reduction target circuit, and that does not cause a timing violation. (5) The circuit design support device according to (2) or (3), wherein, for a circuit structure characterized by causing a circuit malfunction in response to a glitch input, the processing unit suppresses the number of output toggles of a cell that outputs the glitch input, and also reduces the number of toggles of the entire logic cone leading to the cell. (6) The circuit design support device according to any of (1) to (3), wherein the processing unit lists a plurality of the identified cells in order of the magnitude of their influence. (7) The circuit design support device according to (2) or (3), wherein the processing unit performs global optimization by discrete optimization using a greedy algorithm, a branch and bound algorithm, or a genetic algorithm. (8) The circuit design assistance device according to (2) or (3), wherein the processing unit performs global optimization by discrete optimization using particle swarm optimization (PSO) or continuous optimization by a differential evolution algorithm.(9) A circuit design method in which a circuit design assistance device, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch generating cell and the number of toggles and power consumption of the entire power reduction target circuit, and presents the identified cells according to the magnitude of their influence. (10) A program that causes a computer to function as a processing unit that, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch generating cell and the number of toggles and power consumption of the entire power reduction target circuit, and presents the identified cells according to the magnitude of their influence.

[0169] REFERENCE SIGNS LIST 10 Circuit design support device, 11 Processor, 12 Memory, 13 Auxiliary storage device, 14 Input / output interface, 21 Cell set identification unit, 22 Subcell set identification unit, 23 Global optimization unit, 24 Netlist modification unit

Claims

1. A circuit design support device comprising a processing unit that, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of an entire circuit to be reduced in power, and presents the identified cells according to the magnitude of their influence.

2. The circuit design assistance device of claim 1, wherein the processing unit: identifies a first set of cells that affects at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption in the entire power reduction target circuit by calculating an average causal effect; and performs global optimization to reduce at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption in the entire power reduction target circuit by targeting the identified first set of cells as a target for glitch prevention measures.

3. The circuit design support device according to claim 2, wherein the processing unit identifies a second cell set that is a cell set having timing margin in the target circuit, and identifies the first cell set from the identified second cell set.

4. The circuit design assistance device according to claim 2, wherein the processing unit derives, within an optimization framework, a combination of glitch suppression operations that are highly effective in reducing the number of output toggles of a glitch-generating cell, or the number of toggles or power consumption in the entire power reduction target circuit, and that do not cause timing violations, for the first cell set.

5. The circuit design assistance device according to claim 2, wherein the processing unit, for a circuit structure characterized by a glitch input causing a circuit malfunction, suppresses the number of output toggles of a cell that outputs the glitch input, and also reduces the number of toggles of the entire logic cone leading to the cell.

6. The circuit design assistance device according to claim 1, wherein the processing unit lists the identified cells in order of the magnitude of their influence.

7. The circuit design support device according to claim 2, wherein the processing unit performs global optimization by discrete optimization using a greedy algorithm, a branch and bound algorithm, or a genetic algorithm.

8. The circuit design support device according to claim 2, wherein the processing unit performs global optimization by discrete optimization using particle swarm optimization (PSO) or continuous optimization by a differential evolutionary algorithm.

9. A circuit design method in which a circuit design support device, based on data obtained from circuit design data, identifies one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire circuit to be reduced in power, and presents the identified cells according to the magnitude of their influence.

10. A program that causes a computer to function as a processing unit that identifies, based on data obtained from circuit design data, one or more cells that affect at least one of the number of output toggles of a glitch-generating cell and the number of toggles and power consumption of the entire circuit to be reduced in power, and presents the identified cells according to the magnitude of their influence.

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