Semiconductor device and method for producing same

Abstract

[Problem] To provide: a semiconductor device in which a film covering a chip can be suitably formed; and a method for producing the same. [Solution] A semiconductor device according to the present disclosure comprises: a first chip which has a first area in a plan view; a second chip which is provided on the first chip and has a second area that is smaller than the first area in a plan view; a first film which is provided on the first chip; and a second film which is provided on the first chip, the second chip, and the first film. The first film includes a first portion that is provided on a side surface of the second chip. A specific longitudinal cross-section of the first portion has an upper side which has a first length and a lower side which has a second length that is longer than the first length.

Description

Semiconductor device and manufacturing method thereof

[0001] TECHNICAL FIELD The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] When manufacturing a semiconductor device such as a photodetector, for example, a wafer-on-wafer (WoW) process or a chip-on-wafer (CoW) process is employed.

[0003] When the WoW process is employed, an upper wafer and a lower wafer are bonded together and then diced into a plurality of chips (semiconductor devices). Each semiconductor device manufactured by the WoW process includes an upper chip derived from the upper wafer and a lower chip derived from the lower wafer.

[0004] On the other hand, when the CoW process is adopted, the upper wafer is divided into a plurality of upper chips by dicing, these upper chips are bonded to the lower wafer, and the lower wafer is then divided into a plurality of lower chips by dicing. Each semiconductor device manufactured by the CoW process includes the upper chips divided before bonding and the lower chips divided after bonding.

[0005] JP 2023-060563 A JP 2022-077181 A

[0006] Typically, when using the CoW process, after bonding the upper chip and the lower wafer, a film covering the upper chip is formed on the lower wafer, and then the lower wafer is separated into the lower chips. This allows the film to fill the gaps between the upper chips. However, if a seam occurs in this film, the mechanical strength of the semiconductor device may be reduced.

[0007] Therefore, the present disclosure provides a semiconductor device that allows a film covering a chip to be suitably formed, and a method for manufacturing the same.

[0008] A semiconductor device according to a first aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a first portion provided on a side surface of the second chip, and a predetermined vertical cross section of the first portion has an upper edge having a first length and a lower edge having a second length longer than the first length. This makes it possible, for example, to suppress the occurrence of a seam in the second film by the first portion, thereby making it possible to preferably form the second film.

[0009] In addition, in this first aspect, the predetermined longitudinal cross section may further have a hypotenuse that is at an angle of 30 to 60 degrees with respect to the longitudinal direction, which makes it possible to, for example, prevent the first portion from becoming too large in size and suppress the occurrence of seams by the first portion.

[0010] Furthermore, in this first aspect, when the angle is θ, the first length is A, the second length is B, and the height of the predetermined longitudinal section is C, C≦(B−A) / tan θ may be satisfied. This makes it possible to, for example, prevent the size of the first portion from becoming too large, while suppressing the occurrence of seams by the first portion.

[0011] In addition, in this first aspect, the predetermined cross-sectional shape may be a trapezoid with the upper side as the upper base and the lower side as the lower base. This makes it possible to easily prevent the size of the first portion from becoming too large, for example, compared to when the cross-sectional shape is a shape other than a trapezoid (for example, a triangle). Furthermore, by reducing the size of the first portion, it becomes possible to alleviate stress caused by the first portion, for example.

[0012] In this first aspect, the first film may further include a second portion spaced apart from the second chip, thereby enabling the second film to be suitably formed by, for example, reinforcing the mechanical strength of the semiconductor device with the second portion.

[0013] In addition, on the first side surface, the first portion may be in contact with the second portion and may be provided between the second chip and the second portion, which makes it possible to form the second portion extending linearly or expanding in a plane from the first portion, for example.

[0014] In this first aspect, the first portion may be separated from the second portion, which makes it possible to form the second portion at a position far away from the first portion, for example.

[0015] Furthermore, in the first side surface, the top surface of the first portion may be located at a position lower than the top surface of the second chip, thereby making it possible to prevent the first portion from covering the edge between the top surface and side surface of the second chip, for example.

[0016] Furthermore, in the first side surface, the top surface of the first portion may be located higher than the top surface of the second chip, thereby making it possible to make the height of the first portion sufficiently large, for example.

[0017] Furthermore, in the first side surface, the first portion may include a portion provided on the top surface of the second chip, which makes it possible to cover, for example, an edge between the top surface and side surface of the second chip with the first portion.

[0018] In this first aspect, the second chip may include a substrate containing silicon or a compound semiconductor substrate, which makes it possible to manufacture the second chip using a substrate suitable for use as a semiconductor device, for example.

[0019] A semiconductor device according to a second aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film may include a second portion provided spaced apart from the second chip. This makes it possible, for example, to reinforce the mechanical strength of the semiconductor device with the second portion, thereby making it possible to suitably form the second film.

[0020] In this second aspect, the first film may further include a first portion provided on a side surface of the second chip, thereby making it possible to preferably form the second film by, for example, suppressing the occurrence of a seam in the second film with the first portion.

[0021] In addition, in this second aspect, the predetermined vertical cross section of the first portion may have an upper side having a first length and a lower side having a second length longer than the first length, thereby making it possible, for example, for the first portion to more effectively suppress the occurrence of seams in the second film.

[0022] In addition, in this second aspect, the predetermined cross-sectional shape may be a trapezoid with the upper side as the upper base and the lower side as the lower base. This makes it possible to easily prevent the size of the first portion from becoming too large, for example, compared to when the cross-sectional shape is a shape other than a trapezoid (for example, a triangle). Furthermore, by reducing the size of the first portion, it becomes possible to alleviate, for example, stress caused by the first portion.

[0023] Furthermore, in the second side surface, the predetermined cross-sectional shape of the first portion may be a triangle having a first side facing the top surface of the first chip, a second side facing the side surface of the second chip, and a third side located between the first and second sides, thereby making it possible to form a first portion with a simple shape, for example.

[0024] A third aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: mounting a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into first chips, wherein the first film is formed to include at least one of a first portion provided on a side surface of the second chip and a second portion provided spaced apart from the second chip, and the first portion is formed so that a predetermined vertical cross section of the first portion has an upper edge having a first length and a lower edge having a second length longer than the first length. This makes it possible to preferably form the second film, for example, by suppressing the generation of a seam in the second film by the first portion or by reinforcing the mechanical strength of the semiconductor device by the second portion.

[0025] In the third aspect, the first chip may have a first area in a plan view, and the second chip may have a second area smaller than the first area in a plan view, thereby making it possible to preferably form the second film when, for example, a CoW process is employed.

[0026] In the third aspect, the first film may be formed by printing, deposition, or coating, which makes it possible to easily form the first film capable of forming the first portion, for example.

[0027] In the third aspect, the first portion may be formed by processing the first film by etching back, which makes it possible to easily form the first portion, for example.

[0028] A semiconductor device according to a fourth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a second film provided on the first chip and the second chip, and a first film provided within the second film, wherein the first film includes a plurality of third portions provided at different heights on sides of the second chip, thereby making it possible to preferably form the second film by, for example, suppressing the growth of a seam within the second film by the plurality of third portions.

[0029] In addition, in this fourth aspect, the first film may further include a plurality of fourth portions provided at different heights above the second chip.

[0030] In addition, in this fourth aspect, one of the plurality of fourth portions may be provided so as to be in contact with one of the plurality of third portions.

[0031] A fifth aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: mounting a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip, wherein the second film is formed to include a first film; and the first film is formed to include a plurality of third portions provided at different heights on sides of the second chip. This makes it possible to preferably form the second film, for example, by suppressing seam growth in the second film by the third portions.

[0032] In the fifth aspect, the first film and the second film may be formed by alternately forming a plurality of first layers forming the second film and a plurality of third portions forming the first film, thereby making it possible to suppress the growth of seams at various locations in the second film during the formation of the second film, for example.

[0033] A semiconductor device according to a sixth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a fifth portion provided on a side surface of the second chip, the fifth portion having a first side surface facing a side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and being continuous between the first side surface and the second side surface. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film by the fifth portion, which can be easily formed.

[0034] In addition, in this sixth aspect, the fifth portion may further include a portion provided on the upper surface of the second chip.

[0035] In addition, in this sixth aspect, the fifth portion may further include a portion provided in a recess provided in a side surface of the second chip.

[0036] In the sixth aspect, the fifth portion may further include a portion provided in a recess provided in the top surface of the first chip, which makes it possible, for example, to suppress the expansion of the first film by the recess.

[0037] A seventh aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: mounting a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into first chips, wherein the first film is formed to include a fifth portion provided on a side surface of the second chip; the fifth portion is formed to have a first side surface facing a side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and is formed continuously between the first side surface and the second side surface. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film using the easily formable fifth portion.

[0038] A semiconductor device according to an eighth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the sixth portion further covers the entire top surface of the second chip. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film by the sixth portion.

[0039] A semiconductor device according to a ninth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the uppermost end of the sixth portion is lower than the uppermost end of a multilayer wiring structure in the second chip and higher than the lowermost end of the multilayer wiring structure in the second chip. This makes it possible to suitably form the second film, for example, by adjusting the position at which a seam occurs in the second film using the sixth portion.

[0040] A semiconductor device according to a tenth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the uppermost end of the sixth portion is higher than the uppermost end of a multilayer wiring structure in the second chip or the lower surface of a substrate in the second chip and lower than the upper surface of the substrate in the second chip. This makes it possible to suitably form the second film, for example, by adjusting the position at which a seam occurs in the second film using the sixth portion.

[0041] A method for manufacturing a semiconductor device according to an eleventh aspect of the present disclosure includes: mounting a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include a sixth portion provided on a side surface of the second chip; the sixth portion is further formed to cover the entire top surface of the second chip; or the sixth portion is formed so that an uppermost end of the sixth portion is lower than an uppermost end of a multilayer wiring structure in the second chip and higher than an uppermost end of the multilayer wiring structure in the second chip; or the sixth portion is formed so that an uppermost end of the sixth portion is higher than an uppermost end of the multilayer wiring structure in the second chip or a lower surface of a substrate in the second chip and lower than an upper surface of the substrate in the second chip. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film by the sixth portion or by adjusting the position at which a seam occurs in the second film by the sixth portion.

[0042] In the eleventh aspect, the first film may be formed by coating, which makes it possible to easily form the first film capable of forming the sixth portion, for example.

[0043] A semiconductor device according to a twelfth aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, and a second film provided on the first chip, the second chip, and the first film, wherein a surface of the first chip or the second chip includes a curved or tapered surface provided near a side surface of the second chip. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film by the curved or tapered surface.

[0044] Furthermore, in the twelfth side surface, the radius of curvature of the curved surface may be larger than the radius of curvature of the region between the top surface and the side surface of the second chip.

[0045] In addition, in this twelfth side, the tapered surface may be provided continuously with the surfaces of the substrate and insulating film in the second chip.

[0046] A thirteenth aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: mounting a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip, wherein the first chip or the second chip is formed such that a surface of the first chip or the second chip includes a curved or tapered surface near a side surface of the second chip. This makes it possible to preferably form the second film, for example, by suppressing the occurrence of a seam in the second film due to the curved or tapered surface.

[0047] In the thirteenth aspect, the curved surface or the tapered surface may be formed by a blade, which makes it possible to easily form the curved surface or the tapered surface in a predetermined shape, for example.

[0048] 1 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment; FIG. 2 is a plan view showing the structure of the semiconductor device of the first embodiment; FIG. 3 is a cross-sectional view for explaining details of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view for explaining details of the semiconductor device of the comparative example of the first embodiment; FIG. 5 is a cross-sectional view (1 / 6) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 6 is a cross-sectional view (2 / 6) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 7 is a cross-sectional view (3 / 6) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 8 is a cross-sectional view (4 / 6) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 9 is a cross-sectional view (5 / 6) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 10 is a cross-sectional view (1 / 5) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 11 is a cross-sectional view (2 / 5) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 12 is a cross-sectional view (3 / 5) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 13 is a cross-sectional view (4 / 5) showing a method for manufacturing the semiconductor device of the first embodiment; FIG. 14 is a cross-sectional view (5 / 5) showing a method for manufacturing the semiconductor device of the first embodiment. FIG. 1 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. FIG. 2 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. FIG. 3 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a second modification of the first embodiment. FIG. 4 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a second modification of the first embodiment. FIG. 5 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device according to a second modification of the first embodiment. FIG. 6 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a third modification of the first embodiment. FIG. 7 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a third modification of the first embodiment. FIG. 8 is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a plan view showing structures of semiconductor devices according to fourth and fifth modifications of the first embodiment. FIG. 10 is a plan view showing structures of semiconductor devices according to sixth and seventh modifications of the first embodiment. FIG. 11 is a plan view showing structures of semiconductor devices according to eighth and ninth modifications of the first embodiment. FIG. 12 is a cross-sectional view showing structures of semiconductor devices according to tenth and eleventh modifications of the first embodiment. FIG. 13 is a cross-sectional view showing structures of semiconductor devices according to twelfth and thirteenth modifications of the first embodiment.35. A cross-sectional view showing the structure of a semiconductor device of a second embodiment. A cross-sectional view showing the structure of a semiconductor device of a third embodiment. A cross-sectional view showing the structure of a semiconductor device of a fourth embodiment. A block diagram showing the configuration of a semiconductor device of a fifth embodiment. A block diagram showing an example of the configuration of an electronic device. A block diagram showing an example of the configuration of a mobile object control system. A plan view showing a specific example of the setting position of the imaging unit of FIG. 35. A diagram showing an example of a schematic configuration of an endoscopic surgery system. A block diagram showing an example of the functional configuration of a camera head and a CCU. A cross-sectional view showing the structure of a semiconductor device of a sixth embodiment. A cross-sectional view showing a manufacturing method of a semiconductor device of the sixth embodiment. A plan view showing a manufacturing method of a semiconductor device of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of a first modified example of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of a second modified example of the sixth embodiment. A cross-sectional view showing the structure of semiconductor devices of first and second modified examples of the sixth embodiment. A cross-sectional view showing the structure of semiconductor devices of third to sixth modified examples of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of a seventh modified example of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of an eighth modified example of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of a ninth modified example of the sixth embodiment. A cross-sectional view showing the structure of a semiconductor device of the seventh embodiment. A cross-sectional view showing the structure of a semiconductor device of a first modified example of the seventh embodiment. A cross-sectional view showing the structure of a semiconductor device of a second modified example of the seventh embodiment. 10A is a cross-sectional view showing the structure of a semiconductor device according to a third modified example of the seventh embodiment; FIG. 10B is a cross-sectional view showing the structure of a semiconductor device according to a fourth modified example of the seventh embodiment; FIG. 10C is a cross-sectional view showing the structure of a semiconductor device according to a fifth modified example of the seventh embodiment; FIG. 10D is a cross-sectional view showing the structure of a semiconductor device according to a sixth modified example of the seventh embodiment; FIG. 10E is a cross-sectional view showing the structure of a semiconductor device according to a seventh modified example of the seventh embodiment; FIG. 10F is a cross-sectional view showing the structure of a semiconductor device according to an eighth modified example of the seventh embodiment; FIG. 10G is a cross-sectional view showing the structure of a semiconductor device according to a ninth modified example of the seventh embodiment; FIG. 10H is a cross-sectional view (1 / 9) showing a method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 10H is a cross-sectional view (2 / 9) showing a method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 10H is a cross-sectional view (3 / 9) showing a method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 10H is a cross-sectional view (4 / 9) showing a method for manufacturing the semiconductor device according to the seventh embodiment.FIG. 10 is a cross-sectional view (5 / 9) showing a method for manufacturing a semiconductor device of the seventh embodiment. FIG. 11 is a cross-sectional view (6 / 9) showing a method for manufacturing a semiconductor device of the seventh embodiment. FIG. 12 is a cross-sectional view (7 / 9) showing a method for manufacturing a semiconductor device of the seventh embodiment. FIG. 13 is a cross-sectional view (8 / 9) showing a method for manufacturing a semiconductor device of the seventh embodiment. FIG. 14 is a cross-sectional view (9 / 9) showing a method for manufacturing a semiconductor device of the seventh embodiment. FIG. 15 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device of a seventh modification of the seventh embodiment. FIG. 16 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device of a seventh modification of the seventh embodiment. FIG. 17 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device of a seventh modification of the seventh embodiment. FIG. 18 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device of an eighth modification of the seventh embodiment. FIG. 19 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device of an eighth modification of the seventh embodiment. FIG. 19 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device of the eighth embodiment. FIG. 20 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device of the eighth embodiment. FIG. 21 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device of the eighth embodiment. FIG. 19 is a cross-sectional view showing a structure of a semiconductor device of the eighth embodiment. FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the eighth embodiment. FIG. 11 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a first modification of the eighth embodiment. FIG. 12 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a first modification of the eighth embodiment. FIG. 13 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device according to a first modification of the eighth embodiment. FIG. 14 is a cross-sectional view showing the structure of a semiconductor device according to a ninth embodiment. FIG. 15 is a cross-sectional view (1 / 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment. FIG. 16 is a cross-sectional view (2 / 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment. FIG. 17 is a cross-sectional view (3 / 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment. FIG. 18 is a cross-sectional view (4 / 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment. FIG. 19 is a cross-sectional view (5 / 5) showing a method for manufacturing a semiconductor device according to the ninth embodiment. FIG. 19 is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the ninth embodiment. FIG. 19 is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to a second modification of the ninth embodiment. FIG. 19 is a cross-sectional view (2 / 4) showing a method for manufacturing a semiconductor device according to a fourth modification of the ninth embodiment.FIG. 10 is a cross-sectional view (3 / 4) showing a method for manufacturing a semiconductor device according to a fourth modification of the ninth embodiment; FIG. 11 is a cross-sectional view (4 / 4) showing a method for manufacturing a semiconductor device according to a fourth modification of the ninth embodiment; FIG. 12 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a fifth modification of the ninth embodiment; FIG. 13 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a fifth modification of the ninth embodiment; FIG. 14 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a sixth modification of the ninth embodiment; FIG. 15 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a sixth modification of the ninth embodiment; FIG. 16 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a seventh modification of the ninth embodiment; FIG. 17 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a seventh modification of the ninth embodiment.

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0050] First Embodiment (1) Structure of the Semiconductor Device FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0051] The semiconductor device of this embodiment is, for example, a photodetector such as a solid-state imaging device, but may also be other devices, such as a light-emitting device such as a surface-emitting laser device, or a control device such as a logic circuit device.

[0052] FIG. 1 shows X, Y, and Z axes that are perpendicular to each other. The X and Y directions correspond to the lateral (horizontal) direction, and the Z direction corresponds to the longitudinal (vertical) direction. The +Z direction corresponds to the upward direction, and the −Z direction corresponds to the downward direction. Note that the −Z direction may or may not strictly coincide with the direction of gravity.

[0053] The semiconductor device of this embodiment includes a lower chip 1, an upper chip 2, a lower film 3, and an upper film 4. The lower chip 1 and the upper chip 2 are examples of the first and second chips of the present disclosure, respectively. The lower film 3 and the upper film 4 are examples of the first and second films of the present disclosure, respectively. The semiconductor device of this embodiment is manufactured by, for example, a CoW process.

[0054] The lower chip 1 includes a substrate 11, an interlayer insulating film 12, a multilayer wiring structure 13, etc. The multilayer wiring structure 13 includes a wiring layer 13a including multiple wirings, multiple via plugs 13b, and multiple metal pads 13c. Similarly, the upper chip 2 includes a substrate 21, an interlayer insulating film 22, a multilayer wiring structure 23, etc. The multilayer wiring structure 23 includes a wiring layer 23a including multiple wirings, multiple via plugs 23b, and multiple metal pads 23c. The lower film 3 includes an outer periphery portion 3a and a reinforcing portion 3b. The outer periphery portion 3a and the reinforcing portion 3b are examples of the first and second portions of the present disclosure. FIG. 1 shows vertical cross sections of two portions of one outer periphery portion 3a and two portions of one reinforcing portion 3b.

[0055] FIG. 2 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0056] 2 shows the above-mentioned lower chip 1, upper chip 2, and lower film 3, and does not show the upper film 4. In Fig. 2, the lower chip 1 is shown in white, the upper chip 2 is shown with dotted hatching, and the lower film 3 is shown with thick oblique hatching. Fig. 1 shows a vertical cross section taken along line A-A' shown in Fig. 2.

[0057] The semiconductor device of this embodiment will be described in detail below with reference to Fig. 1. In this description, Fig. 2 will also be referred to as appropriate.

[0058] [Lower Chip 1] In the lower chip 1, an interlayer insulating film 12 is provided on a substrate 11, and a multilayer wiring structure 13 is provided in the interlayer insulating film 12. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The multilayer wiring structure 13 includes one or more wiring layers in the interlayer insulating film 12. The wiring layer 13a is one of these wiring layers. A via plug 13b is provided on the wiring layer 13a, and a metal pad 13c is provided on the via plug 13b.

[0059] [Upper Chip 2] In the upper chip 2, an interlayer insulating film 22 is provided below a substrate 21, and a multilayer wiring structure 23 is provided within the interlayer insulating film 22. The substrate 21 is, for example, a semiconductor substrate such as a Si substrate. The multilayer wiring structure 23 includes one or more wiring layers within the interlayer insulating film 22. The wiring layer 23a is one of these wiring layers. A via plug 23b is provided below the wiring layer 23a, and a metal pad 23c is provided below the via plug 23b.

[0060] Upper chip 2 is bonded to lower chip 1, and as a result, is stacked on lower chip 1. In Fig. 1, interlayer insulating film 22 and metal pad 23c are disposed on interlayer insulating film 12 and metal pad 13c, and metal pad 23c is bonded to metal pad 13c.

[0061] In this embodiment, the lower chip 1 has a large area in a plan view, and the upper chip 2 has a small area in a plan view ( FIG. 2 ). Therefore, in FIG. 2 , the contour (side surface) of the upper chip 2 is located inside the contour (side surface) of the lower chip 1. The area of ​​the lower chip 1 is an example of the first area of ​​the present disclosure. The area of ​​the upper chip 2 is an example of the second area of ​​the present disclosure.

[0062] [Lower Film 3] The lower film 3 is provided on the lower chip 1. The lower film 3 is, for example, an insulating film. The lower film 3 of this embodiment includes an outer peripheral portion 3a provided on the side surface of the upper chip 2 and a reinforcing portion 3b provided at a distance from the upper chip 2. The lower film 3 of this embodiment has a lattice (mesh) shape in plan view ( FIG. 2 ).

[0063] 2, the boundary line between the outer periphery portion 3a and the reinforcing portion 3b is indicated by a dashed line R. In this embodiment, each portion of the lower film 3 extends in the X direction or the Y direction, with the portion extending along the side surface of the upper chip 2 being referred to as the outer periphery portion 3a and the other portion being referred to as the reinforcing portion 3b. In this embodiment, the outer periphery portion 3a is in contact with the reinforcing portion 3b and is provided between the upper chip 2 and the reinforcing portion 3b. In other words, the outer periphery portion 3a and the reinforcing portion 3b in this embodiment are not separate but are integrated.

[0064] The outer peripheral portion 3a is disposed along the outer periphery of the upper chip 2 ( FIG. 2 ). In FIG. 1 , the shape of the vertical cross section of the outer peripheral portion 3a is triangular. This vertical cross section is an example of a predetermined vertical cross section of the present disclosure. This triangle has a side X1 facing the top surface of the lower chip 1, a side X2 facing the side surface of the upper chip 2, and a side X3 located between the sides X1 and X2. In this embodiment, this triangle is a right-angled triangle. The sides X1, X2, and X3 are examples of the first, second, and third sides of the present disclosure, respectively. In FIG. 1 , the side X1 is in contact with the top surface of the lower chip 1, and the side X2 is in contact with the side surface of the upper chip 2. Note that the shape of the vertical cross section of the outer peripheral portion 3a may be a shape other than a triangle (e.g., a trapezoid), as will be described later.

[0065] The reinforcing portion 3b is located at a distance from the upper chip 2 (FIG. 2). The reinforcing portion 3b functions to reinforce the mechanical strength of the semiconductor device of this embodiment. In FIG. 2, the lower chip 1 has four corners, and the upper chip 2 is located near one corner of the lower chip 1. Therefore, the mechanical strength of the semiconductor device of this embodiment may be strong near this one corner but weak near the other three corners. Similarly, the mechanical strength of the semiconductor device of this embodiment may be weak at a distance from the upper chip 2. Therefore, in this embodiment, the reinforcing portion 3b is located at a distance from the upper chip 2. The reinforcing portion 3b of this embodiment functions as a beam that reinforces the mechanical strength of the semiconductor device. Therefore, it is desirable that the lower film 3 be a hard film. Although the cross-sectional shape of the reinforcing portion 3b is trapezoidal in FIG. 1, it may have other shapes.

[0066] The function of reinforcing the mechanical strength of the semiconductor device may be provided not only by reinforcing portion 3b but also by outer peripheral portion 3a. Although outer peripheral portion 3a has a ring-shaped planar shape in FIG. 2, it may have a non-ring-shaped planar shape. Reinforcing portion 3b may also have a shape other than the shape shown in FIG. 2.

[0067] [Upper film 4] The upper film 4 is provided on the lower chip 1, the upper chip 2, and the lower film 3. The upper film 4 is, for example, an insulating film different from the lower film 3. In this embodiment, the upper film 4 is formed so as to cover the upper surface of the lower chip 1, the upper surface of the upper chip 2, and the upper surface of the lower film 3.

[0068] The strength of the upper film 4 may be weaker than that of the lower film 3. This is because the mechanical strength of the semiconductor device can be reinforced by the reinforcing portion 3b. This allows for greater freedom in selecting the material for the upper film 4 and makes it possible to suppress damage to the upper film 4 by the reinforcing portion 3b.

[0069] 3 is a cross-sectional view for explaining the details of the semiconductor device of the first embodiment, in which the multilayer wiring structures 13 and 23 and the reinforcing portion 3b are not shown.

[0070] In this embodiment, the shape of the vertical cross section of the outer peripheral portion 3a may be a trapezoid as shown in FIG. 3 instead of a triangle as shown in FIG. 1 . This vertical cross section is also an example of a predetermined vertical cross section of the present disclosure. This trapezoid has sides X1, X2, and X3 corresponding to sides X1, X2, and X3 of the triangle described above, respectively, and an additional side X4. Side X4 is the upper side of the vertical cross section and corresponds to the upper base of the trapezoid. Side X1 is the lower side of the vertical cross section and corresponds to the lower base of the trapezoid. Side X2 is located between side X4 and side X1 and is located on the side of the upper chip 2 in the vertical cross section. Side X3 is located between side X4 and side X1 and is located on the opposite side of the upper chip 2 in the vertical cross section.

[0071] In this embodiment, sides X4 and X1 are perpendicular to the Z direction, side X2 is parallel to the Z direction, and side X3 is inclined at an angle θ with respect to the Z direction. In this embodiment, the angle θ is 30 to 60 degrees (30°≦θ≦60°), for example, approximately 45 degrees (θ≈45°). Side X3 is a hypotenuse inclined with respect to the Z direction. Side X3 is shown as a straight line in FIG. 3 but may instead be curved. Similarly, side X4 is shown as a straight line in FIG. 3 but may instead be curved. Furthermore, sides X4 and X1 are shown as parallel to each other in FIG. 3 but may instead be non-parallel to each other.

[0072] 3 shows the length A of side X4, the length B of side X1, and the length C of side X2. The lengths A, B, and C correspond to the upper base length, lower base length, and height of the trapezoid, respectively. The lengths A and B are examples of the first and second lengths of the present disclosure. In this embodiment, the length B is set to be longer than the length A (B>A). Furthermore, the lengths A, B, C, and the angle θ of this embodiment are set so that the relationship C≦(B−A) / tan θ holds.

[0073] 3 further shows the thickness T of the upper film 4, the thickness T1 of the upper chip 2, and the thickness T2 of the upper film 4 above the upper chip 2. The relationship T = T1 + T2 holds among the thicknesses T, T1, and T2. In this embodiment, it is desirable to set the thickness T sufficiently larger than the thickness T1 so that the value of the thickness T2 is sufficiently large. This allows the upper chip 2 to be sufficiently covered by the upper film 4. The thickness T2 is set to, for example, at least half the thickness T1 (T2 ≥ T1 / 2), or may even be set to be greater than the thickness T1 (T2 ≥ T1).

[0074] The relationship C≦(B−A) / tan θ may be applied to the outer peripheral portion 3a in FIG. 1 by setting A=0. Similarly, the relationship 30°≦θ≦60° may be applied to the outer peripheral portion 3a in FIG. 1. Similarly, the relationships T2≧T1 / 2 and T2≧T1 may be applied to the semiconductor device in FIG. 1.

[0075] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0076] The semiconductor device of this comparative example has a structure in which the lower film 3 is removed from the semiconductor device of the first embodiment. In this case, a seam S may occur in the upper film 4 due to a step between the top surface of the lower chip 1 and the top surface of the upper chip 2. As a result, the mechanical strength of the semiconductor device may be reduced by the seam S. In FIG. 4, the seam S occurs near the interface between the lower chip 1 and the upper chip 2.

[0077] FIG. 5 is a cross-sectional view for explaining details of a semiconductor device as a comparative example of the first embodiment.

[0078] 5, when the upper film 4 is formed, film portions 4a and 4b, which are parts of the upper film 4, are gradually formed on the surfaces of the lower chip 1 and the upper chip 2. In FIG. 5, film portion 4a is formed on the surface of the lower chip 1, and film portion 4b is formed on the surface of the upper chip 2.

[0079] The film portions 4a and 4b are then integrated to form the upper film 4. However, because there is a step between the top surface of the lower chip 1 and the top surface of the upper chip 2, it is difficult to form the upper film 4 at the point indicated by the dashed line S'. This is the cause of the seam S mentioned above.

[0080] Therefore, when manufacturing the semiconductor device of this embodiment, the outer peripheral portion 3a is formed on the side surface of the upper chip 2, and then the upper film 4 is formed on the lower chip 1 and the upper chip 2 (see FIGS. 1 and 3). As a result, the outer peripheral portion 3a reduces the step between the top surface of the lower chip 1 and the top surface of the upper chip 2, making it possible to suppress the occurrence of seams S. According to this embodiment, by forming the outer peripheral portion 3a, it is possible to form a suitable upper film 4 in which the occurrence of seams S is suppressed. Furthermore, according to this embodiment, by forming the reinforcing portion 3b, it is possible to form a suitable upper film 4 reinforced by the reinforcing portion 3b.

[0081] In this embodiment, the length B of side X1 in FIG. 3 is longer than the length A of side X4. This allows the inclination of side X3 to be tapered, and the step can be reduced by the outer peripheral portion 3a. The relationship B>A also holds true in FIG. 1 when A=0, so this effect can also be achieved in the structure of FIG. 1. On the other hand, making A≠0 as in FIG. 3 has the advantages of reducing stress caused by the outer peripheral portion 3a and suppressing the occurrence of seams S in the outer peripheral portion 3a with a small area and volume. Therefore, in FIG. 3, by making A≠0, the shape of the vertical cross section of the outer peripheral portion 3a is set to be trapezoidal.

[0082] The angle θ in FIG. 3 is preferably set to 30 to 60 degrees. This is because if the angle θ is small, the step will not be reduced, and if the angle θ is large, the area and volume of the outer peripheral portion 3a may become excessively large. Furthermore, the lengths A, B, and C and the angle θ in FIG. 3 are preferably set so that the relationship C≦(B−A) / tan θ holds. This makes it possible to prevent the area of ​​the side X3 in the outer peripheral portion 3a from becoming excessively large. These relationships may also be applied to the semiconductor device in FIG. 1.

[0083] In order to achieve the above-mentioned effects, it is desirable that the lower film 3 be made of a material with high heat resistance. Various examples of materials for the lower film 3 will be described later.

[0084] (2) Method for Manufacturing the Semiconductor Device FIGS. 6 to 11 are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment.

[0085] First, the lower wafer 1 is fabricated by forming an interlayer insulating film 12 and a multilayer wiring structure 13 on a substrate 11 ( FIG. 6A ). Next, the upper wafer 2 is fabricated by forming an interlayer insulating film 22 and a multilayer wiring structure 23 on a substrate 21 ( FIG. 6A ). Next, the upper wafer 2 is divided into multiple upper chips 2 by dicing, and these upper chips 2 are bonded to the lower wafer 1 ( FIG. 6A ). FIG. 6A shows how one of these upper chips 2 is placed on the lower wafer 1. In the description of this embodiment, the symbol "1" is used as a common symbol for the lower chip and the lower wafer, and the symbol "2" is used as a common symbol for the upper chip and the upper wafer. The lower wafer 1 is an example of the first wafer of the present disclosure.

[0086] Next, the lower wafer 1 and the upper chip 2 are annealed (FIG. 6B), so that the metal pads 23c in the upper chip 2 are bonded to the metal pads 13c in the lower wafer 1.

[0087] Next, a paste 3', which is the material for the lower film 3, is formed on the lower wafer 1 ( FIG. 7A ). The paste 3' is, for example, a glass paste containing glass particles, and is formed on the lower wafer 1 by glass paste printing. FIG. 7A shows a screen mask 31 and a squeegee 32 used in the glass paste printing. The screen mask 31 has an opening P1a for passing the paste 3'. The squeegee 32 is used to push the paste 3' into the opening P1a. According to the process of FIG. 7A , a paste 3' having a pattern similar to the outer peripheral portion 3a and the reinforcing portion 3b is formed on the lower wafer 1. Note that the material of the particles in the paste 3' may be other than glass, such as silicon oxide, silicone, or alumina.

[0088] Next, the paste 3' is reflowed (FIG. 7B). As a result, the paste 3' is transformed into the lower film 3 including the peripheral portion 3a and the reinforcing portion 3b (not shown). This reflow is performed at a temperature at which the resin in the paste 3' melts. As a result, the peripheral portion 3a is formed to have a triangular cross section, as shown in FIG. 7B.

[0089] Next, the lower film 3 is baked (FIG. 8A), which causes the resin to be released from the lower film 3 and bakes the lower film 3 to harden it.

[0090] Next, an upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 3 (FIG. 8B). FIG. 8B shows a protrusion P2a formed on the upper film 4. The protrusion P2a is formed above the upper chip 2 and the lower film 3 because the upper surfaces of the upper chip 2 and the lower film 3 are higher than the upper surfaces of the lower wafer 1.

[0091] Next, a resist film 33 is formed on the upper film 4 and patterned (FIG. 9A), resulting in the formation of an opening P3a in the resist film 33 on the protrusion P2a.

[0092] Next, recesses P4a are formed in the protrusions P2a of the upper film 4 by etching using the resist film 33 (FIG. 9B). As a result, most of the protrusions P2a are removed from the upper film 4.

[0093] Next, the resist film 33 is removed (FIG. 10A). FIG. 10A shows the convex portion P2a of the upper film 4 and the concave portion P4a formed in the convex portion P2a.

[0094] Next, the surface of the upper film 4 is planarized by CMP (Chemical Mechanical Polishing) (FIG. 10B), resulting in the protrusions P2a and recesses P4a being removed from the upper film 4.

[0095] Next, the lower wafer 1, upper chip 2, lower film 3, and upper film 4 are bonded to a support substrate 5 ( FIG. 11A ). The support substrate 5 is, for example, a semiconductor wafer such as a Si wafer. The orientations of the lower wafer 1, upper chip 2, lower film 3, and upper film 4 shown in FIG. 11A are opposite to the orientations of the lower wafer 1, upper chip 2, lower film 3, and upper film 4 shown in FIG. 10B .

[0096] Next, the substrate 11 is thinned by grinding, and then the lower wafer 1 (and the support substrate 5) is divided into a plurality of lower chips 1 by dicing (FIG. 11B). In this way, a semiconductor device including the lower chip 1 and the upper chip 2 is manufactured.

[0097] The semiconductor device shown in FIG. 11B is the same as the semiconductor device shown in FIG. 1. However, the support substrate 5 is not shown in FIG. 1. The orientation of the semiconductor device shown in FIG. 1 is opposite to the orientation of the semiconductor device shown in FIG. 11B. As described above, the lower chip 1 has a large area in a plan view, and the upper chip 2 has a small area in a plan view. As described above, the semiconductor device of this embodiment is manufactured to include the lower chip 1 processed from the lower wafer 1 and the upper chip 2 processed from the upper wafer 2.

[0098] 12 to 16 are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment.

[0099] 6 to 11 show the steps of forming the outer peripheral portion 3a, while FIGS. 12 to 16 show the steps of forming the reinforcing portion 3b. In this embodiment, the steps shown in FIGS. 6 to 11 and the steps shown in FIGS. 12 to 16 are performed simultaneously to form the outer peripheral portion 3a and the reinforcing portion 3b simultaneously. However, the outer peripheral portion 3a and the reinforcing portion 3b may be formed sequentially. For example, the steps shown in FIGS. 6 to 11 and the steps shown in FIGS. 12 to 16 may be performed sequentially to form the outer peripheral portion 3a and the reinforcing portion 3b sequentially.

[0100] 6A and 6B, a paste 3', which is the material of the lower film 3, is formed on the lower wafer 1 (FIG. 12A). FIG. 12A shows the above-mentioned screen mask 31 and squeegee 32. The screen mask 31 has an opening P1b in addition to the above-mentioned opening P1a (not shown). The opening P1a is used to form a pattern corresponding to the outer peripheral portion 3a, and the opening P1b is used to form a pattern corresponding to the reinforcing portion 3b.

[0101] Next, the paste 3' is reflowed (FIG. 12B). As a result, the paste 3' is transformed into the lower film 3 including the peripheral portion 3a (not shown) and the reinforcing portion 3b. This reflow forms the reinforcing portion 3b so that it has a trapezoidal cross section. Note that the cross section of the reinforcing portion 3b may have a shape other than a trapezoid, such as a semicircular or semielliptical shape.

[0102] Next, the lower film 3 is baked (FIG. 13A), which causes the resin to be released from the lower film 3 and the lower film 3 is baked and hardened.

[0103] Next, an upper film 4 is formed on the lower wafer 1, upper chip 2, and lower film 3 (FIG. 13B). FIG. 13B shows a convex portion P2b formed on the upper film 4. While the above-mentioned convex portion P2a (not shown) is formed above the upper chip 2 and the outer peripheral portion 3a, the convex portion P2b is formed above the reinforcing portion 3b.

[0104] Next, a resist film 33 is formed on the upper film 4 and patterned (FIG. 14A), resulting in the formation of an opening P3b in the resist film 33 on the protrusion P2b.

[0105] Next, a recess P4b is formed in the protrusion P2b of the upper film 4 by etching using the resist film 33 (FIG. 14B). As a result, most of the protrusion P2b is removed from the upper film 4.

[0106] Next, the resist film 33 is removed (FIG. 15A). FIG. 15A shows the convex portion P2b of the upper film 4 and the concave portion P4b formed in the convex portion P2b.

[0107] Next, the surface of the upper film 4 is planarized by CMP (FIG. 15B), resulting in the protrusions P2a and recesses P4a being removed from the upper film 4.

[0108] Next, the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 are bonded to a support substrate 5 (FIG. 16A). The orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 16A are opposite to the orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 15B.

[0109] Next, the substrate 11 is thinned by grinding, and then the lower wafer 1 (and the support substrate 5) is divided into a plurality of lower chips 1 by dicing (FIG. 16B). In this manner, a semiconductor device including a lower chip 1 and an upper chip 2 is manufactured. The semiconductor device shown in FIG. 16B is the same as the semiconductor device shown in FIG.

[0110] 17 and 18 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. In this modification, a lower film 41 is formed instead of the lower film 3. The lower film 41 is an example of the first film of the present disclosure.

[0111] 6A and 6B, a lower film 41 is conformally formed on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 17A). The lower film 41 in this modification is formed by CVD (Chemical Vapor Deposition), for example, ALD (Atomic Layer Deposition). As a result, the lower film 41 is deposited on the surfaces of the lower wafer 1 and the upper chip 2. The lower film 41 is made of, for example, SiO ２ (silicon oxide) film, SiN (silicon nitride) film, SiC (silicon carbide) film, or SiCN (silicon carbonitride) film.

[0112] Next, the lower film 41 is etched back ( FIG. 17B ). As a result, the outer peripheral portion 41a is formed by the lower film 41. The outer peripheral portion 41a of this modification has a shape similar to that of the outer peripheral portion 3a shown in FIG. 3 , for example, a trapezoidal cross section. Note that the reinforcing portion of this modification may be formed simultaneously with the outer peripheral portion 41a, or may be formed in sequence with the outer peripheral portion 41a. The outer peripheral portion 41a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0113] 8B to 10B are then performed, resulting in the formation of an upper film 4 on the lower wafer 1, the upper chip 2, and the lower film 41, as shown in FIG.

[0114] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 18B).

[0115] According to this modification, it is possible to form the lower film 41 by CVD, which is widely used in semiconductor processes. Furthermore, according to this modification, by employing CVD, it is possible to form the lower film 41 with good film quality.

[0116] 19 to 21 are cross-sectional views showing a method for manufacturing a semiconductor device according to a second modification of the first embodiment. In this modification, a lower film 42 is formed instead of the lower film 3. The lower film 42 is an example of the first film of the present disclosure.

[0117] 6A and 6B, a lower film material 42', which is the material for the lower film 42, is applied to the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 19A). The lower film material 42' includes an organic material such as a resin. Examples of the resin include polyimide, silicone, and amorphous fluororesin (Cytop (registered trademark)).

[0118] Next, the lower film material 42' is patterned (FIG. 19B). As a result, the lower film material 42' is processed into a pattern similar to that of the outer peripheral portion 42a, which will be described later. The lower film material 42' may also be processed into a pattern similar to that of the outer peripheral portion 42a and the reinforcing portion, which will be described later.

[0119] Next, the lower film material 42' is reflowed (baked) (FIG. 20A). As a result, the lower film material 42' is transformed into the lower film 42 including the peripheral portion 42a. This reflow is performed at a temperature at which the resin in the lower film material 42' melts. As a result, as shown in FIG. 20A, the peripheral portion 42a is formed to have a generally triangular vertical cross section. Note that the reinforcing portion of this modified example may be formed simultaneously with the peripheral portion 42a, or may be formed sequentially with the peripheral portion 42a. The peripheral portion 42a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0120] Next, the lower film 42 is baked (FIG. 20B), which causes the resin to be released from the lower film 42 and the lower film 42 to be baked and hardened.

[0121] 8B to 10B are then performed, resulting in the formation of an upper film 4 on the lower wafer 1, the upper chip 2, and the lower film 42, as shown in FIG.

[0122] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 21B).

[0123] According to this modification, it is possible to form the lower film 42 by a coating method that is widely used in semiconductor processes. For example, if the lower film material 42′ contains polyimide, it is possible to form the lower film 42 with high heat resistance.

[0124] 22 and 23 are cross-sectional views showing a method for manufacturing a semiconductor device according to a third modification of the first embodiment. In this modification, a lower film 43 is formed instead of the lower film 3. The lower film 43 is an example of the first film of the present disclosure.

[0125] 6A and 6B, a lower film 43 is formed by coating on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 22A). The lower film 43 is, for example, an inorganic film such as an SOG (Spin on Glass) film.

[0126] Next, the lower film 43 is etched back ( FIG. 22B ). As a result, the outer peripheral portion 43a is formed by the lower film 43. The outer peripheral portion 43a of this modification has a shape similar to that of the outer peripheral portion 3a shown in FIG. 3 , for example, a trapezoidal cross section. Note that the reinforcing portion of this modification may be formed simultaneously with the outer peripheral portion 43a, or may be formed in sequence with the outer peripheral portion 43a. The outer peripheral portion 43a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0127] 8B to 10B are then performed, resulting in the formation of an upper film 4 on the lower wafer 1, the upper chip 2, and the lower film 41, as shown in FIG.

[0128] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 23B).

[0129] According to this modification, the lower film 43 can be formed by a coating method that is widely used in semiconductor processes.

[0130] (4) Manufacturing Method of Semiconductor Device Fig. 24 is a plan view showing a manufacturing method of the semiconductor device of the first embodiment. In the explanation of Fig. 24, in order to distinguish between the lower chip and the lower wafer, the lower chip will be represented by the symbol "1" and the lower wafer will be represented by the symbol "W".

[0131] 24 shows the lower wafer W before being divided into a plurality of lower chips 1. The lower wafer W has a plurality of chip regions W1 each having a rectangular planar shape and a scribe (dicing) region W2 having a mesh-like planar shape. Each chip region W1 is an area that will become a lower chip 1 after division. Therefore, each chip region W1 has a structure similar to that of the lower chip 1 shown in FIG. 2. For example, each chip region W1 is bonded to one upper chip 2 that has already been divided.

[0132] In this embodiment, the lower wafer W is divided into a plurality of chip regions W1 (lower chips 1) by cutting the lower wafer W along the scribe region W2. In this manner, a plurality of semiconductor devices are manufactured from the lower wafer W. Each semiconductor device includes a lower chip 1 and an upper chip 2.

[0133] Each semiconductor device may have a different structure in plan view from that shown in Figures 2 and 24. Various examples of such structures will be described below.

[0134] (5) Fourth to Ninth Modifications FIG. 25 is a plan view showing the structure of semiconductor devices according to fourth and fifth modifications of the first embodiment.

[0135] 25A shows a semiconductor device according to a fourth modification. The lower film 3 of this modification includes an outer peripheral portion 3a and a plurality of reinforcing portions 3b separated from the outer peripheral portion 3a. These reinforcing portions 3b are arranged in a staggered pattern. In this manner, the outer peripheral portion 3a may be in contact with the reinforcing portions 3b or may be separated from the reinforcing portions 3b.

[0136] 25B shows a semiconductor device according to a fifth modification. The lower film 3 of this modification includes an outer peripheral portion 3a and a reinforcing portion 3b that is in contact with the outer peripheral portion 3a. The reinforcing portion 3b has the same planar shape as the upper chip 2. According to this modification, the reinforcing portion 3b can be formed by simple patterning.

[0137] FIG. 26 is a plan view showing the structures of semiconductor devices according to sixth and seventh modifications of the first embodiment.

[0138] 26A shows a semiconductor device according to a sixth modified example. The lower film 3 of this modified example includes the reinforcing portion 3b but does not include the peripheral portion 3a. In other words, the lower film 3 of this modified example does not include the portion provided on the side surface of the upper chip 2. In this way, the lower film 3 may or may not include the peripheral portion 3a.

[0139] 26B shows a semiconductor device according to a seventh modification. The lower film 3 of this modification includes an outer peripheral portion 3a but does not include a reinforcing portion 3b. In other words, the lower film 3 of this modification does not include a portion that is spaced apart from the upper chip 2. In this way, the lower film 3 may or may not include the reinforcing portion 3b.

[0140] FIG. 27 is a plan view showing the structures of semiconductor devices according to eighth and ninth modifications of the first embodiment.

[0141] 27A shows a semiconductor device according to an eighth modification. The lower film 3 of this modification also includes a reinforcing portion 3 b, but does not include an outer peripheral portion 3 a. However, the reinforcing portion 3 b of this modification has the same planar shape as the reinforcing portion 3 b of the fourth modification.

[0142] 27B shows a semiconductor device according to a ninth modification. The lower film 3 of this modification also includes a reinforcing portion 3 b but does not include a peripheral portion 3 a. However, the reinforcing portion 3 b of this modification has the same planar shape as the reinforcing portion 3 b of the fifth modification.

[0143] In this way, the lower membrane 3 can include reinforcing portions 3b of various shapes, regardless of whether or not it includes the peripheral portion 3a.

[0144] (6) Tenth to Thirteenth Modifications FIG. 28 is a cross-sectional view showing the structures of semiconductor devices according to tenth and eleventh modifications of the first embodiment.

[0145] 28A shows a semiconductor device according to a tenth modification. The semiconductor device according to this modification has a structure similar to that of the semiconductor device shown in FIG. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is trapezoidal rather than triangular. This is similar to the outer peripheral portion 3a shown in FIG.

[0146] 28A shows the top surface S1 of the upper chip 2 and the top surface S2 of the outer circumferential portion 3 a. The side X4 corresponds to part of the top surface S2 (see FIG. 3). In this modification, the top surface S2 of the outer circumferential portion 3 a is located at a lower position than the top surface S1 of the upper chip 2.

[0147] 28B shows a semiconductor device according to an eleventh modification. The semiconductor device according to this modification has a structure similar to that of the semiconductor device shown in Fig. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is a shape other than a triangle or a trapezoid.

[0148] 28B also shows the upper surface S1 of the upper chip 2 and the upper surface S2 of the outer circumferential portion 3a. In this modification, the upper surface S2 of the outer circumferential portion 3a is provided at a position higher than the upper surface S1 of the upper chip 2.

[0149] In this way, the upper surface S2 of the outer peripheral portion 3a may be provided at a position lower than the upper surface S1 of the upper chip 2, or may be provided at a position higher than the upper surface S1 of the upper chip 2. Furthermore, the upper surface S2 of the outer peripheral portion 3a may be provided at the same height as the upper surface S1 of the upper chip 2.

[0150] FIG. 29 is a cross-sectional view showing the structures of semiconductor devices according to twelfth and thirteenth modifications of the first embodiment.

[0151] 29A shows a semiconductor device according to a twelfth modification. The semiconductor device according to this modification has a structure similar to that of the semiconductor device according to the eleventh modification. However, the peripheral portion 3 a according to this modification includes a portion provided on the upper surface S1 of the upper chip 2. Therefore, the upper surface S2 of the peripheral portion 3 a according to this modification is also provided at a position higher than the upper surface S1 of the upper chip 2.

[0152] 29B shows a semiconductor device according to a thirteenth modification. The semiconductor device according to this modification has a structure similar to that of the semiconductor device shown in FIG. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is rectangular rather than triangular, and the cross-sectional shape of the reinforcing portion 3b is rectangular rather than trapezoidal. In this way, the cross-sectional shapes of the outer peripheral portion 3a and the reinforcing portion 3b can be various shapes.

[0153] The lower film 3 shown in FIGS. 28A to 29B may be replaced with any one of the lower films 41, 42, and 43.

[0154] As described above, the semiconductor device of this embodiment includes the lower chip 1, the upper chip 2, the lower film 3, and the upper film 4, and the lower film 3 includes the outer periphery portion 3a provided on the side of the upper chip 1 and the reinforcing portion 3b provided at a distance from the upper chip 1. Therefore, according to this embodiment, the outer periphery portion 3a can suppress the occurrence of a seam S in the upper film 4, and the reinforcing portion 3b can reinforce the mechanical strength of the semiconductor device. This makes it possible to suitably form the upper film 4 that covers the upper chip 2, etc.

[0155] Second Embodiment FIG. 30 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0156] The semiconductor device of this embodiment has a structure similar to that of the semiconductor device of the first embodiment shown in Fig. 3. However, the upper chip 2 of this embodiment includes a substrate 21 and a bonding film 24 instead of the substrate 21, the interlayer insulating film 22, and the multilayer wiring structure 23. Note that the multilayer wiring structure 13 is not shown in Fig. 30.

[0157] The upper chip 2 of this embodiment is a bare chip that does not include any circuitry. The substrate 21 is, for example, a Si substrate, but may be a semiconductor substrate other than a Si substrate. For example, the substrate 21 may be a compound semiconductor substrate such as an InGaAs substrate or a GaN substrate (In represents indium, Ga represents gallium, As represents arsenic, and N represents nitrogen). The bonding film 24 is formed on the lower surface of the substrate 21 and is bonded to the upper surface of the lower chip 1. The bonding film 24 may be, for example, a SiO ２The film is a SiN film.

[0158] According to this embodiment, when an upper chip 2 having a structure different from that of the upper chip 2 of the first embodiment is adopted, it is possible to suppress the occurrence of seams S in the upper film 4 by the peripheral portion 3a, and to reinforce the mechanical strength of the semiconductor device by the reinforcing portion 3b.

[0159] Third Embodiment FIG. 31 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0160] The semiconductor device of this embodiment functions as, for example, a SWIR (short wavelength infrared) image sensor. Fig. 31 shows an upper chip 2, a lower film 3, and an upper film 4 provided on a support substrate 6. The upper chip 2 of this embodiment is, for example, an InGaAs chip including an InGaAs substrate.

[0161] The support substrate 6 includes a substrate 61, an interlayer insulating film 62 provided on the substrate 61, and a multilayer wiring structure 63 provided in the interlayer insulating film 62. The multilayer wiring structure 63 is electrically connected to the upper chip 2 via contact plugs 51 in the upper film 4, etc.

[0162] According to this embodiment, the semiconductor device of the first or second embodiment can be suitably applied to a SWIR image sensor.

[0163] Fourth Embodiment FIG. 32 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment.

[0164] The semiconductor device of this embodiment functions as, for example, a micro LED (light emitting diode) display. Fig. 32 shows an upper chip 2 and a lower film 3 provided on a support substrate 7. The upper chip 2 of this embodiment is, for example, a GaN chip including a GaN substrate.

[0165] The support substrate 7 includes a substrate 71, an interlayer insulating film 72 provided on the substrate 71, and a multilayer wiring structure 73 provided in the interlayer insulating film 72. The multilayer wiring structure 73 is electrically connected to the upper chip 2 via the wiring layer 52 between the support substrate 7 and the upper chip 2, etc.

[0166] According to this embodiment, the semiconductor device of the first or second embodiment can be suitably applied to a micro LED display.

[0167] Fifth Embodiment FIG. 33 is a block diagram showing the configuration of a semiconductor device according to a fifth embodiment.

[0168] The semiconductor device of this embodiment corresponds to an example of the semiconductor device of any one of the first to fourth embodiments. The semiconductor device of this embodiment is a photodetector such as a solid-state imaging device, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS). The semiconductor device of this embodiment includes a pixel array 82 including a plurality of pixels 81, a control circuit 83, a vertical drive circuit 84, a plurality of column signal processing circuits 85, a horizontal drive circuit 86, an output circuit 87, a plurality of vertical signal lines (VSL) 88, and a horizontal signal line (HSL) 89.

[0169] Each pixel 81 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. The pixel transistor may be, for example, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, etc. These pixel transistors may be shared by several pixels 81.

[0170] The pixel array 82 includes a plurality of pixels 81 arranged in a two-dimensional array. The pixel array 82 also includes an effective pixel region that receives light, performs photoelectric conversion, and outputs signal charges generated by the photoelectric conversion, and a black reference pixel region that outputs optical black, which serves as a reference for the black level. In general, the black reference pixel region is arranged on the periphery of the effective pixel region.

[0171] The control circuit 83 generates various signals that serve as references for the operation of the vertical drive circuit 84, the column signal processing circuit 85, the horizontal drive circuit 86, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 83 are, for example, clock signals and control signals, and are input to the vertical drive circuit 84, the column signal processing circuit 85, the horizontal drive circuit 86, etc.

[0172] The vertical drive circuit 84 includes, for example, a shift register, and vertically scans each pixel 81 in the pixel array 82 row by row. The vertical drive circuit 84 further supplies a pixel signal based on the signal charge generated by each pixel 81 to a column signal processing circuit 85 through a vertical signal line 88.

[0173] The column signal processing circuit 85 is arranged, for example, for each column of pixels 81 in the pixel array 82, and performs signal processing for each column of signals output from one row of pixels 81 based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification.

[0174] The horizontal drive circuit 86 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 85 to a horizontal signal line 89 .

[0175] The output circuit 87 processes the signals supplied from each column signal processing circuit 85 through a horizontal signal line 89, and outputs the processed signals.

[0176] According to this embodiment, it is possible to realize a suitable photodetector (for example, a solid-state imaging device) by applying the configuration of this embodiment to the semiconductor device of any of the first to fourth embodiments. This embodiment can also be applied to the semiconductor device of any of the sixth to ninth embodiments described later.

[0177] Sixth Embodiment FIG. 39 is a cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment.

[0178] Figure 39 shows a vertical cross section of the semiconductor device of this embodiment. However, Figure 39 shows the semiconductor device of this embodiment before the lower wafer 1 is divided into multiple lower chips 1 by dicing. Therefore, Figure 39 shows multiple upper chips 2 bonded to the lower wafer 1. Figure 39 shows, with dashed lines, an area that will become one semiconductor device (chip Ch) including one lower chip 1 and one upper chip 2. Figure 39 shows a support substrate 5, similar to Figures 11A and 11B.

[0179] The structure shown in FIG. 39 will be described below, focusing mainly on the structure of one chip Ch shown in FIG.

[0180] The semiconductor device (chip Ch) of this embodiment has the same components as the semiconductor device of the first embodiment. However, in the semiconductor device of this embodiment, the lower film 3 includes a plurality of side portions 3c provided on the sides of the upper chip 2 within the upper film 4, and a plurality of upper portions 3d provided above the upper chip 2 within the upper film 4. Each of the side portions 3c is an example of the third portion of the present disclosure. Each of the upper portions 3d is an example of the fourth portion of the present disclosure.

[0181] In this embodiment, each side portion 3c of the chip Ch has an annular shape surrounding the upper chip 2 in a plan view. Figure 39 shows three side portions 3c surrounding the upper chip 2 in the chip Ch, and also shows vertical cross sections of two locations in each side portion 3c. In the chip Ch shown in Figure 39, multiple side portions 3c are provided at different heights. Specifically, the lower film 3 in this embodiment is formed so that the centers of gravity of these side portions 3c have different Z coordinates. In this embodiment, these side portions 3c are separated from each other.

[0182] In this embodiment, each upper portion 3d of the chip Ch has a plate-like shape in a plan view that partially covers the top surface of the upper chip 2. Figure 39 shows three upper portions 3d that partially cover the top surface of the upper chip 2 in the chip Ch, and also shows a vertical cross section of one location in each upper portion 3d. In the chip Ch shown in Figure 39, the multiple upper portions 3d are provided at different heights. Specifically, the lower film 3 in this embodiment is formed so that the centers of gravity of these upper portions 3d have different Z coordinates. In this embodiment, these upper portions 3d are separated from each other and also from the multiple side portions 3c.

[0183] The lower film 3 is made of, for example, a material with a low Young's modulus or a material with low moisture permeability. An example of a material with a low Young's modulus is SiO. ２ (e.g., porous SiO ２), SOG, polymers (e.g., PEN, PET, or PEG), etc. Other examples of low Young's modulus materials are organic materials such as hybrid polymers, silicones, siloxanes, and polyimides. Examples of low moisture permeability materials are SiN, SiCN, and SiON (silicon oxynitride). The lower film 3 may be formed of multiple types of materials, and each material may be formed of a material with a low Young's modulus or a material with low moisture permeability.

[0184] 40A to 40C are cross-sectional views showing a method for manufacturing the semiconductor device of the sixth embodiment.

[0185] 40A to 40D show the flow of forming the lower film 3 and the upper film 4. In this embodiment, the lower film 3 and the upper film 4 are formed by alternately forming multiple layers forming the lower film 3 and multiple layers forming the upper film 4. FIGS. 40A to 40D show layers 3-1 and 3-2 as examples of the multiple layers forming the lower film 3, and layers 4-1 and 4-2 as examples of the multiple layers forming the upper film 4. Each layer (e.g., layer 4-1, 4-2) forming the upper film 4 is an example of the first layer of the present disclosure. Meanwhile, each layer (e.g., layer 3-1, 3-2) forming the lower film 3 is formed to include one side portion 3c and one upper portion 3d (not shown). In this embodiment, the upper chip 2 is mounted on the lower wafer 1, and the upper film 4 including the lower film 3 is formed on the lower wafer 1 and the upper chip 2, and the lower wafer 1 is divided into multiple lower chips 1.

[0186] When forming the lower film 3 and the upper film 4, first, a layer 4-1 is formed on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 40A). At this time, a depression is formed in the surface of the layer 4-1 near the boundary between the top surface of the lower wafer 1 and the side surface of the upper chip 2. If this depression is left unattended, there is a risk that the depression will grow into a seam. Therefore, in this embodiment, a layer 3-1 is formed on the surface of the layer 4-1 so that the side portion 3c is embedded in the depression (FIG. 40B). This makes it possible to suppress the growth of the seam.

[0187] Next, layer 4-2 is formed on the surfaces of layers 4-1 and 3-1 (FIG. 40C). At this time, a depression is formed on the surface of layer 4-2 near the boundary between the top surface of lower wafer 1 and the side surface of upper chip 2. If this depression is left unattended, there is a risk that the depression will grow into a seam. Therefore, in this embodiment, layer 3-2 is formed on the surface of layer 4-2 so that side portion 3c is embedded in the depression (FIG. 40D). This makes it possible to suppress the growth of the seam.

[0188] The lower film 3 and the upper film 4 in this embodiment are formed by alternately forming a plurality of layers forming the lower film 3 and a plurality of layers forming the upper film 4. This makes it possible to form the structure shown in FIG.

[0189] FIG. 41 is a plan view showing a method for manufacturing the semiconductor device of the sixth embodiment.

[0190] 41A shows the shape of layer 3-1 in a plan view. Near each upper chip 2, layer 3-1 includes annular side portions 3c that surround the upper chip 2 and a plate-like upper portion 3d that partially covers the top surface of the upper chip 2.

[0191] 41B shows the shape of layer 3-2 in a plan view. Near each upper chip 2, layer 3-2 includes annular side portions 3c that surround the upper chip 2 and a plate-like upper portion 3d that partially covers the top surface of the upper chip 2. In this embodiment, the sizes of side portions 3c and upper portions 3d in layer 3-2 are larger than the sizes of side portions 3c and upper portions 3d in layer 3-1, respectively.

[0192] FIG. 42 is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the sixth embodiment.

[0193] The semiconductor device of this modification (FIG. 42) has the same components as the semiconductor device of the sixth embodiment (FIG. 39). However, in FIG. 42, each side portion 3c around one upper chip 2 extends to contact one side portion 3c around another upper chip 2. As a result, after dicing of the lower wafer 1, each side portion 3c in the chip Ch has a shape that extends to the side surface of the chip Ch located on the dashed line.

[0194] According to this modification, similarly to the sixth embodiment, it is possible to suppress the growth of seams in the upper film 4. Furthermore, according to this modification, it is possible to increase the area of ​​each side portion 3 c in a plan view.

[0195] FIG. 43 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the sixth embodiment.

[0196] The semiconductor device of this modification ( FIG. 43 ) has the same components as the semiconductor device of the sixth embodiment ( FIG. 39 ). However, the lower film 3 of this modification includes multiple composite portions 3 e provided within the upper film 4 on the sides and above multiple upper chips 2. In the chip Ch of this modification, each composite portion 3 e has a shape including one side portion 3 c and one upper portion 3 d that extend to contact each other. As a result, after dicing the lower wafer 1, each composite portion 3 c in the chip Ch has a shape that extends to the side of the chip Ch that is located on the dashed line. Each composite portion 3 e is an example of the third and fourth portions of the present disclosure.

[0197] According to this modification, similarly to the sixth embodiment, it is possible to suppress the growth of seams in the upper film 4. Furthermore, according to this modification, it is possible to further increase the area of ​​each side portion 3 c in a plan view.

[0198] FIG. 44 is a cross-sectional view showing the structure of a semiconductor device according to a first modification and a second modification of the sixth embodiment.

[0199] Figure 44A shows a layer 3-1 in the lower film 3 of the first modified example shown in Figure 42. The layer 3-1 of this modified example includes a side portion 3c and an upper portion 3d that are separated from each other.

[0200] Figure 44B shows a layer 3-1 in the lower membrane 3 of the second modified example shown in Figure 43. The layer 3-1 of this modified example includes a composite portion 3e shaped to include a side portion 3c and an upper portion 3d that extend in contact with each other.

[0201] FIG. 45 is a cross-sectional view showing the structures of semiconductor devices according to third to sixth modifications of the sixth embodiment.

[0202] 45A shows a semiconductor device according to a third modification. The lower film 3 and upper film 4 of this modification are formed by alternately forming layers 3-1 to 3-5 that form the lower film 3 and layers 4-1 to 4-5 that form the upper film 4. The layers 3-1 to 3-5 of this modification are formed of, for example, a material with high fluidity. An example of a material with high fluidity is SiO ２ , FCVD, polymer, etc. According to this modification, it is possible to form the lower film 3 and the upper film 4 with high reliability.

[0203] 45B shows a semiconductor device according to a fourth modification. The lower film 3 and upper film 4 of this modification are formed by alternately forming layers 3-1 to 3-5 that form the lower film 3 and layers 4-1 to 4-5 that form the upper film 4. The layers 3-1 to 3-5 of this modification are formed, for example, from a material that has good coverage. Examples of materials that have good coverage include SiN, SiCN, and SiON. This modification makes it possible to form a lower film 3 and an upper film 4 that can suppress moisture penetration.

[0204] 45C shows a semiconductor device according to a fifth modification. The lower film 3 and upper film 4 of this modification are formed by alternately forming layers 3-1 to 3-5 that form the lower film 3 and layers 4-1 to 4-5 that form the upper film 4. Each of the layers 3-1 to 3-5 of this modification includes layers L1 and L2 that are stacked in sequence. One of the layers L1 and L2 is formed, for example, from a material with high fluidity. The other of the layers L1 and L2 is formed, for example, from a material with good coverage. This modification makes it possible to form a lower film 3 and upper film 4 that are highly reliable and capable of suppressing moisture penetration.

[0205] 45D shows a semiconductor device according to a sixth modification. The lower film 3 and upper film 4 of this modification are formed by alternately depositing layers 3-1 to 3-5 that form the lower film 3 and layers 4-1 to 4-5 that form the upper film 4. Each of the layers 3-1 to 3-5 of this modification is formed to have the shape of a sidewall layer. These layers 3-1 to 3-5 can be formed, for example, by layer deposition and etch-back. This modification makes it possible to form a lower film 3 and an upper film 4 that are capable of suppressing moisture penetration.

[0206] FIG. 46 is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the sixth embodiment.

[0207] The semiconductor device of this modification (FIG. 46) has the same components as the semiconductor device of the second modification (FIG. 43). However, the lower film 3 and upper film 4 of this modification are formed so that small voids V remain under one or more composite portions 3e near the boundary between the top surface of the lower wafer 1 and the side surface of the upper chip 2. Each void V originates from the depression or seam described above. The lower film 3 of this modification is formed, for example, from a material with low moisture permeability.

[0208] The lower film 3 and the upper film 4 of this modified example may be formed to include such voids V. According to this modified example, such voids V make it possible to form the lower film 3 and the upper film 4 that are highly reliable and capable of suppressing the intrusion of moisture.

[0209] FIG. 47 is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the sixth embodiment.

[0210] The semiconductor device of this modification (FIG. 47) has the same components as the semiconductor device of the sixth embodiment (FIG. 39). However, the lower film 3 of this modification includes a plurality of side portions 3c having the shape of a sidewall layer, similar to the lower film 3 of the sixth modification. According to this modification, it is possible to form a lower film 3 and an upper film 4 that can suppress the penetration of moisture, similar to the sixth modification.

[0211] FIG. 48 is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the sixth embodiment.

[0212] The semiconductor device of this modification (FIG. 46) includes the same components as the semiconductor device of the second modification (FIG. 43). However, the lowest composite portion 3e of this modification includes layers L1 and L2 stacked in this order, similar to the lower film 3 of the fifth modification. According to this modification, similar to the fifth modification, it is possible to form a lower film 3 and an upper film 4 that are highly reliable and capable of suppressing moisture penetration.

[0213] As described above, the lower film 3 of this embodiment includes a plurality of side portions 3c provided on the sides of each upper chip 2 within the upper film 4. Therefore, according to this embodiment, these side portions 3c can suppress the growth of seams within the upper film 4.

[0214] Seventh Embodiment FIG. 49 is a cross-sectional view showing the structure of a semiconductor device according to a seventh embodiment.

[0215] Figure 49 shows a vertical cross section of the semiconductor device of this embodiment. However, like Figure 39, Figure 49 shows the semiconductor device of this embodiment before the lower wafer 1 is divided into multiple lower chips 1 by dicing. Therefore, Figure 49 shows multiple upper chips 2 bonded to the lower wafer 1. Figure 49 shows, with dashed lines, an area that will become one semiconductor device (chip Ch) including one lower chip 1 and one upper chip 2. Like Figure 39, Figure 49 shows a support substrate 5.

[0216] The structure shown in FIG. 49 will be described below, focusing mainly on the structure of one chip Ch shown in FIG.

[0217] The semiconductor device of this embodiment (FIG. 49) includes a protective film 91 and a protective film 92 in addition to the components of the semiconductor device of the sixth embodiment (FIG. 39).

[0218] The protective film 91 is formed on the surfaces of the lower wafer 1 and the plurality of upper chips 2. As a result, the lower film 3 of this embodiment is formed on the lower wafer 1 via the protective film 91, and the upper film 4 of this embodiment is formed on the lower wafer 1 and the plurality of upper chips 2 via the protective film 91 and the lower film 3. The protective film 91 is, for example, a SiN film.

[0219] The protective film 92 is formed on the upper film 4. In this embodiment, the protective film 92 is a part of the chip Ch. The protective film 92 is, for example, a SiN film.

[0220] Furthermore, the lower film 3 of this embodiment includes side portions 3f provided on the sides of the multiple upper chips 2 via a protective film 91. In a plan view, the side portions 3f of this embodiment are embedded between the upper chips 2 and have a mesh-like shape that spreads two-dimensionally between the upper chips 2. The side portions 3f of this embodiment are also provided on the side surfaces of each upper chip 2 adjacent to the edge of the lower wafer 1 via the protective film 91. As shown in FIG. 49, the side portions 3f of this embodiment are provided on the sides of the multiple upper chips 2 and above the lower wafer 1 via the protective film 91. FIG. 49 shows vertical cross sections of three portions of the side portions 3f. The side portions 3f are an example of a fifth portion of the present disclosure.

[0221] When the lower wafer 1 is divided into multiple lower chips 1 by dicing, the side portion 3f in each chip Ch has an inner side surface facing the side surface of the upper chip 2 and an outer side surface located between the side surface of the lower chip 1 and the side surface of the upper chip 2. The outer side surface of the side portion 3f is the side surface located on the dashed line representing the chip Ch in FIG. 49. In the chip Ch after dicing, the side portion 3f extends between the inner side surface and the outer side surface and is continuous between the inner side surface and the outer side surface. The inner side surface is an example of a first side surface of the present disclosure. The outer side surface is an example of a second side surface of the present disclosure. The lower film 3 in this embodiment is formed, for example, by coating.

[0222] In this embodiment, after the lower film 3 (side portion 3 f) is formed on the side surface of the upper chip 2, the upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 3. Therefore, according to this embodiment, it is possible to suppress the occurrence of seams in the upper film 4 by the lower film 3. Furthermore, according to this embodiment, by embedding the lower film 3 between the upper chips 2, it is possible to easily planarize (CMP) the upper film 2 and improve the planarity of the upper film 2.

[0223] FIG. 50 is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the seventh embodiment.

[0224] The semiconductor device of this embodiment (FIG. 50) includes a warpage adjustment film 93 in addition to the components of the semiconductor device of the seventh embodiment (FIG. 49).

[0225] The warpage adjustment film 93 is formed between the protective film 92 and the support substrate 5. The warpage adjustment film 93 is formed to suppress warpage of the support substrate 5. According to this modification, the warpage adjustment film 93 makes it possible to suppress warpage of the support substrate 5.

[0226] FIG. 51 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the seventh embodiment.

[0227] The semiconductor device of this modification (FIG. 51) has the same components as the semiconductor device of the seventh embodiment (FIG. 49). However, the side portions 3f of this modification further include portions provided on the upper surface of each upper chip 2. The side portions 3f of this modification are provided on the upper surface of each upper chip 2 with a protective film 91 interposed therebetween.

[0228] In this way, the side portions 3 f may be provided not only on the side surfaces of each upper chip 2 but also on the side surfaces of each upper chip 2 .

[0229] FIG. 52 is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the seventh embodiment.

[0230] The semiconductor device of this modification (FIG. 52) has the same components as the semiconductor device of the seventh embodiment (FIG. 49). However, the semiconductor device of this modification does not have the protective film 91. This makes it possible to omit the step of forming the protective film 91.

[0231] In this way, the side portions 3f may be formed directly on the side surfaces of the respective upper chips 2, or may be formed on the side surfaces of the respective upper chips 2 via another film.

[0232] FIG. 53 is a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the seventh embodiment.

[0233] The semiconductor device of this modification (FIG. 53) has the same components as the semiconductor device of the seventh embodiment (FIG. 49). However, the height of the upper surface of each of the multiple upper chips 2 of this modification is different for each upper chip 2. Furthermore, the height of the upper end of each side portion 3f of this modification is different for each location of the side portion 3f. FIG. 53 shows vertical cross sections of three locations of the side portion 3f, and the height of the upper end of the left portion is lower than the height of the upper end of the right portion and the height of the upper end of the central portion.

[0234] According to this modification, it is possible to mount various types of upper chips 2 on the lower wafer 1.

[0235] FIG. 54 is a cross-sectional view showing the structure of a semiconductor device according to a fifth modification of the seventh embodiment.

[0236] The semiconductor device of this modification (FIG. 54) has a structure similar to that of the semiconductor device of the second modification (FIG. 51). However, the upper chip 2 in the chip Ch of this modification has a recess K formed in the side surface of the interlayer insulating film 22. The side portion 3f of this modification further includes a portion embedded in this recess K.

[0237] In this modification, the outer periphery of the upper chip 2 floats relative to the lower wafer 1 due to the recess K. According to this modification, it is possible to address this floating problem by using the side portion 3f.

[0238] FIG. 55 is a cross-sectional view showing the structure of a semiconductor device according to a sixth modification of the seventh embodiment.

[0239] The semiconductor device of this modification (FIG. 55) has a structure similar to that of the semiconductor device of the second modification (FIG. 51). However, the lower film 3 of this modification includes a dummy portion formed on the lower wafer 1 away from any side surface of the upper chip 2. The dummy portion may be formed continuously with the side portion 3f, or may be separated from the side portion 3f. In other words, the dummy portion may be part of the side portion 3f, or may not be part of the side portion 3f.

[0240] According to this modification, the dummy portion of the lower film 3 can be disposed, for example, near the edge of the lower wafer 1 .

[0241] FIG. 56 is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the seventh embodiment.

[0242] The semiconductor device of this modification (FIG. 56) has the same components as the semiconductor device of the seventh embodiment (FIG. 49). However, the lower wafer 1 of this modification has a recess 12a provided in the upper surface of the interlayer insulating film 12. The recess 12a is formed in the interlayer insulating film 12 by processing the interlayer insulating film 12 by, for example, dry etching. Furthermore, the side portion 3f of this modification further includes a portion formed in the recess 12a. In FIG. 56, a portion of the lower film 3 and a portion of the upper film 4 are formed in the recess 12a.

[0243] In this modification, when the lower film 3 is formed by coating, the coating liquid for the lower film 3 flows over the upper surface of the lower wafer 1. According to this modification, the position of the recess 12a can prevent the coating liquid from flowing more than necessary over the upper surface of the lower wafer 1. This is because the recess 12a functions like a dam that stores the coating liquid. Therefore, in Figure 56, a portion of the lower film 3 (side portion 3f) is formed within the recess 12a. It is desirable to provide the recess 12a near the position where it is desired to stop the flow of the coating liquid.

[0244] FIG. 57 is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the seventh embodiment.

[0245] The semiconductor device of this modification (FIG. 57) has the same components as the semiconductor device of the seventh modification (FIG. 56). However, the lower wafer 1 of this modification has a plurality of recesses 12a provided on the upper surface of the interlayer insulating film 12. Each recess 12a is formed in the interlayer insulating film 12 by removing one metal pad 13c by, for example, wet etching. Furthermore, the side portion 3f of this modification further includes a portion formed in these recesses 12a. In FIG. 57, a portion of the lower film 3 or a portion of the upper film 4 is formed in each recess 12a.

[0246] According to this modification, similarly to the seventh modification, it is possible to prevent the coating liquid from flowing more than necessary at the position of each recess 12a on the upper surface of the lower wafer 1. Note that although the semiconductor device of this modification does not include the protective film 91, the protective film 91 may be included.

[0247] FIG. 58 is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the seventh embodiment.

[0248] The semiconductor device of this modification (FIG. 56) includes the same components as the semiconductor device of the seventh embodiment (FIG. 49). However, the semiconductor device of this modification further includes an intermediate wafer 1' disposed between the lower wafer 1 and multiple upper chips 2. FIG. 58 shows the semiconductor device of this modification before the lower wafer 1 and the intermediate wafer 1' are divided into multiple lower chips 1 and multiple intermediate chips 1' by dicing. Therefore, FIG. 58 shows multiple upper chips 2 bonded to the lower wafer 1 via the intermediate chip 1'. FIG. 58 shows, with dashed lines, an area that will become one semiconductor device (chip Ch) including one lower chip 1, one intermediate chip 1', and one upper chip 2. Like FIG. 49, FIG. 58 also shows a support substrate 5.

[0249] As shown in Figure 58, the intermediate wafer 1' includes a substrate 11', an interlayer insulating film 12' and a multilayer wiring structure 13' on the underside of the substrate 11', an interlayer insulating film 12' and a multilayer wiring structure 13' on the upper side of the substrate 11', and a plurality of through plugs 14'. The multilayer wiring structure 13' on the underside of the substrate 11' is electrically connected to the multilayer wiring structure 13 in the lower wafer 1. The multilayer wiring structure 13' on the upper side of the substrate 11' is electrically connected to the multilayer wiring structure 23 in each upper chip 2. Each through plug 14' electrically connects the multilayer wiring structure 13' on the underside of the substrate 11' to the multilayer wiring structure 13' on the upper side of the substrate 11'.

[0250] Each lower chip 1 in this modification is, for example, a CIS chip. According to this modification, it is possible to realize a solid-state imaging device including a lower chip 1, a middle chip 1', and an upper chip 2.

[0251] 59 to 67 are cross-sectional views showing a method for manufacturing the semiconductor device of the seventh embodiment.

[0252] First, a lower wafer 1 and a plurality of upper chips 2 are bonded together (FIG. 59). The lower wafer 1 is fabricated by forming an interlayer insulating film 12 and a multilayer wiring structure 13 on a substrate 11. The plurality of upper chips 2 are fabricated by fabricating an upper wafer 2 by forming an interlayer insulating film 22 and a multilayer wiring structure 23 on a substrate 21, and then dividing the upper wafer 2 into a plurality of upper chips 2 by dicing.

[0253] Next, the substrate 21 in each upper chip 2 is thinned (FIG. 60). The substrate 21 is thinned using, for example, a grinder.

[0254] Next, a protective film 91 is formed on the surfaces of the lower wafer 1 and the upper chips 2 (FIG. 61). The protective film 91 is formed by, for example, CVD.

[0255] Next, a lower film 3 including side portions 3f is formed on the lower wafer 1 (FIG. 62). The side portions 3f are formed on the sides of each upper chip 2 and above the lower wafer 1 via a protective film 91. In the step shown in FIG. 62, the side portions 3f having the shape shown in FIG. 49 are formed. The lower film 3 is formed by, for example, coating.

[0256] Next, an upper film 4 is formed on the lower wafer 1, the upper chips 2, and the lower film 3 (FIG. 63). The upper film 4 is formed by, for example, CVD.

[0257] Next, the surface of the upper film 4 is planarized (FIG. 64). This planarization is performed by, for example, CMP. This planarization may be performed so that the lower film 3 is exposed from the upper film 4.

[0258] Next, a warpage adjustment film 94 and a protective film 92 are formed in this order on the upper film 4 ( FIG. 65 ). The warpage adjustment film 94 is formed, for example, to suppress warpage of the substrate 11. The protective film 92 of this embodiment also functions as a bonding film for bonding to the support substrate 5.

[0259] Next, the surface of the protective film 92 is planarized (FIG. 66). This makes it easier to bond the support substrate 5 to the protective film 92. The planarization is performed by, for example, CMP.

[0260] Next, the support substrate 5 is bonded to the protective film 92 (FIG. 67). This results in the structure shown in FIG. 49. However, the structure shown in FIG. 67 includes a warpage adjustment film 94 in addition to the components shown in FIG.

[0261] The lower wafer 1 is then divided into a plurality of lower chips 1 by dicing. As a result, a plurality of semiconductor devices (chips) according to this embodiment are manufactured. Each semiconductor device according to this embodiment is manufactured to include one lower chip 1 and one upper chip 2, etc.

[0262] 68 to 70 are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh modification of the seventh embodiment.

[0263] 59 to 61 are performed, a resist film 95 is formed on the lower wafer 1 and the upper chips 2 via a protective film 91 (FIG. 68). Next, an opening 95a is formed in the resist film 95 (FIG. 68). As a result, the upper surface of the protective film 91 is exposed in the opening 95a.

[0264] Next, the protective film 91 and the interlayer insulating film 12 below the opening 95a are processed by dry etching (FIG. 69). As a result, a recess 12a is formed in the interlayer insulating film 12. In this modification, the recess 12a is formed in the protective film 91 and the interlayer insulating film 12. Thereafter, the resist film 95 is removed.

[0265] Next, a lower film 3 including side portions 3f is formed on the lower wafer 1 (Figure 70). The process shown in Figure 70 is performed in the same manner as the process shown in Figure 62. In this modification, when the lower film 3 is formed by coating, the coating liquid for the lower film 3 flows over the upper surface of the lower wafer 1. This modification makes it possible to prevent the coating liquid from flowing more than necessary over the upper surface of the lower wafer 1 at the position of the recess 12a. Therefore, in Figure 70, a portion of the lower film 3 (side portions 3f) is formed within the recess 12a.

[0266] 63 to 67 are then carried out, thus completing the manufacture of the semiconductor device of this modified example.

[0267] 71 and 72 are cross-sectional views showing a method for manufacturing a semiconductor device according to an eighth modification of the seventh embodiment.

[0268] 59 and 60 are performed, the metal pads 13c are removed by wet etching (FIG. 71), resulting in the formation of a plurality of recesses 12a in the interlayer insulating film 12.

[0269] Next, a lower film 3 including side portions 3f is formed on the lower wafer 1 (Figure 72). The process shown in Figure 72 is performed in the same manner as the process shown in Figure 62. In this modification, when the lower film 3 is formed by coating, the coating liquid for the lower film 3 flows over the upper surface of the lower wafer 1. This modification makes it possible to prevent the coating liquid from flowing more than necessary over the upper surface of the lower wafer 1 at the position of each recess 12a. Therefore, in Figure 72, a portion of the lower film 3 (side portions 3f) is formed in one or more recesses 12a.

[0270] 63 to 67 are then carried out, thus completing the manufacture of the semiconductor device of this modified example.

[0271] As described above, the lower film 3 of this embodiment includes the side portions 3 f provided on the sides of each upper chip 2 below the upper film 4. Therefore, according to this embodiment, the side portions 3 f can suppress the occurrence of seams in the upper film 4.

[0272] Eighth Embodiment FIG. 73 is a cross-sectional view showing the structure of a semiconductor device according to an eighth embodiment.

[0273] The semiconductor device of this embodiment (FIG. 73) has the same components as the semiconductor device of the first embodiment (FIG. 1). Thus, the semiconductor device of this embodiment has a lower chip 1 obtained from a lower wafer 1, an upper chip 2 obtained from an upper wafer 2, an upper film 4, etc. However, like the semiconductor device of the third modified example of the first embodiment shown in FIGS. 22 and 23, the semiconductor device of this embodiment has a lower film 43 instead of the lower film 3. The lower film 43 of this embodiment is, for example, an inorganic film such as an SOG film, and is formed by coating.

[0274] The lower film 43 of this embodiment includes an outer periphery portion 43a arranged along the outer periphery of the upper chip 2. The outer periphery portion 43a of this embodiment is formed not only on the side surface of the upper chip 2 but also on the top surface of the upper chip 2. In this embodiment, the entire top surface and the entire side surface of the upper chip 2 are covered by the outer periphery portion 43a. The outer periphery portion 43a of this embodiment is an example of the sixth portion of the present disclosure.

[0275] In this embodiment, after the lower film 43 (peripheral portion 43 a) is formed on the side and top surfaces of the upper chip 2, the upper film 4 is formed on the lower wafer 1 and the upper chip 2 via the lower film 43. Therefore, according to this embodiment, the lower film 43 can suppress the occurrence of seams in the upper film 4.

[0276] 74 to 76 are cross-sectional views showing a method for manufacturing the semiconductor device of the eighth embodiment. The semiconductor device of this embodiment is manufactured by a method similar to the method for manufacturing the semiconductor device of the third modified example of the first embodiment shown in FIGS.

[0277] 6A and 6B are performed, a lower film 43 is formed by coating on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 74). As a result, a peripheral portion 43a of the lower film 43 is formed on the upper surface of the lower wafer 1 and the side and upper surfaces of the upper chip 2. In this embodiment, the lower film 43 is formed on the entire upper surface and the entire side surfaces of the upper chip 2 by spin coating and reflow.

[0278] Next, an upper film 4 is formed on the lower wafer 1 and the upper chip 2 via a lower film 43 (FIG. 75). The upper film 4 is formed by, for example, CVD.

[0279] Next, the surface of the upper film 4 is planarized (FIG. 76). The planarization is performed by, for example, CMP.

[0280] The lower wafer 1 is then divided into a plurality of lower chips 1 by dicing. As a result, a plurality of semiconductor devices (chips) according to this embodiment are manufactured. Each semiconductor device according to this embodiment is manufactured to include one lower chip 1 and one upper chip 2, etc.

[0281] FIG. 77 is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the eighth embodiment.

[0282] The semiconductor device of this modification (FIG. 77) has the same components as the semiconductor device of the eighth embodiment (FIG. 73). However, the outer peripheral portion 43a of this modification is formed on the side surface of the upper chip 2, but not on the top surface of the upper chip 2.

[0283] Specifically, the uppermost end of the peripheral portion 43a in this modification is lower than the uppermost end of the multilayer wiring structure 23 and higher than the lowermost end of the multilayer wiring structure 23. In FIG. 77, the uppermost end of the peripheral portion 43a is located on the side of the peripheral portion 43a that faces the side of the lower chip 2. Also, in FIG. 77, the uppermost end of the multilayer wiring structure 23 is the upper surface of the wiring layer 23a in the multilayer wiring structure 23, and the lowermost end of the multilayer wiring structure 23 is the lower surface of the metal pad 23c in the multilayer wiring structure 23. Therefore, the uppermost end of the peripheral portion 43a in this modification is lower than the upper surface of the wiring layer 23a and higher than the lower surface of the metal pad 23c. Also, the peripheral portion 43a in this modification is formed on the side surface of the interlayer insulating film 22 but not on the side surface of the substrate 21.

[0284] 77 , there is a risk of a seam S occurring near the top end of the outer circumferential portion 43 a in the upper film 4 of this modified example. According to this modified example, the top end of the outer circumferential portion 43 a is located higher than the interface between the lower chip 1 and the upper chip 2, which makes it possible to prevent the seam S from occurring at the interface between the lower chip 1 and the upper chip 2. This makes it possible to prevent the upper chip 2 from peeling off from the lower chip 1 due to the seam S.

[0285] FIG. 78 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the eighth embodiment.

[0286] The semiconductor device of this modification (FIG. 78) has the same components as the semiconductor device of the eighth embodiment (FIG. 73). However, the outer peripheral portion 43a of this modification is formed on the side surface of the upper chip 2, but not on the top surface of the upper chip 2.

[0287] Specifically, the uppermost end of the peripheral portion 43a in this modification is higher than the uppermost end of the multilayer wiring structure 23, and is also higher than the lower surface of the substrate 21, but lower than the upper surface of the substrate 21. In FIG. 78, the uppermost end of the peripheral portion 43a is located on the side surface of the peripheral portion 43a that faces the side surface of the lower chip 2. Also, in FIG. 78, the uppermost end of the multilayer wiring structure 23 is the upper surface of the wiring layer 23a in the multilayer wiring structure 23. Therefore, the uppermost end of the peripheral portion 43a in this modification is higher than the upper surface of the wiring layer 23a. Also, the peripheral portion 43a in this modification is formed on the entire side surface of the interlayer insulating film 22 and part of the side surface of the substrate 21.

[0288] 78 , in the upper film 4 of this modified example, there is a risk of a seam S occurring near the top end of the outer circumferential portion 43 a. According to this modified example, the top end of the outer circumferential portion 43 a is located higher than the interface between the lower chip 1 and the upper chip 2, which makes it possible to prevent the seam S from occurring at the interface between the lower chip 1 and the upper chip 2. This makes it possible to prevent the upper chip 2 from peeling off from the lower chip 1 due to the seam S.

[0289] Furthermore, since the top end of the peripheral portion 43a in this modification is located higher than the interface between the interlayer insulating film 22 and the substrate 21, it is possible to generate the seam S from the side surface of the substrate 21. Since the substrate 21 is hard, generating the seam S from the side surface of the substrate 21 makes it possible to prevent the upper chip 2 from being damaged by the seam S.

[0290] In this modification, the uppermost end of the peripheral portion 43 a may be higher than the uppermost end of the multilayer wiring structure 23 and lower than the lower surface of the substrate 21 .

[0291] 79 to 81 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the eighth embodiment.

[0292] 6A and 6B are performed, a lower film 43 is formed by coating on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 79). The process shown in FIG. 79 is performed in the same manner as the process shown in FIG. 74. However, the lower film 43 of this modified example is formed so that the shape of the outer peripheral portion 43a becomes the shape shown in FIG. 77. When manufacturing a semiconductor device of the second modified example instead of the semiconductor device of this modified example, the lower film 43 is formed so that the shape of the outer peripheral portion 43a becomes the shape shown in FIG.

[0293] Next, an upper film 4 is formed on the lower wafer 1 and the upper chip 2 via a lower film 43 (FIG. 80). The upper film 4 is formed by, for example, CVD. In FIG. 80, a seam S is formed near the top edge of the outer peripheral portion 43a. This modification makes it possible to prevent the seam S from occurring at the interface between the lower chip 1 and the upper chip 2.

[0294] Next, the surface of the upper film 4 is planarized (FIG. 81). The planarization is performed by, for example, CMP.

[0295] The lower wafer 1 is then diced into a plurality of lower chips 1. As a result, a plurality of semiconductor devices (chips) according to this modification are manufactured. Each semiconductor device according to this modification is manufactured to include one lower chip 1 and one upper chip 2, etc.

[0296] As described above, the lower film 43 of this embodiment includes the outer peripheral portion 43a provided on the side and top surface of the upper chip 2. Furthermore, the lower film 43 of each modification of this embodiment includes the outer peripheral portion 43a provided on the side surface of the upper chip 2. Therefore, according to this embodiment and each modification, it is possible to suppress the occurrence of seams in the upper film 4 and adjust the position at which seams occur in the upper film 4.

[0297] Ninth Embodiment FIG. 82 is a cross-sectional view showing the structure of a semiconductor device according to a ninth embodiment.

[0298] Figure 82 shows a vertical cross section of the semiconductor device of this embodiment. However, like Figures 39 and 49, Figure 82 shows the semiconductor device of this embodiment before the lower wafer 1 is divided into multiple lower chips 1 by dicing. Therefore, Figure 82 shows multiple upper chips 2 bonded to the lower wafer 1, and more specifically, shows two upper chips 2 of different sizes. In Figure 82, the region that becomes one semiconductor device (chip Ch) including one lower chip 1 and one upper chip 2 is indicated by a dashed line.

[0299] The chip Ch of this embodiment may include one lower chip 1 and two or more upper chips 2. For example, the chip Ch shown in Fig. 82 may include not only the upper chip 2 on the left side of Fig. 82 but also the upper chip 2 on the right side of Fig. 82. In this case, the component indicated by the reference numeral "1" in Fig. 82 may be the lower chip rather than the lower wafer.

[0300] The structure shown in FIG. 82 will be described below, focusing mainly on the structure of one chip Ch shown in FIG.

[0301] The semiconductor device of this embodiment (FIG. 82) has a structure similar to that of the semiconductor device of the sixth embodiment (FIG. 39) and the semiconductor device of the seventh embodiment (FIG. 49). However, the semiconductor device of this embodiment does not include the lower film 3, but includes an upper film 4 on the lower wafer 1 and the upper chip 2. Note that FIG. 82 omits illustration of the wiring layers 13a, 23a and via plugs 13b, 23b in the multilayer wiring structures 13, 23.

[0302] In the chip Ch of this embodiment, the surface of the interlayer insulating film 12 includes a curved surface R1 provided near the side surface of the upper chip 2, as shown in Fig. 82. In Fig. 82, the radius of curvature of the curved surface R1 is larger than the radius of curvature of a region R2 between the top surface and side surface of the upper chip 2 (substrate 21). Although the radius of curvature of the region R2 is zero in Fig. 82, it may be larger than zero.

[0303] In this embodiment, a curved surface R1 is provided at a point near the side surface of the upper chip 2. This makes it possible to prevent a seam from occurring near this point and to reduce stress near this point. In Figure 82, not only is a curved surface R1 provided at a point near the side surface of the left upper chip 2 (the upper chip 2 in chip Ch), but a curved surface R1 is also provided at a point near the side surface of the right upper chip 2.

[0304] The curved surface R1 may be provided in the interlayer insulating film 22 instead of in the interlayer insulating film 12. The curved surface R1 may be provided continuously in the interlayer insulating film 12 and the interlayer insulating film 22. This also applies to the tapered surface Tp described later.

[0305] 83 to 87 are cross-sectional views showing a method for manufacturing the semiconductor device of the ninth embodiment.

[0306] First, a lower wafer 1 and a plurality of upper chips 2 are bonded together (FIG. 83). The lower wafer 1 is fabricated by forming an interlayer insulating film 12 and a multilayer wiring structure 13 on a substrate 11. The plurality of upper chips 2 are fabricated by fabricating an upper wafer 2 by forming an interlayer insulating film 22 and a multilayer wiring structure 23 on a substrate 21, and then dividing the upper wafer 2 into a plurality of upper chips 2 by dicing.

[0307] 83 shows a region R1 between the top surface of the lower wafer 1 (interlayer insulating film 12) and the side surface of the upper chip 2 (interlayer insulating film 22), and a region R2 between the top surface and side surface of the upper chip 2 (substrate 21). In Fig. 83, the radius of curvature of region R1 and the radius of curvature of region R2 are both zero.

[0308] Next, blade trimming is performed to trim the surfaces of the lower wafer 1 and the plurality of upper chips 2 with a blade ( FIG. 84 ). In this embodiment, blade trimming is performed using a blade having a curved surface, thereby changing the region R1 described above into a curved surface R1 having a radius of curvature greater than zero. On the other hand, although the position of the region R2 described above changes, the radius of curvature of the region R2 is maintained at zero. According to the process shown in FIG. 84 , the lower wafer 1 and the plurality of upper chips 2 having the shape shown in FIG. 82 are obtained. Further details of blade trimming will be described later.

[0309] Next, the substrate 21 in each upper chip 2 is thinned (FIG. 85). The substrate 21 is thinned using, for example, a grinder.

[0310] Next, an upper film 4 is formed on the lower wafer 1 and the plurality of upper chips 2 (FIG. 86). The upper film 4 is formed by, for example, CVD.

[0311] Next, the surface of the upper film 4 is planarized (FIG. 87). The planarization is performed by, for example, CMP.

[0312] The lower wafer 1 is then divided into a plurality of lower chips 1 by dicing. As a result, a plurality of semiconductor devices (chips) according to this embodiment are manufactured. Each semiconductor device according to this embodiment is manufactured to include one lower chip 1 and one upper chip 2, etc.

[0313] FIG. 88 is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the ninth embodiment.

[0314] Fig. 88 shows an example of the step shown in Fig. 84. In Fig. 88, the surfaces of the lower wafer 1 and the upper chip 2 are trimmed by a blade Bd. The dashed lines shown in Fig. 88 indicate the outlines of the lower wafer 1 and the upper chip 2 before blade trimming.

[0315] The blade Bd of this modification has a width wider than the gap between the upper chips 2 before blade trimming, and has a curved surface. According to this modification, by trimming the surfaces of the lower wafer 1 and the upper chip 2 using the blade Bd shown in FIG. 88, it is possible to form a curved surface R1 on the surface of the interlayer insulating film 12.

[0316] FIG. 89 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the ninth embodiment.

[0317] Fig. 89 shows another example of the step shown in Fig. 84. The blade Bd of this modification has a width narrower than the distance between the upper chips 2 before blade trimming, and has a curved surface. According to this modification, by trimming the surface of the upper chip 2 using the blade Bd shown in Fig. 89, it is possible to form a curved surface R1 on the surface of the interlayer insulating film 22.

[0318] FIG. 90 is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the ninth embodiment.

[0319] Fig. 90 shows another example of the step shown in Fig. 84. The blade Bd of this modification has a width narrower than the distance between the upper chips 2 before blade trimming, and has a curved surface. According to this modification, by using the blade Bd shown in Fig. 89 to trim the surfaces of the lower wafer 1 and the upper chip 2, it is possible to form a curved surface R1 on the surface of the substrate 11.

[0320] 91 to 94 are cross-sectional views showing a method for manufacturing a semiconductor device according to a fourth modification of the ninth embodiment.

[0321] First, the lower wafer 1 and the plurality of upper chips 2 are bonded together (FIG. 91). This bonding is performed in the same manner as the bonding in the process shown in FIG. 83. In FIG. 91, the radius of curvature of the region R1 and the radius of curvature of the region R2 are both zero. Next, a resist film 96 is formed on the lower wafer 1 and the plurality of upper chips 2 (FIG. 91).

[0322] Next, blade trimming is performed to trim the surfaces of the upper chips 2 and the resist film 96 with a blade (FIG. 92). As a result, the curved surface shown in FIG. 92 is formed on the surface of the substrate 21 in each upper chip 2.

[0323] Next, the substrate 21 and interlayer insulating film 22 in each upper chip 2 are processed by plasma etching using the resist film 96 as a mask (FIG. 93). As a result, the curved surface of the substrate 21 is transferred to the interlayer insulating film 22, and a curved surface R1 is formed on the surface of the interlayer insulating film 22 in each upper chip 2. In FIG. 93, the radius of curvature of the curved surface R1 is larger than the radius of curvature of the region R2.

[0324] Next, the resist film 96 is removed by washing (FIG. 94).

[0325] 86 and 87 are then carried out, thus completing the manufacture of the semiconductor device of this modified example.

[0326] 95 and 96 are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth modification of the ninth embodiment.

[0327] Figure 95 shows the upper wafer 2 before being divided into a plurality of upper chips 2. In this modification, a dicing tape 97 is attached to the surface of the interlayer insulating film 22 in the upper wafer 2 (Figure 95). In Figure 95, the upper wafer 2 is placed on the dicing tape 97 in a downward position.

[0328] Next, blade trimming is performed to divide the upper wafer 2 into multiple upper chips 2 using a blade Bd (FIG. 95). In this modification, blade trimming is performed using a blade Bd having a curved surface, thereby forming a curved surface R1 and a region R2 in each upper chip 2 (FIG. 96). In FIG. 96, the curved surface R1 is formed in the interlayer insulating film 22, and the region R2 is formed in the substrate 21, with the radius of curvature of the curved surface R1 being larger than the radius of curvature of the region R2.

[0329] 83 and 85 to 87 are then carried out, thus completing the manufacture of the semiconductor device of this modified example.

[0330] 97 and 98 are cross-sectional views showing a method for manufacturing a semiconductor device according to a sixth modification of the ninth embodiment.

[0331] Figure 97 shows the upper wafer 2 before it is divided into a plurality of upper chips 2. In this modification, a dicing tape 97 is attached to the surface of the interlayer insulating film 22 in the upper wafer 2 (Figure 97). In Figure 97, the upper wafer 2 is placed facing downward on the dicing tape 97. Also, in this modification, a resist film 96 is formed on the surface of the substrate 21 in the upper wafer 2 (Figure 97).

[0332] Next, blade trimming of the upper wafer 2 is performed using a blade Bd ( FIG. 97 ). In this modified example, blade trimming is performed so as not to divide the upper wafer 2 into multiple upper chips 2. In this modified example, blade trimming is performed using a blade Bd having a curved surface, thereby forming a curved surface R1 and a region R2 in the upper wafer 2 ( FIG. 98 ). In FIG. 98 , curved surface R1 is formed on the substrate 21, region R2 is formed on the substrate 21, and the radius of curvature of curved surface R1 is larger than the radius of curvature of region R2.

[0333] Next, the substrate 21 and interlayer insulating film 22 in the upper wafer 2 are processed by plasma etching using the resist film 96 as a mask (FIG. 98). As a result, the upper wafer 2 is divided into a plurality of upper chips 2. Furthermore, the curved surface R1 of the substrate 21 is transferred to the interlayer insulating film 22, and the curved surface R1 is formed on the surface of the interlayer insulating film 22. In FIG. 98, the radius of curvature of the curved surface R1 is larger than the radius of curvature of the region R2.

[0334] Thereafter, the resist film 96 is removed by washing, and then the steps shown in Figure 83 and Figures 85 to 87 are carried out, etc. In this manner, the semiconductor device of this modified example is manufactured.

[0335] 99 and 100 are cross-sectional views showing a method for manufacturing a semiconductor device according to the seventh modification of the ninth embodiment.

[0336] Figure 99 shows the upper wafer 2 before it is divided into a plurality of upper chips 2. In this modification, a dicing tape 97 is attached to the surface of the interlayer insulating film 22 in the upper wafer 2 (Figure 99). In Figure 99, the upper wafer 2 is placed on the dicing tape 97 in a downward position.

[0337] Next, blade trimming is performed to divide the upper wafer 2 into a plurality of upper chips 2 using a blade Bd (FIG. 100). In this modification, blade trimming is performed using a blade Bd having a tapered surface on its surface, thereby forming a tapered surface Tp on each upper chip 2 (FIG. 100). In FIG. 100, the tapered surface Tp is formed continuously on the surfaces of the substrate 21 and the insulating film 22.

[0338] 83 and 85 to 87 are then performed. In this manner, the semiconductor device of this modification is manufactured. According to this modification, the tapered surface Tp as described above can suppress the occurrence of seams and reduce stress, similar to the curved surface R1.

[0339] 34 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0340] The camera 100 includes an optical unit 101 including a lens group and the like, an imaging device 102 which is a semiconductor device (e.g., a solid-state imaging device) according to any one of the first to ninth embodiments, a DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, a frame memory 104, a display unit 105, a recording unit 106, an operation unit 107, and a power supply unit 108. The DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, the operation unit 107, and the power supply unit 108 are connected to one another via a bus line 109.

[0341] The optical unit 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light formed on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0342] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one frame of a moving image or still image captured by the imaging device 102.

[0343] The display unit 105 includes a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 on a recording medium such as a hard disk or semiconductor memory.

[0344] The operation unit 107, under the operation of the user, issues operation commands for various functions of the camera 100. The power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources.

[0345] By using any one of the semiconductor devices according to the first to ninth embodiments as the imaging device 102, it is possible to expect to obtain a good image.

[0346] The semiconductor device can be applied to various other products. For example, the semiconductor device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0347] 35 is a block diagram showing an example of the configuration of a mobile object control system. The mobile object control system shown in FIG. 35 is a vehicle control system 200.

[0348] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 35, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 35 further shows, as components of the integrated control unit 250, a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0349] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates braking force for the vehicle, etc.

[0350] Body system control unit 220 controls the operation of various devices equipped in the vehicle body in accordance with various programs. For example, body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, backup lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 220. Body system control unit 220 receives input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0351] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture images outside the vehicle and receives the captured images from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0352] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 231 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 231 may be visible light or invisible light such as infrared light. The imaging unit 231 includes the semiconductor device according to any one of the first to ninth embodiments.

[0353] The in-vehicle information detection unit 240 detects information about the inside of a vehicle equipped with the vehicle control system 200. For example, a driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver or determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. This camera may include any of the semiconductor devices according to the first to ninth embodiments, and may be, for example, the camera 100 shown in FIG. 34 .

[0354] The microcomputer 251 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside information detection unit 230 or the inside information detection unit 240, and output control commands to the drivetrain control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), such as vehicle collision avoidance, impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, collision warning, and lane departure warning.

[0355] In addition, the microcomputer 251 can perform cooperative control for purposes such as autonomous driving, in which the vehicle travels autonomously without the driver's operation, by controlling the driving force generating device, steering mechanism, or braking device based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0356] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information about the outside of the vehicle acquired by the outside information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0357] The audio / video output unit 252 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 35, such output devices include an audio speaker 261, a display unit 262, and an instrument panel 263. The display unit 262 may include, for example, an on-board display or a head-up display.

[0358] FIG. 36 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0359] 36 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided, for example, at positions such as the front nose of the vehicle 300, the side mirrors, the rear bumper, the back door, and the top of the windshield inside the vehicle cabin.

[0360] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the top of the windshield inside the vehicle mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0361] FIG. 36 shows an example of the imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of imaging unit 304 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 301 to 304, a bird's-eye view image of vehicle 300 viewed from above can be obtained. Hereinafter, imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311 to 314."

[0362] At least one of the image capturing units 301 to 304 may have a function of acquiring distance information. For example, at least one of the image capturing units 301 to 304 may be a stereo camera including multiple image capturing devices, or may be an image capturing device having pixels for detecting a phase difference.

[0363] For example, the microcomputer 251 (FIG. 35) calculates the distance to each three-dimensional object within the imaging ranges 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 300 and traveling in approximately the same direction as the vehicle 300 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 251 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle and perform automatic braking control (including adaptive cruise control), automatic acceleration control (including adaptive cruise control), and the like. In this way, according to this example, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without driver operation.

[0364] For example, based on the distance information obtained from the imaging units 301 to 304, the microcomputer 251 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. The microcomputer 251 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drivetrain control unit 210.

[0365] At least one of the image capturing units 301-304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 301-304. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 301-304 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the images captured by the image capturing units 301-304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like representing the pedestrian in a desired position.

[0366] FIG. 37 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0367] 37 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0368] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the example shown in the figure, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0369] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target inside the body cavity of the patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0370] An optical system and an image sensor are provided inside the camera head 502, and light reflected from an object to be observed (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 601 as RAW data.

[0371] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502 and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0372] Under the control of the CCU 601 , the display device 602 displays an image based on the image signal that has been subjected to image processing by the CCU 601 .

[0373] The light source device 603 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0374] The input device 604 is an input interface for the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0375] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 sends gas into the body cavity of the patient 532 via the insufflation tube 511 to ensure a clear field of view for the endoscope 500 and a working space for the surgeon. The recorder 607 is a device capable of recording various types of information related to the surgery. The printer 608 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0376] The light source device 603, which supplies illumination light to the endoscope 500 when photographing the surgical site, can be configured from a white light source formed, for example, by an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 603 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 502 in synchronization with the irradiation timing. This method allows color images to be obtained without providing a color filter to the image sensor.

[0377] Furthermore, the light source device 603 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0378] The light source device 603 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0379] FIG. 38 is a block diagram showing an example of the functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0380] The camera head 502 has a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera head control unit 705. The CCU 601 has a communication unit 711, an image processing unit 712, and a control unit 713. The camera head 502 and the CCU 601 are connected to each other via a transmission cable 700 so as to be able to communicate with each other.

[0381] The lens unit 701 is an optical system provided at the connection portion with the lens barrel 501. Observation light taken in from the tip of the lens barrel 501 is guided to the camera head 502 and enters the lens unit 701. The lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0382] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 702 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these image signals. Alternatively, the imaging unit 702 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 531 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 702 is composed of a multi-chip type, multiple lens units 701 may be provided corresponding to each imaging element. The imaging unit 702 may be, for example, a semiconductor device according to any of the first to ninth embodiments.

[0383] Furthermore, the imaging unit 702 does not necessarily have to be provided in the camera head 502. For example, the imaging unit 702 may be provided inside the lens barrel 501, immediately after the objective lens.

[0384] The driving unit 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control unit 705. This allows the magnification and focus of the image captured by the imaging unit 702 to be adjusted appropriately.

[0385] The communication unit 704 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0386] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601 and supplies the control signal to the camera head control unit 705. The control signal includes information relating to the image capturing conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing an image, and / or information specifying the magnification and focus of the captured image.

[0387] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0388] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0389] The communication unit 711 is configured by a communication device for transmitting and receiving various information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0390] Furthermore, the communication unit 711 transmits to the camera head 502 a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0391] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data, sent from the camera head 502 .

[0392] The control unit 713 performs various controls related to the imaging of the surgical site, etc. by the endoscope 500 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0393] Furthermore, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal subjected to image processing by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated during use of the energy treatment tool 512, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 602, the control unit 713 may use the recognition results to superimpose various surgical support information on the image of the surgical site. Superimposing the surgical support information and presenting it to the surgeon 531 reduces the burden on the surgeon 531 and enables the surgeon 531 to proceed with the surgery reliably.

[0394] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable of these.

[0395] In the illustrated example, communication is performed by wire using the transmission cable 700, but communication between the camera head 502 and the CCU 601 may also be performed wirelessly.

[0396] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0397] The present disclosure may also be configured as follows.

[0398] (1) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a first portion provided on a side surface of the second chip, and a predetermined vertical cross section of the first portion has an upper edge having a first length and a lower edge having a second length longer than the first length.

[0399] (2) The semiconductor device according to (1), wherein the predetermined vertical cross section further has a hypotenuse that is at an angle of 30 to 60 degrees with respect to the vertical direction.

[0400] (3) The semiconductor device according to (2), wherein, when the angle is θ, the first length is A, the second length is B, and the height of the predetermined vertical cross section is C, C≦(B−A) / tan θ holds.

[0401] (4) The semiconductor device according to (1), wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

[0402] (5) The semiconductor device according to (1), wherein the first film further includes a second portion spaced apart from the second chip.

[0403] (6) The semiconductor device according to (5), wherein the first portion is in contact with the second portion and is provided between the second chip and the second portion.

[0404] (7) The semiconductor device according to (5), wherein the first portion is separated from the second portion.

[0405] (8) The semiconductor device according to (1), wherein the top surface of the first portion is located lower than the top surface of the second chip.

[0406] (9) The semiconductor device according to (1), wherein the top surface of the first portion is provided at a position higher than the top surface of the second chip.

[0407] (10) The semiconductor device according to (1), wherein the first portion includes a portion provided on an upper surface of the second chip.

[0408] (11) The semiconductor device according to (1), wherein the second chip includes a substrate containing silicon or a compound semiconductor substrate.

[0409] (12) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a second portion provided at a distance from the second chip.

[0410] (13) The semiconductor device according to (12), wherein the first film further includes a first portion provided on a side surface of the second chip.

[0411] (14) The semiconductor device according to (13), wherein the predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

[0412] (15) The semiconductor device according to (14), wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

[0413] (16) The semiconductor device according to (13), wherein the shape of the predetermined vertical cross section of the first portion is a triangle having a first side facing the top surface of the first chip, a second side facing the side surface of the second chip, and a third side located between the first side and the second side.

[0414] (17) A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include at least one of a first portion provided on a side surface of the second chip and a second portion provided spaced apart from the second chip, and the first portion is formed so that a predetermined vertical cross section of the first portion has an upper edge having a first length and a lower edge having a second length longer than the first length.

[0415] (18) The method for manufacturing a semiconductor device according to (17), wherein the first chip has a first area in a plan view, and the second chip has a second area smaller than the first area in a plan view.

[0416] (19) The method for manufacturing a semiconductor device according to (17), wherein the first film is formed by printing, deposition, or coating.

[0417] (20) The method for manufacturing a semiconductor device according to (17), wherein the first portion is formed by processing the first film by etching back.

[0418] (21) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a second film provided on the first chip and the second chip; and a first film provided within the second film, wherein the first film includes a plurality of third portions provided at different heights on the sides of the second chip.

[0419] (22) The semiconductor device according to (21), wherein the first film further includes a plurality of fourth portions provided at different heights above the second chip.

[0420] (23) The semiconductor device according to (22), wherein one of the plurality of fourth portions is provided so as to be in contact with one of the plurality of third portions.

[0421] (24) A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip; wherein the second film is formed to include a first film; and the first film is formed to include a plurality of third portions provided at different heights on the sides of the second chip.

[0422] (25) The method for manufacturing a semiconductor device according to (24), wherein the first film and the second film are formed by alternately forming a plurality of first layers forming the second film and a plurality of third portions forming the first film.

[0423] (26) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a fifth portion provided on a side surface of the second chip, and the fifth portion has a first side surface facing a side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and is provided continuously between the first side surface and the second side surface.

[0424] (27) The semiconductor device according to (26), wherein the fifth portion further includes a portion provided on the upper surface of the second chip.

[0425] (28) The semiconductor device according to (26), wherein the fifth portion further includes a portion provided in a recess provided on a side surface of the second chip.

[0426] (29) The semiconductor device according to (26), wherein the fifth portion further includes a portion provided in a recess provided in the top surface of the first chip.

[0427] (30) A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include a fifth portion provided on a side surface of the second chip, and the fifth portion is formed to have a first side surface facing the side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and is formed continuously between the first side surface and the second side surface.

[0428] (31) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the sixth portion further covers the entire top surface of the second chip.

[0429] (32) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the uppermost end of the sixth portion is lower than the uppermost end of a multilayer wiring structure in the second chip and higher than the lowermost end of the multilayer wiring structure in the second chip.

[0430] (33) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the uppermost end of the sixth portion is higher than the uppermost end of a multilayer wiring structure in the second chip or the lower surface of a substrate, and is lower than the upper surface of the substrate in the second chip.

[0431] (34) A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include a sixth portion provided on a side of the second chip, and the sixth portion is further formed to cover the entire top surface of the second chip, or the sixth portion is formed so that the uppermost end of the sixth portion is lower than the uppermost end of a multilayer wiring structure in the second chip and higher than the lowermost end of the multilayer wiring structure in the second chip, or the sixth portion is formed so that the uppermost end of the sixth portion is higher than the bottom surface of a substrate in the second chip and lower than the top surface of the substrate in the second chip.

[0432] (35) The method for manufacturing a semiconductor device according to (34), wherein the first film is formed by coating.

[0433] (36) A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; and a second film provided on the first chip, the second chip, and the first film, wherein a surface of the first chip or the second chip includes a curved or tapered surface provided near a side surface of the second chip.

[0434] (37) The semiconductor device according to (36), wherein the radius of curvature of the curved surface is larger than the radius of curvature of the region between the top surface and the side surface of the second chip.

[0435] (38) The semiconductor device according to (36), wherein the tapered surface is provided continuously with the surfaces of the substrate and insulating film in the second chip.

[0436] (39) A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip, wherein the first chip or the second chip is formed so that a surface of the first chip or the second chip includes a curved surface or a tapered surface near a side surface of the second chip.

[0437] (40) The method for manufacturing a semiconductor device according to (39), wherein the curved surface or the tapered surface is formed by a blade.

[0438] 1: lower chip (lower wafer), 1': intermediate chip (intermediate wafer), 2: upper chip (upper wafer), 3: lower film, 3a: peripheral portion, 3b: reinforcing portion, 3c: side portion, 3d: upper portion, 3e: composite portion, 3f: side portion, 3': paste, 3-1: layer, 3-2: layer, 3-3: layer, 3-4: layer, 3-5: layer, 4: upper film, 4a: film portion, 4b: film portion, 4-1: layer, 4-2: layer, 4-3: layer, 4-4: layer, 4-5: layer, 5: supporting substrate, 6: supporting substrate, 7: supporting substrate, 11: substrate, 12: interlayer insulating film, 12a: recess, 13: multilayer wiring structure, 13a: wiring layer, 13b: via plug, 13c: metal pad, 11': substrate, 12': interlayer insulating film, 13': multilayer wiring structure, 14': through plug, 21: substrate, 22: interlayer insulating film, 23: multilayer wiring structure, 23a: wiring layer, 23b: via plug, 23c: metal pad, 24: bonding film, 31: screen mask, 32: squeegee, 33: resist film, 41: lower film, 41a: peripheral portion, 42: lower film, 42a: peripheral portion, 42': lower film material, 43: lower film, 43a: peripheral portion, 51: contact plug, 52: wiring layer, 61: substrate, 62: interlayer insulating film, 63: multilayer wiring structure, 71: substrate, 72: interlayer insulating film, 73: multilayer wiring structure, 81: pixel, 82: pixel array, 83: control circuit, 84: vertical drive circuit, 85: column signal processing circuit, 86: horizontal drive circuit, 87: Output circuit, 88: Vertical signal line, 89: Horizontal signal line, 91: Protective film, 92: Protective film, 93: Warpage adjustment film, 94: Warpage adjustment film, 95: Resist film, 95a: Opening, 96: Resist film, 97: Dicing tape

Claims

1. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a first portion provided on a side of the second chip, and a predetermined vertical cross section of the first portion has an upper edge having a first length and a lower edge having a second length longer than the first length.

2. The semiconductor device according to claim 1, wherein said predetermined vertical cross section further has a hypotenuse that is at an angle of 30 to 60 degrees with respect to the vertical direction.

3. The semiconductor device according to claim 2, wherein, when the angle is θ, the first length is A, the second length is B, and the height of the predetermined vertical cross section is C, C≦(B−A) / tan θ holds.

4. The semiconductor device according to claim 1, wherein the shape of said predetermined vertical cross section is a trapezoid with said upper side as an upper base and said lower side as a lower base.

5. The semiconductor device according to claim 1, wherein said first film further includes a second portion spaced apart from said second chip.

6. The semiconductor device according to claim 5, wherein said first portion is in contact with said second portion and is provided between said second chip and said second portion.

7. The semiconductor device according to claim 5, wherein said first portion is separated from said second portion.

8. The semiconductor device according to claim 1, wherein an upper surface of said first portion is located lower than an upper surface of said second chip.

9. The semiconductor device according to claim 1, wherein an upper surface of said first portion is located higher than an upper surface of said second chip.

10. The semiconductor device according to claim 1, wherein said first portion includes a portion provided on an upper surface of said second chip.

11. The semiconductor device according to claim 1, wherein the second chip includes a substrate containing silicon or a compound semiconductor substrate.

12. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a second portion provided at a distance from the second chip.

13. The semiconductor device according to claim 12, wherein the first film further includes a first portion provided on a side surface of the second chip.

14. The semiconductor device according to claim 13, wherein the predetermined longitudinal cross section of said first portion has an upper side having a first length and a lower side having a second length longer than said first length.

15. The semiconductor device according to claim 14, wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

16. The semiconductor device described in claim 13, wherein the shape of a predetermined vertical cross section of the first portion is a triangle having a first side facing the top surface of the first chip, a second side facing the side surface of the second chip, and a third side located between the first side and the second side.

17. A method for manufacturing a semiconductor device comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include at least one of a first portion provided on a side of the second chip and a second portion provided at a distance from the second chip, and the first portion is formed so that a predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the first chip has a first area in a plan view, and the second chip has a second area smaller than the first area in a plan view.

19. The method for manufacturing a semiconductor device according to claim 17, wherein the first film is formed by printing, deposition, or coating.

20. The method for manufacturing a semiconductor device according to claim 17, wherein the first portion is formed by processing the first film by etching back.

21. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a second film provided on the first chip and the second chip; and a first film provided within the second film, wherein the first film includes a plurality of third portions provided at different heights on the sides of the second chip.

22. The semiconductor device according to claim 21, wherein said first film further includes a plurality of fourth portions provided at different heights above said second chip.

23. The semiconductor device according to claim 22, wherein one of the plurality of fourth portions is provided so as to be in contact with one of the plurality of third portions.

24. A method for manufacturing a semiconductor device comprising: loading a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip, wherein the second film is formed to include a first film, and the first film is formed to include a plurality of third portions provided at different heights on the sides of the second chip.

25. The method for manufacturing a semiconductor device as described in claim 24, wherein the first film and the second film are formed by alternately forming a plurality of first layers forming the second film and a plurality of third portions forming the first film.

26. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a fifth portion provided on a side of the second chip, the fifth portion having a first side surface facing a side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and being continuously provided between the first side surface and the second side surface.

27. The semiconductor device according to claim 26, wherein the fifth portion further includes a portion provided on the top surface of the second chip.

28. The semiconductor device according to claim 26, wherein the fifth portion further includes a portion provided within a recess provided in a side surface of the second chip.

29. The semiconductor device according to claim 26, wherein the fifth portion further includes a portion provided within a recess provided in the top surface of the first chip.

30. A method for manufacturing a semiconductor device comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include a fifth portion provided on a side of the second chip, and the fifth portion is formed to have a first side surface facing the side surface of the second chip and a second side surface provided between the side surface of the first chip and a side surface of the second film, and is formed continuously between the first side surface and the second side surface.

31. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side surface of the second chip, and the sixth portion further covers an entire top surface of the second chip.

32. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side of the second chip, and a top end of the sixth portion is lower than a top end of a multilayer wiring structure in the second chip and higher than a bottom end of the multilayer wiring structure in the second chip.

33. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; a first film provided on the first chip; and a second film provided on the first chip, the second chip, and the first film, wherein the first film includes a sixth portion provided on a side of the second chip, and an uppermost end of the sixth portion is higher than an uppermost end of a multilayer wiring structure in the second chip or a lower surface of a substrate, and is lower than an upper surface of the substrate in the second chip.

34. A method for manufacturing a semiconductor device comprising: loading a second chip on a first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; and processing the first wafer into a first chip, wherein the first film is formed to include a sixth portion provided on a side of the second chip, and the sixth portion is further formed to cover the entire top surface of the second chip, or wherein the sixth portion is formed so that the uppermost end of the sixth portion is lower than the uppermost end of a multilayer wiring structure in the second chip and higher than the lowermost end of the multilayer wiring structure in the second chip, or wherein the uppermost end of the sixth portion is higher than the uppermost end of the multilayer wiring structure in the second chip or the lower surface of a substrate, and lower than the upper surface of the substrate in the second chip.

35. The method for manufacturing a semiconductor device according to claim 34, wherein the first film is formed by coating.

36. A semiconductor device comprising: a first chip having a first area in a planar view; a second chip provided on the first chip and having a second area smaller than the first area in a planar view; and a second film provided on the first chip, the second chip, and the first film, wherein a surface of the first chip or the second chip includes a curved or tapered surface provided near a side surface of the second chip.

37. The semiconductor device according to claim 36, wherein the radius of curvature of the curved surface is greater than the radius of curvature of the region between the top surface and the side surface of the second chip.

38. The semiconductor device according to claim 36, wherein the tapered surface is provided continuously with the surfaces of the substrate and insulating film in the second chip.

39. A method for manufacturing a semiconductor device, comprising: loading a second chip on a first wafer; forming a second film on the first wafer and the second chip; and processing the first wafer into a first chip, wherein the first chip or the second chip is formed so that a surface of the first chip or the second chip includes a curved or tapered surface near a side surface of the second chip.

40. The method for manufacturing a semiconductor device according to claim 39, wherein the curved or tapered surface is formed by a blade.

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