Silicon carbide substrate, method for producing epitaxial substrate, and method for producing semiconductor device

Abstract

This silicon carbide substrate has a main surface. The maximum diameter of the main surface is 100 mm or more. The main surface is composed of an outer edge, an outer peripheral region extending up to 5 mm from the outer edge, and a central region surrounded by the outer peripheral region. At 27°C, the electrical resistivity at an any position in the central region is 1 × 1012 Ωcm or more. At 200°C, the average value of the electrical resistivity of the central region is 1 × 1010 Ωcm or more. The area of the region having an electrical resistivity within ±5% of the average value is 70% or more of the area of the central region.

Description

Silicon carbide substrate, epitaxial substrate manufacturing method, and semiconductor device manufacturing method

[0001] The present disclosure relates to a silicon carbide substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a semiconductor device. This application claims priority to Japanese Patent Application No. 2023-137951, filed on August 28, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Publication No. 2003-500321 (Patent Document 1) discloses a semi-insulating bulk single crystal having a resistivity of at least 5000 Ωcm at room temperature.

[0003] Special Publication No. 2003-500321

[0004] A silicon carbide substrate according to the present disclosure has a main surface. The main surface has a maximum diameter of 100 mm or more. The main surface is configured with an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. At 27°C, the electrical resistivity at any position in the central region is 1×10 12 At 200°C, the average electrical resistivity of the central region is 1 x 10 10 The area of ​​the region having an electrical resistivity within ±5% of the average value is 70% or more of the area of ​​the central region.

[0005] FIG. 1 is a plan view schematic showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic taken along line II-II in FIG. 1 . FIG. 3 is a cross-sectional view schematic showing the crystal structure of a silicon carbide substrate according to this embodiment. FIG. 4 is a cross-sectional view schematic showing a region where the electrical resistivity of the silicon carbide substrate is measured. FIG. 5 is a cross-sectional view schematic showing the position where an impurity concentration is measured. FIG. 6 is an enlarged plan view of region VI in FIG. 1 . FIG. 7 is a scanning transmission electron microscope image of a cross section taken along line VII-VII in FIG. 6 . FIG. 8 is a cross-sectional view schematic showing a step of placing a seed substrate and a silicon carbide raw material in a crucible. FIG. 9 is a cross-sectional view schematic showing a silicon carbide crystal growth step. FIG. 10 is a cross-sectional view schematic showing a step of heating the silicon carbide crystal. FIG. 11 is a flowchart generally showing a method for manufacturing a semiconductor device according to this embodiment. FIG. 12 is a cross-sectional view schematic showing a step of forming a buffer layer on a silicon carbide substrate. Fig. 13 is a cross-sectional view showing a process of forming an electron transit layer and an electron supply layer, and Fig. 14 is a cross-sectional view showing a configuration of the semiconductor device according to this embodiment.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide substrate having high electrical resistivity and uniformity of the high electrical resistivity at high temperatures. [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide substrate having high electrical resistivity and uniformity of the high electrical resistivity at high temperatures.

[0007] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0008] (1) Silicon carbide substrate 100 according to the present disclosure has a main surface 1. Main surface 1 has a maximum diameter of 100 mm or more. Main surface 1 is configured with an outer edge 6, a peripheral region 4 within 5 mm from outer edge 6, and a central region 5 surrounded by peripheral region 4. At 27°C, the electrical resistivity at any position in central region 5 is 1×10 12 At 200°C, the average electrical resistivity of the central region 5 is 1 x 10 10 The area of ​​the region having an electrical resistivity within ±5% of the average value is 70% or more of the area of ​​the central region 5.

[0009] (2) The silicon carbide substrate 100 according to (1) above may include threading screw dislocations 9. The areal density of the threading screw dislocations 9 in the central region 5 is 500 cm -2 It may be more than that.

[0010] (3) According to the silicon carbide substrate 100 according to the above (2), the areal density of threading screw dislocations 9 in the central region 5 is 1000 cm -2 It may be more than that.

[0011] (4) According to silicon carbide substrate 100 according to any one of (1) to (3) above, the density of iron at center 61 of main surface 1 is 2×10 14 cm -3 It may be less than.

[0012] (5) According to silicon carbide substrate 100 according to any one of (1) to (4) above, the density of titanium at center 61 of main surface 1 is 1×10 13 cm -3 It may be less than.

[0013] (6) According to silicon carbide substrate 100 according to any one of (1) to (5) above, the density of chromium at center 61 of main surface 1 is 5×10 13 cm -3 It may be less than.

[0014] (7) Silicon carbide substrate 100 according to any one of (1) to (3) above may include titanium, iron, and chromium. At center 61 of main surface 1, the sum of the density of titanium, the density of iron, and the density of chromium is 1×10 16 cm -3 1x10 or more 17 cm -3 It may be the following:

[0015] (8) Silicon carbide substrate 100 according to any one of (1) to (7) above may include nitrogen. At center 61 of main surface 1, the concentration of nitrogen is 1×10 16 cm -3 It may be the following:

[0016] (9) Silicon carbide substrate 100 according to any one of (1) to (8) above may include line defect 10 having first end 21 and second end 22 opposite first end 21. Line defect 10 may be composed of a plurality of linear defects. When viewed along a line perpendicular to main surface 1, line defect 10 may be curved, and the linear distance between first end 21 and second end 22 may be 10 μm or more and 200 μm or less.

[0017] (10) A method for manufacturing an epitaxial substrate according to the present disclosure includes the following steps: A silicon carbide substrate 100 according to any one of (1) to (9) above is prepared. A nitride epitaxial layer 30 is formed on the silicon carbide substrate 100.

[0018] (11) A method for manufacturing an epitaxial substrate according to the present disclosure includes the following steps: preparing a silicon carbide substrate 100 according to any one of (1) to (9) above; forming a nitride epitaxial layer 30 on the silicon carbide substrate 100; and forming an electrode 41 on the nitride epitaxial layer 30.

[0019] [Details of the Embodiments of the Present Disclosure] Hereinafter, details of the embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0020] First, a description will be given of the configuration of silicon carbide substrate 100 according to this embodiment. Fig. 1 is a plan view schematically showing the configuration of silicon carbide substrate 100 according to this embodiment.

[0021] As shown in FIG. 1 , silicon carbide substrate 100 according to this embodiment has a first main surface 1. First main surface 1 extends along a first direction 101 and a second direction 102. First direction 101 is not particularly limited, but is, for example, the <11-20> direction. Second direction 102 is not particularly limited, but is, for example, the <1-100> direction. Silicon carbide substrate 100 contains an n-type impurity such as nitrogen. Silicon carbide substrate 100 is made of, for example, hexagonal silicon carbide. The polytype of the hexagonal silicon carbide is, for example, 4H.

[0022] Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. The cross section shown in Fig. 2 is perpendicular to first main surface 1 and parallel to first direction 101. As shown in Fig. 2, silicon carbide substrate 100 according to this embodiment further has an outer peripheral side surface 3 and a second main surface 2. The second main surface 2 is located on the opposite side of first main surface 1. The outer peripheral side surface 3 is continuous with each of the first main surface 1 and the second main surface 2. The outer peripheral side surface 3 is continuous with the first main surface 1 at an outer edge 6.

[0023] Third direction 103 is a direction from second main surface 2 toward first main surface 1. Third direction 103 is perpendicular to each of first direction 101 and second direction 102. In third direction 103, silicon carbide substrate 100 has a thickness of not less than 300 μm and not more than 700 μm, for example.

[0024] 1 , the maximum diameter W1 of the first main surface 1 is, for example, 100 mm. The maximum diameter W1 may be 150 mm or more, or may be 200 mm or more. The maximum diameter W1 is not particularly limited, but may be, for example, 300 mm or less. When viewed along a line perpendicular to the first main surface 1, the maximum diameter W1 is the longest linear distance between two different points on the outer peripheral side surface 3.

[0025] As shown in FIG. 1 , the first main surface 1 is composed of an outer edge 6, a peripheral region 4, and a central region 5. The peripheral region 4 is a region within 5 mm from the outer edge 6. From another perspective, when viewed along a line perpendicular to the first main surface 1, the distance W2 between the outer edge 6 and the boundary between the peripheral region 4 and the central region 5 is 5 mm. The central region 5 is surrounded by the outer edge region 4. The central region 5 is continuous with the outer edge region 4.

[0026] As shown in Fig. 1, the outer peripheral side surface 3 has an orientation flat portion 7 and an arc-shaped portion 8. The arc-shaped portion 8 is continuous with the orientation flat portion 7. As shown in Fig. 1, when viewed along a straight line perpendicular to the first main surface 1, the orientation flat portion 7 may extend along a first direction 101.

[0027] The first main surface 1 is a surface tilted in the off direction with respect to the {0001} plane or the {0001} plane. Specifically, the first main surface 1 may be a surface tilted in the off direction with respect to the (0001) plane or the (0001) plane. The first main surface 1 may be a surface tilted in the off direction with respect to the (000-1) plane or the (000-1) plane. The off direction may be, for example, a first direction 101 or a second direction 102.

[0028] The off angle is the tilt angle of first main surface 1 with respect to the {0001} plane. The off angle is, for example, greater than 0° and equal to or less than 8°. The off angle may be, for example, equal to or less than 6°, or equal to or less than 4°. The off angle may be, for example, equal to or greater than 1°, or equal to or greater than 2°.

[0029] As shown in FIG. 2 , silicon carbide substrate 100 may have threading screw dislocations 9. Threading screw dislocations 9 are exposed on each of first main surface 1 and second main surface 2. The areal density of threading screw dislocations 9 in central region 5 is, for example, 500 cm -2 The areal density of the threading screw dislocations 9 in the central region 5 is, for example, 600 cm -2 It may be more than 1000 cm -2 It may be 2000 cm or more. -2 It may be 3000 cm or more.-2 The areal density of the threading screw dislocations 9 in the central region 5 may be, for example, 10,000 cm -2 It may be less than 5000 cm -2 It may be more than that.

[0030] Fig. 3 is a schematic diagram showing the crystal structure of silicon carbide substrate 100 according to this embodiment. As shown in Fig. 3, silicon carbide substrate 100 has silicon atoms 51 and carbon atoms 52. Carbon atoms 52 are bonded to silicon atoms 51. Silicon atoms 51 and carbon atoms 52 form a crystal lattice.

[0031] Silicon carbide substrate 100 may have carbon vacancies 99 and interstitial carbon 98. Interstitial carbon 98 is located in gaps in the crystal lattice of silicon carbide. Carbon vacancies 99 are formed in the crystal lattice. Carbon vacancies 99 are formed by carbon atoms 52 being missing from the crystal lattice. In silicon carbide substrate 100, the density of interstitial carbon 98 may be lower than the density of carbon vacancies 99.

[0032] (Electrical Resistivity of Silicon Carbide Substrate) According to silicon carbide substrate 100 according to this embodiment, the electrical resistivity at any position in central region 5 at 27° C. (room temperature) is 1×10 12 From another perspective, the electrical resistivity of silicon carbide substrate 100 over the entire surface of central region 5 is 1×10 12 It is Ωcm or more.

[0033] According to silicon carbide substrate 100 according to this embodiment, the average value of electrical resistivity in central region 5 at 200° C. is 1×10 10 From another perspective, in central region 5, the average value of electrical resistivity of silicon carbide substrate 100 is 1×10 10 It is Ωcm or more.

[0034] At 200°C, the average electrical resistivity of the central region 5 is 5 x 10 10 It may be Ωcm or more, or 1×10 11 It may be 3×10 Ωcm or more. 11It may be 5×10 Ωcm or more. 11 At 200°C, the average electrical resistivity of the central region 5 may be 1×10 12 It may be Ωcm or less.

[0035] Silicon carbide substrate 100 according to the present embodiment has high in-plane uniformity of electrical resistivity in central region 5. From another perspective, there is little variation in electrical resistivity in central region 5. Specifically, the area of ​​the region having an electrical resistivity within ±5% of the average electrical resistivity is 70% or more of the area of ​​central region 5.

[0036] The area of ​​the region having an electrical resistivity within ±5% of the average electrical resistivity may be 75% or more, or 80% or more, of the area of ​​the central region 5. The area of ​​the region having an electrical resistivity within ±5% of the average electrical resistivity may be 90% or less, or 85% or less, of the area of ​​the central region 5.

[0037] In silicon carbide substrate 100 according to the present embodiment, the area of ​​the region having an electrical resistivity within ±10% of the average electrical resistivity is 80% or more of the area of ​​central region 5. The area of ​​the region having an electrical resistivity within ±10% of the average electrical resistivity may be 84% or more, or 88% or more, of the area of ​​central region 5. The area of ​​the region having an electrical resistivity within ±10% of the average electrical resistivity may be 98% or less, or 94% or less, of the area of ​​central region 5.

[0038] (Method of Measuring Electrical Resistivity) The electrical resistivity of silicon carbide substrate 100 at room temperature (27°C) is measured using COREMA-WT, an electrical resistivity measuring device manufactured by Semilab. The voltage applied to silicon carbide substrate 100 is, for example, 5.0 V. The diameter of the probe is 1 mm. The measurement temperature is room temperature (27°C).

[0039] The electrical resistivity of silicon carbide substrate 100 at 200°C is measured using a COREMA-VT electrical resistivity measuring device manufactured by Semilab. The voltage applied to silicon carbide substrate 100 is, for example, 5.0 V. The diameter of the probe is 10 mm. The measurement temperature range is from room temperature (27°C) to 600K.

[0040] Fig. 4 is a plan schematic diagram showing measurement regions of the electrical resistivity of a silicon carbide substrate. As shown in Fig. 4, measurement regions 60 of the electrical resistivity of silicon carbide substrate 100 are arranged at third intervals W3 in each of first direction 101 and second direction 102 from a circle (central measurement region) centered on center 61 of first main surface 1. Third interval W3 is 10 mm.

[0041] Specifically, electrical resistivity measurement region 60 of silicon carbide substrate 100 includes regions shifted 10 mm, 20 mm, 30 mm, and 40 mm in the first direction from the central measurement region, and regions shifted 10 mm, 20 mm, 30 mm, and 40 mm from the central measurement region in the opposite direction to the first direction. Similarly, electrical resistivity measurement region 60 of silicon carbide substrate 100 includes regions shifted 10 mm, 20 mm, 30 mm, and 40 mm from the central measurement region in the second direction, and regions shifted 10 mm, 20 mm, 30 mm, and 40 mm from the central measurement region in the opposite direction to the second direction.

[0042] 4, the numbers of measurement areas 60 arranged in the first direction 101 are 1, 5, 7, 7, 9, 7, 7, 5, and 1, in order from the orientation flat portion toward the second direction 102. The total number of measurement areas 60 is 49.

[0043] (Impurity Concentration) The silicon carbide substrate 100 according to this embodiment is not actively doped with vanadium. Specifically, the silicon carbide substrate 100 is not actively doped with vanadium during the manufacturing process. Vanadium may be incorporated into the silicon carbide substrate 100 as an unintentional impurity during the manufacturing process. When the vanadium concentration is 1×10 14 cm -3 If it is below this value, it is determined that vanadium is not actively doped.

[0044] Silicon carbide substrate 100 according to this embodiment may be substantially free of iron (Fe). Specifically, the iron density at center 61 of first main surface 1 is 2×10 14 cm -3 It may be less than.

[0045] Silicon carbide substrate 100 according to this embodiment may be substantially free of titanium (Ti). Specifically, the density of titanium at center 61 of first main surface 1 is 1×10 13 cm -3 It may be less than.

[0046] Silicon carbide substrate 100 according to this embodiment may be substantially free of chromium (Cr). Specifically, the density of chromium at center 61 of first main surface 1 is 5×10 13 cm -3 It may be less than.

[0047] Silicon carbide substrate 100 according to this embodiment may contain titanium (Ti), iron (Fe), and chromium (Cr). At center 61 of first main surface 1, the density of titanium is 1×10 15 cm -3 1x10 or more 16 cm -3 At the center 61 of the first main surface 1, the density of iron may be 2×10 15 cm -3 2x10 or more 16 cm -3 At the center 61 of the first main surface 1, the density of chromium may be 3×10 15 cm -3 3x10 or more 16 cm -3 It may be the following:

[0048] At the center 61 of the first main surface 1, the sum of the density of titanium, the density of iron, and the density of chromium is 1×10 16 cm -3 1x10 or more 17 cm -3 At the center 61 of the first main surface 1, the sum of the density of titanium, the density of iron, and the density of chromium may be 1.5×10 or less. 16 cm -3or more, or 2.0 × 10 16 cm -3 At the center 61 of the first main surface 1, the sum of the density of titanium, the density of iron, and the density of chromium may be 5×10 17 cm -3 It may be 3×10 or less. 17 cm -3 It may be the following:

[0049] Silicon carbide substrate 100 according to this embodiment may contain nitrogen. Nitrogen is an n-type impurity. The concentration of nitrogen at center 61 of first main surface 1 is 1×10 16 cm -3 At the center 61 of the first main surface 1, the concentration of nitrogen may be 8×10 or less. 15 cm -3 It may be 6×10 or less. 15 cm -3 At the center 61 of the first main surface 1, the concentration of nitrogen may be 5×10 14 cm -3 It may be 1×10 or more. 15 cm -3 It may be more than that.

[0050] (Method of Measuring Impurity Concentration) FIG. 5 is a schematic plan view showing the measurement positions of impurity concentration. As shown in FIG. 5, the concentrations of vanadium, iron, titanium, chromium, and nitrogen are measured at the center 61 of the first main surface 1. The concentrations of vanadium, iron, titanium, chromium, and nitrogen are measured, for example, by secondary ion mass spectrometry (SIMS). For SIMS, for example, an IMS7f secondary ion mass spectrometer manufactured by Cameca Corporation can be used. The measurement conditions for SIMS are, for example, that the primary ions are O ２ ＋ The measurement conditions can be such that the primary ion energy is 8 keV.

[0051] (Strip Defect) Figure 6 is an enlarged plan view of region VI in Figure 1. As shown in Figure 6, silicon carbide substrate 100 according to this embodiment may have stripe defect 10. Stripe defect 10 has a first end 21 and a second end 22. Second end 22 is located on the opposite side of first end 21. First end 21 is exposed at first main surface 1. Second end 22 is located inside silicon carbide substrate 100. In other words, second end 22 is not exposed at first main surface 1.

[0052] As shown in Fig. 6, the line defect 10 is curved. When viewed along a straight line perpendicular to the first main surface 1, the line defect 10 may be bent. From another perspective, when viewed along a straight line perpendicular to the first main surface 1, the line defect 10 may intersect with an imaginary line 24 connecting the first end 21 and the second end 22. The line defect 10 only needs to have a curved portion, and does not have to be entirely curved. When viewed along a straight line perpendicular to the first main surface 1, the line defect 10 may have a curved portion and a straight portion connected to the curved portion.

[0053] When viewed along a line perpendicular to the first main surface 1, the linear distance A2 between the first end 21 and the second end 22 is 10 μm or more and 200 μm or less. The linear distance A2 may be 20 μm or more, or 30 μm or more. The linear distance A2 may be 180 μm or less, or 160 μm or less.

[0054] Fig. 7 is a schematic diagram of a scanning transmission electron microscope image of a cross section taken along line VII-VII in Fig. 6. In the cross section shown in Fig. 7, the interior of the cross section taken along line VII-VII in Fig. 6 is observed through the microscope. As shown in Fig. 7, the line defect 10 is composed of a plurality of linear defects. The line defect 10 may be composed of, for example, a plurality of first linear defects 11, a plurality of second linear defects 12, and a plurality of third linear defects 13.

[0055] 7 , each of the plurality of first linear defects 11, each of the plurality of second linear defects 12, and each of the plurality of third linear defects 13 are linear when viewed along a straight line parallel to first main surface 1. On the other hand, each of the plurality of first linear defects 11, each of the plurality of second linear defects 12, and each of the plurality of third linear defects 13 may be curved when viewed along a straight line perpendicular to first main surface 1.

[0056] 7 , in a cross section perpendicular to first main surface 1, the length of each of the plurality of linear defects (third length A3) is, for example, 1 μm or more and 10 μm or less. The third length A3 may be 2 μm or more, or 3 μm or more. The third length A3 may be 9 μm or less, or 8 μm or less.

[0057] Each of the plurality of first linear defects 11 may extend within the basal plane. Similarly, each of the plurality of second linear defects 12 may extend within the basal plane. Similarly, each of the plurality of third linear defects 13 may extend within the basal plane.

[0058] 7 , in a cross section perpendicular to first main surface 1, the positions of two adjacent linear defects among a plurality of linear defects may be shifted in first direction 101. From another perspective, when viewed along a line perpendicular to first main surface 1, the two adjacent linear defects may be positioned such that a portion of each adjacent linear defect overlaps with another portion of each adjacent linear defect, and the remaining portion of each adjacent linear defect does not overlap.

[0059] 7 , two adjacent linear defects may be spaced apart from each other in third direction 103. The distance between two adjacent linear defects in third direction 103 is not particularly limited, and may be, for example, 0.1 μm or more and 1 μm or less.

[0060] Each of the plurality of first linear defects 11 may contain carbon. Similarly, each of the plurality of second linear defects 12 may contain carbon. Similarly, each of the plurality of third linear defects 13 may contain carbon.

[0061] 7 , in a cross section perpendicular to the first main surface 1, the threading screw dislocation 9 may extend so as to intersect with at least one of the plurality of linear defects. Specifically, the threading screw dislocation 9 may extend so as to intersect with at least one of the plurality of first linear defects 11. The threading screw dislocation 9 may extend so as to intersect with at least one of the plurality of second linear defects 12. The threading screw dislocation 9 may extend so as to intersect with at least one of the plurality of third linear defects 13.

[0062] The line defect 10 may have a region 14 containing carbon. The region 14 containing carbon may be, for example, an inner wall surface forming a cavity. As shown in FIG. 7 , in a cross section perpendicular to the first main surface 1, the region 14 containing carbon may extend so as to intersect with at least one of the plurality of line defects. Specifically, the region 14 containing carbon may extend so as to intersect with at least one of the plurality of second line defects 12. In a cross section perpendicular to the first main surface 1, the region 14 containing carbon may not intersect with each of the plurality of first line defects 11. Similarly, in a cross section perpendicular to the first main surface 1, the region 14 containing carbon may not intersect with each of the plurality of third line defects 13.

[0063] In the above description, the line defect 10 is described as being composed of, for example, a plurality of first linear defects 11, a plurality of second linear defects 12, and a plurality of third linear defects 13. However, the line defect 10 is not limited to the above configuration. The line defect 10 may be composed of, for example, one first linear defect 11, one second linear defect 12, and one third linear defect 13. The line defect 10 may be composed of only a plurality of first linear defects 11. In other words, the line defect 10 may not include a plurality of second linear defects 12 or a plurality of third linear defects 13.

[0064] (Method for measuring line defects) The line defect 10 can be measured using, for example, a digital microscope (model number: VHX-6000) manufactured by Keyence Corporation. When the first main surface 1 is observed using the digital microscope, the line defect 10 appears darker (in other words, black) than the surrounding area. The measurement area for the line defect 10 is a square area on the first main surface 1. The length of one side of the square area is 100 μm.

[0065] <Method of Manufacturing Silicon Carbide Substrate> Next, a method of manufacturing silicon carbide substrate 100 according to this embodiment will be described. FIG. 8 is a cross-sectional view schematically illustrating a step of placing a seed substrate and a silicon carbide raw material in a crucible. First, crucible 130 is prepared. Crucible 130 is made of graphite. Crucible 130 has a housing portion 132 and a lid portion 131. Lid portion 131 is placed on housing portion 132. A heating portion (not shown) is arranged around the outer periphery of crucible 130. The heating portion may be a resistance heating type or an induction heating type.

[0066] As shown in FIG. 8 , silicon carbide raw material 156 is placed in accommodation portion 132. Silicon carbide raw material 156 is, for example, polycrystalline silicon carbide powder. A source of metal impurities is mixed into silicon carbide raw material 156. The source of metal impurities may contain, for example, iron, titanium, or chromium. Specifically, the source of metal impurities is iron powder, titanium powder, chromium powder, or the like.

[0067] Seed substrate 150 is fixed to lid portion 131 using, for example, an adhesive (not shown). Seed substrate 150 has third main surface 151 and fourth main surface 152. Third main surface 151 faces silicon carbide raw material 156. Fourth main surface 152 faces lid portion 131. Third main surface 151 of seed substrate 150 is arranged to face the surface of silicon carbide raw material 156. As described above, seed substrate 150 and silicon carbide raw material 156 are arranged in crucible 130.

[0068] 9 is a cross-sectional schematic diagram showing the silicon carbide crystal growth process. First, the pressure inside crucible 130 is reduced while the temperature of third main surface 151 of seed substrate 150 is lower than the temperature of silicon carbide source material 156. The pressure of the ambient gas inside crucible 130 is reduced to, for example, 1.0 kPa. As a result, silicon carbide source material 156 begins to sublimate, and the sublimated silicon carbide gas is recrystallized on third main surface 151 of seed substrate 150.

[0069] The metal impurity source also sublimes along with silicon carbide raw material 156. As a result, silicon carbide crystal 57 containing the metal impurity grows on third main surface 151. While silicon carbide crystal 57 is growing, the pressure inside crucible 130 is maintained at, for example, approximately not less than 0.1 kPa and not more than 3 kPa.

[0070] As described above, silicon carbide crystal 57 grows on third main surface 151 by sublimating silicon carbide raw material 156. In the step of growing silicon carbide crystal 57, the temperature of the crucible is, for example, 2100°C or higher and 2300°C or lower. The temperature of the crucible is not particularly limited, but may be, for example, 2150°C or higher and 2250°C or lower. Silicon carbide crystal 57 has main body 56 and growth surface 50. Growth surface 50 may be curved so as to be convex toward silicon carbide raw material 156.

[0071] The silicon carbide crystal 57 contains a metal impurity other than vanadium. The metal impurity may contain titanium, iron, and chromium. The sum of the density of titanium, iron, and chromium contained in the silicon carbide crystal 57 is 1×10 17 cm -3 The total density of titanium, iron, and chromium contained in silicon carbide crystal 57 may be 1.2×10 17 cm -3 It may be 1.5×10 or more. 17 cm -3 The total density of titanium, iron, and chromium contained in silicon carbide crystal 57 may be 1×10 18 cm -3 or less, or 5.0 × 10 17 cm -3 It may be the following:

[0072] Next, a step of heating the silicon carbide crystal is carried out. Fig. 10 is a cross-sectional schematic diagram showing the step of heating silicon carbide crystal 57. Silicon carbide crystal 57 is removed from crucible 130 and then placed inside heating device 301. As shown in Fig. 10, silicon carbide crystal 57 is annealed while placed inside heating device 301. Silicon carbide crystal 57 is heated, for example, in an argon atmosphere at 2400°C for about 1 hour.

[0073] Next, silicon carbide crystal 57 is rapidly cooled. Silicon carbide crystal is rapidly cooled from 2400°C to a temperature of 1200°C or less. The cooling rate of silicon carbide crystal is, for example, 30°C / min or more and 150°C / min or less. This causes point defects to be formed in silicon carbide crystal 57. As a result, the electrical resistivity of silicon carbide crystal 57 increases. Next, a step of cutting silicon carbide crystal is carried out. For example, a saw wire is used to slice the silicon carbide crystal along a plane perpendicular to the central axis of the silicon carbide crystal. In this manner, silicon carbide substrate 100 according to this embodiment is obtained (see FIG. 1 ).

[0074] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 400 according to this embodiment will be described. Fig. 11 is a flowchart that outlines the method for manufacturing the semiconductor device 400 according to this embodiment. The method for manufacturing the semiconductor device 400 according to this embodiment mainly includes a step (S1) of manufacturing an epitaxial substrate and a step (S2) of forming an electrode on the epitaxial layer.

[0075] First, a step (S1) of manufacturing epitaxial substrate 200 is performed. Step (S1) of manufacturing epitaxial substrate 200 includes a step (S10) of preparing silicon carbide substrate 100 and a step (S20) of forming an epitaxial layer. First, step (S10) of preparing silicon carbide substrate 100 is performed. In step (S10) of preparing silicon carbide substrate 100, silicon carbide substrate 100 according to the present embodiment is prepared (see FIG. 1 ).

[0076] Next, the step (S20) of forming an epitaxial layer is performed. Specifically, buffer layer 31 is formed on silicon carbide substrate 100. Fig. 12 is a schematic cross-sectional view showing the step of forming buffer layer 31 on silicon carbide substrate 100. Buffer layer 31 is formed on first main surface 1 of silicon carbide substrate 100 by epitaxial growth. Buffer layer 31 is formed by MOCVD (Metal Organic Chemical Vapor Deposition), for example.

[0077] The buffer layer 31 is made of, for example, aluminum gallium nitride (AlGaN). The buffer layer 31 has a thickness of, for example, 150 nm. As a source gas for aluminum (Al), for example, TMA (trimethylaluminum) is used. As a source gas for gallium (Ga), for example, TMG (trimethylgallium) is used. As a source gas for nitrogen (N), for example, ammonia is used.

[0078] Next, the electron transit layer 32 and the electron supply layer 33 are formed. Fig. 13 is a cross-sectional view showing the process of forming the electron transit layer 32 and the electron supply layer 33. First, the electron transit layer 32 is formed on the buffer layer 31 by MOCVD. The electron transit layer 32 is made of, for example, gallium nitride (GaN). The thickness of the electron transit layer 32 is, for example, 1 µm.

[0079] Next, the electron supply layer 33 is formed on the electron transit layer 32. The electron supply layer 33 is formed by, for example, MOCVD. The electron supply layer 33 is made of, for example, AlGaN. The thickness of the electron supply layer 33 is, for example, 20 μm. Two-dimensional electron gas is generated in a portion of the electron transit layer 32 near the interface between the electron transit layer 32 and the electron supply layer 33.

[0080] In this manner, the epitaxial substrate 200 is manufactured. As shown in Fig. 13 , the epitaxial substrate 200 includes the silicon carbide substrate 100 and the nitride epitaxial layer 30. The nitride epitaxial layer 30 includes a buffer layer 31, an electron transit layer 32, and an electron supply layer 33. The buffer layer 31 is provided on the silicon carbide substrate 100. The electron transit layer 32 is provided on the buffer layer 31. The electron supply layer 33 is provided on the electron transit layer 32.

[0081] Next, the step of forming electrodes is performed. First, the source electrode 41 and the drain electrode 42 are formed. Specifically, a first resist pattern (not shown) is formed on the electron supply layer 33. In the first resist pattern, openings are formed in the regions where the source electrode 41 and the drain electrode 42 are to be formed.

[0082] Next, a first metal stack film is formed on the first resist pattern using, for example, a vacuum deposition method. The first metal stack film includes, for example, a titanium (Ti) film and an aluminum (Al) film. Next, the first metal stack film formed on the first resist pattern is removed by lift-off. As a result, the source electrode 41 and the drain electrode 42 made of the first metal stack film are formed on the electron supply layer 33.

[0083] Next, alloying annealing may be performed. Specifically, the source electrode 41 and the drain electrode 42 are annealed. The annealing temperature is, for example, 600° C. This may allow each of the source electrode 41 and the drain electrode 42 to make ohmic contact with the electron supply layer 33.

[0084] Next, the gate electrode 43 is formed. Specifically, a second resist pattern (not shown) is formed on the electron supply layer 33. In the second resist pattern, an opening is formed in the region where the gate electrode 43 is to be formed.

[0085] Next, a second metal stack film is formed on the second resist pattern using, for example, a vacuum deposition method. The second metal stack film includes, for example, a nickel (Ni) film and a gold (Au) film. Next, the second metal stack film formed on the second resist pattern is removed by lift-off. As a result, a gate electrode 43 made of the second metal stack film is formed on the electron supply layer 33.

[0086] 14 is a cross-sectional view showing a configuration of a semiconductor device 400 according to this embodiment. The semiconductor device 400 is, for example, a field-effect transistor, more specifically, a high electron mobility transistor (HEMT). The semiconductor device 400 mainly includes an epitaxial substrate 200, a gate electrode 43, a source electrode 41, and a drain electrode 42.

[0087] 14 , the gate electrode 43, the source electrode 41, and the drain electrode 42 are each provided on the epitaxial substrate 200. Specifically, the gate electrode 43, the source electrode 41, and the drain electrode 42 are each in contact with the electron supply layer 33. The gate electrode 43 may be located between the source electrode 41 and the drain electrode 42.

[0088] Next, the effects of the method for manufacturing silicon carbide substrate 100, epitaxial substrate 200, and semiconductor device 400 according to this embodiment will be described.

[0089] In order to produce silicon carbide crystals having high electrical resistivity, high-temperature heat treatment is performed on the silicon carbide crystals to introduce point defects caused by carbon vacancies. As a result of extensive research into methods for obtaining silicon carbide crystals having high electrical resistivity, the inventors have arrived at the following findings.

[0090] Specifically, when silicon carbide crystal is heat-treated in a high-temperature range of about 2600°C, a phenomenon in which carbon atoms aggregate around threading screw dislocations 9 (TSDs) is observed (gettering effect). When carbon atoms aggregate around threading screw dislocations 9, the carbon vacancies compensate for carriers, increasing the density of carbon vacancies in the silicon carbide crystal. In particular, when the areal density of threading screw dislocations 9 is high, carbon atoms aggregate evenly over a wide region of the silicon carbide crystal. Therefore, a high density of carbon vacancies is maintained uniformly over a wide range. As a result, a silicon carbide substrate 100 having high electrical resistivity and uniformity of the high electrical resistivity can be manufactured.

[0091] Silicon carbide substrate 100 according to this embodiment has a main surface 1. The main surface 1 has a maximum diameter of 100 mm or more. Main surface 1 is composed of an outer edge 6, a peripheral region 4 within 5 mm from the outer edge 6, and a central region 5 surrounded by the peripheral region 4. At 27°C, the electrical resistivity at any position in central region 5 is 1×10 12 At 200°C, the average electrical resistivity of the central region 5 is 1 x 10 10 The resistivity is Ωcm or more. The area of ​​the region having an electrical resistivity within ±5% of the average value is 70% or more of the area of ​​central region 5. It is possible to obtain silicon carbide substrate 100 having high electrical resistivity and high uniformity of electrical resistivity at high temperatures. Therefore, when semiconductor device 400 is fabricated using silicon carbide substrate 100, stable operation of semiconductor device 400 at high temperatures can be ensured, and the yield of the semiconductor device can be improved.

[0092] The silicon carbide substrate 100 according to this embodiment may include threading screw dislocations 9. The areal density of the threading screw dislocations 9 in the central region 5 is 500 cm -2 This can further improve the uniformity of the electrical resistivity of silicon carbide substrate 100.

[0093] According to the silicon carbide substrate 100 according to this embodiment, the areal density of threading screw dislocations 9 in the central region 5 is 1000 cm -2This can further improve the uniformity of the electrical resistivity of silicon carbide substrate 100.

[0094] According to silicon carbide substrate 100 according to this embodiment, the density of iron at center 61 of main surface 1 is 2×10 14 cm -3 It may be less than.

[0095] According to silicon carbide substrate 100 according to this embodiment, the density of titanium at center 61 of main surface 1 is 1×10 13 cm -3 It may be less than.

[0096] According to silicon carbide substrate 100 according to this embodiment, the density of chromium at center 61 of main surface 1 is 5×10 13 cm -3 It may be less than.

[0097] Silicon carbide substrate 100 according to this embodiment may contain titanium, iron, and chromium. At center 61 of main surface 1, the sum of the density of titanium, the density of iron, and the density of chromium is 1×10 16 cm -3 1x10 or more 17 cm -3 The sum of the density of titanium, the density of iron, and the density of chromium may be 1×10 or less. 16 cm -3 By satisfying the above, the scattering effect between the carrier and titanium is strengthened, thereby making it possible to further increase the electrical resistivity of silicon carbide substrate 100. If the total of the density of titanium, the density of iron, and the density of chromium is excessively high, these impurities may aggregate, deteriorating the crystal quality of silicon carbide substrate 100. According to silicon carbide substrate 100 according to this embodiment, it is possible to further increase the electrical resistivity of silicon carbide substrate 100 while suppressing deterioration of the crystal quality.

[0098] Silicon carbide substrate 100 according to this embodiment may contain nitrogen. At center 61 of main surface 1, the concentration of nitrogen is 1×10 16 cm -3 This allows silicon carbide substrate 100 to have a higher electrical resistivity.

[0099] The silicon carbide substrate 100 according to this embodiment may have a line defect having a first end and a second end opposite to the first end. The line defect is thought to be formed by the aggregation of carbon atoms around the threading screw dislocation 9. The formation of the line defect can increase the density of carbon vacancies in the silicon carbide substrate 100. As a result, the electrical resistivity of the silicon carbide substrate 100 can be increased.

[0100] According to the method for manufacturing an epitaxial substrate in accordance with this embodiment, nitride epitaxial layer 30 is formed on silicon carbide substrate 100. This makes it possible to obtain an epitaxial substrate that can maintain high electrical resistivity at high temperatures.

[0101] According to the method for manufacturing an epitaxial substrate according to this embodiment, nitride epitaxial layer 30 is formed on silicon carbide substrate 100. An electrode is formed on nitride epitaxial layer 30. This makes it possible to obtain a semiconductor device that can maintain high electrical resistivity at high temperatures.

[0102] (Sample Preparation) First, silicon carbide crystal 57 having a polytype of 4H was produced using manufacturing conditions A to D. Under the manufacturing conditions A to D, seed substrate 150 and silicon carbide source material 156 were first placed in crucible 130 (see FIG. 8 ). Third main surface 151 of seed substrate 150 had a diameter of 100 mm. Next, silicon carbide crystal 57 was formed on third main surface 151 of seed substrate 150 using a sublimation method (see FIG. 9 ). Next, silicon carbide crystal 57 was sliced ​​using a saw wire, thereby obtaining silicon carbide substrates 100 according to samples 1 to 4.

[0103] Under the manufacturing conditions related to condition A, the surface density of threading screw dislocations 9 in the seed substrate was 620 / cm 2The vanadium was not intentionally doped into the silicon carbide crystal. After being removed from the crucible 130, the silicon carbide crystal 57 was placed inside the heating device 301. The silicon carbide crystal 57 was heated in the heating device 301 under conditions such that the maximum temperature reached 2400°C. After the silicon carbide crystal 57 was heated, the silicon carbide crystal 57 was rapidly cooled. The cooling rate was set to be equal to or greater than 50°C / min and equal to or less than 130°C / min.

[0104] Under the manufacturing conditions related to condition B, the surface density of threading screw dislocations 9 in the seed substrate was 630 / cm 2 The vanadium was not intentionally doped into the silicon carbide crystal. After being removed from the crucible 130, the silicon carbide crystal 57 was placed inside the heating device 301. The silicon carbide crystal 57 was heated in the heating device 301 under conditions such that the maximum temperature reached 2600°C. The silicon carbide crystal 57 was heated at a temperature of 2500°C or higher for 10 minutes or longer. After the silicon carbide crystal 57 was heated, the silicon carbide crystal 57 was rapidly cooled. The cooling rate was set to 50°C / min or higher and 130°C / min or lower.

[0105] Under the manufacturing conditions of condition C, the surface density of threading screw dislocations 9 in the seed substrate was 3200 / cm 2 The vanadium was not intentionally doped into the silicon carbide crystal. After being removed from the crucible 130, the silicon carbide crystal 57 was placed inside the heating device 301. The silicon carbide crystal 57 was heated in the heating device 301 under conditions such that the maximum temperature reached 2600°C. The silicon carbide crystal 57 was heated at a temperature of 2500°C or higher for 10 minutes or longer. After the silicon carbide crystal 57 was heated, the silicon carbide crystal 57 was rapidly cooled. The cooling rate was set to 50°C / min or higher and 130°C / min or lower.

[0106] Under the manufacturing conditions of condition D, the surface density of threading screw dislocations 9 in the seed substrate was 3300 / cm 2 Vanadium was not intentionally doped into the silicon carbide crystal. Iron, titanium, and chromium were intentionally doped into the silicon carbide crystal. The sum of the iron concentration, titanium concentration, and chromium concentration was 1×10 16 / cm 3 1x10 or more 17 / cm 3The standard deviation of the total concentration is 3 × 10 16 / cm 3 The temperature was controlled to be as follows. Silicon carbide crystal 57 was removed from crucible 130 and then placed inside heating device 301. Silicon carbide crystal 57 was heated in heating device 301 under conditions such that the maximum temperature was 2600°C. Silicon carbide crystal 57 was heated at a temperature of 2500°C or higher for 10 minutes or longer. After silicon carbide crystal 57 was heated, silicon carbide crystal 57 was rapidly cooled. The cooling rate was set to be 50°C / min or higher and 130°C / min or lower.

[0107] (Measurement Method) The concentrations of nitrogen, vanadium, iron, titanium, and chromium were measured using a secondary ion mass spectrometer (model number: IMS7f) manufactured by Cameca. In the SIMS measurement, the primary ions were O ２ ＋ The primary ion energy was set to 8 keV. The measurement position was set to the center 61 of the first main surface 1.

[0108] The electrical resistivity of silicon carbide substrate 100 at room temperature (27°C) was measured using an electrical resistivity measuring device (model number: COREMA-WT) manufactured by SemiMap. The probe diameter was 1 mm. The electrical resistivity of silicon carbide substrate 100 at high temperature (200°C) was measured using an electrical resistivity measuring device (model number: COREMA-VT) manufactured by SemiMap. The probe diameter was 10 mm. The electrical resistivity was measured at 49 locations as shown in FIG. 4.

[0109] The threading screw dislocations 9 were identified by a melt etching method. A potassium hydroxide (KOH) melt was used in the melt etching method. The temperature of the KOH melt was 500° C. or higher and 550° C. or lower. The etching time was 5 minutes or higher and 10 minutes or lower.

[0110] Immersing the silicon carbide substrate 100 in a KOH melt causes etch pits due to threading screw dislocations 9 to be formed on the main surface 1 of the silicon carbide substrate 100. The threading screw dislocations 9 form etch pits having a substantially hexagonal shape. The maximum length of the etch pits due to the threading screw dislocations 9 is typically 30 μm or more and 50 μm or less. The areal density of the threading screw dislocations 9 is the value obtained by dividing the number of etch pits due to the threading screw dislocations 9 by the measured area.

[0111] (Measurement results)

[0112]

[0113] Table 1 shows the impurity concentration at center 61 of first main surface 1 of each of silicon carbide substrates 100 of Samples 1 to 4. As shown in Table 1, the nitrogen concentration in each of silicon carbide substrates 100 of Samples 1 to 4 is 4×10 15 / cm 3 The vanadium concentration in each of silicon carbide substrates 100 of samples 1 to 4 was 1×10 12 / cm 3 It was less than.

[0114] The iron concentration in each of the silicon carbide substrates 100 of Samples 1, 2, and 3 was 2×10 14 / cm 3 The titanium concentration in each of the silicon carbide substrates 100 of Samples 1, 2, and 3 was less than 1×10 13 / cm 3 The chromium concentration in each of the silicon carbide substrates 100 of Samples 1, 2, and 3 was less than 5×10 13 / cm 3 The total of the iron concentration, titanium concentration, and chromium concentration in silicon carbide substrate 100 of sample 4 was less than 2.1 × 10 16 / cm 3 The concentrations of impurities such as titanium and nitrogen measured at center 61 of first main surface 1 were sufficiently low. Therefore, even if there is some distribution in the concentration of the impurities within first main surface 1, silicon carbide substrate 100 has high in-plane uniformity in electrical resistivity.

[0115] As shown in Table 1, the areal density of threading screw dislocations 9 on first main surface 1 of silicon carbide substrate 100 of samples 1 to 4 was 590 / cm 2 , 610 / cm 2 , 3200 / cm 2 and 3100 / cm 2 It was.

[0116] As shown in Table 1, the electrical resistivity at 27° C. of silicon carbide substrates 100 of Samples 1 to 4 was 1×10 in all measurement regions. 12 The average electrical resistivity of the silicon carbide substrates 100 of Samples 1 to 4 at 200° C. was 7.6×10 9 Ωcm, 1.0 x 10 10 Ωcm, 3.1 x 10 11 Ωcm and 5.2 × 10 11 The resistance was Ωcm.

[0117] The area percentage of the regions having an electrical resistivity within ±5% of the average value of the electrical resistivity of silicon carbide substrate 100 is calculated as the number of measurement regions having an electrical resistivity within ±5% of the average value of the electrical resistivity divided by the total number of measurement regions (49). As shown in Table 1, the area percentages of the regions having an electrical resistivity within ±5% of the average value of the electrical resistivity (200°C) of silicon carbide substrate 100 of samples 1 to 4 were 15 / 49 = 31%, 35 / 49 = 71%, 41 / 49 = 84%, and 38 / 49 = 78%, respectively.

[0118] The area percentage of the regions having an electrical resistivity within ±10% of the average value of the electrical resistivity of silicon carbide substrate 100 is calculated as the number of measurement regions having an electrical resistivity within ±10% of the average value of the electrical resistivity divided by the total number of measurement regions (49). As shown in Table 1, the area percentages of the regions having an electrical resistivity within ±10% of the average value of the electrical resistivity (200°C) of silicon carbide substrate 100 of samples 1 to 4 were 25 / 49 = 51%, 39 / 49 = 80%, 46 / 49 = 94%, and 44 / 49 = 90%, respectively.

[0119] From the above results, it was confirmed that compared to silicon carbide substrate 100 of sample 1, silicon carbide substrates 100 of samples 2 to 4 have high electrical resistivity at high temperatures and a higher area proportion of regions with high electrical resistivity at high temperatures.

[0120] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0121] 1 First main surface (main surface), 2 Second main surface, 3 Outer peripheral side surface, 4 Outer peripheral region, 5 Central region, 6 Outer edge, 7 Orientation flat portion, 8 Arc-shaped portion, 9 Threading screw dislocation, 10 Line defect, 11 First linear defect, 12 Second linear defect, 13 Third linear defect, 14 Region, 21 First end, 22 Second end, 24 Virtual straight line, 30 Nitride epitaxial layer, 31 Buffer layer, 32 Electron transit layer, 33 Electron supply layer, 41 Source electrode (electrode), 42 Drain electrode, 43 Gate electrode, 50 Growth surface, 51 Silicon atom, 52 Carbon atom, 56 Main body, 57 Silicon carbide crystal, 60 Measurement region, 61 Center, 98 Interstitial carbon, 99 Carbon vacancy, 100 Silicon carbide substrate, 101 First direction, 102 Second direction, 103 third direction, 130 crucible, 131 lid portion, 132 storage portion, 150 seed substrate, 151 third main surface, 152 fourth main surface, 156 silicon carbide raw material, 200 epitaxial substrate, 301 heating device, 400 semiconductor device, A2 linear distance, A3 third length, W1 maximum diameter, W2 distance, W3 third interval.

Claims

1. A ceramic substrate having a main surface, the maximum diameter of which is 100 mm or more, the main surface being composed of an outer edge, an outer peripheral region within 5 mm from the outer edge, and a central region surrounded by the outer peripheral region, and the electrical resistivity at any position in the central region at 27° C. is 1×10 12 At 200° C., the average electrical resistivity of the central region is 1×10 10 a surface area of ​​a region having an electrical resistivity within ±5% of the average value is 70% or more of a surface area of ​​the central region.

2. The structure includes threading screw dislocations, and the areal density of the threading screw dislocations in the central region is 500 cm -2 The silicon carbide substrate according to claim 1 .

3. The areal density of the threading screw dislocations in the central region is 1000 cm -2 The silicon carbide substrate according to claim 2 .

4. At the center of the main surface, the density of iron is 2×10 14 cm -3 The silicon carbide substrate according to claim 1 , wherein the thickness of the silicon carbide substrate is less than 100 μm.

5. At the center of the main surface, the density of titanium is 1×10 13 cm -3 The silicon carbide substrate according to claim 1 , wherein the thickness of the silicon carbide substrate is less than 100 nm.

6. At the center of the main surface, the density of chromium is 5×10 13 cm -3 The silicon carbide substrate according to claim 1 , wherein the thickness of the silicon carbide substrate is less than 100 nm.

7. A metal alloy comprising titanium, iron, and chromium, wherein the sum of the density of the titanium, the density of the iron, and the density of the chromium at the center of the main surface is 1×10 16 cm -3 Above 1 x 10 17 cm -3 The silicon carbide substrate according to claim 1 , wherein:

8. The semiconductor device includes nitrogen, and the concentration of the nitrogen at the center of the main surface is 1×10 16 cm -3 The silicon carbide substrate according to claim 1 , wherein:

9. A silicon carbide substrate according to any one of claims 1 to 8, comprising a line defect having a first end and a second end opposite the first end, the line defect being composed of a plurality of linear defects, the line defect being curved when viewed along a straight line perpendicular to the main surface, and the linear distance between the first end and the second end being 10 μm or more and 200 μm or less.

10. A method for manufacturing an epitaxial substrate, comprising the steps of: preparing a silicon carbide substrate according to any one of claims 1 to 9; and forming a nitride epitaxial layer on the silicon carbide substrate.

11. A method for manufacturing a semiconductor device, comprising the steps of: preparing a silicon carbide substrate according to any one of claims 1 to 9; forming a nitride epitaxial layer on the silicon carbide substrate; and forming an electrode on the nitride epitaxial layer.

Images