Bonding process

Abstract

Provided is a bonding process in which: a chip-shaped layer is partially placed on a substrate having metal wiring so as to form a recess; and thereafter, a chip having metal wiring is placed in the recess.

Description

Bonding Process

[0001] The present invention relates to a bonding process.

[0002] Conventionally, hybrid bonding (hereinafter sometimes referred to as "wafer-wafer bonding"), which bonds wafers having metal wiring together, has been used as one of the 3D bonding methods from the viewpoints of low resistance, high heat dissipation, low profile, fine bonding, etc. In wafer-wafer bonding, high precision can be achieved by using appropriate equipment and systems for aligning wafers with large surface areas such as 8 inches and 12 inches, and bump bonding of 5 μm or less (e.g., 1 μm, submicron) is possible.

[0003] On the other hand, there is also a growing demand for hybrid bonding (hereinafter sometimes referred to as "chip-on-wafer bonding"), which bonds a chip and a wafer having metal wiring. However, in chip-on-wafer bonding, the sizes of the chip and the wafer to be bonded are different, so there is a problem that the bond between the metal wiring on the chip surface and the metal wiring on the wafer surface (hereinafter sometimes referred to as "bump bonding") is misaligned due to misalignment of each chip. For this reason, the bump bonding limit for conventional chip-on-wafer bonding is 5 μm.

[0004] Here, as the Chip on Wafer Bonding, for example, a method for manufacturing a semiconductor device including a first semiconductor substrate having an opening hole formed on one surface and a first wiring layer formed on the other surface, a second semiconductor substrate configured inside the opening hole and having a second wiring layer formed on a surface facing the bottom surface of the opening hole, and wiring electrically connecting the first wiring layer and the second wiring layer is known (see, for example, Patent Document 1).

[0005] However, the method described in Patent Document 1 does not mention a process for preventing misalignment of each chip.

[0006] Japanese Patent Application Publication No. 2021-190440

[0007] An object of one embodiment of the present invention is to provide a bonding process that can prevent chip misalignment in chip-on-wafer bonding.

[0008] Means for solving the above problems are as follows: <1> A bonding process comprising partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess. <2> The bonding process according to <1>, wherein the chip-shaped layer is a resin layer containing a resin, and the resin layer is formed by coating, exposing, and developing. <3> The bonding process according to <1> or <2>, which is carried out in a reducing atmosphere. <4> The bonding process according to any one of <1> to <3>, wherein at least one of pressure and heat is applied after placing the chip having metal wiring in the recess.

[0009] According to one embodiment of the present invention, it is possible to provide a bonding process that can prevent chip misalignment during chip-on-wafer bonding.

[0010] 1A-1C are schematic diagrams illustrating an example of a wafer in a bonding process of an embodiment of the present invention, a step of placing a chip-shaped layer in a bonding process of an embodiment of the present invention, and a step of placing a chip in a bonding process of an embodiment of the present invention.

[0011] (Bonding Process) The bonding process according to this embodiment preferably includes a step of partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess, and further includes other steps such as pressurizing and heating as necessary. In this specification, a circular substrate having metal wiring and a substrate is referred to as a "wafer," and a chip-shaped substrate having metal wiring and a substrate is referred to as a "chip." The term "wafer" also includes a printed circuit board.

[0012] 1 to 3 are schematic diagrams showing an example of a bonding process according to the present embodiment. As shown in FIG. 1, the bonding process according to the present embodiment is performed by a wafer 10 including a substrate 11A, a SiO ２ 2, a chip-shaped layer 20 is placed partially on the wafer 10 to form a recess 30. Next, as shown in FIG. 3, a substrate 11B, a SiO ２ A chip 40 having a film 12B and metal wiring 13B is placed on the recess 30. By these steps, the chip can be bonded while preventing misalignment.

[0013] <Wafer> The wafer has metal wiring and a substrate, and may further include SiO ２ It is preferable that the substrate has a membrane.

[0014] The metal wiring is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include gold (Au), silver (Ag), nickel (Ni), copper (Cu), titanium (Ti), aluminum (Al), etc. These may be used alone or in combination of two or more.

[0015] The width of the metal wiring is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 100 nm or more and 1,000 nm or less.

[0016] -Substrate- The substrate is not particularly limited and can be appropriately selected depending on the purpose. For example, silicon (Si), silicon oxide (SiO), silicon carbide (SiC), sapphire (Al ２ O ３ ), compound semiconductors, etc. When the substrate is a printed circuit board, examples of the substrate include glass epoxy, paper epoxy, paper phenol, plastic film, etc.

[0017] The thickness of the substrate is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 1 μm or more and 1,000 μm or less.

[0018] -Chip-shaped layer- The chip-shaped layer is not particularly limited and can be appropriately selected depending on the purpose, and examples include a resist film, a metal film, and an organic film. Among these, a resist film is preferred from the viewpoint of ensuring the flatness of the substrate and from the viewpoint of facilitating removal of the chip-shaped layer when the film is no longer needed after bonding. By providing the chip-shaped layer, a recess can be formed on the wafer, and by providing a chip so that it fits into the formed recess, bonding can be performed without causing chip misalignment. The chip-shaped layer may or may not be removed after bonding.

[0019] --Resist Film-- The resist film is a resin layer containing a resin, and may further contain fillers, organic particles, etc., as needed. The resist film containing fillers, organic particles, etc., is excellent in maintaining the shape of the recesses and the shape when pressure is applied. The resist film may be either positive or negative, but a positive type is preferred from the viewpoint of removability after bonding.

[0020] The resin is not particularly limited and can be appropriately selected depending on the purpose. For example, novolac-based, resol-based, PHS-based, acrylic-based, siloxane-based, urethane-based, or amide-based skeletons can be used, and an acetal group, a secondary or tertiary ester group, a sulfonate ester group, or an interpolymer bonding group can be combined with an acid generator. Also available are positive resists using naphthoquinone diazide and its derivatives, and negative resists combining novolac-based, resol-based, PHS-based, acrylic-based, siloxane-based, urethane-based, or amide-based resins with methylol compounds, acrylic compounds, methacrylic compounds, acrylamide compounds, methacrylamide compounds, styrene compounds, vinyl compounds, or the like, an acid generator, or a radical generator.

[0021] The method for forming recesses by applying the resist film is not particularly limited and can be appropriately selected depending on the purpose. Examples include a method in which a composition containing the resin is applied, and then exposure and development are performed to apply a resist film to form recesses, and a method in which a film resist is applied.

[0022] The exposure method is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include a method of applying energy by light from a light source such as a stepper, proxy exposure, direct writing exposure, etc. The light source may be an electron beam, UV light, visible light, or infrared light.

[0023] The development method is not particularly limited and can be appropriately selected depending on the purpose. For example, development methods using an organic base, an inorganic base, an organic solvent, water, an aqueous solution, or the like can be used.

[0024] --Metal Film-- The metal film is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include metals such as titanium (Ti), nickel (Ni), silver (Ag), copper (Cu), tungsten (W), etc. The method for providing the metal film and forming recesses is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include a method of forming recesses by performing etching after plating, vapor deposition, or sputtering.

[0025] --Organic Film-- The organic film can be made of the same material as the resist film described above, and can be formed by the same method as that for forming the recesses.

[0026] The thickness of the chip-shaped layer is not particularly limited and can be appropriately selected depending on the purpose as long as it does not cause the chip positional deviation described below, but is preferably 0.5 μm or more and 200 μm or less, more preferably 1 μm or more and 150 μm or less, and particularly preferably 5 μm or more and 100 μm or less.

[0027] <Chip> The chip has metal wiring and a substrate, and may further include SiO ２ It is preferable that the substrate has a membrane.

[0028] Metal wiring, substrate, and SiO ２ The film may be the same as that used for the wafer described above.

[0029] The chip is placed so as to fit into a recess formed by placing the chip-shaped layer, thereby enabling bonding without causing misalignment of the chip.

[0030] The bonding of the chip and the wafer is preferably carried out in a reducing atmosphere, which is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include formic acid and hydrogen.

[0031] After the chip is fitted into the recess, it is preferable to apply pressure and / or heat using a flip chip bonder or the like having ceramic heaters attached to the head and stage.

[0032] The heating temperature is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 100° C. or higher and 300° C. or lower. The heating temperature refers to the surface temperature of the head and stage of the flip chip bonder.

[0033] The load for the pressure application is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 1 N or more and 200 N or less.

[0034] Examples of this embodiment will be described below, but this embodiment is not limited to these examples.

[0035] Example 1 Metal wiring (Au / Ni / Cu / Ti) and SiO ２ A chip-shaped layer was partially placed on an 8-inch wafer having a film (thickness: 500 nm) and a substrate (Si substrate, thickness: 525 μm) to form a recess. As the chip-shaped layer, a positive resist with a thickness of 5 μm was formed in an isotropic direction at 100.6% of the size. Then, metal wiring (Au / Ni / Cu / Ti) and SiO ２ A 5 mm x 5 mm chip having a film (thickness: 500 nm) and a substrate (Si substrate, thickness: 525 μm) was placed. ２The film was formed by electroplating Au (5 μm diameter) bonding sites with 100 pins at a 20 μm pitch on Au / Ni / Cu / Ti wiring formed by electron beam evaporation. The bonding sites were then polished by CMP to a surface thickness of 5 nm or less. Bonding was then performed using a flip-chip bonder (FC2000, Toray Engineering Co., Ltd.). Both the head and stage of the flip-chip bonder were equipped with ceramic heaters, and the Au bumps on the chip and wafer were brought into contact under conditions of a temperature of 30°C for both the head and stage, a load of 100 N, and a pressure time of 5 seconds. Next, while maintaining pressure, the temperatures of both the head and stage of the flip-chip bonder were raised to 150°C, and then held for 300 seconds. Finally, the bonder head temperature was raised to 250°C for hardening.

[0036] Comparative Example 1 Bonding was carried out in the same manner as in Example 1, except that the chip-shaped layer was not formed.

[0037] In Example 1 and Comparative Example 1, the positional deviation of the chip was measured and evaluated by the following method.

[0038] In Example 1 and Comparative Example 1, the chip and wafer after bonding were cut, and the average value of the overlapping area of ​​10 points was calculated for the deviation of 5 μm of the Au metal bond and Cu metal bond on the chip and wafer in the cross section. The chip position deviation was evaluated based on the average overlapping area and the following evaluation criteria. The results are shown in Table 1 below. [Evaluation Results] ○: Average overlapping area is 90% or more △: Average overlapping area is 80% or more but less than 90% ×: Average overlapping area is less than 80%

[0039]

[0040] This application claims priority based on Japanese Patent Application No. 2023-140895, filed with the Japan Patent Office on August 31, 2023, and incorporates the entire contents of said application by reference.

[0041] 10 Wafer 11A, 11B Substrate 12A, 12B SiO ２Films 13A, 13B Metal wiring 20 Chip-shaped layer 30 Recess 40 Chip

Claims

1. A bonding process characterized by partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess.

2. The bonding process according to claim 1, wherein the chip-shaped layer is a resin layer containing a resin, and the resin layer is formed by coating, exposing, and developing.

3. The joining process according to claim 1 or 2, carried out in a reducing atmosphere.

4. The bonding process according to claim 1 or 2, wherein at least one of pressure and heat is applied after the chip having the metal wiring is placed in the recess.

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