Logical unit circuit and adder circuit

Abstract

Disclosed in the present application are a logical unit circuit and an adder circuit, which are applied to a multi-bit adder. A logical operation unit circuit is used for realizing ! P logic and ! G logic, and comprises two NAND gates and one OR gate, wherein two inputs of one NAND gate are respectively ai and bi, an output thereof is ! Gi, and ! Gi is output to one input of the other NAND gate; two inputs of the OR gate are respectively ai and bi, and an output thereof is the other input of the other NAND gate; and two inputs of the other NAND gate are respectively the output of one NAND gate and an output of the OR gate, and an output thereof is ! Pi, i representing an ith bit in a multi-bit adder.

Description

A logic unit circuit and adder circuit Technical Field

[0001] The present application relates to, but is not limited to, digital circuit technology, and in particular to a logic unit circuit and an adder circuit. Background Art

[0002] As the most basic logical unit, adders are widely used in various types of processors. In circuit systems, adders are primarily responsible for calculations and indexing. They are also crucial components of other hardware logical units, such as multipliers and subtractors. Adders can be categorized based on their circuit topology. Common adder topologies include ripple carry and carry-lookahead.

[0003] Adders of different topologies have varying area and speed requirements. With the increasing demand for high operating frequencies and low power consumption in processor cores, higher requirements are being placed on adders. Balancing power consumption and speed has become a pressing issue: how to maintain high speed while reducing power consumption? Or, in specific speed scenarios, adopting a topology with a smaller area and lower power consumption.

[0004] SUMMARY OF THE INVENTION

[0005] The present application provides a logic unit circuit and an adder circuit, which have a simple circuit structure and can well balance the relationship between power consumption and speed.

[0006] The embodiment of the present application provides a logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement !P logic and !G logic, including: two NAND gates and one OR gate; wherein,

[0007] The two inputs of a NAND gate are a i 、b i , the output is !G i and will! G i The output is fed to one input of another NAND gate;

[0008] The two inputs of the OR gate are a i 、b i , the output is the other input of another NAND gate;

[0009] The two inputs of another NAND gate are the output of a NAND gate and the output of the OR gate, and the output is! P i ;

[0010] Here, i represents the i-th bit in the multi-bit addition.

[0011] The embodiment of the present application further provides a logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement !G logic and !P logic, including: an AND-NOR gate, a NAND gate;

[0012] The three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j ;

[0013] The two inputs of the NAND gate are P k-1:j 、The P i:k , the output of the NAND gate is! P i:j ;

[0014] Wherein, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.

[0015] The embodiment of the present application further provides a logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement G logic and P logic, including: an OR-NAND gate, a NOR gate;

[0016] The three inputs of the OR-NAND gate are: i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j ;

[0017] The two inputs of the NOR gate are respectively! k-1:j , as mentioned! P i:k , the output of the NOR gate is P i:j ;

[0018] Wherein, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.

[0019] The embodiment of the present application further provides a logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement P logic and G logic, including: two NOR gates and one AND gate; wherein,

[0020] The two inputs of a NOR gate are a i 、b i , the output is one input of another NOR gate;

[0021] The two inputs of the AND gate are a i 、b i , the output is G i , and G i The output is fed to the other input of another NOR gate;

[0022] The two inputs of another NOR gate are the output of a NOR gate and the output of the AND gate, and the output is P i ;

[0023] Here, i represents the i-th bit in the multi-bit addition.

[0024] An embodiment of the present application also provides an adder circuit, comprising any combination of the above-mentioned logic operation unit circuits.

[0025] In an exemplary embodiment, the adder is an LFA adder or a BK adder.

[0026] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected arithmetic units, wherein:

[0027] The first-stage operation unit includes n+1 ninth unit circuits described in the embodiment of the present application and n+1 NOT gates; the output of each ninth unit circuit described in the embodiment of the present application is connected to the input of a NOT gate, and the output of each NOT gate serves as the output of the first-stage operation unit;

[0028] The second-level arithmetic unit includes A second unit circuit and a third unit circuit; wherein the second unit circuit is used to implement P i:j =and(P i-1:j ,P i:k ), G i:j =ao(G i:k ,P i:k ,G k-1:j ); The third unit circuit is used to implement G i:j =ao(G i:k ,P i:k ,G k-1:j );

[0029] The third-level arithmetic unit includes the second unit circuits and two the third unit circuits;

[0030] The fourth-level arithmetic unit includes the second unit circuits and four the third unit circuits;

[0031] The fifth-level arithmetic unit includes the second unit circuits and eight the third unit circuits;

[0032] The sixth level arithmetic unit includes the third unit circuit;

[0033] The seventh-level operation unit includes n fourth unit circuits; wherein, the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after the adder operation.

[0034] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected arithmetic units, wherein:

[0035] The first-level operation unit includes n+1 ninth unit circuits described in the embodiment of the present application;

[0036] The second-level arithmetic unit includes The sixth unit circuit and the eighth unit circuit described in the embodiment of the present application are respectively: wherein the eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively: i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;

[0037] The third-level arithmetic unit includes A NOT gate, The fifth unit circuit and two seventh unit circuits described in the embodiment of the present application; wherein the seventh unit circuit is used to implement! G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;

[0038] The fourth-level arithmetic unit includes A NOT gate, The sixth unit circuit described in the embodiment of the present application and four of the eighth unit circuits;

[0039] The fifth-level arithmetic unit includes A NOT gate, The fifth unit circuit described in the embodiment of the present application and eight of the seventh unit circuits;

[0040] The sixth level arithmetic unit includes The eighth unit circuit and five NOT gates;

[0041] The seventh-level operation unit includes n fourth unit circuits and 11 NOT gates; wherein, the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after the adder operation.

[0042] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected arithmetic units, wherein:

[0043] The first-stage operation unit includes n+1 ninth unit circuits described in the embodiment of the present application and n+1 NOT gates; the output of each ninth unit circuit described in the embodiment of the present application is connected to the input of a NOT gate, and the output of each NOT gate serves as the output of the first-stage operation unit;

[0044] The second-level arithmetic unit includes A second unit circuit and a third unit circuit; wherein the second unit circuit is used to implement P i:j =and(P i-1:j ,P i:k ), G i:j =ao(P i:k ,G k-1:j ,G i:k ); The third unit circuit is used to implement G i:j =ao(P i:k ,G k-1:j ,G i:k );

[0045] The third-level arithmetic unit includes the second unit circuit and one the third unit circuit;

[0046] The fourth-level arithmetic unit includes the second unit circuit and one the third unit circuit;

[0047] The fifth-level arithmetic unit includes one of the second unit circuits and one of the third unit circuits;

[0048] The sixth-stage arithmetic unit includes two of the third unit circuits;

[0049] The seventh-level arithmetic unit includes the third unit circuit;

[0050] The eighth-level arithmetic unit includes the third unit circuit;

[0051] The ninth level arithmetic unit includes the third unit circuit;

[0052] The tenth-level operation unit includes n fourth unit circuits; wherein, the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after the adder operation.

[0053] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected arithmetic units, wherein:

[0054] The first-level operation unit includes n+1 ninth unit circuits described in the embodiment of the present application;

[0055] The second-level arithmetic unit includes The sixth unit circuit and the eighth unit circuit described in the embodiment of the present application are respectively: wherein the eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively: i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;

[0056] The third-level arithmetic unit includes The fifth unit circuit and the seventh unit circuit described in the embodiment of the present application are configured to implement G logic, including an AND-NOR gate, wherein the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;

[0057] The fourth-level arithmetic unit includes the sixth unit circuit described in the embodiment of the present application and one eighth unit circuit;

[0058] The fifth-stage operation unit includes one fifth unit circuit described in the embodiment of the present application and one seventh unit circuit;

[0059] The sixth-level arithmetic unit includes two eighth-unit circuits and a NOT gate;

[0060] The seventh-level arithmetic unit includes two seventh unit circuits and two NOT gates, and one eighth unit circuit;

[0061] The eighth-level arithmetic unit includes four eighth unit circuits and four NOT gates, and three seventh unit circuits;

[0062] The ninth level arithmetic unit includes The eighth unit circuit and 8 NOT gates;

[0063] The tenth-level operation unit includes n fourth unit circuits and a NOT gate; wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after the adder operation.

[0064] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0065] Summary of the Figures

[0066] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0067] FIG1 is a schematic diagram of a circuit topology structure of a logic operation unit that implements P logic and G logic in one embodiment;

[0068] FIG2 is a schematic diagram of a circuit topology structure of an XOR gate in an embodiment of the present application;

[0069] FIG3 is a schematic diagram of a circuit topology structure of a logic operation unit implementing P logic and G logic in another embodiment;

[0070] FIG4 is a schematic diagram of a circuit topology structure of a logic operation unit implementing !P logic and !G logic in one embodiment;

[0071] FIG5 is a schematic diagram of a circuit topology structure of an XNOR gate in an embodiment of the present application;

[0072] FIG6 is a schematic diagram of a circuit topology structure of a logic operation unit implementing !P logic and !G logic in another embodiment;

[0073] FIG7 is a schematic diagram of a circuit topology structure of a core logic operation unit in an adder according to an embodiment;

[0074] FIG8( a ) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in one embodiment;

[0075] FIG8( b ) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in another embodiment;

[0076] FIG9( a ) is a schematic diagram of a circuit structure for implementing continuous two-stage G logic in one embodiment;

[0077] FIG9( b ) is a schematic diagram of a circuit structure for implementing continuous two-stage G logic in another embodiment;

[0078] FIG10 is a schematic diagram of a topological structure of an LFA adder circuit;

[0079] FIG11( a ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the first unit circuit in the LFA adder circuit shown in FIG10 ;

[0080] FIG11( b ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the second unit circuit in the LFA adder circuit shown in FIG10 ;

[0081] FIG11( c ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the third unit circuit in the LFA adder circuit shown in FIG10 ;

[0082] FIG11( d ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the fourth unit circuit in the LFA adder circuit shown in FIG10 ;

[0083] FIG12( a ) is a schematic diagram of the circuit structure and corresponding schematic symbols of a first replacement unit circuit in an LFA adder circuit according to another embodiment;

[0084] FIG12( b ) is a schematic diagram of the circuit structure and corresponding schematic symbols of a second replacement unit circuit in an LFA adder circuit according to another embodiment;

[0085] FIG12( c ) is a schematic diagram of the circuit structure and corresponding schematic symbols of a third replacement unit circuit in an LFA adder circuit according to another embodiment;

[0086] FIG12( d ) is a schematic diagram of the circuit structure and corresponding schematic symbols of a fourth replacement unit circuit in an LFA adder circuit according to another embodiment;

[0087] FIG12( e ) is a schematic diagram of the circuit structure and corresponding schematic symbols of a fifth replacement unit circuit in an LFA adder circuit according to another embodiment;

[0088] FIG13 is a schematic diagram of the topological structure of a first embodiment of an LFA adder circuit;

[0089] FIG14 is a schematic diagram of the topological structure of a second embodiment of an LFA adder circuit;

[0090] FIG15 is a schematic diagram of the topological structure of a third embodiment of an LFA adder circuit;

[0091] FIG16 is a schematic diagram of a topological structure of a BK adder circuit;

[0092] FIG17 is a schematic diagram of the topological structure of a first embodiment of a BK adder circuit;

[0093] FIG18 is a schematic diagram of the topological structure of a second embodiment of a BK adder circuit;

[0094] FIG19 is a schematic diagram of the topological structure of the third embodiment of the BK adder circuit.

[0095] Details

[0096] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0097] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0098] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0099] In the mainstream adder topology, the core logic units include Propagate logic (abbreviated as P logic) and Generate logic (abbreviated as G logic). In the adder topology derived by P logic and G logic, there is a logic operation unit circuit as shown in Figure 1. In Figure 1, P i =xor(a i ,b i ), G i =and(a i ,b i ), where i represents the i-th bit in the multi-bit addition, a i 、b iThey represent the i-th bit of data a and data b involved in the operation, respectively. xor represents an exclusive-or gate operation, and and represents an and gate operation.

[0100] In order to implement equivalent logic using a circuit with the simplest structure and the least logic gates as much as possible, an embodiment of the present application provides a logic operation unit circuit that uses logic sharing to reduce circuits as much as possible.

[0101] In an exemplary embodiment, FIG2 is a schematic diagram of the circuit topology of the XOR gate in the embodiment of the present application. As shown in FIG2 , the XOR gate in this embodiment includes two NOR gates and one AND gate; the two inputs of one NOR gate are a and b respectively. i 、b i , the output is one input of another NOR gate; the two inputs of the AND gate are a i 、b i , the output is the other input of another NOR gate; the output of another NOR gate is P i .

[0102] As can be seen from Figure 2, the two inputs of the AND gate are a i 、b i , as shown in Figure 1, the output of this AND gate is G i , that is, in the logic operation unit circuit shown in Figure 2, G is generated at the same time i and P i The inventor of this application cleverly utilized this point and adjusted Figure 2 to obtain a circuit topology diagram of a logic operation unit that implements P logic and G logic in another embodiment as shown in Figure 3. As shown in Figure 3, in one embodiment, the logic operation unit circuit that implements P logic and G logic may include: two NOR gates and one AND gate; the two inputs of one NOR gate are respectively a i 、b i , the output is one input of another NOR gate; the two inputs of the AND gate are a i 、b i , the output is G i , G i =and(a i ,b i ), and G i Output to the other input of another NOR gate; the output of the other NOR gate is P i , P i =nor(and(a i ,b i ),nor(a i ,b i)). The logic operation unit circuit shown in FIG3 can also be regarded as including a NOR gate and an AND-NOR (AOI) gate, wherein, as shown in FIG6, the OAI gate is composed of an AND gate and a NOR gate, P i It can also be expressed as: P i =aoi(nor(a i ,b i ),a i ,b i ).

[0103] Comparing the logic operation unit circuit for implementing P logic and G logic shown in FIG1 and the other logic operation unit circuit for implementing P logic and G logic shown in FIG3, the XOR gate in FIG1 is a complex logic, and both the area used and the power consumption are greater than two NOR gates. In other words, the other logic operation unit circuit for implementing P logic and G logic shown in FIG3 has a smaller area and lower power consumption. In other words, the logic operation unit circuit for implementing P logic and G logic provided by the embodiment of the present application has a simple structure, is better in terms of area used and delay, and strikes a good balance between power consumption and speed.

[0104] From the relevant technology, we know that there is the following P logical relationship: P i:j =and(P i:k ,P k-1:j ), P i:j =nor(!P i:k ,! P k-1:j ), from the above P logical relationship, we can see that P i:j The logical value does not matter whether the input value is P i:k Still! i:k , is P k-1:j Still! k-1:j From the related art, we know that there is the following G logical relationship: G i:j =aoi(G i:k ,P i:k ,P k-1:j ), G i:j =oai(!G i:k ,! P i:k ,! P k-1:j ), from the above G logical relationship, we can see that G i:j The logical value does not matter whether the input value is G i:k Still! G i:k , is P i:k Still! i:k , is P k-1:j Still! k-1:j According to this deduction, modifying Figure 1 can get the implementation shown in Figure 4! i Logical AND! G iSchematic diagram of the logic circuit structure.

[0105] As shown in Figure 4, it is achieved! i Logical AND! G i The logic circuit structure includes a NAND gate and an XNR gate. i =xnr(a i ,b i ),! G i =nand(a i ,b i In order to implement equivalent logic using the simplest structure and the least logic gates possible, an embodiment of the present application provides a logic operation unit circuit that uses logic sharing to reduce circuits as much as possible.

[0106] In an exemplary embodiment, FIG5 is a schematic diagram of the circuit topology of the XNOR gate in the embodiment of the present application. As shown in FIG5 , the XNOR gate in the embodiment includes two NAND gates and one OR gate; the two inputs of one NAND gate are a and b respectively. i 、b i , the output is one input of another NAND gate; the two inputs of the OR gate are a i 、b i , the output is the other input of another NAND gate; the two inputs of another NOR gate are the output of a NOR gate and the output of the AND gate, and the output is! P i .

[0107] As can be seen from Figure 5, the two inputs of one of the NAND gates are a i 、b i , as shown in Figure 4, the output of this NAND gate is! G i , that is to say, in the logic operation unit circuit shown in FIG5, G is generated at the same time! i and! P i The inventors of this application cleverly utilized this point and adjusted Figure 5 to obtain another circuit topology diagram of a logic operation unit that implements !P logic and !G logic, as shown in Figure 6. In one embodiment, the logic operation unit circuit that implements !P logic and !G logic may include: two NAND gates and one OR gate; the two inputs of one NAND gate are respectively a i 、b i , the output is !G i ,! G i =nand(a i ,b i ) and will! G i The output is given to one input of another NAND gate; the two inputs of the OR gate are a i 、b i, the output is the other input of another NAND gate; the two inputs of another NAND gate are the output of a NAND gate and the output of the OR gate, and the output is! P i ,! P i =nand(nand(a i ,b i ),or(a i ,b i )). The logic operation unit circuit shown in FIG6 can also be regarded as including a NAND gate and an OR-NAND (OAI) gate, wherein, as shown in FIG6, the OAI gate is composed of an OR gate and a NAND gate. i It can also be expressed as: !P i =oai(nand(a i ,b i ),a i ,b i ).

[0108] Comparing the implementation of the logic operation unit circuit shown in Figure 4, which uses P logic and G logic, with the alternative implementation of the logic operation unit circuit shown in Figure 6, which uses P logic and G logic, the XNOR gate in Figure 4 is complex logic, requiring more area and consuming more power than an OR-NAND (OAI) gate. In other words, the alternative implementation of the logic operation unit circuit shown in Figure 6, which uses P logic and G logic, requires less area and consumes less power. In other words, the logic operation unit circuit implementing the logic operation unit circuit provided by the present embodiment uses logic sharing to reduce circuitry, resulting in a simple circuit structure, improved area and latency, and a good balance between power consumption and speed.

[0109] Because G logic and !G logic, P logic and !P logic can be flexibly converted without incurring additional circuit overhead, the difference between them lies solely in the logical function; the area and delay are the same. In other words, while the circuits shown in Figures 1 and 4 have different logical functions, the area and delay are the same. In the embodiment of this application, the logic operation unit circuit shown in Figure 6 for implementing !P logic and !G logic is compared to the logic operation unit circuit shown in Figure 3 for implementing P logic and G logic. The circuit structure shown in Figure 6 includes a NAND gate and an OAI gate, while the circuit structure shown in Figure 3 includes two NOR gates and one AND gate. The area and delay of a NAND gate and a NOR gate are comparable, while the area and delay of an OAI gate are smaller than those of a NOR gate plus an AND gate. Therefore, of the logic operation unit circuits shown in Figures 3 and 6 in the embodiment of this application, the logic operation unit circuit shown in Figure 6 for implementing !P logic and !G logic has a better area and delay.

[0110] To achieve equivalent logic using the simplest possible circuit structure and the fewest logic gates, this application proposes a logic unit circuit, wherein a P logic circuit includes a P logic circuit composed of a NOR gate and / or a NAND gate to achieve P logic or P NOT (!P) logic; and a G logic circuit includes a G logic circuit composed of an AND-NOR (aoi) gate and / or an OR-NAND (oai) gate to achieve G logic or !G logic.

[0111] In an exemplary embodiment, taking continuous two-level P logic as an example, FIG8(a) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in one embodiment, and FIG8(b) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in another embodiment. The two circuit structures of FIG8(a) and FIG8(b) are equivalent, wherein i>k>m>n>j, i, k, m, n, j respectively represent the bit (bit) of the input data, such as i represents the i-th bit. As shown in FIG8(a), the circuit structure for implementing continuous two-level P logic in one embodiment is composed of three AND gates, and as shown in FIG8(b), the circuit structure for implementing continuous two-level P logic in another embodiment is composed of two NAND gates and one NOR gate. In one embodiment, the circuit structure for implementing continuous two-level P logic of P logic includes: two NAND gates and a NOR gate; wherein, the two inputs of one NAND gate are P, respectively. i:k 、P k-1:m , the output is !P i:m ; The two inputs of the other NAND gate are P m-1:n 、P n-1:j , the output is !P m-1:j ; The two inputs of the NOR gate are the outputs of the two NAND gates! i:m and! P m-1:j , the output of the NOR gate is P i:j , where i>k>m>n>j, P i:j =nor(nand(P i:k ,P k-1:m ),nand(P m-1:n ,P n-1:j )).

[0112] In the two circuit structures shown in Figures 8(a) and 8(b), compared with the AND gate and the NAND gate, the AND gate uses an additional area of ​​1 inv and has an additional delay of 1 inv. Compared with the NAND gate and the NOR gate, the areas used and the delays used by the two are almost the same. So, overall, the circuit structure of the continuous two-stage P logic in another embodiment shown in Figure 8(b) saves 3 inv in area compared to the circuit structure of the continuous two-stage P logic in one embodiment shown in Figure 8(a), and the longest path delay of the circuit is reduced by 2 inv. It can be seen that the P logic provided in the embodiment of the present application uses the simplest structure and the least logic gates to achieve the same function as the typical P logic. In other words, the P logic circuit structure provided in the embodiment of the present application is simple, better in area and delay, and well balances the relationship between power consumption and speed.

[0113] In an exemplary embodiment, taking continuous two-stage G logic as an example, FIG9(a) is a schematic diagram of the circuit structure of continuous two-stage G logic in one embodiment, and FIG9(b) is a schematic diagram of the circuit structure of continuous two-stage G logic in another embodiment. The two circuit structures of FIG9(a) and FIG9(b) are equivalent, wherein i>k>m>n>j. Assume that the expression of FIG9(a) is: G i:j =function1(G i:k ,P i:k ,G k-1:m ,G m-1:n ,P m-1:n ,G n-1:j ,P i:m ). The expression of Figure 9(b) is: G i:j =function2(G i:k ,P i:k ,G k-1:m ,G m-1:n ,P m-1:n ,G n-1:j ,! P i:m ). Comparing the two expressions, the results on the left side of the two equations are the same, and there is one different input item on the right side of the two equations. The different part is P i:m and! P i:m According to relevant technology, P i:m =and(P i:k ,P k-1:m ),! P i:m =nor(P i:k ,P k-1:m ), therefore, under the premise of the same input items, P i:m and! P i:m The implementation can be converted using AND gate and NOR gate.

[0114] FIG7 is a schematic diagram of the circuit topology of the core logic operation unit in an adder in an embodiment. As shown in FIG7 , the P logic is composed of an AND gate. i:j =and(P i:k ,P k-1:j ); G logic consists of an AND-OR gate, G i:j =or(G i:k ,and(P i:k ,G k-1:j ))=ao(G i:k ,P i:k ,G k-1:j ); wherein, i>k>j, i, k, j respectively represent the bit of the input data, such as i represents the i-th bit.

[0115] As shown in FIG9(a), in one embodiment, the continuous two-stage G logic circuit structure is composed of three ao gates. As shown in FIG9(b), in another embodiment, the continuous two-stage G logic circuit structure is composed of two and-or-invert (aoi) gates and one or-and-invert (oai) gate. In one embodiment, the continuous two-stage G logic circuit structure for implementing G logic includes: two and-or-invert gates and an or-and-invert gate; wherein, the three inputs of one of the and-or-invert gates are P i:k , G k-1:m and G i:k , the output is !G i:m ; The three inputs of the other AND-NOR gate are P m-1:n , G n-1:j and G m-1:n , the output is !G m-1:j ; The three inputs of the OR-NAND gate are the outputs of the two AND-NOR gates, namely! G i:m and! G m-1:j , and! P i:m , the output is G i:j , where i>k>m>n>j,

[0116] In the two circuit structures shown in Figures 9(a) and 9(b), compared with the aoi gate, the ao gate has an area of ​​1 more inv and a delay of 1 more inv. Compared with the aoi gate and the oai gate, the two have the same area and delay. So, overall, the circuit structure of the continuous two-stage G logic in another embodiment shown in Figure 9(b) saves 3 inv in area and reduces the longest path delay of the circuit by 2 inv compared to the continuous two-stage G logic circuit structure shown in Figure 9(a). It can be seen that the P logic provided in the embodiment of the present application uses the simplest structure and the least logic gates to achieve the same function as the typical G logic. In other words, the G logic circuit structure provided in the embodiment of the present application is simple, better in area and delay, and has a good balance between power consumption and speed.

[0117] The adder is the most basic logical operation unit. In mainstream adder topologies, the core logic units include P logic circuits and G logic circuits. To reduce the adder circuit's footprint, lower its power consumption, and minimize its circuit delay, thereby enabling the adder circuit to operate at a higher frequency and achieve better performance, an embodiment of the present application provides an adder circuit, wherein the P logic circuit utilizes the P logic circuit provided in any of the embodiments of the present application, and the G logic circuit utilizes the G logic circuit provided in any of the embodiments of the present application.

[0118] In an exemplary embodiment, an LFA adder is used as an example, where LFA is the abbreviation of Lander Fischer Adder, and the LFA adder is derived using PG logic. FIG10 is a schematic diagram of the topology of an LFA adder circuit in an embodiment. The logic circuit represented by the black hexagonal schematic symbol in FIG10 is the first unit circuit shown in FIG11(a). The first unit circuit is used to generate P logic, G logic, and G i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i The logic circuit represented by the black square symbol in FIG10 is the second unit circuit shown in FIG11(b). The second unit circuit is used to implement P i:j =and(P i-1:j ,P i:k ), G i:j =ao(G i:k ,P i:k ,G k-1:j). The logic circuit represented by the gray square schematic symbol in FIG10 is the third unit circuit shown in FIG11(c). The third unit circuit is used to implement G i:j =ao(G i:k ,P i:k ,G k-1:j ). The logic circuit represented by the gray hexagonal schematic symbol in FIG10 is the fourth unit circuit shown in FIG11(d). The fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i The logic circuit represented by the black square symbol in FIG10 is a P logic + G logic circuit. The logic circuit represented by the black hexagonal symbol in FIG10 is the logic operation unit circuit shown in FIG1.

[0119] In one embodiment, to reduce the area of ​​the LFA adder circuit, lower its power consumption, and minimize its circuit delay, as shown in FIG13 , a combination of the fifth unit circuit (black pentagon symbol) shown in FIG12(a) and the sixth unit circuit (black diamond symbol) shown in FIG12(b) is used, as well as a combination of the seventh unit circuit (gray pentagon symbol) shown in FIG12(c) and the eighth unit circuit (gray diamond symbol) shown in FIG12(d). The logic circuit represented by the black pentagonal symbol in FIG13 is a P logic + G logic circuit implemented using the P logic circuit and G logic circuit provided in the embodiment of the present application shown in FIG12(a). The logic circuit represented by the black diamond symbol in FIG13 is a P logic + G logic circuit implemented using the P logic circuit and G logic circuit provided in the embodiment of the present application shown in FIG12(b). The logic circuit represented by the gray pentagonal symbol in FIG13 is a G logic circuit implemented using the G logic circuit provided in the embodiment of the present application shown in FIG12(c). The logic circuit represented by the gray diamond schematic symbol in FIG13 is a G logic circuit implemented by the G logic circuit provided in an embodiment of the present application as shown in FIG12( d ).

[0120] In one embodiment, FIG12(c) provides an implementation! The circuit structure of the G logic is the seventh unit circuit, as shown in FIG12(c). The G logic circuit in this embodiment includes an AND-NOR gate, and the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , that is! G i:j =aoi(G i:k ,Pi:k ,G k-1:j ), where i>k>j.

[0121] In one embodiment, FIG12(a) provides a circuit structure for implementing !P logic and !G logic, i.e., the fifth circuit unit. As shown in FIG12(a), the P logic + G logic circuit in this embodiment further includes a NAND gate based on FIG12(c). As shown in FIG12(a), the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j ,! G i:j =aoi(G i:k ,P i:k ,G k-1:j );The two inputs of the NAND gate are P k-1:j 、P i:k , the output of the NAND gate is! P i:j ,! P i:j =nand(P k-1:j ,P i:k ).

[0122] In one embodiment, FIG12(d) provides a circuit structure for implementing G logic, namely, the eighth circuit unit. As shown in FIG12(d), the corresponding schematic symbol is a gray diamond. The G logic circuit in this embodiment includes an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , that is, G i:j =oai(!G i:k ,! P i:k ,! G k-1:j ).

[0123] In one embodiment, FIG12(b) provides a circuit structure for implementing P logic and G logic, namely the sixth circuit unit. As shown in FIG12(b), the P logic + G logic circuit in this embodiment further includes a NOR gate based on FIG6(d). As shown in FIG12(b), the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , G i:j =oai(!G i:k ,! P i:k ,! G k-1:j ); The two inputs of the NOR gate are respectively! P k-1:j ,! P i:k, the output of the NOR gate is P i:j , P i:j =nor(!P k-1:j ,! P i:k ).

[0124] As shown in FIG13 , taking a multi-bit LFA adder of n+1=32 bits as an example, the LFA adder circuit of the first embodiment of the present application includes seven stages of sequentially connected operation units, wherein the first stage operation unit includes n+1 first unit circuits; the second stage operation unit includes The third-level operation unit includes a fifth unit circuit and a seventh unit circuit; A NOT gate, The fourth-level operation unit includes a sixth unit circuit and two eighth unit circuits; A NOT gate, The fifth unit circuit and four seventh unit circuits; the fifth-level operation unit includes A NOT gate, The sixth unit circuit and eight eighth unit circuits; the sixth level operation unit includes The seventh unit circuit and 5 NOT gates; the seventh-level operation unit includes n fourth unit circuits and 21 NOT gates; among them,

[0125] In the first-level operation unit, each first unit circuit has an input including a i and b i , which is used to output G after operation i and P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.

[0126] In the second-level operation unit, each fifth unit circuit has an input including G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k=i, j=i-1, i=3, n-26, n-24…n-6, n-4, n-2, n; the input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i, j=i-1, i=1.

[0127] In the third-level arithmetic unit, every two sixth-unit circuits and a NOT gate form a third-level small arithmetic unit (called the first third-level small arithmetic unit), and two eighth-unit circuits and a NOT gate form another third-level small arithmetic unit (called the second third-level small arithmetic unit). In the first third-level small arithmetic unit, the input of the NOT gate is G i-1 and P i-1 , used to output !G i-1 and! P i-1 ; One of the inputs of the sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; The input of another sixth unit circuit includes the output of the NOT gate, namely G i-1:k ,! P i-1:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-1:j and P i-1:j , where k = i-1, j = i-3, i = 7, n-20, n-16, n-12, n-8, n-4, n. In the second and third level small operation units, the input of the NOT gate is G i-1 and P i-1 , used to output !G i-1 and! P i-1 ; One of the inputs of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; The input of another eighth unit circuit includes the output of the NOT gate, namely! G i-1 ,! P i-1 And! G k-1:j , which is used to output G after operation i-1:j , where k=i-1, j=i-3, i=3.

[0128] In the fourth-level arithmetic unit, every four fifth-unit circuits and a NOT gate form a fourth-level small arithmetic unit (called the first fourth-level small arithmetic unit), and four seventh-unit circuits and a NOT gate form another fourth-level small arithmetic unit (called the second fourth-level small arithmetic unit). In the first fourth-level small arithmetic unit, the input of the NOT gate is! G i-2:k and! P i-2:k , used to output G i-2:k and P i-2:k ; One of the fifth unit circuit inputs includes G i:k 、P i:k, G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j ; Another fifth unit circuit input includes G i-1:k-1 、P i-1:k-1 , G k-1:j 、P k-1:j , which is used to output after operation! G i-1:j and! P i-1:j ; Another fifth unit circuit input includes the output of the NOT gate, namely G i-2:k ,! P i-2:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-2:j and! P i-2:j ; Another fifth unit circuit input includes G i-3:k 、P i-3:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-3:j and! P i-3:j , where k = i-3, j = i-7, i = n-16, n-8, n. In the second and fourth level small operation units, the input of the NOT gate is! G i-2:k and! P i-2:k , used to output G i-2:k and P i-2:k ; One of the seventh unit circuit inputs includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j ; Another seventh unit circuit input includes G i-1:k 、P i-1:k , G k-1:j , which is used to output after operation! G i-1:j ; Another seventh unit circuit input includes the output of the NOT gate, namely G i-2:k 、P i-2:k and G k-1:j , which is used to output after operation! G i-2:j ; Another seventh unit circuit input includes G i-3:k 、P i-3:k , G k-1:j , which is used to output after operation! G i-3:j , where k=i-3, j=i-7, i=n-24.

[0129] In the fifth-level arithmetic unit, every eight sixth-unit circuits and three NOT gates form a fifth-level small arithmetic unit (called the first fifth-level small arithmetic unit), and eight eighth-unit circuits and three NOT gates form another fifth-level small arithmetic unit (called the second fifth-level small arithmetic unit). In the first fifth-level small arithmetic unit, the input of the first NOT gate is G i-4:k 、P i-4:k , the output is !G i-4:k ,! P i-4:k ;The input of the second NOT gate is G i-5:k 、P i-5:k , the output is !G i-5:k ,! P i-5:k ;The input of the third NOT gate is G i-7 、P i-7 , the output is !G i-7 ,! P i-7 ; Wherein, the input of the first and sixth unit circuits include! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; The inputs of the second and sixth unit circuits include! G i-1:k ,! P i-1:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-1:j and P i-1:j ; The inputs of the third and sixth unit circuits include! G i-2:k ,! P i-2:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-2:j and P i-2:j ; The inputs of the fourth and sixth unit circuits include! G i-3:k ,! P i-3:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-3:j and P i-3:j The input of the fifth and sixth unit circuits includes the output of the first NOT gate, namely G i-4:k ,! P i-4:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-4:j and P i-4:j ; The input of the sixth unit circuit includes the output of the second NOT gate, that is, G i-5:k ,! P i-5:k And! G k-1:j ,! Pk-1:j , which is used to output G after operation i-5:j and P i-5:j The input of the seventh and sixth unit circuits includes the output of the first NOT gate, namely G i-6:k ,! P i-6:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-6:j and P i-6:j ; The input of the eighth and sixth unit circuits includes the output of the third NOT gate, namely! G i-7:k ,! P i-7:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-7:j and P i-7:j ; Wherein, k = i-7, j = i-15, i = n, and in this embodiment, n = 31. In the second and fifth level small operation units, the input of the first NOT gate is G i-4:k 、P i-4:k , the output is !G i-4:k ,! P i-4:k ;The input of the second NOT gate is G i-5:k 、P i-5:k , the output is !G i-5:k ,! P i-5:k ;The input of the third NOT gate is G i-7 、P i-7 , the output is !G i-7 ,! P i-7 ; Among them, the input of the first and eighth unit circuits includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; The input of the second and eighth unit circuits include! G i-1:k ,! P i-1:k ,! G k-1:j , which is used to output G after operation i-1:j ; The inputs of the third and eighth unit circuits include! G i-2:k ,! P i-2:k ,! G k-1:j , which is used to output G after operation i-2:j ; The inputs of the fourth and eighth unit circuits include! G i-3:k ,! P i-3:k ,! G k-1:j , which is used to output G after operation i-3:j The input of the fifth and eighth unit circuits includes the output of the first NOT gate, namely G i-4:k ,! P i-4:k And! G k-1:j , which is used to output G after operationi-4:j The input of the sixth and eighth unit circuits includes the output of the second NOT gate, namely G i-5:k ,! P i-5:k And! G k-1:j , which is used to output G after operation i-5:j The input of the seventh and eighth unit circuits includes the output of the first NOT gate, namely G i-6:k ,! P i-6:k And! G k-1:j , which is used to output G after operation i-6:j ; The input of the eighth unit circuit includes the output of the third NOT gate, that is, G i-7:k ,! P i-7:k And! G k-1:j , which is used to output G after operation i-7:j ; Among them, k=i-7, j=i-15, i=n-16.

[0130] The sixth level arithmetic unit includes The seventh unit circuit and 5 NOT gates, where the input of each NOT gate is! G i-8-P:k and! P i-8-P:k , used to output G i-8-P:k and P i-8-P:k , p = 0, 1, 2, 3 and 6; the input of each seventh unit circuit includes G i-m:k 、P i-m:k , G k-1:j , which is used to output after operation! G i-m:j , where k=i-15, j=i-31, i=17, 18, 19…n, and m represents the number of the seventh unit circuit, m=0, 1, 2…15.

[0131] The seventh-level operation unit includes n fourth unit circuits and 21 NOT gates, where the input of each NOT gate is! G i-P:0 and! P i-P:0 , used to output G i-P:0 and P i-P:0 , p=0,1,2,3…15,24,25,26,27 and 30; the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after addition operation i , where i = 1, 2, 3...n, S0 = P0, carry = G 31:0 .

[0132] By comparing FIG10 and FIG13 , it is readily apparent that the reconstructed topology of the entire LFA adder circuit shown in FIG13 , relative to the topology of the LFA adder circuit shown in FIG10 , and in combination with the analysis of FIG8( b ) and FIG9( b ), employs a circuit with the simplest structure and the fewest logic gates to implement the LFA adder. In other words, the LFA adder circuit provided in the embodiment of the present application has a simple structure, is superior in terms of area and latency, and consumes less power, achieving a good balance between power consumption and rate, thereby enabling the circuit to operate at a faster frequency and achieve better performance.

[0133] In one embodiment, FIG12(e) provides a circuit structure of a ninth unit circuit that implements !P logic and !G logic. As shown in FIG12(e), the schematic symbol corresponding to the ninth unit circuit is a black heptagon. The ninth unit circuit has two NAND gates and one OR gate; the two inputs of one of the NAND gates are a i 、b i , the output is !G i ,! G i =nand(a i ,b i ) and put ! G i The output is given to one input of another NAND gate; the two inputs of the OR gate are a i 、b i , the output is the other input of another NAND gate; the two inputs of another NAND gate are the output of a NAND gate and the output of the OR gate, and the output is! P i ,! P i =nand(nand(a i ,b i ),or(a i ,b i )). The logic operation unit circuit shown in FIG12(e) can also be regarded as including a NAND gate and an OR-NAND (oai) gate, wherein, as shown in FIG12(e), the oai gate is composed of an OR gate and a NAND gate! P i It can also be expressed as: !P i =oai(nand(a i ,b i ),a i ,b i ).

[0134] In one embodiment, to reduce the area of ​​the LFA adder circuit, lower its power consumption, and minimize its circuit delay, as shown in FIG14 , the ninth unit circuit (with the corresponding black heptagonal symbol) and multiple NOT gates shown in FIG12( e) are employed. The logic circuit represented by the black heptagonal symbol in FIG14 is a circuit implemented using the P logic circuit and G logic circuit provided in the embodiment of the present application, as shown in FIG12( e )! P logic + G logic! The logic circuit represented by the black small square symbol in FIG14 is the second unit circuit shown in FIG11( b ), the logic circuit represented by the gray small square symbol in FIG14 is the third unit circuit shown in FIG11( c ), and the logic circuit represented by the gray hexagonal symbol in FIG14 is the fourth unit circuit shown in FIG11( d ).

[0135] As shown in FIG14 , taking a multi-bit LFA adder of n+1=32 bits as an example, the LFA adder circuit of the second embodiment of the present application includes seven stages of sequentially connected arithmetic units, the first stage arithmetic unit includes n+1 ninth unit circuits and n+1 NOT gates; the second stage arithmetic unit includes A second unit circuit and a third unit circuit; the third-level operation unit includes The fourth-level operation unit includes a second unit circuit and two third unit circuits; The fifth-level operation unit includes The second unit circuit and 8 third unit circuits; the sixth level operation unit includes The seventh-level operation unit includes n fourth unit circuits; wherein,

[0136] In the first-level operation unit, each ninth unit circuit has an input including a i and b i , which is used to output after operation! G i and! P i The output of each ninth unit circuit is connected to the input of a NOT gate, and the output of each NOT gate is used as the output of the first-level operation unit, namely G i and P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.

[0137] In the second-level operation unit, each second unit circuit has an input including G i:k 、P i:k , G k-1:j 、P k-1:j, which is used to output G after operation i:j and P i:j , where k=i, j=i-1, i=3, n-26, n-24…n-6, n-4, n-2, n; the input of the third unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j , where k=i, j=i-1, i=1.

[0138] In the third-level operation unit, every two second unit circuits are one type of third-level small operation unit (called the first third-level small operation unit), and the two third unit circuits are another type of third-level small operation unit (called the second third-level small operation unit). In the first third-level small operation unit, the input of one of the second unit circuits includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i:j and P i:j ; Another second unit circuit input includes G i-1:k 、P i-1:k and G k-1:j 、P k-1:j , which is used to output G after operation i-1:j and P i-1:j , where k=i-1, j=i-3, i=7, n-20, n-16, n-12, n-8, n-4, n. In the second and third level small operation units, the input of one of the third unit circuits includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j ; Another third unit circuit input includes G i-1 、P i-1 and G k-1:j , which is used to output G after operation i-1:j , where k=i-1, j=i-3, i=3.

[0139] In the fourth-level arithmetic unit, every four second-unit circuits form a fourth-level small arithmetic unit (called the first fourth-level small arithmetic unit), and four third-unit circuits form another fourth-level small arithmetic unit (called the second fourth-level small arithmetic unit). In the first fourth-level small arithmetic unit, the input of one of the second-unit circuits includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i:j and Pi:j ; Another second unit circuit input includes G i-1:k-1 、P i-1:k-1 , G k-1:j 、P k-1:j , which is used to output G after operation i-1:j and P i-1:j ; Another second unit circuit input includes G i-2:k 、P i-2:k , G k-1:j 、P k-1:j , which is used to output G after operation i-2:j and P i-2:j ; Another second unit circuit input includes G i-3:k 、P i-3:k , G k-1:j 、P k-1:j , which is used to output G after operation i-3:j and P i-3:j , where k=i-3, j=i-7, i=n-16, n-8, n. In the second and fourth level small operation units, the input of one of the third unit circuits includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j ; Another third unit circuit input includes G i-1:k 、P i-1:k , G k-1:j , which is used to output G after operation i-1:j ; The input of the third unit circuit includes the output of the NOT gate, namely G i-2:k 、P i-2:k and G k-1:j , which is used to output G after operation i-2:j ; Another third unit circuit input includes G i-3:k 、P i-3:k , G k-1:j , which is used to output G after operation i-3:j , where k=i-3, j=i-7, i=n-24.

[0140] In the fifth-level arithmetic unit, every eight second-unit circuits form a fifth-level small arithmetic unit (called the first fifth-level small arithmetic unit), and eight third-unit circuits form another fifth-level small arithmetic unit (called the second fifth-level small arithmetic unit). In the first fifth-level small arithmetic unit, the inputs of the first and second unit circuits include G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i:j and P i:j; The input of the second unit circuit includes G i-1:k 、P i-1:k , G k-1:j 、P k-1:j , which is used to output G after operation i-1:j and P i-1:j ; The input of the third and second unit circuits includes G i-2:k 、P i-2:k , G k-1:j 、P k-1:j , which is used to output G after operation i-2:j and P i-2:j ; The input of the fourth second unit circuit includes G i-3:k 、P i-3:k , G k-1:j 、P k-1:j , which is used to output G after operation i-3:j and P i-3:j The input of the fifth second unit circuit includes the output of the first NOT gate, namely G i-4:k 、P i-4:k and G k-1:j 、P k-1:j , which is used to output G after operation i-4:j and P i-4:j The input of the sixth second unit circuit includes the output of the second NOT gate, namely G i-5:k 、P i-5:k and G k-1:j 、P k-1:j , which is used to output G after operation i-5:j and P i-5:j The input of the seventh second unit circuit includes the output of the first NOT gate, namely G i-6:k 、P i-6:k and G k-1:j 、P k-1:j , which is used to output G after operation i-6:j and P i-6:j The input of the eighth second unit circuit includes the output of the third NOT gate, namely G i-7:k 、P i-7:k and G k-1:j 、P k-1:j , which is used to output G after operation i-7:j and P i-7:j ; Wherein, k=i-7, j=i-15, i=n, ​​and in this embodiment, n=31. In the second and fifth stage small operation units, the inputs of the first and third unit circuits include G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j The inputs of the second and third unit circuits include G i-1:k 、P i-1:k , Gk-1:j , which is used to output G after operation i-1:j ; The input of the third unit circuit includes G i-2:k 、P i-2:k , G k-1:j , which is used to output G after operation i-2:j ; The input of the fourth and third unit circuits includes G i-3:k 、P i-3:k , G k-1:j , which is used to output G after operation i-3:j The input of the fifth third unit circuit includes the output of the first NOT gate, namely G i-4:k 、P i-4:k and G k-1:j , which is used to output G after operation i-4:j The input of the sixth third unit circuit includes the output of the second NOT gate, namely G i-5:k 、P i-5:k and G k-1:j , which is used to output G after operation i-5:j The input of the seventh third unit circuit includes the output of the first NOT gate, namely G i-6:k 、P i-6:k and G k-1:j , which is used to output G after operation i-6:j ; The input of the eighth third unit circuit includes the output of the third NOT gate, namely G i-7:k 、P i-7:k and G k-1:j , which is used to output G after operation i-7:j ; Among them, k=i-7, j=i-15, i=n-16.

[0141] The sixth level arithmetic unit includes A third unit circuit, wherein the input of each third unit circuit includes G n-m:k 、P n-m:k , G k-1:j , which is used to output G after operation i-m:j , where k=i-15, j=i-31, i=17, 18, 19...n; m=0, 1, 2...15.

[0142] The seventh-level operation unit includes n fourth unit circuits, wherein the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after addition operation i , where i = 1, 2, 3...n, S0 = P0, carry = G 31:0 .

[0143] In the embodiment shown in FIG14 , the circuit is reduced by sharing logic, and the original Pi The logic circuit structure is converted into a part of the generation! i The logic circuit structure uses NAND and OAI gates to replace the XNR circuit, thus saving a NAND gate.

[0144] In another embodiment, to further reduce the area of ​​the LFA adder circuit, lower its power consumption, and minimize its circuit delay, as shown in FIG15 , the LFA adder is implemented using FIG12( a ) to FIG12( e ). The logic circuit represented by the black heptagonal schematic symbol in FIG15 is the ninth unit circuit shown in FIG12( e ), the logic circuit represented by the black pentagonal schematic symbol in FIG15 is the fifth unit circuit shown in FIG12( a ), and the logic circuit represented by the black diamond schematic symbol in FIG15 is the sixth unit circuit shown in FIG12( b ). The logic circuit represented by the gray pentagonal schematic symbol in FIG15 is the seventh unit circuit shown in FIG12( c ), and the logic circuit represented by the gray diamond schematic symbol in FIG15 is the eighth unit circuit shown in FIG12( d ).

[0145] As shown in FIG15 , taking a multi-bit LFA adder of n+1=32 bits as an example, the LFA adder circuit of the third embodiment of the present application includes seven stages of sequentially connected operation units, the first stage operation unit includes n+1 ninth unit circuits; the second stage operation unit includes The sixth unit circuit, one eighth unit circuit; the third-level operation unit includes A NOT gate, The fourth-level operation unit includes a fifth unit circuit and two seventh unit circuits; A NOT gate, The sixth unit circuit and four eighth unit circuits; the fifth-level operation unit includes A NOT gate, The sixth-level operation unit includes The seventh-level operation unit includes n fourth-level unit circuits and 11 non-gates; among them,

[0146] In the first-level operation unit, each ninth unit circuit has an input including a i and b i , which is used to output after operation! G i and! P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.

[0147] In the second-level operation unit, each sixth unit circuit has inputs including! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j , where k=i, j=i-1, i=3, n-26, n-24…n-6, n-4, n-2, n; the input of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i, j=i-1, i=1.

[0148] In the third-level arithmetic unit, every two fifth-unit circuits and a NOT gate form a third-level small arithmetic unit (called the first third-level small arithmetic unit), and two seventh-unit circuits and a NOT gate form another third-level small arithmetic unit (called the second third-level small arithmetic unit). In the first third-level small arithmetic unit, the input of the NOT gate is! G i-1 and! P i-1 , used to output G i-1 and P i-1 ; One of the fifth unit circuit inputs includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j The input of the fifth unit circuit includes the output of the NOT gate, namely G i-1:k 、P i-1:k and G k-1:j 、P k-1:j , which is used to output after operation! G i-1:j and! P i-1:j , where k=i-1, j=i-3, i=7, n-20, n-16, n-12, n-8, n-4, n. In the second and third level small operation units, the input of the NOT gate is! G i-1 and! P i-1 , used to output G i-1 and P i-1 ; One of the seventh unit circuit inputs includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j The input of the seventh unit circuit includes the output of the NOT gate, namely G i-1 、P i-1 And! Gk-1:j , which is used to output after operation! G i-1:j , where k=i-1, j=i-3, i=3.

[0149] In the fourth-level arithmetic unit, every four sixth-unit circuits and a NOT gate form a fourth-level small arithmetic unit (called the first fourth-level small arithmetic unit), and four eighth-unit circuits and a NOT gate form another fourth-level small arithmetic unit (called the second fourth-level small arithmetic unit). In the first fourth-level small arithmetic unit, the input of the NOT gate is G i-2:k and P i-2:k , used to output !G i-2:k and! P i-2:k ; One of the inputs of the sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; Another input of the sixth unit circuit includes! G i-1:k-1 ,! P i-1:k-1 ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-1:j and P i-1:j ; The input of the sixth unit circuit includes the output of the NOT gate, namely G i-2:k ,! P i-2:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-2:j and P i-2:j ;Another input of the sixth unit circuit includes! G i-3:k ,! P i-3:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-3:j and P i-3:j , where k = i-3, j = i-7, i = n-16, n-8, n. In the second and fourth level small operation units, the input of the NOT gate is G i-2:k and P i-2:k , used to output !G i-2:k and! P i-2:k ; One of the inputs of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; Another input of the eighth unit circuit includes! G i-1:k ,! P i-1:k ,! G k-1:j, which is used to output G after operation i-1:j ; Another eighth unit circuit input includes the output of the NOT gate, namely! G i-2:k ,! P i-2:k And! G k-1:j , which is used to output G after operation i-2:j ;Another input of the eighth unit circuit includes! G i-3:k ,! P i-3:k ,! G k-1:j , which is used to output G after operation i-3:j , where k=i-3, j=i-7, i=n-24.

[0150] In the fifth-level arithmetic unit, every eight fifth-unit circuits and three NOT gates form a fifth-level small arithmetic unit (called the first fifth-level small arithmetic unit), and eight seventh-unit circuits and three NOT gates form another fifth-level small arithmetic unit (called the second fifth-level small arithmetic unit). In the first fifth-level small arithmetic unit, the input of the first NOT gate is! G i-4:k ,! P i-4:k , the output is G i-4:k 、P i-4:k ;The input of the second NOT gate is! G i-5:k ,! P i-5:k , the output is G i-5:k 、P i-5:k ;The input of the third NOT gate is! G i-7 ,! P i-7 , the output is G i-7 、P i-7 ; Wherein, the input of the first and fifth unit circuits includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j ; The input of the second and fifth unit circuits includes G i-1:k 、P i-1:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-1:j and! P i-1:j ; The input of the third and fifth unit circuits includes G i-2:k 、P i-2:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-2:j and! P i-2:j ; The input of the fourth and fifth unit circuits includes G i-3:k 、P i-3:k , G k-1:j 、P k-1:j, which is used to output after operation! G i-3:j and! P i-3:j The input of the fifth unit circuit includes the output of the first NOT gate, namely G i-4:k 、P i-4:k and G k-1:j 、P k-1:j , which is used to output after operation! G i-4:j and! P i-4:j The input of the sixth and fifth unit circuits includes the output of the second NOT gate, namely G i-5:k 、P i-5:k and G k-1:j 、P k-1:j , which is used to output after operation! G i-5:j and! P i-5:j The input of the seventh and fifth unit circuits includes the output of the first NOT gate, namely G i-6:k 、P i-6:k and G k-1:j 、P k-1:j , which is used to output after operation! G i-6:j and! P i-6:j The input of the eighth and fifth unit circuits includes the output of the third NOT gate, namely G i-7:k 、P i-7:k and G k-1:j 、P k-1:j , which is used to output after operation! G i-7:j and! P i-7:j ; Wherein, k = i-7, j = i-15, i = n, and in this embodiment, n = 31. In the second and fifth level small operation units, the input of the first NOT gate is! G i-4:k ,! P i-4:k , the output is G i-4:k 、P i-4:k ;The input of the second NOT gate is! G i-5:k ,! P i-5:k , the output is G i-5:k 、P i-5:k ;The input of the third NOT gate is! G i-7 ,! P i-7 , the output is G i-7 、P i-7 ; Wherein, the input of the first and seventh unit circuits includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j ; The input of the second and seventh unit circuits includes G i-1:k 、P i-1:k , G k-1:j , which is used to output after operation! G i-1:j ; The input of the third and seventh unit circuits includes G i-2:k、P i-2:k , G k-1:j , which is used to output after operation! G i-2:j ; The input of the fourth and seventh unit circuits includes G i-3:k 、P i-3:k , G k-1:j , which is used to output after operation! G i-3:j The input of the fifth and seventh unit circuits includes the output of the first NOT gate, namely G i-4:k 、P i-4:k and G k-1:j , which is used to output after operation! G i-4:j The input of the sixth and seventh unit circuits includes the output of the second NOT gate, namely G i-5:k 、P i-5:k and G k-1:j , which is used to output after operation! G i-5:j The input of the seventh unit circuit includes the output of the first NOT gate, namely G i-6:k 、P i-6:k and G k-1:j , which is used to output after operation! G i-6:j The input of the eighth and seventh unit circuits includes the output of the third NOT gate, namely G i-7:k 、P i-7:k and G k-1:j , which is used to output after operation! G i-7:j ; Among them, k=i-7, j=i-15, i=n-16.

[0151] The sixth level arithmetic unit includes The eighth unit circuit and 5 NOT gates, where the input of each NOT gate is G i-8-P:k and P i-8-P:k , used to output !G i-8-P:k and! P i-8-P:k , p = 0, 1, 2, 3 and 6; the input of each eighth unit circuit includes! G n-m:k ,! P n-m:k ,! G k-1:j , which is used to output G after operation n-m:j , where k=i-15, j=i-31, i=17, 18, 19...n; m=0, 1, 2...15.

[0152] The seventh-level operation unit includes n fourth unit circuits and 11 NOT gates, where the input of each NOT gate is G n-p:0 and P n-p:0 , used to output !G n-p:0 and! P n-p:0 , p=16, 17…23, 28, 29 and 31; the input of each fourth unit circuit includes G i-1:0 、Pi , used to output S after addition operation i , where i = 1, 2, 3...n, S0 = P0, carry = G 31:0 .

[0153] In the embodiment shown in FIG15 , the circuit is reduced by sharing logic, and the original P i The logic circuit structure is converted into a production! i The logic circuit structure uses NAND and OAI gates to replace the XNR circuit, thus saving a NAND gate.

[0154] In one exemplary embodiment, a BK adder is used as an example, where BK stands for Brent Kung Adder. The BK adder was proposed by Richard P. Brent and Professor H.T. Kung in the 1980s and is derived using typical PG logic. FIG16 is a schematic diagram of the topology of a BK adder circuit in one embodiment, and FIG17 is a schematic diagram of the topology of a first embodiment of a BK adder circuit. Similarly, in the BK adder circuit shown in FIG17 , the fifth unit circuit (black pentagon symbol) shown in FIG12(a) and the sixth unit circuit (black diamond symbol) shown in FIG12(b) are combined, and the seventh unit circuit (gray pentagon symbol) shown in FIG12(c) and the eighth unit circuit (gray diamond symbol) shown in FIG12(d) are combined.

[0155] As shown in FIG17 , taking a multi-bit BK adder of n+1=32 bits as an example, the BK adder circuit of the first embodiment of the present application includes ten stages of sequentially connected operation units, the first stage operation unit includes n+1 first unit circuits; the second stage operation unit includes The third-level operation unit includes a fifth unit circuit and a seventh unit circuit; The fourth-level operation unit includes a sixth unit circuit and an eighth unit circuit; The fifth unit circuit and the seventh unit circuit are included; the fifth-level operation unit includes one sixth unit circuit and one eighth unit circuit; the sixth-level operation unit includes two seventh unit circuits and one NOT gate; the seventh-level operation unit includes two eighth unit circuits and two NOT gates, and one seventh unit circuit; the eighth-level operation unit includes four seventh unit circuits and four NOT gates, and three eighth unit circuits; the ninth-level operation unit includes seven seventh unit circuits, eight eighth unit circuits, and eight NOT gates; the tenth-level operation unit includes n fourth unit circuits and nine NOT gates; among them,

[0156] In the first-level operation unit, each first unit circuit has an input including a i and b i , which is used to output G after operation i and P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the information of each bit of data b involved in the addition operation, i=0, 1, 2...n, n represents the number of bits of data a and data b involved in the addition operation.

[0157] In the second-level operation unit, each fifth unit circuit has an input including G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k=i, j=i-1, i=n, ​​n-2, n-4, n-6…n-24, n-26, 3; the input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i, j=i-1, i=1.

[0158] In the third-level operation unit, the input of each sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-m:j and P i-m:j ; Wherein, k = i-1, j = i-3, i = n, n-4, n-8, n-2, n-12, n-16, n-20, 7. The input of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i-1, j=i-3, i=3.

[0159] In the fourth-level operation unit, the input of each fifth unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k=i-3, j=i-7, i=n, ​​n-8, n-16.

[0160] In the fifth-level operation unit, the input of a sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; Wherein, k = i-7, j = i-15, i = n; the input of an eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i-7, j=i-15, i=n-16=15.

[0161] In the sixth-level operation unit, the input of a NOT gate is! G i-8:k and! P i-8:k , used to output G i-8:k and P i-8:k ; One of the seventh unit circuit inputs includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j The input of the seventh unit circuit includes the output of the NOT gate, namely G i-8:k 、P i-8:k and G k-1:j , which is used to output after operation! G i-8:j , where k=i-15, j=i-31, i=n.

[0162] In the seventh-level arithmetic unit, the input of a seventh unit circuit includes G i-12:k 、P i-12:k and G k-1:j , which is used to output after operation! G i-12:j ; The input of one of the NOT gates (the first NOT gate) is G i-4:k+8 and P i-4:k+8 , used to output !G i-4:k+8 and! P i-4:k+8 , one of the inputs of the eighth unit circuit includes the output of the first NOT gate, that is! G i-4:k+8 and! P i-4:k+8 And! G k-1:j , which is used to output G after operation i-4:j ; The input of the other NOT gate (the second NOT gate) is G i-20:k-8 and P i-20:k-8 , used to output !G i-20:k-8 and! P i-20:k-8 , the input of another eighth unit circuit includes the output of the second NOT gate, that is! G i-20:k-8 and! P i-20:k-8And! G k-1:j , which is used to output G after operation i-20:j ; Among them, k=16, j=i-31, i=n.

[0163] In the eighth-level arithmetic unit, the inputs of the four NOT gates are:! G i:k and! P i:k ,! G i-12:k-12 and! P i-12:k-12 ,! G i-16:k and! P i-16:k ,! G i-24:k and! P i-24:k , respectively used to output G i:k and P i:k , G i-12:k-12 and P i-12:k-12 , G i-16:k and P i-16:k , G i-24:k and P i-24:k ; The inputs of the 4 seventh unit circuits include: the output of the NOT gate, i.e. G i:k 、P i:k and G k-2:j The output of the NOT gate is G i-12:k-12 、P i-12:k-12 and G k-14:j The output of the NOT gate is G i-16:k-16 、P i-16:k-16 and G k-18:j The output of the NOT gate is G i-24:k-24 、P i-24:k-24 and G k-26:j , which are used to output respectively after operation:! G i:j ,! G i-12:j ,! G i-16:j and,! G i-24:j ; The inputs of the three eighth unit circuits include:! G i-4:k-4 ,! P i-4:k-4 and! G k-5:j ,! G i-8:k-8 ,! P i-8:k-8 and! G k-9:j ,! G i-20:k-20 ,! P i-20:k-20 and! G k-21:j , which are used to output G after operation. i-4:j , G i-8:j and G i-20:j ; Among them, k=i-1, j=i-29, i=n-2.

[0164] In the ninth-level arithmetic unit, the inputs of the seven seventh-unit circuits are: G i:k 、P i:k and G k-2:j, where k=i, j=0, and the values ​​of i for the seven seventh unit circuits are: i=n-3, n-5, n-9, n-15, n-19, n-21, n-27; the input of each NOT gate is: G i:k and P i:k , for output! G i:k and! P i:k , the output of each NOT gate is connected to an input of each eighth unit circuit, and the input of each eighth unit circuit includes! G i:k ,! P i:k and! G k-1:j-i , which are used to output G after operation i-4:j ; Among them, k=i, j=i, and the values ​​of i corresponding to the 8 NOT gates are: i=n-1, n-7, n-11, n-13, n-17, n-23, n-25, n-29.

[0165] The tenth-level operation unit includes n fourth unit circuits and 9 NOT gates, where the input of each NOT gate is! G i-P:0 and! P i-P:0 , used to output G i-P:0 and P i-P:0 , the value of i corresponding to each NOT gate is n, p=0, 3, 5, 9, 15, 19, 21, 27 and 30; the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after operation i , where the value of i corresponding to each fourth unit is: i=1, 2, 3…n, except S0=P0, carry=G 31:0 .

[0166] By comparing Figures 16 and 17, it is not difficult to see that the topology of the reconstructed entire BK adder circuit shown in Figure 17, relative to the topology of the BK adder circuit shown in Figure 16, combined with the analysis of Figures 8(b) and 9(b), adopts the circuit with the simplest structure and the least logic gates to implement the BK adder. In other words, the BK adder circuit provided in the embodiment of the present application has a simple structure, is better in terms of area and delay, has lower power consumption, and has a good balance between power consumption and rate, thereby making the circuit run faster and having better performance.

[0167] In one embodiment, to reduce the area of ​​the BK adder circuit, lower its power consumption, and minimize its circuit delay, as shown in FIG18 , the ninth unit circuit and multiple NOT gates, whose corresponding schematic symbol is a black heptagon, are used in FIG12( e). The logic circuit represented by the black heptagonal schematic symbol in FIG14 is a circuit implemented using the P logic circuit and G logic circuit provided in the embodiment of the present application, as shown in FIG12( e )! P logic +! G logic. The logic circuit represented by the black small square schematic symbol in FIG14 is the second unit circuit shown in FIG11( b ). The logic circuit represented by the gray small square schematic symbol in FIG14 is the third unit circuit shown in FIG11( c ). The logic circuit represented by the gray hexagonal schematic symbol in FIG14 is the fourth unit circuit shown in FIG11( d ).

[0168] As shown in FIG18 , taking a multi-bit BK adder of n+1=32 bits as an example, the BK adder circuit of the second embodiment of the present application includes ten stages of sequentially connected operation units, the first stage operation unit includes n+1 ninth unit circuits and n+1 NOT gates; the second stage operation unit includes The second unit circuit, 1 third unit circuit; the third-level operation unit includes The fourth-level operation unit includes a second unit circuit and a third unit circuit; The fifth-level operation unit includes a second unit circuit and a third unit circuit; the sixth-level operation unit includes two third unit circuits; the seventh-level operation unit includes The third unit circuit; the eighth level operation unit includes The ninth-level operation unit includes The tenth-level operation unit includes n fourth unit circuits; wherein,

[0169] In the first-level operation unit, each ninth unit circuit has an input including a i and b i , which is used to output after operation! G i and! P i , the output of each ninth unit circuit is connected to the input of a NOT gate, and the output of each NOT gate is used as the output of the first-level operation unit; where a i is the information of each bit of data a involved in the addition operation, b i is the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.

[0170] In the second-level operation unit, each second unit circuit has an input including G i:k 、P i:k, G k-1:j 、P k-1:j , which is used to output G after operation i:j and P i:j , where k=i, j=i-1, i=n, ​​n-2, n-4, n-6…n-24, n-26, 3; the input of the third unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j , where k=i, j=i-1, i=1.

[0171] In the third-level operation unit, the input of each second unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i-m:j and P i-m:j ; Wherein, k = i-1, j = i-3, i = n, n-4, n-8, n-2, n-12, n-16, n-20, 7. The input of the third unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j , where k=i-1, j=i-3, i=3.

[0172] In the fourth-level operation unit, the input of each second unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i:j and P i:j , where k = i-3, j = i-7, i = n, n-8, n-16. The third unit circuit input includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j , where k=i-3, j=i-7, i=7.

[0173] In the fifth-level operation unit, the input of a second unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output G after operation i:j and P i:j ; Wherein, k = i-7, j = i-15, i = n; the input of a third unit circuit includes G i:k 、P i:k , Gk-1:j , which is used to output G after operation i:j , where k=i-7, j=i-15, i=n-16=15.

[0174] In the sixth-level operation unit, the input of one of the third unit circuits includes G i:k 、P i:k , G k-1:j , which is used to output G after operation i:j ; Another third unit circuit input includes G i-8:k 、P i-8:k and G k-1:j , which is used to output G after operation i-8:j , where k=i-15, j=i-31, i=n.

[0175] In the seventh-level arithmetic unit, the input of one of the third unit circuits includes G i-12:k 、P i-12:k and G k-1:j , which is used to output G after operation i-12:j ; Another third unit circuit input includes G i-4:k+8 and P i-4:k+8 and G k-1:j , which is used to output G after operation i-4:j ; The input of the third unit circuit includes G i-20:k-8 and P i-20:k-8 and G k-1:j , which is used to output G after operation i-20:j ; Among them, k=16, j=i-31, i=n.

[0176] In the eighth-level arithmetic unit, the inputs of the seven third-unit circuits include: G i:k 、P i:k and G k-2:j , G i-4:k-4 、P i-4:k-4 and G k-5:j , G i-8:k-8 、P i-8:k-8 and! G k-9:j , G i-12:k-12 、P i-12:k-12 and G k-14:j , G i-16:k-16 、P i-16:k-16 and G k-18:j , G i-20:k-20 、P i-20:k-20 and G k-21:j , G i-24:k-24 、P i-24:k-24 and G k-26:j , which are used to output respectively after operation: G i:j , Gi-4:j , G i-8:j , G i-12:j , G i-16:j , G i-20:j and G i-24:j ; Among them, k=i-1, j=i-29, i=n-2.

[0177] In the ninth-level arithmetic unit, the input of each third unit circuit is: G i:k 、P i:k and G k-1:j , which are used to output G after operation i:j Wherein, k=i, j=0, and the values ​​of i corresponding to each third unit circuit are: i=n-1, n-3, n-5, n-7, n-9, n-11, n-13, n-15, n-17, n-19, n-21, n-23, n-25, n-27, n-29.

[0178] In the tenth-level arithmetic unit, the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after operation i , where the value of i corresponding to each fourth unit is: i=1, 2, 3…n, except S0=P0, carry=G 31:0 .

[0179] In the embodiment shown in FIG18 , the circuit is reduced by sharing logic, and the original P i The logic circuit structure is converted into a production! i The logic circuit structure uses NAND and OAI gates to replace the XNR circuit, thus saving a NAND gate.

[0180] In another embodiment, to further reduce the area of ​​the BK adder circuit, lower its power consumption, and minimize its circuit delay, as shown in FIG19 , a BK adder is implemented using FIG12(a) to FIG12(e). The logic circuit represented by the black heptagonal schematic symbol in FIG19 is the ninth unit circuit of the P logic circuit and the G logic circuit provided in the embodiment of the present application, as shown in FIG12(e). The logic circuit represented by the black pentagonal schematic symbol in FIG19 is the fifth unit circuit of the P logic circuit and the G logic circuit provided in the embodiment of the present application, as shown in FIG12(a). The logic circuit represented by the black diamond schematic symbol in FIG19 is the sixth unit circuit of the P logic + G logic circuit, as shown in FIG12(b), as shown in FIG12(b). The logic circuit represented by the gray pentagonal schematic symbol in FIG19 is the ninth unit circuit of the G logic circuit provided in the embodiment of the present application, as shown in FIG12(c). The seventh unit circuit of the G logic, the logic circuit represented by the gray diamond schematic symbol in Figure 19 is the eighth unit circuit of the G logic implemented using the G logic circuit provided in the embodiment of the present application as shown in Figure 12(d).

[0181] As shown in FIG19 , taking a multi-bit BK adder of n+1=32 bits as an example, the BK adder circuit of the third embodiment of the present application includes ten stages of sequentially connected operation units, the first stage operation unit includes n+1 ninth unit circuits; the second stage operation unit includes The sixth unit circuit, one eighth unit circuit; the third-level operation unit includes The fourth-level operation unit includes a fifth unit circuit and a seventh unit circuit; The fifth-level operation unit includes one fifth-level unit circuit and one seventh-level unit circuit; the sixth-level operation unit includes two eighth-level unit circuits and one NOT gate; the seventh-level operation unit includes two seventh-level unit circuits and two NOT gates, and one eighth-level unit circuit; the eighth-level operation unit includes four eighth-level unit circuits and four NOT gates, and three seventh-level unit circuits; the ninth-level operation unit includes The tenth-level operation unit includes n fourth-level unit circuits and 1 NOT gate; among them,

[0182] In the first-level operation unit, each ninth unit circuit has an input including a i and b i , which is used to output after operation! G i and! P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b iis the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.

[0183] In the second-level operation unit, each sixth unit circuit has inputs including! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j , where k=i, j=i-1, i=n, ​​n-2, n-4, n-6…n-24, n-26, 3; the input of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i, j=i-1, i=1.

[0184] In the third-level operation unit, the input of each fifth unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-m:j and! P i-m:j ; Wherein, k = i-1, j = i-3, i = n, n-4, n-8, n-2, n-12, n-16, n-20, 7. The input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i-1, j=i-3, i=3.

[0185] In the fourth-level operation unit, the input of each sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j , where k = i-3, j = i-7, i = n, n-8, n-16. The eighth unit circuit input includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i-3, j=i-7, i=7.

[0186] In the fifth-level operation unit, the input of a fifth unit circuit includes G i:k 、Pi:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j ; Wherein, k = i-7, j = i-15, i = n; the input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i-7, j=i-15, i=n-16=15.

[0187] In the sixth-level arithmetic unit, the input of a NOT gate is G i-8:k and P i-8:k , used to output !G i-8:k and! P i-8:k ; One of the inputs of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; The input of another eighth unit circuit includes the output of the NOT gate, namely! G i-8:k ,! P i-8:k And! G k-1:j , which is used to output G after operation i-8:j , where k=i-15, j=i-31, i=n.

[0188] In the seventh-level arithmetic unit, the input of an eighth unit circuit includes! G i-12:k ,! P i-12:k And! G k-1:j , which is used to output G after operation i-12:j ; The input of one of the NOT gates (the first NOT gate) is! G i-4:k+8 and! P i-4:k+8 , used to output G i-4:k+8 and P i-4:k+8 , where the input of the seventh unit circuit includes the output of the first NOT gate, namely G i-4:k+8 and P i-4:k+8 and G k-1:j , which is used to output after operation! G i-4:j ; The input of the other NOT gate (the second NOT gate) is! G i-20:k-8 and! P i-20:k-8 , used to output G i-20:k-8 and P i-20:k-8 The input of the seventh unit circuit includes the output of the second NOT gate, namely G i-20:k-8 and P i-20:k-8 and G k-1:j , which is used to output after operation! G i-20:j; Among them, k=16, j=i-31, i=n.

[0189] In the eighth-level arithmetic unit, the inputs of the four NOT gates are: G i:k and P i:k , G i-12:k-12 and P i-12:k-12 , G i-16:k and P i-16:k , G i-24:k and P i-24:k , respectively used for output! G i:k and! P i:k ,! G i-12:k-12 and! P i-12:k-12 ,! G i-16:k and! P i-16:k ,! G i-24:k and! P i-24:k ; The inputs of the four eighth unit circuits include: the output of the NOT gate, that is! G i:k ,! P i:k And! G k-2:j , the output of the NOT gate is G i-12:k-12 ,! P i-12:k-12 And! G k-14:j , the output of the NOT gate is G i-16:k-16 ,! P i-16:k-16 And! G k-18:j , the output of the NOT gate is G i-24:k-24 ,! P i-24:k-24 And! G k-26:j , which are used to output respectively after operation: G i:j , G i-12:j , G i-16:j and G i-24:j ; The inputs of the three seventh unit circuits include: G i-4:k-4 、P i-4:k-4 and G k-5:j , G i-8:k-8 、P i-8:k-8 and G k-9:j , G i-20:k-20 、P i-20:k-20 and G k-21:j , which are used to output after operation respectively! G i-4:j ,! G i-8:j and! G i-20:j ; Among them, k=i-1, j=i-29, i=n-2.

[0190] In the ninth-level arithmetic unit, the input of each NOT gate is: G i:j , for output! G i:jThe output of each NOT gate is connected to one input of each of the eight eighth unit circuits, wherein the value of i corresponding to each NOT gate is i=29, 23, 19, 17, 13, 7, 5 and 1, and j=0. The input of each eighth unit circuit is:! G i:k ,! P i:k And! G k-1:j , which are used to output G after operation i:j , where k=i, j=0, and the value of i corresponding to each eighth unit circuit is i=n-1, n-3, n-5, n-7…n-25, n-27, n-29.

[0191] The tenth-level operation unit includes n fourth-unit circuits and 1 NOT gate, where the input of the NOT gate is the output of one of the NOT gates in the ninth-level operation unit, that is, G. 1:0 , used to output G 1:0 , the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after operation i , where the value of i corresponding to each fourth unit is: i=1, 2, 3…n, except S0=P0, carry=G 31:0 .

[0192] In the embodiment shown in FIG19 , the circuit is reduced by sharing logic, and the original P i The logic circuit structure is converted into a production! i The logic circuit structure uses NAND and OAI gates to replace the XNR circuit, thus saving a NAND gate.

[0193] It should be noted that, as shown in Figures 13, 14, 15, 17, 18, and 19, some NOT gate circuits will be added when necessary, such as in Figure 19. As shown in the schematic diagram symbols, correct logic implementation is ensured, which is something that a person skilled in the art can easily think of when implementing a BK adder based on the P logic circuit and the G logic circuit provided in the embodiment of the present application.

[0194] As described above, an embodiment of the present application provides an adder circuit, wherein the P logic circuit adopts the P logic circuit provided by any one of the embodiments of the present application, and wherein the G logic circuit adopts the G logic circuit provided by any one of the embodiments of the present application.

[0195] The adder circuit provided in the embodiment of the present application reduces the circuit by sharing the logic circuit, for example: i The logic circuit structure is converted into a production! iThe logic circuit structure uses nand and oai gates to replace the exclusive or gate xnr circuit, thus saving a nand gate. This topology of the adder circuit saves the generation of! i Logical AND! G i In other words, the adder circuit provided by the embodiment of the present application uses a circuit with the simplest structure and the least number of logic gates. The adder circuit has a simple structure, is better in terms of area and delay, and has lower power consumption. It strikes a good balance between power consumption and speed, thereby making the circuit run at a faster frequency and better performance.

[0196] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement !P logic and !G logic, including: two NAND gates and one OR gate; wherein, The two inputs of a NAND gate are a i , b i , the output is! G i , and will! G i The output is fed to one input of another NAND gate; The two inputs of the OR gate are a i , b i , the output is the other input of another NAND gate; The two inputs of the other NAND gate are the output of a NAND gate and the output of the OR gate, and the output is! P i ; Here, i represents the i-th bit in the multi-bit addition.

2. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement !G logic and !P logic, including: an AND-NOR gate, an NAND gate; The three inputs of the AND-NOR gate are G i:k , P i:k and G k-1:j , the output of the AND-NOR gate is! G i:j ; The two inputs of the NAND gate are P k-1:j , the P i:k , the output of the NAND gate is! P i:j ; Among them, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.

3. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement G logic and P logic, including: an OR-NAND gate, an NOR gate; The three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j ; The two inputs of the NOR gate are respectively! k-1:j , as mentioned! i:k , the output of the NOR gate is P i:j ; Among them, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.

4. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement P logic and G logic, including: two NOR gates and one AND gate; wherein, The two inputs of a NOR gate are a i 、b i , the output is one input of another NOR gate; The two inputs of the AND gate are a i 、b i , the output is G i , and G i The output is fed to the other input of another NOR gate; The two inputs of the other NOR gate are the output of a NOR gate and the output of the AND gate, and the output is P i ; Here, i represents the i-th bit in the multi-bit addition.

5. An adder circuit, characterized in that: A logic operation unit circuit comprising any combination of claims 1 to 4.

6. The adder circuit according to claim 5, wherein: The adder is an LFA adder or a BK adder.

7. An adder circuit, characterized in that: The adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected operation units, wherein: The first-level operation unit comprises n+1 logic operation unit circuits as claimed in claim 1 and n+1 NOT gates; the output of each logic operation unit circuit as claimed in claim 1 is connected to the input of a NOT gate, and the output of each NOT gate serves as the output of the first-level operation unit; The second-level computing unit includes A second unit circuit and a third unit circuit; wherein the second unit circuit is used to implement P i:j =and(P i-1:j ,P i:k ), G i:j =ao(P i:k ,G k-1:j ,G i:k ); the third unit circuit is used to implement G i:j =ao(P i:k ,G k-1:j ,G i:k ); The third-level computing unit includes the second unit circuit and two the third unit circuits; The fourth level arithmetic unit includes the second unit circuits and four the third unit circuits; The fifth level arithmetic unit includes the second unit circuits and eight the third unit circuits; The sixth level arithmetic unit includes the third unit circuit; The seventh-level operation unit includes n fourth unit circuits; wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after adder operation.

8. An adder circuit, characterized in that: The adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected operation units, wherein: The first-level operation unit includes n+1 logic operation unit circuits as claimed in claim 1; The second-level computing unit includes a logic operation unit circuit as claimed in claim 3, and an eighth unit circuit; wherein, The eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The third-level computing unit includes A NOT gate, a logic operation unit circuit as claimed in claim 2 and two seventh unit circuits; wherein, The seventh unit circuit is used to implement !G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The fourth level arithmetic unit includes A NOT gate, a logic operation unit circuit as claimed in claim 3 and four of the eighth unit circuits; The fifth level arithmetic unit includes A NOT gate, a logic operation unit circuit as claimed in claim 2 and eight of the seventh unit circuits; The sixth level arithmetic unit includes The eighth unit circuit and five NOT gates; The seventh-level operation unit includes n fourth-unit circuits and 11 NOT gates; among them, The fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after adder operation.

9. An adder circuit, characterized in that: The adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected operation units, wherein: The first-level operation unit comprises n+1 logic operation unit circuits as claimed in claim 1 and n+1 NOT gates; the output of each logic operation unit circuit as claimed in claim 1 is connected to the input of a NOT gate, and the output of each NOT gate serves as the output of the first-level operation unit; The second-level computing unit includes A second unit circuit and a third unit circuit; wherein the second unit circuit is used to implement P i:j =and(P i-1:j ,P i:k ), G i:j =ao(P i:k ,G k-1:j ,G i:k ); the third unit circuit is used to implement G i:j =ao(P i:k ,G k-1:j ,G i:k ); The third-level computing unit includes the second unit circuit and one the third unit circuit; The fourth level arithmetic unit includes the second unit circuit and one the third unit circuit; The fifth-level operation unit includes one of the second unit circuits and one of the third unit circuits; The sixth-level operation unit includes two of the third unit circuits; The seventh level arithmetic unit includes the third unit circuit; The eighth level arithmetic unit includes the third unit circuit; The ninth level arithmetic unit includes the third unit circuit; The tenth-level operation unit includes n fourth unit circuits; wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after adder operation.

10. An adder circuit, characterized in that: The adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected operation units, wherein: The first-level operation unit includes n+1 logic operation unit circuits as claimed in claim 1; The second-level computing unit includes a logic operation unit circuit as claimed in claim 3, and an eighth unit circuit; wherein, The eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The third-level computing unit includes a logic operation unit circuit as claimed in claim 2 and a seventh unit circuit; wherein, The seventh unit circuit is used to implement !G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , where i, k, and j represent the input data of the adder respectively. The bit data, i>k>j; The fourth level arithmetic unit includes a logic operation unit circuit as claimed in claim 3 and one of the eighth unit circuits; The fifth-level operation unit comprises one logic operation unit circuit as claimed in claim 2 and one of the seventh unit circuits; The sixth-level operation unit includes two of the eighth unit circuits and one NOT gate; The seventh-level operation unit includes two seventh unit circuits and two NOT gates, and one eighth unit circuit; The eighth-level operation unit includes four eighth-unit circuits and four NOT gates, and three seventh-unit circuits; The ninth level arithmetic unit includes The eighth unit circuit and 8 NOT gates; The tenth-level operation unit includes n fourth-unit circuits and 1 NOT gate; among them, The fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the output i-th bit data after adder operation.

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