Wiring method and apparatus for chip layout, and device and storage medium

Abstract

The present application particularly relates to the technical field of quantum. Disclosed are a wiring method and apparatus for a chip layout, and a device and a storage medium. The method comprises: determining wiring from a first wiring port to a second wiring port on a chip layout, wherein the wiring comprises tangent segments and arcs which are connected in an alternating manner, the straight line where each tangent segment is located is tangent to the circle where the arc connected to the tangent segment is located, each arc uses a vertex on the chip layout as the center of a circle and bypasses a component corresponding to the vertex, and the vertexes are points corresponding to components between the first wiring port and the second wiring port (710); performing recognition on the arcs comprised in the wiring, so as to determine a target arc, wherein the target arc refers to a looping arc, and the "looping" refers to the central angle corresponding to the arc being greater than a threshold value (720); and removing the target arc, and adjusting the wiring, so as to obtain adjusted wiring (730). The method improves the accuracy of wiring.

Description

Chip layout wiring method, device, equipment and storage medium

[0001] This application claims priority to Chinese patent application number 202311160318.1 filed on September 7, 2023, entitled “Wiring method, device, apparatus and storage medium for chip layout”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of the present application relate to the field of quantum technology, and in particular to a wiring method, apparatus, device, and storage medium for a chip layout. Background Art

[0003] In the field of quantum technology, quantum chips are typically prepared by designing a chip layout. This layout includes designing the layout of components, how they are connected, and more.

[0004] In the related art, when routing components that should be connected in a chip layout, the components that need to be bypassed are usually determined based on the source port and the destination port, and the components are bypassed by laying arc lines at the components that need to be bypassed.

[0005] In the above-mentioned related technologies, the layout of the arc circuit may be circling, that is, the central angle of the arc circuit laid out around the component that needs to be bypassed is too large, causing the arc circuit to overlap with other circuits, making the determined wiring relatively unreasonable.

[0006] Summary of the Invention

[0007] The present invention provides a chip layout wiring method, device, equipment and storage medium, which can improve the accuracy of wiring. The technical solution is as follows:

[0008] According to one aspect of an embodiment of the present application, a chip layout wiring method is provided, the method being executed by a computer device, the method comprising:

[0009] Obtaining a routing from a first routing port to a second routing port on the chip layout, the routing including alternating tangent segments and circular arcs, wherein a straight line on which the tangent segments lie is tangent to a circle on which the circular arcs connected to the tangent segments lie, and each circular arc has a vertex on the chip layout as its center and passes around a component corresponding to the vertex, wherein the vertex is a point corresponding to a component passed between the first routing port and the second routing port;

[0010] Identifying the arcs included in the wiring to determine a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to a central angle of the arc being greater than a threshold;

[0011] The target arc is eliminated, and the wiring is adjusted to obtain an adjusted wiring.

[0012] According to one aspect of an embodiment of the present application, a chip is provided. The chip is processed based on a chip layout, and the wiring of the chip layout is obtained using the wiring method of the above-mentioned chip layout.

[0013] According to one aspect of an embodiment of the present application, a wiring device for a chip layout is provided, the device comprising:

[0014] a routing determination module, configured to determine a routing from a first routing port to a second routing port on the chip layout, wherein the routing includes alternating tangent segments and circular arcs, wherein the straight lines on which the tangent segments lie are tangent to the circles on which the circular arcs connected to the tangent segments lie, and each circular arc has a vertex on the chip layout as its center and passes around a component corresponding to the vertex, wherein the vertex is a point corresponding to a component passed between the first routing port and the second routing port;

[0015] an arc determination module, configured to identify the arcs included in the wiring and determine a target arc, wherein the target arc refers to an arc with a spinning phenomenon, wherein the spinning phenomenon refers to an arc with a central angle greater than a threshold;

[0016] The wiring adjustment module is used to remove the target arc and adjust the wiring to obtain an adjusted wiring.

[0017] According to one aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the above-mentioned chip layout wiring method.

[0018] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the wiring method of the above-mentioned chip layout.

[0019] According to one aspect of an embodiment of the present application, a computer program product is provided, which includes a computer program, and the computer program is loaded and executed by a processor to implement the above-mentioned chip layout wiring method.

[0020] The technical solutions provided in the embodiments of the present application can bring the following beneficial effects:

[0021] By identifying arcs in the wiring, arcs with central angles greater than a threshold are identified and deleted, so that arcs with central angles greater than the threshold are not included in the adjusted wiring, that is, all arcs with circling phenomena are deleted, and arcs without circling phenomena are retained, thereby avoiding the phenomenon of overlapping of lines determined according to the wiring due to circling, making the wiring on the chip layout more reasonable and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of a topological wiring provided by the related art;

[0023] FIG2 is a schematic diagram of a wiring provided by the related art;

[0024] FIG3 is a schematic diagram of a spinning phenomenon provided by the related art;

[0025] FIG4 is a schematic diagram of a topology wiring to a wiring diagram provided by the related art;

[0026] FIG5 is a schematic diagram of another circling phenomenon provided by the related art;

[0027] FIG6 is a schematic diagram of a method for avoiding circling provided by an embodiment of the present application;

[0028] FIG7 is a flow chart of a chip layout wiring method provided by one embodiment of the present application;

[0029] FIG8 is a schematic diagram of a target arc provided by one embodiment of the present application;

[0030] FIG9 is a flowchart of a chip layout wiring method provided by another embodiment of the present application;

[0031] FIG10 is a schematic diagram of a target arc provided by another embodiment of the present application;

[0032] FIG11 is a flowchart of a chip layout wiring method provided by another embodiment of the present application;

[0033] FIG12 is a flowchart of a chip layout wiring method provided by another embodiment of the present application;

[0034] FIG13 is a flowchart of a chip layout wiring method provided by another embodiment of the present application;

[0035] FIG14 is a block diagram of a chip layout wiring method provided in one embodiment of the present application;

[0036] FIG15 is a schematic diagram of another embodiment of the present application to prevent the phenomenon of spinning in circles;

[0037] FIG16 is a block diagram of a wiring device for a chip layout according to an embodiment of the present application;

[0038] FIG17 is a block diagram of a wiring device for a chip layout provided by another embodiment of the present application;

[0039] FIG18 is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0041] Before introducing the embodiments of the present application, some terms involved in the present application are first explained.

[0042] 1. Superconducting quantum chip: The central processing unit of a superconducting quantum computer. A quantum computer is a machine that uses the principles of quantum mechanics to perform calculations. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum computers possess strong parallel processing capabilities, enabling them to solve problems that are intractable for classical computers. The zero-resistance nature of superconducting qubits and their similar manufacturing process to integrated circuits make quantum computing systems based on superconducting qubits one of the most promising approaches for practical quantum computing.

[0043] 2. Electronic Design Automation (EDA): This refers to a design approach in the electronics field that uses computer software (design-aided software) to automate and complete electronics design tasks. This includes processes such as integrated circuit chip functional design, functional verification, and layout and routing. The software tools used in this category are collectively referred to as EDA tools.

[0044] 3. Automatic routing: Use software to automatically complete the layout of circuits and chip designs, and connect components according to rules and requirements. It is mostly used in large-scale and ultra-large-scale integrated circuit design and is one of the links. It is usually performed after the layout is completed.

[0045] 4. Layout: Also known as a circuit diagram, this is a design that describes the layout, placement, and connection of components within a circuit. It represents the physical geometry of the actual circuit. The layout design must adhere to constraints such as manufacturing process, timing, area, and power consumption. The layout design file contains information about the shape, area, and location of each hardware unit on the chip.

[0046] 5. Component: A general term for elements and devices, which are electronic components and constituent elements in the circuit, such as resistors, capacitors, inductors, etc.

[0047] 6. Co-Planar Waveguide (CPW): A microwave planar transmission line with superior performance and easy processing, used to transmit microwave signals. Co-planar waveguide technology is widely used in superconducting quantum chips.

[0048] 7. Radius of curvature: The radius of curvature is the reciprocal of curvature and is represented by R. For a curve, the radius of curvature is equal to the radius of the arc closest to the curve at that point.

[0049] 8. Microwave: This refers to electromagnetic waves with wavelengths between infrared and radio waves, with frequencies between 300 MHz and 300 GHz, higher than radio frequencies and also known as ultra-high frequency electromagnetic waves. Microwaves are used in radar, wireless networks, and sensors. In superconducting quantum devices, microwaves in a resonant cavity can carry and store quantum states, enabling quantum information processing.

[0050] 9. Phase: It is a measure that describes the change in signal waveform, and its unit is angle (deg) or radian (rad).

[0051] 10. Topology: Topology is the study of topological spaces. Developed from geometry and set theory, it primarily investigates the properties of geometric figures or spaces that remain unchanged after continuous changes in shape. It encompasses concepts such as space, dimension, and transformation. Topology considers only the positional relationships between objects, not their shapes or sizes. Topological wiring is a wiring method based on topological structures and networks.

[0052] 11. Resonance: The full name is simple harmonic oscillation, also known as resonance in physics. In electronics, when a circuit's input and output impedances are nearly zero and the transfer function is close to 1, the impedances or admittances of the circuit components cancel each other out, causing the circuit to oscillate at a specific frequency (the resonant frequency), resulting in higher currents and voltages than the input. This phenomenon is called electrical resonance or circuit resonance. In quantum mechanics, particle resonance is similar to what occurs in classical physics.

[0053] In related technologies, topological routing algorithms are distinct from grid routing algorithms. The topological routing process can be roughly divided into the following stages: 1) Applying a mincut (minimum cut algorithm) to the pre-placed circuit layout (with components already placed) to decompose it into independent chip layouts; 2) Performing multi-layer planning on individual chips, decomposing them into independent circuits per layer by introducing cross-layer auxiliary devices such as vias. Generally speaking, the positions of components are fixed, and the positions of components on different layers do not intersect; 3) Triangulating the components on each layer, and applying a topological algorithm to achieve topological routing between multiple pairs of routing ports. A topological routing is a pair of wires connecting a source port and a destination port, bypassing existing devices. Routing ports include source ports (pins) (control / read pins for bits) and destination ports (pads) (solder pads around the chip). The routing process involves finding the appropriate wires to connect the pins and pads. Routing ports are also considered a type of device on the chip layout, equivalent to two special devices. It is necessary to first determine the pins and pads, and then the wiring process is to find the lines connecting the pins and pads, and not intersecting with other devices and the routes are as short as possible. That is, first merge the polygons abstracted from the devices in different layers into the same layer (different devices generally do not intersect), and then triangulate all polygons (Delaunay Triangulation, DT for short). After triangulation, you will get a lot of lines between the points of the polygons corresponding to the components; 4) Generate the corresponding final wiring for each set of topological wiring. One requirement of wiring is to bypass these components, so starting from the upper end point of the polygon and taking a certain distance along the lines of these triangulations, you can determine the path line required for wiring. In some embodiments, triangulation is implemented by a constrained triangulation (Constrained Delaunay Triangulation, CDT for short) algorithm based on the DT algorithm, that is, adding some restriction edges on the basis of DT. The purpose of the DT algorithm is to divide the plane point set into triangles, and the circumscribed circle of each triangle cannot contain the fixed points of other triangles.

[0054] However, in the above-mentioned related technologies, when converting from topological routing to routing, due to some algorithmic blind spots, the converted routing may cause the lines to circle. As shown in Figure 1, it is the algorithm output of topological routing, in which the multiple initial signal lines 110 formed by the initial path points pass through the triangulated grid 100 formed by the components. As shown in Figure 2, it is normal routing, and there is no intersection or overlap among the multiple normally laid out lines 210. In some embodiments, based on the components and routing ports in the chip layout, the triangulation line and the square obstacle to be bypassed (the component to be bypassed) are determined, and then the appropriate distance is selected according to the spacing along the triangulation line from the fixed point of the obstacle. The spacing here is the shortest spacing between different lines and the shortest spacing between devices that have been specified in advance. Figure 2 shows that when multiple lines take different distances to bypass the same obstacle, the multiple topological paths are finally achieved. The intersection of the triangulation line and the initial signal line is the topological path point of the different lines (multiple lines need to be routed at the same time) found in this step. As shown in FIG. 3 , this is abnormal wiring, wherein the routed line 310 circles at 300 , causing the routed line 310 and the routed line 320 to cross at 300 .

[0055] Specifically, in the routing algorithm of the related art, the path points around each signal line that needs to be laid are first determined, and then these path points are traversed to find suitable path points, and the triangulation endpoints near the path points (the triangulation endpoints are the vertices of a series of line segments after the multiple polygons abstracted from all (devices) on the input chip layout and triangulated) are determined to determine which triangulation endpoints need to be bypassed, that is, the center, radius, starting point and end point of a series of arcs on the final routing path are determined, and finally these arcs are connected to form the final signal line through tangents. Among them, the triangulation endpoints here are also the vertices in the embodiment of the present application, and the two represent the same meaning, both of which are used to represent the vertices of the polygons corresponding to the components. As shown in Figure 4, the topological routing 400 includes multiple path points obtained according to the topological algorithm. Optionally, the routing 410 is determined according to the topological routing 400. In some embodiments, the routing may go in circles. As shown in Figure 5, one of the two CPW lines that have been laid out has gone in circles and intersected with the other CPW line at 510. The consequences of circling are clear in both Figures 3 and 5. Not only is the CPW signal itself interrupted due to the incorrect routing, but adjacent wiring is also interrupted due to the circling. Therefore, this flaw, from topology routing algorithms to routing, needs to be addressed.

[0056] The technical solution provided by the implementation of this application proposes a general supplementary algorithm to solve this type of spinning problem through an in-depth analysis of the rendering algorithm from topological wiring to wiring. As shown in Figure 6, sub-graph (a) shows the phenomenon of line crossing caused by spinning in circles, and sub-graph (b) shows the lines that are normally laid out to avoid spinning in circles. This application realizes the transition from sub-graph (a) to sub-graph (b). Based on topological wiring, this application has developed an algorithm that can automatically identify the phenomenon of signal lines spinning in circles during wiring and reasonably avoid it, so that the automatically laid signal lines will not intersect or be too close to each other due to the above reasons, meeting the automatic wiring requirements of superconducting quantum chips. Therefore, this application has the following innovations: EDA automatic wiring for superconducting quantum chips, automatic identification of signal line spinning situations, and selection of only appropriate wiring paths according to different spinning situations.

[0057] Please refer to Figure 7, which shows a flowchart of a wiring method for a chip layout provided by an embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC (Personal Computer), a tablet computer, a server, etc. Exemplarily, a computer program for executing the present method can be run in the computer device, and the wiring method for the chip layout provided by this embodiment is implemented by the computer program. As shown in Figure 7, the method may include at least one of the following steps 710 to 730.

[0058] Step 710: Obtain a wiring from a first wiring port to a second wiring port on the chip layout. The wiring includes alternating tangent segments and circular arcs. The straight line on which the tangent segment is located is tangent to the circle on which the circular arc connected to the tangent segment is located. Each circular arc has a vertex on the chip layout as its center and passes around the component corresponding to the vertex. The vertex is the point corresponding to the component passed between the first wiring port and the second wiring port.

[0059] A chip layout is a design that describes the layout, placement, and connection of components within a circuit. It is a planar geometric representation of the physical structure of the actual circuit. A chip layout can be for a quantum chip, such as a superconducting quantum chip. Superconducting quantum chips utilize extensive coplanar waveguide technology to transmit microwave signals. The chip layout design file contains information about the shape, area, and location of each hardware unit on the chip. Automatic routing can be used to add wiring information to the layout design file to connect each point, ultimately generating a layout design file containing this wiring information. This wiring information can include the location of each component and how the components are connected.

[0060] In some embodiments, the first wiring port and the second wiring port are considered to be a pair of wiring ports. Among them, the first wiring port can be considered as the starting position of wiring, and the second wiring port can be considered as the ending position of wiring. Generally speaking, in a chip layout containing multiple components, multiple pairs of wiring ports should be included. The embodiment of the present application does not limit the number of wiring ports, nor does it limit the number of wiring ports that need to be wired. In the embodiment of the present application, only one pair of wiring ports is used for wiring as an example, and the wiring of other pairs of wiring ports can refer to the embodiment of the present application. When the wiring between all pairs of wiring ports in the chip layout is determined to be completed, the chip layout is considered to be wired. Of course, which specific ports should be connected is set in advance by the developer or determined in advance according to the algorithm. The embodiment of the present application performs subsequent wiring work only after it is determined which wiring ports need to be connected.

[0061] The first wiring port: is a component or a part of the component. In some embodiments, the first wiring port is a special component that is where the wiring starts. In other embodiments, the first wiring port is a pin of the component. Exemplarily, the first wiring port is a pin (bit control / read pin). In some embodiments, different components in the chip layout and different pins in the components have different characteristics. Assuming that component a and component b need to be connected, first find component a, then find a pin that meets the pin characteristics from the various pins of component a, and use that pin as the first wiring port.

[0062] The second wiring port: is a component or a part of the component. In some embodiments, the second wiring port is a special component, which is where the wiring ends. In other embodiments, the second wiring port is the solder pad of the component. Exemplarily, the second wiring port is a pad (the solder pads around the chip). Optionally, the wiring process is to find a suitable line to connect the pin and the pad. Assuming that component a and component b need to be connected, after finding the pin that meets the pin characteristics from the various pins of component a as the first wiring port, find the solder pad of component b and use the solder pad as the second wiring port.

[0063] In some embodiments, there may be many components between the first wiring port and the second wiring port, so it is necessary to bypass the various components in the middle. As shown in Figure 2, rectangle 200 represents a component on the chip layout. Generally speaking, when designing the chip layout, the components will be graphed, that is, the components will be mapped to various graphics in the chip layout. The rectangle 200 shown in Figure 2 is the result of a component graph. Different components may correspond to different graphics, and the number of vertices of different graphics may be different. When wiring, it is necessary to consider which vertices of rectangle 200 to bypass. In some embodiments, when wiring, the component is bypassed by laying out an arc line at the vertex that needs to be bypassed. Therefore, when passing through multiple components, there are multiple vertices that need to be bypassed, that is, there are multiple arcs. In some embodiments, the vertex is the endpoint of the triangulation line obtained after a constrained triangulation algorithm is performed on the components on the chip layout, that is, the triangulation endpoint. Exemplarily, the point corresponding to the component, that is, the triangulation endpoint, refers to the vertex of the polygon corresponding to the component. The polygons corresponding to the components here refer to the representation of real components with polygons at the algorithm level. The polygons represent the size and shape of the components. The real components and the polygons on the chip layout are one-to-one corresponding.

[0064] In some embodiments, the wiring in step 710 can be the initial wiring or the wiring in the adjustment process, and this application does not limit this. The initial wiring refers to the wiring that has not been adjusted for the first time determined based on the first wiring port and the second wiring port. In some embodiments, the initial wiring includes at least one arc with the vertex as the center and at least two tangent segments connecting the arcs. For example, when there is only one component that needs to be bypassed, the arc corresponding to the vertex of the component is determined, the starting position of the arc and the line connecting the first wiring port are tangent to the arc, and the ending position of the arc and the line connecting the second wiring port are tangent to the arc. Of course, the embodiment of the present application does not limit the number of components that need to be bypassed. The number of components that need to be bypassed is positively correlated with the number of arcs in the wiring. When the number of components that need to be bypassed is greater, the number of arcs in the wiring also increases accordingly.

[0065] In addition, the alternating connection in the embodiments of the present application refers to the alternating connection between arcs and tangent segments, that is, one arc is connected to two tangent segments in front and behind, and one tangent segment is connected to at least one arc. When the tangent segment is a tangent segment passing through the first wiring port, the tangent segment is connected to only one arc. When the tangent segment is a tangent segment passing through the second wiring port, the tangent segment is connected to only one arc. Except for the two tangent segments connected to the first wiring port or the second wiring port, all other tangent segments are connected to the two arcs in front and behind.

[0066] In some embodiments, there is no limit on the size of the central angle of each arc and the length of each tangent segment, and the arc is tangent to the two tangent segments before and after it. That is, the arc and the tangent segments are connected alternately one by one in the wiring. In some embodiments. The tangent segments and the arc are connected alternately in the wiring. In some embodiments, the beginning of the wiring is the tangent segment connected to the first wiring port, and the end of the wiring is the tangent segment connected to the second wiring port. In some embodiments, as shown in 1020 of Figure 10, the line segment d3t3, the arc t3 counterclockwise to f3, the line segment f3t4, the arc t4 counterclockwise to f4, and the line segment f4d4 are connected to each other to obtain the wiring from the first wiring port d3 to the second wiring port d4, and the line segment d3t3, the line segment f3t4, and the line segment f4d4 are all tangent segments, that is, the tangent segments are connected alternately with the arcs. Line segment d3t3 is tangent to the circle C3 extending counterclockwise from arc t3 to f3. Line segment f3t4 is tangent to both the circle C3 extending counterclockwise from arc t3 to f3 and the circle C4 extending counterclockwise from arc t4 to f4. Line segment f4d4 is tangent to the circle C4 extending counterclockwise from arc t4 to f4. The routing begins with tangent segment d3t3 connected to the first routing port d3, and ends with tangent segment f4d4 connected to the second routing port d4.

[0067] In some embodiments, there may be a situation where two tangent arcs are connected. In this case, the position where the two arcs are connected is tangent to the two arcs. We believe that there is a tangent segment at the position where the two arcs are connected. The tangent segment connects the two arcs together, but the length of the tangent segment is limited.

[0068] Step 720 , identifying arcs included in the wiring, and determining a target arc. The target arc refers to an arc with a spinning phenomenon. The spinning phenomenon refers to an arc with a central angle greater than a threshold.

[0069] In some embodiments, at least one arc included in the wiring is identified for spinning, and a target arc is determined. In the embodiment of the present application, the arc with the spinning phenomenon is considered to be an arc with a central angle greater than a threshold. Since each arc corresponds to two front and rear tangent segments when the embodiment of the present application is wiring, when the central angle corresponding to the arc is too large, the front and rear tangent segments intersect, resulting in the occurrence of the circle spinning phenomenon. In some embodiments, the threshold is equal to 180 degrees. When the central angle corresponding to the arc is greater than 180 degrees, it is considered that the arc has a spinning phenomenon. Of course, the embodiment of the present application does not limit the specific value of the threshold.

[0070] In some embodiments, as shown in Figure 8, 810 shows that there is a target arc. If the arc from point a1 counterclockwise to point b1 has a center angle less than the threshold, then the arc a1 to b1 does not belong to the target arc. If the arc from point a2 counterclockwise to point b2 has a center angle greater than the threshold, then the arc a2 to b2 belongs to the target arc. In some embodiments, as shown in Figure 8, 820 shows that there is no target arc. If the arc from point a3 counterclockwise to point b3 has a center angle less than the threshold, then the arc a3 to b3 does not belong to the target arc. If the arc from point a4 counterclockwise to point b4 has a center angle less than the threshold, then the arc a4 to b4 belongs to the target arc. That is, the target arc determined according to step 720 in Figure 8 is only the arc a2 counterclockwise to b2.

[0071] In some embodiments, the recognition in step 720 may also be referred to as spinning recognition, circling recognition, or circling recognition.

[0072] Step 730 , remove the target arc, adjust the wiring, and obtain an adjusted wiring.

[0073] In some embodiments, after determining the target arc, the target arc is removed and the routing is redefined. For example, the target arc and the corresponding preceding and following tangent segments are removed simultaneously. The remaining lines are reconnected to meet the aforementioned routing requirements, thereby obtaining an adjusted routing.

[0074] The technical solution provided by the embodiment of the present application identifies arcs in the wiring, identifies arcs with central angles greater than a threshold, and deletes the arcs, so that the adjusted wiring does not include arcs with central angles greater than the threshold, that is, all arcs with circling phenomena are deleted, while arcs without circling phenomena are retained. For the retained arcs, the tangent segments connected to them are re-determined to obtain updated arcs, and the updated arcs are continuously judged to see whether they have circling phenomena, until all arcs in the wiring do not have circling phenomena, and the final wiring is obtained. Therefore, the phenomenon of overlapping of lines determined according to the wiring due to circling is avoided, making the wiring on the chip layout more reasonable and accurate.

[0075] Please refer to Figure 9, which shows a flowchart of a wiring method for a chip layout provided by another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, tablet computer, server, etc. Exemplarily, a computer program for executing the present method can be run in the computer device, and the wiring method for the chip layout provided by this embodiment is implemented by the computer program. As shown in Figure 9, the method may include at least one of the following steps 910 to 940.

[0076] Step 910: Obtain a wiring from a first wiring port to a second wiring port on the chip layout. The wiring includes alternating tangent segments and arcs. The straight line on which the tangent segment is located is tangent to the circle on which the arc connected to the tangent segment is located. Each arc has a vertex on the chip layout as its center and passes around the component corresponding to the vertex. The vertex is the point corresponding to the component passed between the first wiring port and the second wiring port.

[0077] Step 920: For each arc, obtain the starting point of the arc and the first tangent segment, the vertex corresponding to the arc, and the ending point of the arc and the second tangent segment; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc, and the second tangent segment in sequence.

[0078] In some embodiments, the front and rear tangent segments of the arc are considered to include a front tangent segment (a first tangent segment) and a rear tangent segment (a second tangent segment). The point of tangency between the first tangent segment and the arc is considered the starting point of the arc, and the point of tangency between the second tangent segment and the arc is considered the ending point of the arc. The routing direction from the first routing port to the second routing port first passes through the starting point of tangency, then the arc, and finally the ending point of tangency.

[0079] In some embodiments, as shown in 1010 of FIG10 , according to the routing direction from the first routing port to the second routing port, the route first passes through the starting point t1 of the first arc with c1 as the center, then passes through arc t1 counterclockwise to f1, with f1 being the final tangent point of the arc. After passing through the first arc, the route passes through line segment f1 to t2, with t2 being considered the starting point of the second arc with c2 as the center, passes through arc t2 counterclockwise to f2, and finally continues routing backward along the tangent direction of the final tangent point f2. Specifically, line segment d1 to t1 is the first tangent segment of the arc with c1 as the center, and line segment f1 to t2 is the second tangent segment of the arc with c1 as the center. Simultaneously, line segment f1 to t2 is the first tangent segment of the arc with c2 as the center, and line segment f2 to d2 is the second tangent segment of the arc with c2 as the center.

[0080] Step 930: Determine whether the arc is the target arc based on the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the ending point of tangency.

[0081] In some embodiments, when the wiring direction on the arc is counterclockwise, the arc is determined to be a target arc when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is counterclockwise. In some embodiments, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is clockwise, the arc is determined not to be a target arc. Conversely, when the wiring direction on the arc is clockwise, the arc is determined to be a target arc when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is clockwise. In some embodiments, when the direction formed from the starting point of tangency, the vertex corresponding to the arc to the final tangency point is counterclockwise, the arc is determined not to be a target arc.

[0082] The wiring direction of the arc in Figure 10 is counterclockwise. In some embodiments, as shown in 1010 of Figure 10, based on the positional relationship between the starting point t1, the vertex c1 corresponding to the arc, and the end point f1, it is determined whether the arc with c1 as the center is the target arc. Since the direction formed by the starting point t1, the vertex c1 corresponding to the arc to the end point f1 is clockwise, the arc is not the target arc. In some embodiments, based on the positional relationship between the starting point t2, the vertex c2 corresponding to the arc, and the end point f2, it is determined whether the arc with c2 as the center is the target arc. Since the direction formed by the starting point t2, the vertex c2 corresponding to the arc to the end point f2 is counterclockwise, the arc is the target arc.

[0083] In some embodiments, as shown in 1020 of FIG10 , based on the positional relationship between the starting point of tangency t3, the vertex c3 corresponding to the arc, and the final point of tangency f3, it is determined whether the arc with c3 as the center is the target arc. Since the direction formed by the starting point of tangency t3, the vertex c3 corresponding to the arc, and the final point of tangency f3 is clockwise, the arc is not the target arc. In some embodiments, based on the positional relationship between the starting point of tangency t4, the vertex c4 corresponding to the arc, and the final point of tangency f4, it is determined whether the arc with c4 as the center is the target arc. Since the direction formed by the starting point of tangency t4, the vertex c4 corresponding to the arc, and the final point of tangency f4 is clockwise, the arc is not the target arc.

[0084] In some embodiments, step 930 includes at least one of steps 931 to 933 (not shown in the figure).

[0085] Step 931, determine the first direction and the second direction; wherein the first direction refers to the rotation direction from the starting point to the end point and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point along the arc to the end point, and the rotation direction is clockwise or counterclockwise.

[0086] The first direction shown in step 931 refers to the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc. Of course, the first direction can not only be the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc, but also the rotation direction from the final point to the vertex corresponding to the arc and then to the starting point, or the rotation direction from the vertex corresponding to the arc to the starting point and then to the final point. The specific form of the first direction is not limited in this application. Of course, in addition to the first direction, other directions can also be used to determine whether it is the target arc. For example, in the description of Figure 10 in the above embodiment, the direction of judgment is the rotation direction from the starting point to the vertex corresponding to the arc and then to the final point.

[0087] The second direction shown in step 931 can be considered as the routing direction of the arc.

[0088] Step 932: If the first direction and the second direction are different, determine that the arc is a target arc.

[0089] Step 933: If the first direction and the second direction are the same, determine that the arc is not the target arc.

[0090] In step 931, the first direction is the rotation direction from the starting point of tangency to the final point of tangency and then to the vertex corresponding to the arc. If the first direction and the second direction are different, the arc is determined to be the target arc. If the first direction and the second direction are the same, the arc is determined not to be the target arc.

[0091] The arc in Figure 10 is now identified using the method of steps 931 to 933. As shown in Figure 10, the second direction, i.e., the routing direction of the arc, is counterclockwise. In some embodiments, as shown in 1010 of Figure 10, for an arc centered on c1, if the first direction, i.e., the rotation direction from the starting point t1 to the final point f1 and then to the vertex c1 corresponding to the arc, is counterclockwise, and the first and second directions are the same, the arc is determined not to be the target arc. For an arc centered on c2, if the first direction, i.e., the rotation direction from the starting point t2 to the final point f2 and then to the vertex c2 corresponding to the arc, is clockwise, and the first and second directions are different, the arc is determined to be the target arc. In some embodiments, as shown in 1020 of Figure 10, if the first direction, i.e., the rotation direction from the starting point t3 to the final point f3 and then to the vertex c3 corresponding to the arc, is counterclockwise, and the first and second directions are the same, the arc is determined not to be the target arc. For the arc with c4 as the center, the first direction, that is, the rotation direction from the starting point t4 to the final point f4 and then to the vertex c4 corresponding to the arc, is counterclockwise. If the first direction and the second direction are the same, it is determined that the arc is not the target arc.

[0092] Through the above method, whether it is a target arc is determined based on whether the first direction and the second direction are consistent. The solution is simple and convenient, and the accuracy of the determined target arc is high.

[0093] In some embodiments, step 930 also includes at least one of steps 934 to 936 (not shown in the figure).

[0094] Step 934, determine the central angle corresponding to the arc; wherein the central angle has the vertex corresponding to the arc as the vertex, one side of the central angle passes through the starting tangent point, and the other side of the central angle passes through the ending tangent point.

[0095] This application does not limit the specific method for determining the central angle of a circle. When the center position, the starting point of tangency, and the final point of tangency are known, the central angle can be calculated using the arc length formula l = πrα / 180, where l is the arc length, r is the radius of the arc, and α is the number of segments of the central angle.

[0096] Step 935: If the central angle is greater than the threshold, the arc is determined to be the target arc.

[0097] Step 936: If the central angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

[0098] In some embodiments, if the central angle is greater than a threshold, the arc is determined to be the target arc, and if the central angle is less than or equal to the threshold, the arc is determined not to be the target arc. Optionally, the threshold is 180 degrees.

[0099] Step 940: remove the target arc and adjust the wiring to obtain an adjusted wiring.

[0100] Through the above method, whether it is a target arc is determined according to the degree of the central angle of the circle, providing multiple methods for determining the target arc, and improving the diversity of the methods for determining the target arc.

[0101] In the technical solution provided in the embodiment of the present application, whether the arc is the target arc is determined based on the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the final point of tangency, which can make the accuracy of the determined target arc higher. In addition, two specific methods are shown: one is to determine whether it is the target arc based on whether the first direction and the second direction are consistent, and the other is to determine whether it is the target arc based on the degree of the central angle. Therefore, the diversity of the methods for determining the target arc is improved.

[0102] Please refer to Figure 11, which shows a flowchart of a wiring method for a chip layout provided in another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, tablet computer, server, etc. Exemplarily, a computer program for executing the method can be run in the computer device, and the wiring method for the chip layout provided in this embodiment is implemented by the computer program. As shown in Figure 11, the method may include at least one of the following steps 1110 to 1140.

[0103] Step 1110: Obtain a wiring from a first wiring port to a second wiring port on the chip layout. The wiring includes alternating tangent segments and circular arcs. The straight line on which the tangent segment is located is tangent to the circle on which the circular arc connected to the tangent segment is located. Each circular arc has a vertex on the chip layout as its center and passes around the component corresponding to the vertex. The vertex is the point corresponding to the component passed between the first wiring port and the second wiring port.

[0104] Step 1120 : For each circular arc, obtain a first tangent segment and a second tangent segment connected by the circular arc; wherein, according to the routing direction from the first routing port to the second routing port, the routing sequentially passes through the first tangent segment, the circular arc, and the second tangent segment.

[0105] In some embodiments, as shown in FIG10 , line segment d1 to t1 is the first tangent segment of the arc with c1 as the center, and line segment f1 to t2 is the second tangent segment of the arc with c1 as the center. Simultaneously, line segment f1 to t2 is the first tangent segment of the arc with c2 as the center, and line segment f2 to d2 is the second tangent segment of the arc with c2 as the center.

[0106] Step 1130 : Determine whether the arc is a target arc based on the positional relationship between the first tangent segment and the second tangent segment.

[0107] In some embodiments, the positional relationship between the first tangent segment and the second tangent segment can include intersecting and non-intersecting. In some embodiments, if the first tangent segment intersects the second tangent segment, it can be considered that the arc connected to the first tangent segment and the second tangent segment has rotated, and the arc can be determined as the target arc.

[0108] In some embodiments, if the first tangent segment and the second tangent segment intersect, the arc is determined to be the target arc. If the first tangent segment and the second tangent segment do not intersect, the arc is determined not to be the target arc.

[0109] In some embodiments, as shown in 1010 of FIG10 , if the first tangent segment and the second tangent segment of the arc with c1 as the center do not intersect, the arc is determined not to be the target arc. If the first tangent segment and the second tangent segment of the arc with c2 as the center do intersect, the arc is determined to be the target arc.

[0110] In some embodiments, as shown in 1020 of FIG10 , if the first tangent segment and the second tangent segment of the arc with c3 as the center do not intersect, the arc is determined not to be the target arc. If the first tangent segment and the second tangent segment of the arc with c4 as the center do not intersect, the arc is determined not to be the target arc.

[0111] In some embodiments, it is also possible to determine whether the arc is the target arc based on the position of the intersection of the first tangent segment and the second tangent segment. For example, if there is no intersection between the first tangent segment and the second tangent segment, or the intersection of the first tangent segment and the second tangent segment is located on the extension line of the first tangent segment, or the intersection of the first tangent segment and the second tangent segment is located on the extension line of the second tangent segment, then it is considered that the arc is not rotating, and the arc is not the target arc and does not need to be eliminated. If the intersection of the first tangent segment and the second tangent segment is located on the first tangent segment and the second tangent segment, then it is considered that the arc is rotating and needs to be eliminated, and the arc is determined to be the target arc.

[0112] Step 1140 , remove the target arc, adjust the wiring, and obtain an adjusted wiring.

[0113] For other steps in the embodiment of this application, please refer to the explanation of the above embodiment and will not be repeated here.

[0114] The technical solution provided by the embodiments of the present application determines whether an arc is spinning and needs to be eliminated based on whether the front and rear tangent segments of the arc intersect. If the two tangent segments intersect, the arc is considered to be spinning and needs to be eliminated. If the two tangent segments do not intersect, the arc is considered to be non-rotating and does not need to be eliminated. Therefore, the present application improves the efficiency of arc recognition by determining whether there is intersection, further improving the speed of wiring.

[0115] Please refer to Figure 12, which shows a flowchart of a wiring method for a chip layout provided in another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, tablet computer, server, etc. Exemplarily, a computer program for executing the present method can be run in the computer device, and the wiring method for the chip layout provided in this embodiment is implemented by the computer program. As shown in Figure 12, the method may include at least one of the following steps 1210 to 1250.

[0116] Step 1210: Obtain a wiring from a first wiring port to a second wiring port on the chip layout. The wiring includes alternating tangent segments and circular arcs. The straight line on which the tangent segment is located is tangent to the circle on which the circular arc connected to the tangent segment is located. Each circular arc has a vertex on the chip layout as its center and passes around the component corresponding to the vertex. The vertex is the point corresponding to the component passed between the first wiring port and the second wiring port.

[0117] Step 1220 , identifying arcs included in the wiring, and determining a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to an arc with a central angle greater than a threshold.

[0118] Step 1230 , remove the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted routing; wherein the previous connection object is the previous arc or the first routing port, and the next connection object is the next arc or the second routing port.

[0119] In some embodiments, when the target arc is removed, the tangent segments connected to the target arc are also removed. For example, as shown in 1010 of FIG10 , if the first tangent segment and the second tangent segment of the arc centered on c2 intersect, the arc is determined to be the target arc. When the target arc centered on c2 is removed, the tangent segments from f1 to t2 and from f2 to d2 are also removed.

[0120] In some embodiments, after the target arc is removed, rewiring is required. That is, a tangent segment connecting the previous connection object and the next connection object of the target arc needs to be generated to obtain the adjusted wiring. In some embodiments, the previous connection object of the target arc is the first wiring port and the next connection object is the next arc, then a tangent segment connecting the first wiring port and the next arc needs to be generated. When the connection method changes, the size of the center angle corresponding to the next arc also changes. In some embodiments, the previous connection object of the target arc is the previous arc and the next connection object is the next arc, then a common tangent connecting the previous arc and the next arc needs to be generated. When the connection method changes, the size of the center angle corresponding to the previous arc and the next arc also changes. In some embodiments, the previous connection object of the target arc is the previous arc and the next connection object is the second wiring port, then a tangent segment connecting the previous arc and the second wiring port needs to be generated. When the connection method changes, the size of the center angle corresponding to the previous arc also changes.

[0121] In some embodiments, after the target arc is eliminated, an arc connecting the tangent segments connected to the target arc can also be generated. As shown in 1010 of Figure 10, if the first tangent segment and the second tangent segment of the arc with c2 as the center intersect, it is determined that the arc is the target arc. After the target arc with c2 as the center is eliminated, an arc connecting the tangent segment from f1 to t2 and the tangent segment from f2 to d2 is generated. However, the generated arc may be the same as the eliminated target arc with c2 as the center, resulting in repetition in the process of eliminating and generating arcs. Therefore, the embodiment of the present application does not provide a detailed introduction to this method.

[0122] Step 1240: Determine whether there is a target arc in the wiring.

[0123] In some embodiments, all arcs in the adjusted routing continue to be judged one by one to determine whether the target arc exists. In other embodiments, it is not necessary to identify all arcs, and only the arcs before and after the arc deleted in the last adjustment are re-identified. This is because the tangent points corresponding to the front and rear arcs are changed in the adjusted routing, which may cause the rotation of the front and rear arcs to change, but does not affect other arcs except the arcs before and after the target arc. Therefore, only the front and rear arcs after the rerouting are identified, without the need to identify all arcs, thereby improving the recognition efficiency.

[0124] If yes, execute step 1220. If no, execute step 1250.

[0125] Step 1250, end the process and obtain the adjusted chip layout.

[0126] In some embodiments, after removing arcs, if no arcs that need to be removed are found during the traversal of the adjusted routing, it is considered that there is no spinning phenomenon in the routing, and the routing is considered to be the final planned routing. That is, when the physical device is routed according to the routing in the chip layout, the lines in the physical device do not spin. It should be understood that the routing in the embodiments of the present application refers to the chip layout level, not the actual layout of the signal lines, but rather reflects the actual device connection status in electronic form.

[0127] In some embodiments, all arcs are traversed only once. If an arc is determined not to be the target arc, the next arc is identified. If an arc is determined to be the target arc, the arc is discarded and the connected objects are reconnected. It is then determined whether the reconnected connected objects are not objects that need to be discarded. If neither object is required to be discarded, the next arc is identified.

[0128] The technical solution provided by the embodiment of the present application eliminates the target arc that has spun and then generates a tangent segment connecting the previous connection object and the next connection object of the target arc, which can ensure the integrity of the routing. Generating a tangent segment connecting the previous connection object and the next connection object of the target arc, rather than generating an arc connecting the tangent segment connected to the target arc, can avoid the spinning phenomenon during the routing adjustment process, which may cause process errors.

[0129] In addition, re-identifying the adjusted wiring can ensure that there are no arcs in the adjusted wiring due to the spinning phenomenon, thereby avoiding the phenomenon that the lines determined according to the wiring overlap due to spinning, making the wiring on the chip layout more reasonable and accurate.

[0130] Please refer to Figure 13, which shows a flowchart of a wiring method for a chip layout provided in another embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, tablet computer, server, etc. Exemplarily, a computer program for executing the present method can be run in the computer device, and the wiring method for the chip layout provided in this embodiment is implemented by the computer program. As shown in Figure 13, the method may include at least one of the following steps 1310 to 1350.

[0131] Step 1310: Determine at least one vertex from the points corresponding to the components on the chip layout.

[0132] In some embodiments, the vertex corresponding to the initial line segment is determined based on the distance between the vertices corresponding to each component and the initial line segment, and the initial line segment is a line segment formed by the line connecting the first routing port and the second routing port; with the vertex as the midpoint, the first line segment is determined based on the line connecting the midpoint and the starting point of the initial line segment, and the second line segment is determined based on the line connecting the midpoint and the ending point of the initial line segment; the first line segment and the second line segment are respectively used as the initial line segments, and the step of determining the vertex corresponding to the initial line segment is performed until there is no corresponding vertex in the line segment formed by any two adjacent points, and the process is terminated, and any adjacent points include at least one of the following: the first routing port, at least one determined vertex, and the second routing port.

[0133] In some embodiments, the positions of the various components in the chip layout are fixed, that is, the positions of the points corresponding to the various components are fixed. For the line connecting the first wiring port to the second wiring port, determine the vertex with the shortest distance from the line as the vertex that needs to be bypassed based on the line segment. Based on the vertex, divide the line connecting the first wiring port to the second wiring port into two line segments, and determine again whether there are vertices that need to be bypassed for each of the two line segments, until there are no vertices that need to be bypassed in the line segment after the bisection, and stop looking for vertices that need to be bypassed. In some embodiments, the distance from the determined vertex to the line segment, in addition to meeting the minimum value, must at least meet the distance condition. For example, the distance from the vertex to the line segment must also be less than a first value. When the distance from the vertex to the line segment is the minimum value and less than the first value, it is determined that the vertex is the vertex that needs to be bypassed corresponding to the line segment.

[0134] Step 1320: For the k-th vertex among the at least one vertex, determine a circle with the k-th vertex as the center, where k is a positive integer.

[0135] In some embodiments, when determining the routing, it is also necessary to draw a circle for each vertex. The radius of the circle corresponding to each vertex is not limited in this application and can be preset in advance or generated according to an algorithm.

[0136] In some embodiments, the radius of the circle corresponding to the kth vertex is determined based on the number of wires laid at the kth vertex; wherein, when the number of wires laid is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of wires laid is s, the radius of the circle corresponding to the kth vertex is equal to the product of s and the wiring interval and the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; based on the radius of the circle corresponding to the kth vertex, a circle with the kth vertex as the center is determined.

[0137] In some embodiments, the route laid out at the kth vertex here can be considered as a geometric route that needs to be laid out bypassing the kth vertex. It should be understood that for a certain point a, all geometric routes that need to be laid out bypassing point a need to bypass point a. As the number of planned routes increases, the radius of the arc that bypasses point a should also become larger during routing.

[0138] In some embodiments, when the number of laid lines is 0, the radius r of the circle corresponding to the kth vertex is equal to the shortest safe distance; when the number of laid lines is s, the radius r of the circle corresponding to the kth vertex during the (s+1)th line laying is equal to s*wiring interval + shortest safe distance. This application does not limit the specific values ​​of the shortest safe distance and wiring interval.

[0139] Step 1330 : determining an initial routing according to the first routing port, the second routing port, and the circles corresponding to the vertices.

[0140] In the embodiments of the present application, there is no specific limitation on how to determine the initial routing based on the first routing port, the second routing port, and the circles corresponding to each vertex. The determined routing satisfies the constraints. Optionally, the routing constraints include at least two tangent segments and at least one circular arc, where the circular arc is tangent to its preceding and succeeding tangent segments. In some embodiments, the routing only includes tangent segments and circular arcs.

[0141] In some embodiments, the tangent to the circle corresponding to the first vertex is determined through the first routing port, and the tangent point is determined as the starting tangent point corresponding to the first vertex; a common tangent is drawn between the circle corresponding to the kth vertex and the circle corresponding to the k+1th vertex, and the intersection of the common tangent and the circle corresponding to the kth vertex is determined as the ending tangent point corresponding to the kth vertex, and the intersection of the common tangent and the circle corresponding to the k+1th vertex is determined as the starting tangent point corresponding to the k+1th vertex; the tangent to the circle corresponding to the last vertex is determined through the second routing port, and the tangent point is determined as the ending tangent point corresponding to the last vertex; the arc formed by the starting tangent point and the ending tangent point corresponding to the kth vertex is determined as the arc corresponding to the kth vertex; starting from the first routing port, each tangent segment and the arc corresponding to each vertex are alternately connected in sequence until the second routing port is connected to obtain the initial routing.

[0142] In some embodiments, when a common tangent is drawn between the circle corresponding to the kth vertex and the circle corresponding to the k+1th vertex, the tangent segment formed by the two tangent points does not intersect with the line segment connecting the kth vertex and the k+1th vertex.

[0143] Step 1340 , identifying each arc included in the wiring and determining a target arc, where the target arc is an arc with a spinning phenomenon, where the spinning phenomenon means that the central angle of the arc is greater than a threshold;

[0144] Step 1350: remove the target arc and adjust the wiring to obtain an adjusted wiring.

[0145] The technical solution provided in the embodiment of the present application selects suitable vertices from the vertices of the components as vertices in a distance-first manner when determining the wiring, and determines suitable vertices multiple times through bisection. The bisection method of determining vertices can effectively improve the accuracy of the determined vertices and greatly improve the efficiency of vertex determination.

[0146] On the other hand, the routing determined by sequentially connecting arcs and tangent segments requires the shortest signal lines, which helps save wiring costs. Furthermore, determining the arc radius based on the number of laid lines helps avoid line intersections, thereby improving routing accuracy.

[0147] Please refer to Figure 14, which shows a block diagram of a chip layout wiring method provided by one embodiment of the present application. The method can be executed by a computer device, which can be any electronic device with computing and storage capabilities, such as a PC, tablet computer, server, etc. Illustratively, a computer program for executing the method can be run on the computer device, and the chip layout wiring method provided by this embodiment can be implemented through the computer program.

[0148] As shown in 1400 of Figure 14 , this application has designed an algorithm that automatically identifies signal line loops and properly avoids them. This algorithm successfully solves the problem of loops during signal line routing, making signal line routing more efficient and effective. First, the initial path points are laid out, and the routingedge endpoints are traversed to determine circular arcs. The routingedge is the triangulated line on which the initial path point lies, and the routingedge endpoints are the triangulation endpoints. Optionally, the triangulation endpoints are component vertices. During a round of traversal, there will be multiple path points, and thus multiple endpoints of the triangulated line. From these endpoints, the point to be bypassed must be selected by sorting, serving as the center of the circle, and the radius must be determined. The traversal process is similar to the previous embodiment, primarily through recursive traversal. Initially, a line is constructed with only two points: the start and end points. Each subsequent round splits the line in half, selecting the most suitable point for the current round. The recursion stops when no suitable point is found. Once all endpoints to be bypassed are determined, the radius of all arcs and radii is determined based on the radius of the circle corresponding to each endpoint. All arcs are then traversed and loops identified. Determine whether the first direction and the second direction are the same. If they are the same, the arc is considered not to be the target arc. If they are different, the arc is considered to be the target arc and the target arc is eliminated. Determine whether the traversal is completed. When all arcs are traversed, the wiring is completed. That is, the main implementation method is to traverse each arc on the path line and detect whether it is spinning in circles. If spinning occurs, the arc is deleted, and the connection is made by recalculating the tangent point positions of the arcs before and after the deleted arc. Specifically, taking Figure 15 as an example, in the wiring 1510 of Figure 15, assuming that the wiring direction is from the first wiring port h1 to the second wiring port h8, the wiring includes tangent segment h1h2, arc h2 counterclockwise to h3, tangent segment h3 to h4, arc h4 counterclockwise to h5, tangent segment h5 to h6, arc h6 counterclockwise to h7, and tangent segment h7h8. According to the technical solutions provided in the above embodiments, it is not difficult to find that arc h4 counterclockwise to h5 has a circling and reversing phenomenon. Based on the technical solutions provided in the embodiments of the present application, arc h4 counterclockwise to h5 is identified as the target arc, that is, the arc to be deleted. After deleting the arc, the tangent segments h4h4 and h5h6 connected to the arc are also deleted accordingly. As shown in 1520 in Figure 15, the common tangent between the circle containing arc h2 counterclockwise to h3 and arc h6 counterclockwise to h7 is re-determined, that is, tangent segment g3g4. Based on this tangent segment h3h4, the updated arc h2 counterclockwise to g3 and the updated arc g4 counterclockwise to h7 connected to the tangent segment can be obtained. This process can be classified as the operation of deleting a node in a single linked list and connecting its previous and next nodes.The wiring determined based on the technical solution provided in the embodiment of the present application completely solves the problem of signal lines spinning in circles that existed in the previous wiring, and will not be too close to or even overlap with adjacent signal lines.

[0149] The core link of the improved algorithm proposed in this application is the automatic identification and avoidance of signal line circles. When performing corresponding analysis and identification on the arc, if arcwind and fcwind are different, where arcwind is the direction of the arc route, that is, the second direction, and tfcwind is the direction from the starting point of the arc to the end point of the arc and then to the center of the arc, that is, the first direction, then the arc will circle, and subsequent avoidance is required. If arcwind and tfcwind are the same, no circle phenomenon occurs. By deleting the rotating arc and connecting the arcs before and after it by recalculating the tangent point, a reasonable avoidance of the signal line spinning problem is achieved. In some embodiments, since the position of the arc tangent point changes dynamically, the following two situations are likely to occur during the layout process: 1. A certain arc is normal at the beginning and does not go in circles, but later the tangent point position changes, causing the arc to go in circles; 2. A certain arc is going in circles at the beginning, but because the adjacent arc changes, the tangent point position changes accordingly, so the arc returns to normal. Based on the above analysis, we put the recognition and judgment logic of the arc circling phenomenon in the algorithm until the positions of all arc tangent points are completely determined (by recursively traversing the initial path points, continuously finding the most suitable triangulation point as the middle point for binary recursion, and determining all the centers and radii that need to be bypassed, the corresponding tangent points are also determined) and then make corresponding judgments and avoidances. And after deleting the arc that is going in circles, it is necessary to recalculate the tangent point positions of the arcs before and after the deleted arc (if any), so that the transition of the signal line between the arcs is more natural and reasonable.

[0150] In an exemplary embodiment, a chip is further provided. The chip is obtained based on a chip layout, and the wiring of the chip layout is obtained using the wiring method of the chip layout mentioned in the above embodiment. In some embodiments, the chip is a quantum chip.

[0151] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0152] Please refer to Figure 16, which shows a block diagram of a wiring device for a chip layout provided by one embodiment of the present application. The device has the function of implementing the above-mentioned method example, and the function can be implemented by hardware or by hardware executing corresponding software. The device can be the computer device described above, or it can be set in a computer device. As shown in Figure 16, the device 1600 includes: a wiring determination module 1610, an arc determination module 1620, and a wiring adjustment module 1630.

[0153] The routing determination module 1610 is used to determine the routing from the first routing port to the second routing port on the chip layout, where the routing includes alternating tangent segments and arcs, each arc having a vertex on the chip layout as its center and passing around the component corresponding to the vertex, where the vertex is a point corresponding to a component passing between the first routing port and the second routing port.

[0154] The arc determination module 1620 is used to identify each of the arcs included in the wiring and determine a target arc. The target arc refers to an arc with a spinning phenomenon. The spinning phenomenon means that the central angle corresponding to the arc is greater than a threshold.

[0155] The wiring adjustment module 1630 is used to remove the target arc and adjust the wiring to obtain an adjusted wiring.

[0156] In some embodiments, as shown in FIG. 17 , the arc determination module 1620 includes a point acquisition unit 1621 and an arc determination unit 1622 .

[0157] The point acquisition unit 1621 is configured to acquire, for each of the arcs, a starting point of tangency between the arc and a first tangent segment, a vertex corresponding to the arc, and an ending point of tangency between the arc and a second tangent segment. The routing direction from the first routing port to the second routing port sequentially passes through the first tangent segment, the arc, and the second tangent segment.

[0158] The arc determining unit 1622 is configured to determine whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the end point of tangency.

[0159] In some embodiments, the arc determination unit 1622 is used to determine a first direction and a second direction; wherein, the first direction refers to the rotation direction from the starting point to the end point and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point along the arc to the end point, and the rotation direction is clockwise or counterclockwise; if the first direction and the second direction are different, it is determined that the arc is the target arc; if the first direction and the second direction are the same, it is determined that the arc is not the target arc.

[0160] In some embodiments, the arc determination unit 1622 is also used to determine the central angle corresponding to the arc; wherein, the central angle has the vertex corresponding to the arc as the vertex, one side of the central angle passes through the starting tangent point, and the other side of the central angle passes through the end tangent point; if the central angle is greater than the threshold, it is determined that the arc is the target arc; if the central angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

[0161] In some embodiments, as shown in FIG17 , the arc determination module 1620 further includes a line segment acquisition unit 1623 .

[0162] The line segment acquisition unit 1623 is used to obtain, for each of the arcs, a first tangent segment and a second tangent segment connected by the arc; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc and the second tangent segment in sequence.

[0163] The arc determining unit 1622 is further configured to determine whether the arc is the target arc according to the positional relationship between the first tangent segment and the second tangent segment.

[0164] In some embodiments, the arc determination unit 1622 is further used to determine that the arc is the target arc if the first tangent segment and the second tangent segment intersect; and to determine that the arc is not the target arc if the first tangent segment and the second tangent segment do not intersect.

[0165] In some embodiments, the wiring adjustment module 1630 is used to eliminate the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted wiring; wherein the previous connection object is the previous arc or the first wiring port, and the next connection object is the next arc or the second wiring port.

[0166] In some embodiments, the arc determination module 1620 is further used to start from the step of identifying each of the arcs included in the wiring and determining the target arc; if the target arc does not exist in the wiring, the process is terminated to obtain the adjusted chip layout.

[0167] In some embodiments, as shown in FIG. 17 , the routing determination module 1610 includes a vertex determination unit 1611 , a circle determination unit 1612 , and a routing determination unit 1613 .

[0168] The vertex determination unit 1611 is configured to determine at least one vertex from points corresponding to each of the components on the chip layout.

[0169] The circle determining unit 1612 is configured to determine, for at least one of the vertices, a circle with the k-th vertex as its center, where k is a positive integer.

[0170] The wiring determination unit 1613 is configured to determine the initial wiring according to the first wiring port, the second wiring port, and the circles corresponding to the vertices.

[0171] In some embodiments, the wiring determination unit 1613 is used to determine the tangent to the circle corresponding to the first vertex through the first wiring port, and determine the tangent point as the starting tangent point corresponding to the first vertex; draw a common tangent between the circle corresponding to the k-th vertex and the circle corresponding to the k+1-th vertex, determine the intersection of the common tangent and the circle corresponding to the k-th vertex as the ending tangent point corresponding to the k-th vertex, and determine the intersection of the common tangent and the circle corresponding to the k+1-th vertex as the starting tangent point corresponding to the k+1-th vertex; determine the tangent to the circle corresponding to the last vertex through the second wiring port, and determine the tangent point as the ending tangent point corresponding to the last vertex; determine the arc formed by the starting tangent point and the ending tangent point corresponding to the k-th vertex as the arc corresponding to the k-th vertex; starting from the first wiring port, alternately connect each tangent segment and the arc corresponding to each vertex in sequence until the second wiring port is connected to obtain the initial wiring.

[0172] In some embodiments, the circle determination unit 1612 is used to determine the radius of the circle corresponding to the kth vertex based on the number of lines laid at the kth vertex; wherein, when the number of laid lines is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of laid lines is s, the radius of the circle corresponding to the kth vertex is equal to the product of s and the wiring interval and the sum of the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; according to the radius of the circle corresponding to the kth vertex, a circle with the kth vertex as the center is determined.

[0173] In some embodiments, the vertex determination unit 1611 is used to determine the vertex corresponding to the initial line segment based on the distances from the points corresponding to each of the components to the initial line segment, where the initial line segment is a line segment formed by the line connecting the first wiring port and the second wiring port; taking the vertex as the midpoint, determining the first line segment based on the line connecting the midpoint and the starting point of the initial line segment, and determining the second line segment based on the line connecting the midpoint and the ending point of the initial line segment; taking the first line segment and the second line segment as the initial line segments respectively, executing the step of determining the vertex corresponding to the initial line segment, until there is no corresponding vertex in the line segment formed by any two adjacent points, then terminating the process, where the any adjacent points include at least one of the following: the first wiring port, at least one of the determined vertex, and the second wiring port.

[0174] It should be noted that the apparatus provided in the above embodiments, when implementing its functions, is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0175] Please refer to Figure 18, which shows a block diagram of a computer device 1800 provided in one embodiment of the present application. The computer device 1800 can be any electronic device with data computing, processing, and storage capabilities. The computer device 1800 can be used to implement the chip layout wiring method provided in the above embodiments.

[0176] Typically, the computer device 1800 includes a processor 1801 and a memory 1802 .

[0177] The processor 1801 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1801 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), or PLA (Programmable Logic Array). The processor 1801 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1801 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1801 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0178] Memory 1802 may include one or more computer-readable storage media, which may be non-transitory. Memory 1802 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in memory 1802 is used to store a computer program, which is configured to be executed by one or more processors to implement the above-mentioned chip layout wiring method.

[0179] Those skilled in the art will appreciate that the structure shown in FIG. 18 does not limit the computer device 1800 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0180] In an exemplary embodiment, a computer-readable storage medium is further provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the computer program is used to implement the wiring method of the above-mentioned chip layout. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives) or an optical disk, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0181] In an exemplary embodiment, a computer program product is also provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the aforementioned chip layout wiring method.

[0182] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application do not limit this.

[0183] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip layout wiring method, the method being executed by a computer device, the method comprising: Obtaining a wiring from a first wiring port to a second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, each circular arc has a vertex on the chip layout as a center and bypasses a component corresponding to the vertex, and the vertex is a point corresponding to a component passing between the first wiring port and the second wiring port; Identify the arc included in the wiring to determine a target arc, where the target arc refers to an arc with a spinning phenomenon, where the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold; The target arc is eliminated, and the wiring is adjusted to obtain an adjusted wiring.

2. The method according to claim 1, wherein: The step of identifying the arc included in the wiring and determining the target arc includes: For each of the arcs, a starting point of tangency between the arc and the first tangent segment, a vertex corresponding to the arc, and an end point of tangency between the arc and the second tangent segment are obtained; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the arc, and the second tangent segment in sequence; Whether the arc is the target arc is determined according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the final point of tangency.

3. The method according to claim 2, wherein: The determining whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the terminal point of tangency includes: Determine a first direction and a second direction; wherein the first direction refers to the rotation direction from the starting point to the final point and then to the vertex corresponding to the arc, and the second direction refers to the rotation direction from the starting point along the arc to the final point, and the rotation direction is clockwise or counterclockwise; If the first direction and the second direction are different, determining that the arc is the target arc; If the first direction and the second direction are the same, it is determined that the arc is not the target arc.

4. The method according to claim 2, wherein: The determining whether the arc is the target arc according to the positional relationship between the starting point of tangency, the vertex corresponding to the arc, and the terminal point of tangency includes: Determine the central angle corresponding to the arc; wherein the central angle has a vertex corresponding to the arc as a vertex, one side of the central angle passes through the starting tangent point, and the other side of the central angle passes through the final tangent point; If the central angle is greater than the threshold, determining that the arc is the target arc; If the central angle is less than or equal to the threshold, it is determined that the arc is not the target arc.

5. The method according to claim 1, wherein: The step of respectively identifying each of the arcs included in the wiring and determining a target arc includes: For each of the circular arcs, a first tangent segment and a second tangent segment connected by the circular arc are obtained; wherein, according to the wiring direction from the first wiring port to the second wiring port, the wiring passes through the first tangent segment, the circular arc and the second tangent segment in sequence; Whether the arc is the target arc is determined according to the positional relationship between the first tangent segment and the second tangent segment.

6. The method according to claim 5, wherein: The determining, based on the positional relationship between the first tangent segment and the second tangent segment, whether the arc is the target arc includes: If the first tangent segment and the second tangent segment intersect, determining that the arc is the target arc; If the first tangent segment and the second tangent segment do not intersect, it is determined that the arc is not the target arc.

7. The method according to any one of claims 1 to 6, wherein: The step of removing the target arc and adjusting the wiring to obtain the adjusted wiring includes: Eliminate the target arc, generate a tangent segment connecting the previous connection object and the next connection object of the target arc, and obtain an adjusted wiring; wherein the previous connection object is the previous arc or the first wiring port, The latter connection object is the latter arc or the second wiring port.

8. The method according to any one of claims 1 to 7, wherein: The target arc is removed, the wiring is adjusted, and the adjusted wiring further includes: Again, the step of identifying each of the arcs included in the wiring and determining a target arc is started; If the target arc does not exist in the wiring, the process ends and an adjusted chip layout is obtained.

9. The method according to any one of claims 1 to 8, wherein: The obtaining of the wiring from the first wiring port to the second wiring port on the chip layout includes: Determine at least one vertex from points corresponding to each of the components on the chip layout; For a k-th vertex among at least one of the vertices, determine a circle with the k-th vertex as the center, where k is a positive integer; The initial wiring is determined according to the first wiring port, the second wiring port, and the circles corresponding to the vertices.

10. The method according to claim 9, wherein: The determining the initial wiring according to the first wiring port, the second wiring port, and the circles corresponding to the vertices respectively includes: Determine a tangent line to a circle corresponding to a first vertex through the first wiring port, and determine a tangent point as a starting tangent point corresponding to the first vertex; Draw a common tangent line between the circle corresponding to the k-th vertex and the circle corresponding to the k+1-th vertex, determine the intersection point of the common tangent line with the circle corresponding to the k-th vertex as the final tangent point corresponding to the k-th vertex, and determine the intersection point of the common tangent line with the circle corresponding to the k+1-th vertex as the starting tangent point corresponding to the k+1-th vertex; Determine a tangent line to the circle corresponding to the last vertex through the second wiring port, and determine the tangent point as the final tangent point corresponding to the last vertex; The arc formed by the starting point and the ending point of tangency corresponding to the k-th vertex is determined as the arc corresponding to the k-th vertex; Starting from the first wiring port, each tangent segment and the arc corresponding to each vertex are alternately connected in sequence until the second wiring port is connected to obtain the initial wiring.

11. The method according to claim 9 or 10, wherein: The determining of a circle with the k-th vertex as the center includes: Determine the radius of the circle corresponding to the kth vertex according to the number of wires laid at the kth vertex; wherein, when the number of laid wires is 0, the radius of the circle corresponding to the kth vertex is equal to the shortest safety distance; when the number of laid wires is s, the radius of the circle corresponding to the kth vertex is equal to the sum of the product of s and the wiring interval and the shortest safety distance, s is a positive integer, and the shortest safety distance and the wiring interval are constants; According to the radius of the circle corresponding to the k-th vertex, a circle with the k-th vertex as the center is determined.

12. The method according to any one of claims 9 to 11, wherein: Determining at least one vertex from points corresponding to each of the components on the chip layout includes: Determine, according to the distances from the points corresponding to the components to the initial line segment, the vertex corresponding to the initial line segment, wherein the initial line segment is a line segment formed by the line connecting the first wiring port and the second wiring port; Taking the vertex as the middle point, determining the first line segment according to the line connecting the middle point and the starting point of the initial line segment, and determining the second line segment according to the line connecting the middle point and the ending point of the initial line segment; The first line segment and the second line segment are respectively used as the initial line segments, and the step of determining the vertices corresponding to the initial line segments is performed until there are no corresponding vertices for the line segments formed by any two adjacent points, and the process is terminated, wherein the any adjacent points include at least one of the following: the first wiring port, at least one of the determined vertices, and the second wiring port.

13. A chip, wherein the chip is processed based on a chip layout, and the wiring of the chip layout is obtained by the method according to any one of claims 1 to 12.

14. The chip according to claim 13, wherein: The chip is a quantum chip.

15. A wiring device for a chip layout, the device comprising: a wiring determination module, configured to obtain a wiring from a first wiring port to a second wiring port on the chip layout, wherein the wiring includes alternately connected tangent segments and circular arcs, wherein the straight line where the tangent segment is located is tangent to the circle where the circular arc connected to the tangent segment is located, and each circular arc has a vertex on the chip layout as a center and bypasses a component corresponding to the vertex, and the vertex is a point corresponding to a component passing between the first wiring port and the second wiring port; An arc determination module, used for identifying the arc included in the wiring, and determining a target arc, wherein the target arc refers to an arc with a spinning phenomenon, wherein the spinning phenomenon refers to a central angle corresponding to the arc being greater than a threshold value; The wiring adjustment module is used to remove the target arc and adjust the wiring to obtain the adjusted wiring.

16. A computer device, comprising a processor and a memory, wherein a computer program is stored in the memory, and the processor is configured to execute the computer program to implement the method according to any one of claims 1 to 12.

17. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, wherein the computer program is loaded and executed by a processor to implement the method according to any one of claims 1 to 12.

18. A computer program product, comprising a computer program, wherein the computer program is loaded and executed by a processor to implement the method according to any one of claims 1 to 12.

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