Signal reception method and apparatus

Abstract

A signal reception method and apparatus, which can reduce the peak power of signals inputted into an analog-to-digital converter (ADC), thereby reducing the quantization noise, and improving the signal reception performance. The method comprises: a reception device receiving a first signal, performing down-conversion on the first signal to obtain a second signal, then determining a third signal on the basis of the second signal, sampling the third signal, and determining a target signal, wherein the first signal comprises the target signal, and comb mapping is used for the target signal, that is, the target signal occupies one subcarrier in every M consecutive subcarriers. The third signal comprises superposition of K delay signals of the second signal, and the delay time associated with a k-th delay signal among the K delay signals is represented by formula (1), where T is the duration of the first signal; k=1, 2, ..., K; σ is greater than or equal to 0; M is a positive integer greater than 1; and K is a positive integer greater than or equal to M.

Description

Signal receiving method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 8, 2023, with application number 202311160179.2 and application name “A Signal Receiving Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of communications, and in particular to a signal receiving method and apparatus. Background Art

[0003] In the future, wireless sensing may become an important component of mobile communication systems. To achieve friendly coexistence of communication and sensing, allowing communication and sensing to share radio frequency and baseband components, orthogonal frequency domain multiplexing (OFDM) waveforms can be used in mobile communication systems to implement communication and sensing.

[0004] In wireless sensing scenarios based on OFDM waveforms, a sensing device can transmit signals in a comb or interlace format. For example, as shown in Figure 1, one subcarrier out of every M (e.g., M = 2) consecutive subcarriers can be used by the sensing device to transmit a sensing signal, while the remaining subcarriers in the M consecutive subcarriers can be used by other sensing devices or communication devices to transmit signals.

[0005] During OFDM waveform-based signal reception, the receiver inputs the full-bandwidth time-domain signal into an analog-to-digital converter (ADC), converting it into a digital signal. A frequency-domain digital signal is then obtained through serial-to-parallel conversion (S->P) and a fast Fourier transform (FFT). Finally, the subcarrier signal containing the perceived signal is extracted from the frequency-domain digital signal for subsequent processing.

[0006] Due to the limited quantization accuracy of ADCs, signals passing through the ADC typically generate additional quantization noise. During the aforementioned signal reception process, the ADC's quantization noise depends on the combined power of the perceived signal and other user signals. If the power of the other user signals received by the receiver is too high, this will result in significant quantization noise, impacting reception performance.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a signal receiving method and apparatus, which can reduce the peak power of a signal input to an ADC, thereby reducing quantization noise and improving signal receiving performance.

[0009] In a first aspect, a signal receiving method is provided, which can be executed by a receiving device, or by a component of the receiving device, such as a processor, chip, or chip system of the receiving device, or by a logic module or software that can realize all or part of the functions of the receiving device. The method includes: receiving a first signal, the first signal including a target signal, the target signal occupying one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1; down-converting the first signal to obtain a second signal; determining a third signal based on the second signal, the third signal including a superposition of K delayed signals of the second signal, the delay time associated with the kth delayed signal among the K delayed signals being Wherein, T is the time length of the first signal, k=1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the third signal is sampled to determine the target signal.

[0010] Based on this scheme, since the delay time associated with the kth delayed signal is Therefore, the K delayed signals of the second signal can be equivalent to a periodic extension of the second signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as sampling in the frequency domain, after periodically extending and superimposing in the time domain, it can be considered that the target signal has been extracted. As a result, the signal input to the ADC during sampling does not include signals from other users, that is, the peak power of the signal input to the ADC is the power of the target signal, and does not include the power of signals from other users. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing quantization noise and improving signal reception performance.

[0011] In one possible design, the time length of the first signal is the length of one OFDM symbol. That is, the first signal can be understood as a signal on one OFDM symbol. The length of one OFDM symbol can refer to the length excluding the CP part.

[0012] In one possible design, the down-conversion frequency is related to the carrier frequency of the first signal and / or the position of the target signal. Exemplarily, the down-conversion frequency may be the same as the frequency of a subcarrier included in (or occupied by) the target signal.

[0013] Based on this possible design, after downconversion, the high-frequency RF signal (i.e., the first signal) can be moved to baseband for processing. Furthermore, the downconversion frequency is determined based on the carrier frequency of the first signal and / or the location of the target signal. After downconversion, the target signal can be aligned with the baseband zero frequency, facilitating subsequent processing.

[0014] In one possible design, determining the third signal based on the second signal includes: delaying the second signal K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The third signal is obtained by superimposing K delayed signals. Based on this possible design, the third signal can be obtained by directly delaying the second signal K times and superimposing them.

[0015] In one possible design, determining a third signal based on the second signal includes: determining the third signal using X stages of circuits, wherein: the output signal of the i-th stage circuit is a signal obtained by superimposing an input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, where i=1, 2, …, X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th stage circuit is a signal obtained by delaying the second signal by δ; when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit; the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

[0016] In one possible design, K = 2 X The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after superposition of the signals.

[0017] Based on this possible design, since the input signal of the i-th stage circuit only needs to be delayed once, only one delay device is required in each stage circuit, that is, only X delay devices are needed in total to determine the third signal, which can reduce the number of delay devices and thus save the cost of the receiving device.

[0018] In one possible design, The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after the superposition of the signals, ∏ represents the cumulative multiplication, K i Is a positive integer.

[0019] In one possible design, K=M, sampling the third signal includes: The third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0020] Based on this possible design, the length of the time domain range can be That is to say, within the time length T of an OFDM symbol, the ADC used for sampling is only turned on or working for Compared with turning on the ADC all the time within the time length T, the sampling power consumption of the ADC can be reduced, thereby reducing the power consumption of the receiving device. In addition, based on this possible design, if the sampling rate of sampling the third signal within this time range is NΔf C , then the length of the time domain range is In this case, the target signal includes sampling points. A discrete Fourier transformation (DFT) of the N-point DFT is performed on the entire OFDM symbol to obtain the frequency domain signal corresponding to the target signal. Compared to performing a DFT of at least N points on the entire OFDM symbol, this approach can reduce the number of DFT points, lowering the DFT module requirements and cost.

[0021] In one possible design, K=M, sampling the third signal includes: delaying the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A; in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal. Exemplarily, A is a positive integer less than or equal to M. Specifically, A=M.

[0022] In one possible design, the sampling frequency used when sampling the a-th delayed signal of the third signal is greater than or equal to NΔf C / A, where N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer, Δf C Alternatively, the sampling frequency of the a-th delayed signal of the third signal is B / A, where B is the bandwidth of the first signal.

[0023] Based on this possible design, the receiving device delays the third signal A times and samples the delayed third signal within the aforementioned time domain range. This is equivalent to making additional copies of the target signal in the time domain and sampling these multiple copies of the time domain signal. This can be considered to increase the total sample length. While the total number of sampling points remains unchanged, each sample can be sampled at a lower frequency, thereby reducing the sampling frequency and lowering the performance requirements and cost of the ADC.

[0024] In one possible design, among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

[0025] Based on this possible design, the different sampling positions of any two delayed signals can ensure that the sampling points of any two delayed signals are different, and the corresponding sampling results are not repeated, thereby ensuring sufficient sampling and improving sampling performance.

[0026] In one possible design, K=M-1+C, where C is a positive integer. For example, C is a positive integer less than or equal to M. Specifically, C=M.

[0027] In one possible design, sampling the third signal includes: sampling the third signal in segments C. The c-th segment sampling corresponds to the third signal being within a time range c, where c = 1, 2, ..., C, and the time range c is:

[0028] The reference point of time range c is the start time of the first signal.

[0029] In one possible design, the sampling frequency used when sampling the third signal in segment C is greater than or equal to NΔf C / C, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

[0030] Based on the above two possible designs, the sampling frequency and the number of DFT points can also be reduced, thereby reducing the capability requirements and costs of the ADC and DFT modules.

[0031] In a possible design, in the C-segment sampling of the third signal, the sampling positions of any two segments are different.

[0032] In one possible design, the third signal is sampled to determine the target signal, including: sampling the third signal to obtain a first time domain sequence, performing an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0033] Based on this possible design, only A single-point DFT can produce the frequency domain signal corresponding to the target signal. Compared to performing at least N-point DFT on the signal across the entire OFDM symbol, this approach can reduce the number of DFT points, lowering the DFT module requirements and cost.

[0034] In a second aspect, a device is provided, which may be a communication device or a sensing device. The device includes a first circuit. The first circuit is configured to determine a third signal based on a second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is The second signal is a signal obtained by down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k = 1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the third signal is the input signal of the analog-to-digital converter. The technical effects brought about by the second aspect can be referred to the technical effects brought about by the first aspect above, and will not be repeated here.

[0035] In one possible design, the apparatus further includes at least one of the following: an antenna, a mixer, an analog-to-digital converter, a DFT module, and a second circuit.

[0036] In one possible design, the first circuit includes K delays and an adder. The kth delay in the K delays is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the K delayed signals of the second signal to obtain a third signal. The adder is a K-input adder.

[0037] In a possible design, the special δ=0, then the delay associated with the first delayed signal in the above design is 0, which is equivalent to the second signal itself, so the first delayed signal can be obtained without passing through the delayer. Therefore, the first circuit can include K-1 delayers and an adder. The kth delayer in the K-1 delayers is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the second signal and K-1 delayed signals of the second signal to obtain a third signal. The adder is a K-input adder. Based on this possible design, one delayer can be reduced.

[0038] In one possible design, the first circuit includes X stages of circuits. In the X stages of circuits, the output signal of the i-th stage circuit is a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, where i=1, 2, …, X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th stage circuit is a signal obtained by delaying the second signal by δ; when i>1, the input signal of the i-th stage circuit is the output signal of the (i-1)-th stage circuit; the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit comprises the superposition of K delayed signals of the second signal.

[0039] In one possible design, K = 2 X In the case of , the i-th stage circuit includes a delayer and an adder. The delayer is used to delay the input signal of the i-th stage circuit. The adder is used for superimposing an input signal of an i-th stage circuit and an output signal of a delay device in the i-th stage circuit.

[0040] In one possible design, In the case of the i-th stage circuit including K i -1 delay and one adder. The K i -1 delay circuit, used to delay the input signal of the i-th stage circuit The adder is used to superimpose the input signal of the i-th stage circuit and the K i -1 delay output signal.

[0041] In one possible design, where K = M, the analog-to-digital converter is used in the time range The third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0042] In one possible design, when K=M, the second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A. Analog-to-digital converter, used in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0043] In one possible design, K = M-1 + B, where B is a positive integer, the analog-to-digital converter is configured to perform C-segment sampling on the third signal. The c-th segment sampling corresponds to the third signal being within a time range c, where c = 1, 2, ..., C, and the time range c is:

[0044] The reference point of time range c is the start time of the first signal.

[0045] In one possible design, the DFT module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein the first time domain sequence is a sampling result corresponding to the third signal, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0046] In one possible design, the antenna is configured to receive a first signal including a target signal, where the target signal occupies one subcarrier in every M consecutive subcarriers.

[0047] In one possible design, a mixer is used to down-convert the first signal to obtain the second signal.

[0048] In one possible design, the device described in the second aspect is a chip or a chip system.

[0049] Among them, the technical effects brought about by any possible design of the second aspect can refer to the technical effects brought about by the corresponding design in the above-mentioned first aspect, and will not be repeated here.

[0050] In a third aspect, a device is provided, which may be a communication device or a sensing device. The device includes a unit or module configured to perform any of the methods described in the first aspect. The module or unit may be implemented in hardware or software, or the hardware may execute a corresponding software implementation. The hardware or software may include one or more modules or units corresponding to the functions.

[0051] In some possible designs, the apparatus may include a processing module and a transceiver module. The processing module may be configured to implement the processing functionality of any of the above aspects and any possible implementations thereof. The transceiver module may include a receiving module and a transmitting module, respectively configured to implement the receiving functionality and the transmitting functionality of any of the above aspects and any possible implementations thereof.

[0052] In some possible designs, the transceiver module may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.

[0053] In a fourth aspect, a device is provided, which may be a communication device or a perception device. The device includes a processor configured to execute any of the methods described in the first aspect. There may be one or more processors. The device may also include a memory for storing computer instructions that, when executed by the processor, cause the device to execute any of the methods described in the first aspect. The memory may be coupled to the processor or may be independent of the processor. The device may also include a communication interface for communicating with modules external to the device.

[0054] The apparatus in the second, third, and fourth aspects may be the receiving device in the first aspect, or a device included in the receiving device, such as a chip or chip system. When the apparatus is a chip, the sending action / function of the apparatus may be understood as output information, and the receiving action / function of the apparatus may be understood as input information.

[0055] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program or instruction, which, when executed on a device, enables the device to perform any of the methods described in the first aspect. The device may be a communication device or a sensing device.

[0056] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a device, enables the device to perform any of the methods described in the first aspect. The device may be a communication device or a sensing device.

[0057] Among them, the technical effects brought about by any design method in the second to sixth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic structural diagram of a comb provided by the present application;

[0059] FIG2 is a schematic diagram of a signal receiving process provided by the present application;

[0060] FIG3 is a schematic diagram of the structure of a communication system provided by the present application;

[0061] FIG4 is a flow chart of a signal receiving method provided by the present application;

[0062] FIG5 is a schematic diagram of a comb or staggered structure provided by the present application;

[0063] FIG6 is a schematic diagram of a signal receiving process provided by the present application;

[0064] FIG7 is a schematic diagram of another signal receiving process provided by the present application;

[0065] FIG8 is a schematic diagram of another signal receiving process provided by the present application;

[0066] FIG9 is a schematic diagram of a flow chart of another signal receiving process provided by the present application;

[0067] FIG10 is a schematic diagram of the location of a sampling point provided in this application;

[0068] FIG11 is a schematic structural diagram of a communication device provided by the present application;

[0069] FIG12 is a schematic structural diagram of another communication device provided by the present application;

[0070] FIG13 is a schematic structural diagram of another communication device provided by the present application;

[0071] FIG14 is a schematic structural diagram of another communication device provided in this application. DETAILED DESCRIPTION

[0072] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0073] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and / or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0074] In addition, to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0075] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0076] It will be understood that the “embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It will be understood that in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0077] It can be understood that in this application, "when...", "when...", "when..." and "if" all mean that corresponding processing will be taken under certain objective circumstances, and do not limit the time, nor do they require any judgment action when implementing them, nor do they mean that there are other limitations.

[0078] It is understood that some optional features in the embodiments of the present application may, in certain scenarios, be implemented independently of other features, such as the solution on which they are currently based, to solve corresponding technical problems and achieve corresponding effects. They may also be combined with other features in certain scenarios as needed. Accordingly, the devices provided in the embodiments of the present application may also implement these features or functions accordingly, which will not be described in detail here.

[0079] In this application, unless otherwise specified, the same or similar parts between the various embodiments can refer to each other. In this application, unless otherwise specified and there is no logical conflict between the various embodiments, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. Different embodiments can be combined to form new embodiments based on their inherent logical relationships. The following description of the embodiments of this application does not constitute a limitation on the scope of protection of this application.

[0080] Wireless sensing is a key technology for the future. In wireless sensing, a transmitting device sends a specific signal (called a transmitted signal), and a receiving device receives the reflected signal from the environment (called a received signal). The transceiver then compares the received signal with the transmitted signal to analyze relevant information about the surrounding environment. For example, this information can be used to analyze the presence of objects to be detected or sensed, the distance between the scatterer and the transceiver, the orientation or angle of the scatterer relative to the transceiver, and the speed of the scatterer relative to the transceiver.

[0081] Wireless sensing can be widely applied in various fields. For example, in the connected car scenario, vehicles can use wireless sensing to obtain information about their surroundings, such as the location and speed of moving objects like other vehicles and pedestrians, and information about relatively stationary objects like road surfaces and fences. In airports, for example, specialized equipment can be deployed to monitor and sense flying objects like drones, preventing them from impacting aircraft takeoff and landing. In homes, wireless sensing can be used to detect intruders, improving security and privacy.

[0082] Wireless sensing can be achieved using waveforms such as frequency modulation continuous wave (FMCW), pulse waveforms, and orthogonal frequency division multiplexing (OFDM). Wireless sensing may become a key component of future mobile communication systems. To achieve the coexistence of communication and sensing, as well as the sharing of RF and baseband components, wireless sensing can be implemented using the same waveform as the communication waveform in mobile communication systems, namely, using OFDM waveforms.

[0083] In OFDM waveforms, time-frequency resources can be divided into different subcarriers in the frequency domain and different OFDM symbols in the time domain. Furthermore, in cyclic prefix (CP) OFDM waveforms, OFDM symbols in the time domain include the CP to combat multipath delay spread.

[0084] In addition, time-frequency resources can be divided into time-frequency resource grids. In the OFDM waveform, the smallest time-frequency resource unit is a resource element (RE). An RE includes one subcarrier in the frequency domain and one OFDM symbol in the time domain. Generally, the length of an OFDM symbol (excluding the CP) is inversely proportional to the subcarrier spacing, that is, if the subcarrier spacing is Δf c , then the length of OFDM symbol T = 1 / Δf c .

[0085] In wireless sensing, it is usually necessary to use a signal with a larger bandwidth to perceive the surrounding environment. In theory, the larger the bandwidth, the higher the delay resolution of the reflection path caused by the scatterer, and the better the perception performance. In a wireless sensing scenario based on OFDM waveform, a sensing device can send signals in the form of a comb or interlace. For example, taking the CP-OFDM waveform as an example, as shown in Figure 1, one subcarrier in every M (such as M=2) consecutive subcarriers can be used for the sensing device to send a sensing signal, and the remaining subcarriers in the M consecutive subcarriers can be used for other sensing devices or communication devices to send signals.

[0086] When the perception signal is sent in a comb-tooth or staggered form, on the one hand, the perception signal can have a larger bandwidth, and on the other hand, the perception signal occupies fewer subcarriers in the bandwidth, so that the remaining subcarriers can be used by other perception devices or communication devices, thereby improving the user capacity in the perception system and communication system.

[0087] At present, the signal receiving process based on OFDM waveform is shown in Figure 2. Assume that the receiver works in a bandwidth of B = NΔf c Frequency band, Δf c Represents the subcarrier spacing, N represents the total number of subcarriers included in the bandwidth. For example, referring to FIG2 , the receiver first receives the bandwidth B = NΔf c The time domain analog signal is then input into an analog to digital converter (ADC) to sample the analog signal to obtain a time domain digital signal.

[0088] The time-domain digital signal obtained after sampling is typically a serial signal. Therefore, the receiver can perform serial-to-parallel conversion (S->P). After the converted signal undergoes a fast Fourier transform (FFT), the frequency-domain digital signal (also understood as the received signal value for each subcarrier) is obtained. The frequency-domain digital signal includes the signals of all subcarriers within the bandwidth. When the perception signal is transmitted in a comb-shaped or interleaved format, the receiver needs to extract the signals on the subcarriers corresponding to the comb-shaped or interleaved format to obtain the perception signal, which is then used for subsequent processing.

[0089] During the sampling process described above, according to the Nyquist sampling theorem, the sampling frequency must be greater than or equal to the signal bandwidth B. Otherwise, the sampled digital signal will be a frequency-domain aliasing of the original signal, affecting reception performance. Furthermore, the number of FFT points must be greater than or equal to the total number of subcarriers N included in the signal bandwidth.

[0090] However, the higher the sampling frequency of the ADC, the higher the cost of the ADC will be, and the worse the sampling accuracy will be. And because the quantization accuracy of the ADC is limited, additional quantization noise will be generated after the signal passes through the ADC. The quantization noise generally depends on the number of quantization bits of the ADC and the peak power of the signal input to the ADC. In the above-mentioned signal reception process, when the perception signal to be received by the receiver and the signals of other users are frequency-division multiplexed on the same OFDM symbol, the peak power of the signal input to the ADC is the sum of the power of the perception signal and the power of the other user signals. If the power of the other user signals is too large, the quantization noise generated after the signal passes through the ADC will also be large, and may even cause the ADC to block (blocker) problem, that is, the power of the quantization noise is much greater than the power of the target perception signal, thereby affecting the reception performance.

[0091] Based on this, the present application provides a signal receiving method, which can extend the received signal (including the target signal and the signal of other users) in the time domain and superimpose the extended time domain signal to obtain a time domain aliasing signal when the target signal is sent in the form of comb teeth or interleaving. The time domain aliasing signal is then sampled to obtain the target signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain, after extension and aliasing in the time domain, it can be considered that the target signal has been extracted, so that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0092] The technical solutions of the embodiments of the present application can be used in various systems, which can be a third generation partnership project (3GPP) system, for example, a fifth generation (5G) or sixth generation (6G) mobile communication system, a sidelink (SL) system, an ultra-wideband (UWB) system, a vehicle to everything (V2X) system, or a device to device (D2D) communication system, a machine to machine (M2M) communication system, an Internet of Things (IoT), and other next generation communication systems. The communication system can also be a non-3GPP communication system, such as a wireless local area network (WLAN) system such as Wi-Fi, without limitation.

[0093] The technical solutions of the embodiments of the present application can be applied to perception or communication in various scenarios, for example, can be applied to perception or communication in one or more scenarios such as smart home, D2D, V2X, and IoT.

[0094] Among them, the above-mentioned systems and scenarios applicable to the present application are only examples. The systems and scenarios applicable to the present application are not limited to these. They are uniformly described here and will not be repeated below.

[0095] Referring to FIG3 , a system according to an embodiment of the present application is shown. The system includes a transmitting device and a receiving device. The system may be a communication system, a perception system, or an integrated communication and perception system.

[0096] In one possible implementation, in a perception system or integrated communication and perception system, the transmitting device and the receiving device may be the same device, i.e., a self-transmitting, self-receiving scenario; or, the transmitting device and the receiving device may be different devices, i.e., a self-transmitting, self-receiving scenario. In a communication system, the transmitting device and the receiving device may be different devices.

[0097] In one possible implementation, the transmitting device and the receiving device may both be terminal devices, or both may be network devices. Alternatively, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device, which is not specifically limited in this application. Alternatively, the transmitting device and / or the receiving device may be a sensing device, such as a radar, or a device with radar functionality.

[0098] Optionally, the receiving device may be a communication device or a sensing device. The communication device may have channel coding and decoding and channel modulation and demodulation capabilities, and further, the communication device may also have sensing capabilities. The sensing device may have sensing capabilities. Furthermore, the sensing device may or may not have channel coding and decoding and channel modulation and demodulation capabilities, without limitation.

[0099] In the embodiment of the present application, the terminal device may be a user-side device with wireless transceiver functions, or may be a chip or chip system provided in the device. The terminal device may also be referred to as user equipment (UE), terminal, access terminal, user unit, user station, mobile station (MS), remote station, remote terminal, mobile terminal (MT), user terminal, wireless communication device, user agent or user device, etc. The terminal device may be, for example, a terminal device in IoT, V2X, D2D, M2M, 5G network, or a future evolved public land mobile network (PLMN). The terminal device may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it may also be deployed on water (such as ships, etc.); it may also be deployed in the air (such as airplanes, balloons and satellites, etc.).

[0100] Exemplarily, the terminal device may be a drone, an IoT device (e.g., a sensor, an electricity meter, a water meter, etc.), a V2X device, a station (ST) in a wireless local area network (WLAN), a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, an in-vehicle device, a wearable device (also referred to as a wearable smart device), a tablet computer or a computer with wireless transceiver function, a virtual reality (VR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical care, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a smart home, or a similar device. The terminal device can be a mobile or fixed device, which is not specifically limited in this application.

[0101] In an embodiment of the present application, the network device may be a network-side device with wireless transceiver functions, or may be a chip or chip system arranged in the device, located in the radio access network (RAN) of the mobile communication system, and used to provide access services for terminal devices. The network device can be an evolutionary Node B (eNB or eNodeB) in an LTE or evolved LTE system (LTE-Advanced, LTE-A), such as a traditional macro base station eNB and a micro base station eNB in ​​a heterogeneous network scenario; or it can be a next generation node B (gNodeB or gNB) in a 5G system; or it can be a transmission reception point (TRP); or it can be a base station in a future evolved PLMN; or it can be a broadband network service gateway (BNG), an aggregation switch or a non-3GPP access device; or it can be a wireless controller in a cloud radio access network (CRAN); or it can be an access point (AP) in a WiFi system; or it can be a wireless relay node or a wireless backhaul node; or it can be a device that implements base station functions in IoT, V2X, D2D, or M2M, and the embodiments of the present application do not specifically limit this. Exemplarily, the base stations in the embodiments of the present application may include various forms of base stations, such as: macro base stations, micro base stations (also called small stations), relay stations, access points, etc., and the embodiments of the present application do not specifically limit this.

[0102] In some implementation scenarios, the network device may also be a module or unit that can implement some or all of the functions of a base station. For example, the network device may be a centralized unit (CU), a distributed unit (DU), a CU and a DU, a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU may be configured separately or included in the same network element, such as a baseband unit (BBU). The RU may be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0103] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, the network device may be a network device or a module of a network device in an open radio access network (open RAN, ORAN) system. In the ORAN system, CU may also be referred to as open (open, O)-CU, DU may also be referred to as O-DU, CU-CP may also be referred to as O-CU-CP, CU-UP may also be referred to as O-CU-UP, and RU may also be referred to as O-RU. Any of the CU (or CU-CP, CU-UP), DU and RU in this application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0104] In some implementation scenarios, the network device may also be referred to as a RAN node, a RAN device, or an access network device, or the network device may also have other naming methods, which is not specifically limited in this application.

[0105] All or part of the functions of the terminal device or network device in this application may also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (such as a cloud platform). The terminal device or network device in this application may also be a logical node, logical module or software that can implement all or part of the functions of the terminal device or network device.

[0106] The signal receiving method provided in the embodiment of the present application will be described below in detail with reference to the accompanying drawings, taking the interaction between the sending device and the receiving device shown in FIG3 as an example.

[0107] FIG4 is a flow chart of a signal receiving method provided in an embodiment of the present application, wherein the signal receiving method includes the following steps:

[0108] S401: A receiving device receives a first signal.

[0109] The bandwidth of the first signal is B. The first signal includes a target signal. The target signal occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1.

[0110] For example, the first signal may be sent by another sending device. In this scenario, the sending device and the receiving device can be considered to be different devices. Alternatively, the first signal may be a signal sent by the receiving device that is reflected by the environment. In this scenario, the sending device and the receiving device can be considered to be the same device. This embodiment of the present application is not limited to this.

[0111] In one possible implementation, the target signal occupies one subcarrier in every M consecutive subcarriers in bandwidth B. Specifically, the target signal may occupy one subcarrier in every M-1 consecutive subcarriers in bandwidth B. That is, it can be considered that the target signal is comb-tooth distributed or staggered in bandwidth B, or in other words, the target signal is mapped in a comb-tooth or staggered manner in bandwidth B. The comb index associated with the target signal (which can also be understood as the staggered index) can be determined by the position of the subcarrier occupied by the target signal, and the position of the subcarrier occupied by the target signal can also be determined by the comb index associated with the target signal. For example, assuming that the subcarriers in bandwidth B can be associated with indexes 0, 1, 2, ..., respectively, when the target signal occupies subcarriers 0, M, 2M, ..., the comb index or staggered index associated with the target signal can be 0, or, when the comb index associated with the target signal is 0, the target signal occupies subcarriers 0, M, 2M, ...; when the target signal occupies subcarriers 1, M+1, 2M+1, ..., the comb index or staggered index associated with the target signal can be 1, and so on. As shown in FIG5 , taking M=4 as an example, the target signal occupies one subcarrier in every four consecutive subcarriers. The target signal occupies subcarriers 2, 6, 10, ..., and the comb index or interleaving index associated with the target signal is 2.

[0112] In a possible implementation, M may also be understood as the number of comb teeth. The subcarriers occupied by the target signal may also be understood as the interlace where the target signal is located.

[0113] In one possible implementation, in addition to the subcarriers occupied by the target signal, other subcarriers in the bandwidth can carry signals of other users or devices. For example, in Figure 5, comb teeth 0 (including subcarriers 0, 4, 8, etc.), comb teeth 1 (including subcarriers 1, 5, 9, etc.), and comb teeth 3 (including subcarriers 3, 7, 11, etc.) in bandwidth B can be used to carry signals of three other users, respectively.

[0114] S402: The receiving device down-converts the first signal to obtain a second signal.

[0115] In one possible implementation, the down-conversion frequency f c The same as the carrier frequency f0 of the first signal.

[0116] In one possible implementation, the down-conversion frequency f c It is related to the carrier frequency f0 of the first signal and / or the position of the target signal. Exemplarily, the down-conversion frequency may be the same as the frequency of a subcarrier included in (or occupied by) the target signal.

[0117] As an example, the down-conversion frequency may be the frequency of the center subcarrier of the target signal. Taking the target signal occupying Y subcarriers as an example, when Y is an odd number, the center subcarrier of the target signal is the subcarrier number of the Y subcarriers. subcarriers, Indicates rounding up; if Y is an even number, the center subcarrier of the target signal is the Y / 2th or Y / 2+1th subcarrier among the Y subcarriers. Based on the example shown in Figure 5, if the target signal occupies only subcarriers 2, 6, and 10, the center subcarrier is subcarrier 6; if the target signal occupies subcarriers 2, 6, 10, and 14, the center subcarrier is subcarrier 6 or 10.

[0118] As another example, the down-conversion frequency may be the frequency of the subcarrier included in the target signal that is closest to the subcarrier containing carrier frequency f0. Specifically, if the frequency of one of the subcarriers included in the target signal is the same as carrier frequency f0, or includes carrier frequency f0, the down-conversion frequency may be carrier frequency f0. Based on the example shown in FIG5 , if carrier frequency f0 is the frequency of subcarrier 5, then the subcarrier closest to the carrier frequency is subcarrier 6, and the down-conversion frequency is the frequency of subcarrier 6.

[0119] As another example, the down-conversion frequency may be the frequency of the subcarrier closest to the subcarrier where the carrier frequency f0 is located among the subcarriers whose frequencies are greater than (or greater than or equal to) the carrier frequency included in the target signal. Specifically, if the frequency of one of the subcarriers included in the target signal is the same as the carrier frequency f0, or includes the carrier frequency f0, the down-conversion frequency may be the carrier frequency f0. Based on the example shown in FIG5 , if the carrier frequency f0 is the frequency of subcarrier 5, then among the subcarriers occupied by the target signal, the subcarriers whose frequencies are greater than the carrier frequency include subcarrier 6 and subcarrier 10, and the subcarrier closest to the carrier frequency is subcarrier 6, so that the down-conversion frequency is the frequency of subcarrier 6.

[0120] As another example, the down-conversion frequency may be the frequency of the subcarrier closest to the subcarrier where the carrier frequency f0 is located among the subcarriers whose frequencies are less than (or less than or equal to) the carrier frequency included in the target signal. In particular, if the frequency of one of the subcarriers included in the target signal is the same as the carrier frequency f0, or includes the carrier frequency f0, the down-conversion frequency may be the carrier frequency f0. Based on the example shown in FIG5 , if the carrier frequency f0 is the frequency of subcarrier 5, then among the subcarriers occupied by the target signal, the subcarriers whose frequencies are less than the carrier frequency include subcarrier 2, and the subcarrier closest to the carrier frequency is subcarrier 2, so that the down-conversion frequency is the frequency of subcarrier 2.

[0121] Optionally, the frequency of the subcarrier in the embodiment of the present application can be understood as the center frequency of the subcarrier, or the starting frequency of the subcarrier, or the ending frequency of the subcarrier, or other frequencies included in the subcarrier.

[0122] In a possible implementation, down-converting the first signal may include: multiplying the first signal by a single-frequency signal, where the frequency of the single-frequency signal is the down-conversion frequency. c For example, the single frequency signal can be expressed as y(t)=exp(-2πjf c t), where t represents time.

[0123] The above single frequency signal is represented in complex form. There is no complex domain signal in the physical world. Therefore, in actual implementation, the first signal can be multiplied by cos(2πf c t) and sin(2πf c t), and then pass through low-pass filters to obtain the I-path signal and the Q-path signal. That is, the second signal may include the I-path signal and the Q-path signal.

[0124] Optionally, the down-conversion frequency is f c When the first signal is down-converted once, the second signal is obtained, and the frequency of the down-conversion is f c Alternatively, the first signal may be down-converted to a frequency of f0 to obtain an intermediate signal, and then the intermediate signal may be down-converted to a frequency of f c The down-conversion of -f0 obtains the second signal.

[0125] After downconversion, the high-frequency RF signal (i.e., the first signal) can be moved to the baseband for processing. Furthermore, the downconversion frequency is determined based on the carrier frequency of the first signal and the location of the target signal. After downconversion, the target signal can be aligned with the baseband zero frequency, facilitating subsequent processing.

[0126] S403: The receiving device determines a third signal according to the second signal.

[0127] The third signal comprises a superposition of K delayed signals of the second signal. The delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2,…, K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M.

[0128] In a possible implementation, the delay time associated with the delayed signal of the second signal can be understood as: after the second signal is delayed by the delay time, the delayed signal can be obtained. Exemplarily, delaying the signal can also be understood as shifting the signal backward in the time domain.

[0129] In one possible implementation, the time length of the first signal is the length of one OFDM symbol. That is, the first signal can be understood as a signal on one OFDM symbol. The length of one OFDM symbol can refer to the length excluding the CP part, for example, T = 1 / Δf c When the receiving device receives signals on multiple OFDM symbols, the signal on each OFDM symbol can be understood as a first signal, that is, the received signal on each OFDM symbol can be applied to the signal receiving method provided in the embodiment of the present application.

[0130] In a possible implementation, k can also start from 0, that is, k = 0, 1, 2, ..., K-1. In this scenario, the delay time associated with the kth delayed signal is The parts involving k in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of this application, k=1, 2, ..., K is used as an example for explanation.

[0131] In a possible implementation, K=M; or, K=M-1+C, where C is a positive integer, and further, C is a positive integer less than or equal to M. For example, C=M, that is, K=2M-1.

[0132] It can be understood that the above-mentioned first signal, second signal, and third signal are described from the perspective of time domain analog signals.

[0133] In one possible implementation, sampling a signal in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain. Therefore, corresponding to the time domain, it can be equivalent to periodically extending the signal in the time domain. The aliased signal can be obtained by superimposing the signal after periodic extension. The sequence of time domain sampling points of the aliased signal in one cycle is the discrete frequency domain serial number or discrete frequency domain sequence corresponding to the target signal after discrete Fourier transformation (DFT). In other words, the signal of the aliased signal in one cycle can be determined by the third signal, and the discrete frequency domain serial number or discrete frequency domain sequence corresponding to the target signal can be further determined. That is, after the receiving device determines the third signal, it can execute the following steps S404 and S405.

[0134] S404: The receiving device samples the third signal.

[0135] As a possible implementation, sampling the third signal can be understood as converting the third signal from a time-domain analog signal to a time-domain digital signal (or referred to as a discrete time-domain signal or a discrete time-domain sequence).

[0136] As a possible implementation, after sampling the third signal in step S404, an N / M point discrete time domain sequence can be obtained. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. The N / M point discrete time domain sequence can be understood as the time domain sampling points of the above-mentioned aliased signal in one cycle. In particular, when N / M is not an integer, N / M can be rounded up or down, that is, after sampling the third signal, or The embodiment of the present application is mainly described with N / M as an integer.

[0137] S405: The receiving device determines a target signal, where the target signal may refer to a discrete time domain signal or discrete time domain sequence corresponding to the target signal, or may refer to a discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal.

[0138] Optionally, when the target signal refers to a discrete time domain signal or discrete time domain sequence corresponding to the target signal, the target signal can be obtained by sampling the third signal in step S404. Step S405 may not be performed, or step S405 may be understood as determining the discrete time domain signal or discrete time domain sequence obtained after sampling the third signal as the target signal.

[0139] Optionally, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the discrete time domain signal or discrete time domain sequence obtained after sampling the third signal in step S404 is called a first time domain sequence. The receiving device can determine the target signal based on the first time domain sequence, which can also be understood as determining the discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal.

[0140] In one possible implementation, the receiving device may perform N / M point DFT on the first time domain sequence to obtain the target signal. That is, a discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal is obtained. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. In particular, when N / M is not an integer, N / M may be rounded up or down, that is, or The embodiments of the present application are mainly described with N / M as an integer.

[0141] As a possible implementation, performing N / M-point DFT on the first time domain sequence may include performing N / M-point FFT on the first time domain sequence. That is, FFT may be understood as a specific implementation of DFT.

[0142] As a possible implementation, performing N / M-point DFT on the first time domain sequence can be understood as performing N / M-point DFT on a sequence consisting of time domain sampling points of the aliased signal in one period.

[0143] Based on the above scheme, when the target signal is sent in the form of comb teeth or interleaving, the received signal (i.e., the first signal) can be extended in the time domain and the extended time domain signal can be superimposed to obtain the aliased time domain signal. The aliased time domain signal is then sampled to obtain the target signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a kind of sampling in the frequency domain, after extension and aliasing in the time domain, it can be considered that the target signal has been extracted, so that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0144] The above describes the overall process of the signal receiving method provided in the embodiment of the present application. The following describes the determination and sampling of the third signal in detail.

[0145] How to determine the third signal:

[0146] In a first possible implementation, determining the third signal according to the second signal may include: delaying the second signal K times to obtain K delayed signals of the second signal, and superimposing the K delayed signals to obtain the third signal.

[0147] Among them, the delay time associated with the kth delayed signal is That is, the second signal can be delayed by δ, K delayed signals of the second signal are obtained.

[0148] As a possible implementation, when δ=0, the signal after the second signal is delayed by δ can be understood as the second signal itself, that is, it can be considered that the first delayed signal of the second signal does not actually delay the second signal, but for the sake of simplicity and consistency in expression, in this case, we still call it the delayed signal of the second signal.

[0149] For example, taking δ=0, K=M=4 as an example, as shown in FIG6 , after receiving the first signal, the receiving device inputs the first signal into the mixer to down-convert the first signal to obtain the second signal x(t). Then, the second signal is delayed by 0, Get x(t), Then, the K signals are input into the adder for superposition to obtain a third signal. For example, the third signal can be expressed as:

[0150] The reference point of t is the starting time of the first signal, that is, the time 0 corresponding to t (or understood as the time t=0) is the starting time of the first signal.

[0151] Optionally, the start time of the first signal may be the start time excluding the CP portion. For example, assuming that the start time of the OFDM symbol (including the CP) in which the first signal is located is t1, the start time of the CP is t1, and the end time of the CP is t2, then the start time of the first signal may be t2, that is, the reference point of the first time range may be t2.

[0152] In a second possible implementation, determining the third signal according to the second signal may include: determining the third signal by an X-level circuit.

[0153] In this X-level circuit:

[0154] The output signal of the i-th stage circuit is a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, where i = 1, 2, ..., X, where X is a positive integer greater than 1. That is, the input signal of the i-th stage circuit can be delayed to obtain a delayed signal of the input signal, and then the input signal and the delayed signal of the input signal can be superimposed to obtain the output signal.

[0155] Where, when i = 1, the input signal of the i-th stage circuit is the second signal delayed by δ. When i > 1, the input signal of the i-th stage circuit is the output signal of the (i-1)-th stage circuit. The third signal is the output signal of the x-th stage circuit. The output signal of the x-th stage circuit includes the superposition of K delayed signals of the second signal.

[0156] As a first possible implementation, when K=2 X In the case of , the output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after the superposition of the signals. For example, taking δ=0, K=M=4 as an example, as shown in FIG7:

[0157] When i=1, the input signal of the first stage circuit is the second signal x(t), and the second signal x(t) is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0158] When i=2, the input signal of the second-stage circuit is the output signal of the first-stage circuit, that is, The input signal of the second stage circuit is delayed The delayed signal obtained is Therefore, the output signal of the second stage circuit is

[0159] By analogy, the output signal of the X-th stage circuit (i.e., the third signal) can be expressed as:

[0160] As a second possible implementation, K can be expressed as the product of X positive integers, that is, Where ∏ represents cumulative multiplication. K i is a positive integer. Furthermore, K i is a positive integer greater than 1. In this scenario, the output signal of the i-th circuit is: the input signal of the i-th circuit and the input signal of the i-th circuit are delayed That is to say, in the i-th stage circuit, the input signal of the i-th stage circuit may be delayed multiple times.

[0161] In the above description, i=1,2,…,X. In addition, i can also start from 0, that is, i=0,1,2,…,X-1. In this scenario, the output signal of the i-th circuit is: the input signal of the i-th circuit and the input signal of the i-th circuit are delayed. The signal after the superposition of the signals of the ith stage circuit and the ith stage circuit input signal are respectively delayed The part involving i in the text or formula in the subsequent embodiments can also be adaptively adjusted accordingly. The following embodiments of this application are described using i=1, 2, ..., X as an example.

[0162] For example, δ=0, K=6, X=2, K i =2,3, that is, K = 2×3, as shown in Figure 8:

[0163] When i=1, K i =2, the input signal of the first stage circuit needs to be delayed once, and the associated delay time is The input signal of the first stage circuit is the second signal x(t), which is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0164] When i=2, K i =3, the input signal of the second stage circuit needs to be delayed twice, and the associated delay time is The input signal of the second stage circuit is the output signal of the first stage circuit, that is, The input signal of the second stage circuit is delayed The delayed signal obtained is The input signal of the second stage circuit is delayed The delayed signal obtained is Therefore, the output signal of the second stage circuit is Right now Right now

[0165] In a third possible implementation, the third signal may be determined by combining the first and second possible implementations. In this scenario, K can be expressed as K′+2 X At this time, the intermediate signal 1 can be obtained by the first possible implementation method. The intermediate signal 1 is the superposition of K′ delayed signals of the second signal, where the delay time associated with the kth (k=1, 2, …, K′) delayed signal is Then delay the second signal After that, the intermediate signal 2 is obtained, and then the intermediate signal 2 is input to the X-level circuit for further delay, where the output signal of the i-th level circuit is: the input signal of the i-th level circuit and the input signal of the i-th level circuit are delayed The output signal of the X-th stage circuit is recorded as intermediate signal 3; finally, the third signal can be obtained by superimposing intermediate signal 1 and intermediate signal 3.

[0166] Alternatively, the intermediate signal 3 can also be obtained as follows: the intermediate signal 4 is obtained by the second possible implementation method, that is, the second signal is first passed through the X-stage circuit, wherein the output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The output signal of the X-th stage circuit is the intermediate signal 4, and then the intermediate signal 4 is delayed The intermediate signal 3 can be obtained. The above method can also be extended to The situation will not be described here.

[0167] For example, δ=0, K=9, K′=1, X=3, that is, K=1+2 3 For example, the second signal x(t) can be delayed by 0 to obtain the intermediate signal 1, that is, the intermediate signal 1 is the second signal itself x(t), and then the second signal is delayed by Get the intermediate signal 2, that is Then, the intermediate signal 2 is delayed by the three-stage circuit to obtain the intermediate signal 3. The delay time corresponding to the three-stage circuit is Right now:

[0168] When i=1, the input signal of the first stage circuit is The input signal is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0169] When i=2, the input signal of the second-stage circuit is the output signal of the first-stage circuit, that is, The input signal of the second stage circuit is delayed Then get the delayed signal Therefore, the output signal of the second stage circuit is

[0170] When i=3, the input signal of the third-stage circuit is the output signal of the second-stage circuit, that is, The input signal of the 3rd stage circuit is delayed Then get the delayed signal Therefore, the output signal of the third stage circuit (i.e., intermediate signal 3) is

[0171] The signal after the intermediate signal 1 and the intermediate signal 3 are superimposed is Right now

[0172] It is understandable that the “third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is” can be achieved in many ways. ". In addition, it is not limited to that each delayed signal of the second signal has a specific corresponding circuit (for example, in the second embodiment described above, each delayed signal component is not directly generated, but the final generated signal is consistent with the required form), that is, the embodiment of the present application does not limit the specific method of determining or obtaining the third signal.

[0173] For sampling of the third signal:

[0174] In a first possible implementation manner, when K=M, sampling the third signal may include: sampling the third signal within a first time range.

[0175] Exemplarily, the first time range may be one of the following: or The third signal in the first time range can be understood as the signal of the above-mentioned aliased signal in one cycle. For example, the third signal is sampled in the first time range, and the first time domain range is In this case, the sampled signal can be expressed as:

[0176] Exemplarily, as shown in FIG6 to FIG8 , among the signals output by the adder, the signal within the rectangular dotted box is the sampled signal, or can be understood as the signal of the target signal in the time domain.

[0177] The reference point of the first time range (or the reference point of t) is the starting time of the first signal, that is, the time 0 corresponding to the first time range (or the time t=0) is the starting time of the first signal, or the time interval between the starting time of the first time range and the starting time of the first signal is

[0178] Optionally, for a portion of the first signal outside the first time range (e.g., including a CP portion in the OFDM symbol in which it is located), whether the receiving device samples the portion may depend on the implementation of the receiving device, and this application does not specifically limit this. For example, a discrete time domain signal or discrete time domain sequence obtained by sampling the third signal within the first time range is referred to as a first time domain sequence:

[0179] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or discrete time domain sequence corresponding to the target signal.

[0180] As another possible implementation, when the target signal refers to a discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal, the receiving device may perform an N / M-point DFT on the first time domain sequence to obtain the discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal, where N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal and is a positive integer.

[0181] Based on this possible implementation, since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, extracting the target signal from the entire bandwidth can be understood as a kind of sampling in the frequency domain, corresponding to (or equivalent to) periodic extension in the time domain. The signal of the third signal within the first time domain range just corresponds to the signal of the signal after the above-mentioned periodic extension in one cycle, so when the third signal is sampled within the first time domain range, it can be considered that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the peak power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0182] In addition, the length of the first time domain range can be That is to say, within the time length T of an OFDM symbol, the ADC used for sampling is only turned on or working for Compared with turning on the ADC all the time within the time length T, the sampling power consumption of the ADC can be reduced, thereby reducing the power consumption of the receiving device.

[0183] Furthermore, based on this possible implementation, if the sampling rate of sampling the third signal within the first time range is NΔf C , then the length of the first time domain range is In this case, the target signal includes sampling points. A frequency domain signal corresponding to the target signal can be obtained by performing a DFT of at least N points. Where N is a positive integer and is greater than or equal to the number of subcarriers included in the bandwidth of the first signal. Compared to a solution that performs at least N-point DFT on the signal across the entire OFDM symbol, this approach can reduce the number of DFT points, lowering the capability requirements and cost of the DFT module (e.g., the FFT module).

[0184] In a second possible implementation, when K=M, A delayed signals of the third signal can be sampled separately, and then the target signal can be determined based on the sampling results of the A delayed signals. Wherein, A is a positive integer, and further, A is a positive integer less than or equal to M. In particular, A=M. Exemplarily, as shown in FIG9 , the following steps can be included:

[0185] a) Delay the third signal A times to obtain A delayed signals of the third signal. The delay time associated with the a-th delayed signal is δ a is greater than or equal to 0, a=1,2,…,A. Similarly, the value of a can also be 0,1,…,A-1, then the delay time associated with the ath delayed signal is The parts involving a in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of this application, a=1, 2,…, A is used as an example for illustration.

[0186] As a possible implementation, when a takes different values, δ a The values ​​of can be the same or different. For example, a=1, δ a Can be equal to 0; when a≠1, δ a Can be greater than or equal to 0.

[0187] b) sampling the ath delayed signal of the third signal within the second time range. That is, sampling each delayed signal of the third signal separately. Different delayed signals of the third signal, that is, when a takes different values, correspond to different second time ranges.

[0188] As a possible implementation, the reference point of the second time range is the start time of the first signal. Please refer to the relevant description of the first time range and will not be repeated here.

[0189] As a possible implementation, the second time range corresponding to the a-th delayed signal may be one of the following: or

[0190] As a possible implementation, as shown in FIG9 , the A delayed signals of the third signal can be respectively input into the ADC for sampling at different times (ie, different second time ranges) through a selector.

[0191] Optionally, the signal of each delayed signal of the third signal within the second time range can also be understood as the signal of the aliased signal in one period after periodically extending and superimposing the second signal (i.e., the signal of the target signal in the time domain, such as the signal framed by the dotted line in FIG9 ). In other words, the target signal is copied A times in the time domain.

[0192] As a possible implementation, the sampling frequency used when sampling the a-th delayed signal of the third signal is greater than or equal to NΔf C / A, or the sampling frequency of the ath delayed signal of the third signal may be greater than or equal to B / A. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. Δf C is the bandwidth of the subcarrier, or the subcarrier spacing. N is the bandwidth of the first signal.

[0193] Optionally, the ath delayed signal of the third signal may be processed within the second time range. Point sampling, that is, sampling the ath delayed signal of the third signal within the second time range to obtain the sampling results including The signal at each sampling point.

[0194] As a possible implementation, among the A delayed signals of the third signal, the sampling positions of any two delayed signals are different. For example, as shown in FIG10 , Taking A=2 as an example, it is originally necessary to sample the third signal at 10 points within the first time range. The sampling position of the first delayed signal of the third signal within the second time range 1 can correspond to the 1st, 3rd, 5th, 7th, and 9th sampling points of the third signal within the first time range, and the sampling position of the second delayed signal of the third signal within the second time range 2 can correspond to the 2nd, 4th, 6th, 8th, and 10th sampling points of the third signal within the first time range.

[0195] In Figure 10, δ1=0, δ2≠0 is used as an example for explanation. Therefore, when the reference points of the first time range and the second time range are the same, both are the start time of the first signal, the start time of the second time range 1 is the same as that of the first time range, and the time interval between the end time of the second time range 2 and the start time of the second time range 1 is δ2.

[0196] c) determining a target signal according to sampling results of the A delayed signals of the third signal.

[0197] Optionally, the sampling results of the A delayed signals of the third signal may be reordered to obtain a first time domain sequence. Exemplarily, the sampling results of the A delayed signals may be arranged in sequence from front to back according to the time domain order of the sampling points of the third signal within the first time range corresponding to the actual sampling points within the second time range to obtain the first time domain sequence.

[0198] For example, based on the example shown in FIG10 , 5 sampling points can be obtained in the second time range 1, and 5 sampling points can be obtained in the second time range 2. Then, the 10 sampling points are reordered, for example, the two groups of 5 sampling points are interspersed with each other. Then, the first time domain sequence can be: the sampling result of the first sampling point in the second time range 1 (corresponding to the first sampling point in the first time range), the sampling result of the first sampling point in the second time range 2 (corresponding to the second sampling point in the first time range), the sampling result of the second sampling point in the second time range 1 (corresponding to the third sampling point in the first time range), the sampling result of the second sampling point in the second time range 2 (corresponding to the fourth sampling point in the first time range), and the sampling result of the second sampling point in the second time range 2 (corresponding to the fourth sampling point in the first time range). the sampling result of the 3rd sampling point in the second time range 1 (corresponding to the 5th sampling point in the first time range), the sampling result of the 3rd sampling point in the second time range 2 (corresponding to the 6th sampling point in the first time range), the sampling result of the 4th sampling point in the second time range 1 (corresponding to the 7th sampling point in the first time range), the sampling result of the 4th sampling point in the second time range 2 (corresponding to the 8th sampling point in the first time range), the sampling result of the 5th sampling point in the second time range 1 (corresponding to the 9th sampling point in the first time range), and the sampling result of the 5th sampling point in the second time range 2 (corresponding to the 10th sampling point in the first time range).

[0199] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or discrete time domain sequence corresponding to the target signal.

[0200] As another possible implementation, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the receiving device can perform N / M point DFT on the first time domain sequence to obtain a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal.

[0201] Based on this possible implementation, the receiving device makes additional copies of the target signal in the time domain, and performs a multiplication of each copied signal with a frequency of NΔf. C / A, compared to sampling at frequency NΔf C Sampling is performed, which reduces the sampling frequency, thereby reducing the performance requirements and cost of the ADC.

[0202] In addition, based on this possible implementation, the time domain also only includes sampling points. A single-point DFT can produce the frequency domain signal corresponding to the target signal. Compared to performing at least N-point DFT on the signal across the entire OFDM symbol, this approach can reduce the number of DFT points, lowering the DFT module requirements and cost.

[0203] In a third possible implementation, when K=M-1+C, the third signal may be sampled in sections, and the target signal may be determined based on the results of the section sampling. Exemplarily, the following steps may be included:

[0204] a) Perform C-segment sampling on the third signal.

[0205] The c-th sampling segment corresponds to the third signal being within the third time range c, where c = 1, 2, ..., C. In other words, the third signal can be temporally divided into C sub-signals, which are then sampled separately. The c-th sub-signal segment corresponds to the third signal being within the third time range c.

[0206] The third time range c can be one of the following: The reference point of the third time range c is the starting time of the first signal. Please refer to the relevant description of the first time range and will not be repeated here.

[0207] Optionally, the value of c can also be 0, 1, ..., C-1, and the c-th sub-signal is the signal of the third signal within the third time range c. The third time range c can be one of the following: or The parts involving c in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of this application, c=1, 2,…, C is used as an example for explanation.

[0208] As a possible implementation, the sampling frequency of the cth segment of the third signal is greater than or equal to NΔf C / C, or the sampling frequency of the cth segment of the third signal may be greater than or equal to B / C. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. Δf C is the bandwidth of the subcarrier, or the subcarrier spacing. B is the bandwidth of the first signal.

[0209] Optionally, the cth segment sub-signal of the third signal may be processed within the third time range c. Point sampling, that is, sampling the cth sub-signal of the third signal within the third time range c to obtain a sampling result including The signal at each sampling point.

[0210] As a possible implementation, in the C segment sub-signals of the third signal, the sampling positions of any two sub-signals are different. For example, if C=2, then the third signal originally needs to be sampled at 10 points within the first time range. The sampling positions of the first sub-signal of the third signal within the third time range can correspond to the first, second, third, fourth, and fifth sampling points of the third signal within the first time range. The sampling positions of the second sub-signal of the third signal within the third time range can correspond to the sixth, seventh, eighth, ninth, and tenth sampling points of the third signal within the first time range. For details, please refer to the description above regarding "Among the A delayed signals of the third signal, the sampling positions of any two delayed signals are different."

[0211] b) Determine the target signal based on the sampling results of segment C.

[0212] Optionally, the sampling results of the C-segment sampling can be reordered to obtain a first time domain sequence. For example, the sampling results of the C-segment sampling can be arranged in order from front to back according to the time domain order of the sampling points of the third signal within the first time range corresponding to the actual sampling points within the third time range to obtain the first time domain sequence. For details, refer to the description of "Reordering the sampling results of the A delayed signals of the third signal to obtain the first time domain sequence" above.

[0213] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or discrete time domain sequence corresponding to the target signal.

[0214] As another possible implementation, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the receiving device can perform N / M point DFT on the first time domain sequence to obtain a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal.

[0215] Based on this possible implementation, the sampling frequency and the number of DFT points can also be reduced, thereby reducing the capability requirements and costs of the ADC and DFT modules.

[0216] In a possible implementation, the functions related to the above steps S401-S402 may be implemented in radio frequency, and the functions related to the above steps S403-S405 may be implemented in baseband (eg, through a baseband chip).

[0217] The embodiments of the present application repeatedly involve a method of dividing an input signal into multiple signals and then delaying the signals of some of the signals, such as delaying the second signal K times (as shown in Figure 6), or delaying the input signal of the i-th path in an X-level circuit (as shown in Figures 7 and 8). In an actual system, the step of dividing the signals into multiple channels will reduce the amplitude or energy of the multiple signals compared to the original signal. However, since the amplitude or energy of each signal evenly divides the amplitude or energy of the source signal, it will not affect the receiving performance of the receiver. In addition, after dividing the signals into multiple channels, the multiple signals can be amplified by some amplifiers so that the average energy or amplitude of the multiple signals remains consistent with the original signal. Therefore, the relevant mathematical expressions involved in this application do not take into account the above-mentioned reduction in amplitude or energy, but this does not affect the inventive nature of the present invention.

[0218] It is understandable that in the embodiments of the present application, the receiving device may perform some or all of the steps or operations in the embodiments of the present application, and these steps or operations are merely examples. The embodiments of the present application may also perform other steps or operations or variations of the various steps or operations. In addition, the various steps or operations may be performed in a different order as presented in the embodiments of the present application, and it is possible that not all of the steps or operations in the embodiments of the present application need to be performed. For example, when the receiving device only has a radio frequency processing function or only has a baseband processing function, it may only perform some of the steps or operations performed by the receiving device described in the embodiments of the present application, such as only performing steps S401-S402 when only having a radio frequency processing function, and only performing steps S403-S405 when only having a baseband processing function. Other operations may be performed by at least one other device.

[0219] It is understood that in each of the above embodiments, the methods and / or steps of the receiving device may also be implemented by components (e.g., a processor, a chip, a chip system, a circuit, a logic module, or software) that can be used in the receiving device. The chip system may be composed of a chip, or the chip system may include a chip and other discrete components.

[0220] It is understandable that, in order to realize the above functions, the communication device or the perception device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0221] The embodiment of the present application can divide the functional modules of the communication device or the perception device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0222] Device Figure 11 shows a schematic structural diagram of a communication device or sensing device 110. The device 110 includes a processing module 1101 and a transceiver module 1102. The device 110 can be used to implement the functions of the above-mentioned receiving device.

[0223] In some embodiments, the apparatus 110 may further include a storage module (not shown in FIG. 11 ) for storing program instructions and data.

[0224] In some embodiments, the transceiver module 1102, which may also be referred to as a transceiver unit, is configured to implement a transmitting and / or receiving function. The transceiver module 1102 may be composed of a transceiver circuit, a transceiver, a transceiver, or a communication interface.

[0225] In some embodiments, the transceiver module 1102 may include a receiving module and a sending module, which are respectively used to execute the receiving and sending steps performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described herein; the processing module 1101 may be used to execute the processing steps (such as determination, etc.) performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described herein.

[0226] Among them, the transceiver module 1102 is used to receive a first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, and M is a positive integer greater than 1; the processing module 1101 is used to down-convert the first signal to obtain a second signal; the processing module 1101 is also used to determine a third signal based on the second signal, the third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the processing module 1101 is further used to sample the third signal to determine the target signal.

[0227] Optionally, the processing module 1101 is further configured to determine a third signal based on the second signal, including: the processing module 1101 is further configured to delay the second signal K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The processing module 1101 is further configured to superimpose K delayed signals to obtain a third signal.

[0228] Optionally, the processing module 1101 is further configured to determine a third signal based on the second signal, including: the processing module 1101 is further configured to determine the third signal using X-stage circuits, wherein the output signal of the i-th stage circuit is a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, i=1, 2, ..., X, where X is a positive integer greater than 1. When i=1, the input signal of the i-th stage circuit is a signal obtained by delaying the second signal by δ; when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit; the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

[0229] Optionally, in the case of K=M, the processing module 1101 is further configured to sample the third signal, including: the processing module 1101 is further configured to sample the third signal within the time range The third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0230] Optionally, when K=M, the processing module 1101 is further configured to sample the third signal, including: the processing module 1101 is further configured to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1, 2, ..., A; Processing module 1101 is also used to The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0231] Optionally, when K=M-1+C, and C is a positive integer, the processing module 1101 is further configured to sample the third signal, including: the processing module 1101 is further configured to perform C-segment sampling on the third signal. The c-th segment sampling corresponds to the third signal being within a time range c, where c=1, 2, ..., C, and the time range c is: The reference point of time range c is the start time of the first signal.

[0232] Optionally, the processing module 1101 is also used to sample the third signal to determine the target signal, including: the processing module 1101 is used to sample the third signal to obtain a first time domain sequence, and is also used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0233] In a possible implementation, the functions / actions implemented by the processing module 1101 may also be implemented by the transceiver module 1102 .

[0234] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0235] In the present application, the communication device or sensing device 110 may be presented in the form of functional modules divided in an integrated manner. The "module" here may refer to a specific application-specific integrated circuit (ASIC), a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0236] In some embodiments, when the communication device or perception device 110 in Figure 11 is a chip or a chip system, the function / implementation process of the transceiver module 1102 can be implemented through the input and output interface (or communication interface) of the chip or chip system, and the function / implementation process of the processing module 1101 can be implemented through the processor (or processing circuit) of the chip or chip system.

[0237] Since the communication device or perception device 110 provided in this embodiment can execute the above method, the technical effects that can be obtained can refer to the above method embodiments and will not be repeated here.

[0238] FIG12 shows a schematic diagram of the structure of another communication device or sensing device 120. The device 120 can be used to implement the functions of the above-mentioned receiving device. The device 120 includes a first circuit 1201.

[0239] Optionally, the apparatus 120 may further include at least one of the following: an antenna 1202 , a mixer 1203 , an analog-to-digital converter 1204 , a DFT module 1205 , and a second circuit (not shown in FIG. 12 ).

[0240] The first circuit is used to determine the third signal based on the second signal, where the second signal is a signal after down-conversion of the first signal. The first signal includes a target signal, which occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1. The third signal is the input signal of the analog-to-digital converter. The third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2,…, K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M.

[0241] Optionally, antenna 1202 is configured to receive a first signal. The first signal includes a target signal, where the target signal occupies one subcarrier in every M consecutive subcarriers.

[0242] Optionally, the mixer 1203 is configured to down-convert the first signal to obtain a second signal.

[0243] Optionally, the analog-to-digital conversion module 1204 is configured to sample the third signal to obtain a first time domain sequence. The DFT module 1205 is configured to determine a target signal based on the first time domain sequence.

[0244] As a possible implementation, the first circuit includes K delays and an adder. The kth delay in the K delays is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the K delayed signals of the second signal to obtain a third signal. Exemplarily, the adder is a K-input adder.

[0245] As a possible implementation, the first circuit includes K-1 delays and an adder. The kth (k=1, 2, ..., K-1) delay of the K-1 delays is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the second signal and K-1 delayed signals of the second signal to obtain a third signal. Exemplarily, the adder is a K-input adder.

[0246] As another possible implementation, the first circuit includes X stages of circuits, wherein the output signal of the i-th stage circuit is a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, where i=1, 2, ..., X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th stage circuit is a signal obtained by delaying the second signal by δ; when i>1, the input signal of the i-th stage circuit is the output signal of the (i-1)-th stage circuit; the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit comprises the superposition of K delayed signals of the second signal.

[0247] As a possible example, K=2 X In the case of , the i-th stage circuit includes a delayer and an adder. The delayer is used to delay the input signal of the i-th stage circuit. The adder is used to superimpose the input signal of the i-th stage circuit and the output signal of the delay device in the i-th stage circuit. Exemplarily, the adder is a 2-input adder.

[0248] As another possible example, In the case of the i-th stage circuit including K i -1 and a delay and an adder. The K i -1 delay circuit, used to delay the input signal of the i-th stage circuit The adder is used to superimpose the input signal of the i-th stage circuit and the K i -1 delay output signal. Exemplarily, the adder is K i Input adder.

[0249] Optionally, in the case of K=M, the analog-to-digital converter 1204 is used to The third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0250] Optionally, when K=M, the second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1, 2, ..., A. The analog-to-digital converter 1204 is used to The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0251] Exemplarily, the second circuit includes A delayers, the A delayers being used to delay the third signal The communication device or the sensing device may further comprise a selector for selecting the time range is connected to the ath delay so that the analog-to-digital converter 1204 is within the time range The ath delayed signal of the third signal is sampled.

[0252] Optionally, when K=M-1+B, and B is a positive integer, the analog-to-digital converter 1204 is configured to perform C-segment sampling on the third signal. The c-segment sampling corresponds to the third signal being within a time range c, where c=1, 2, ..., C, and the time range c is:

[0253] The reference point of time range c is the start time of the first signal.

[0254] Optionally, the DFT module 1205 is specifically used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0255] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding circuit, component or functional module, and will not be repeated here.

[0256] As a possible product form, the receiving device described in the embodiment of the present application can also be implemented using the following: one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gate logic, discrete hardware components, any other suitable circuits, or any combination of circuits capable of performing the various functions described throughout this application.

[0257] As another possible product form, the receiving device described in the embodiment of the present application can be implemented by a general bus architecture. For ease of explanation, refer to Figure 13, which is a structural diagram of a communication device or perception device 130 provided in an embodiment of the present application. The device 130 includes a processor 1301 and a transceiver 1302. The device 130 can be a receiving device, or a chip or chip system therein. Figure 13 only shows the main components of the device 130. In addition to the processor 1301 and the transceiver 1302, the device may further include a memory 1303, and an input and output device (not shown).

[0258] Optionally, the processor 1301 is primarily used to process communication protocols and communication data, as well as control the entire communication device or sensing device, execute software programs, and process software program data. The memory 1303 is primarily used to store software programs and data. The transceiver 1302 may include a radio frequency circuit and an antenna. The radio frequency circuit is primarily used to convert baseband signals into radio frequency signals and process radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as a touch screen, display, and keyboard, are primarily used to receive user input data and output data to the user.

[0259] Optionally, the processor 1301 , the transceiver 1302 , and the memory 1303 may be connected via a communication bus.

[0260] When the communication device or sensing device is turned on, the processor 1301 can read the software program in the memory 1303, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 1301 performs baseband processing on the data to be sent and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves through the antenna. When data is sent to the communication device or sensing device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 1301. The processor 1301 converts the baseband signal into data and processes the data.

[0261] In another implementation, the RF circuit and antenna can be set independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna can be arranged remotely from the communication device or the sensing device.

[0262] In some embodiments, in terms of hardware implementation, those skilled in the art may appreciate that the above-mentioned device 110 may take the form of the device 130 shown in FIG. 13 .

[0263] As an example, the functions / implementation process of the processing module 1101 in FIG11 can be implemented by the processor 1301 in the apparatus 130 shown in FIG13 calling the computer-executable instructions stored in the memory 1303. The functions / implementation process of the transceiver module 1102 in FIG11 can be implemented by the transceiver 1302 in the apparatus 130 shown in FIG13.

[0264] As another possible product form, the receiving device in this application may adopt the structure shown in Figure 14, or include the components shown in Figure 14. Figure 14 is a schematic diagram of the composition of a communication device or sensing device 1400 provided in this application. The device 1400 can be a receiving device or a chip or system on a chip in a receiving device.

[0265] As shown in FIG14 , the apparatus 1400 includes at least one processor 1401 and at least one communication interface ( FIG14 is merely an example of one communication interface 1404 and one processor 1401). Optionally, the apparatus 1400 may further include a communication bus 1402 and a memory 1403.

[0266] Processor 1401 can be a general-purpose central processing unit (CPU), a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. Processor 1401 can also be other devices with processing capabilities, such as circuits, devices, or software modules, without limitation.

[0267] Communication bus 1402 is used to connect the different components in the communication device or sensing device 1400, enabling communication between the different components. Communication bus 1402 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. This bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG14 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0268] Communication interface 1404 is used to communicate with other devices or communication networks. Exemplarily, communication interface 1404 can be a module, circuit, transceiver, or any other device capable of communication. Optionally, communication interface 1404 can also be an input / output interface within processor 1401, used to implement signal input and output to the processor.

[0269] The memory 1403 may be a device with a storage function, used to store instructions and / or data, wherein the instructions may be computer programs.

[0270] Exemplarily, the memory 1403 may be a read-only memory (ROM) or other types of static storage devices that can store static information and / or instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and / or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, etc., without limitation.

[0271] It should be noted that the memory 1403 can exist independently of the processor 1401 or can be integrated with the processor 1401. The memory 1403 can be located within the communication device or sensing device 1400 or outside the communication device or sensing device 1400, without limitation. The processor 1401 can be used to execute instructions stored in the memory 1403 to implement the methods provided in the following embodiments of the present application.

[0272] As an optional implementation, the communication device or perception device 1400 may further include an output device 1405 and an input device 1406. The output device 1405 communicates with the processor 1401 and can display information in a variety of ways. For example, the output device 1405 can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 1406 communicates with the processor 1401 and can receive user input in a variety of ways. For example, the input device 1406 can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0273] In some embodiments, in terms of hardware implementation, those skilled in the art may conceive that the apparatus 110 shown in FIG. 11 may take the form of the apparatus 1400 shown in FIG. 14 .

[0274] As an example, the functions / implementation process of the processing module 1101 in FIG11 can be implemented by the processor 1401 in the apparatus 1400 shown in FIG14 calling the computer-executable instructions stored in the memory 1403. The functions / implementation process of the transceiver module 1102 in FIG11 can be implemented by the communication interface 1404 in the apparatus 1400 shown in FIG14.

[0275] It should be noted that the structure shown in FIG14 does not constitute a specific limitation on the receiving device. For example, in other embodiments of the present application, the receiving device may include more or fewer components than shown, or may combine or separate certain components, or may have different component arrangements. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0276] In some embodiments, the embodiments of the present application further provide a communication device or a perception device, which includes a processor for implementing the method in any of the above method embodiments.

[0277] As a possible implementation, the communication device or perception device further includes a memory. The memory is used to store necessary computer programs and data. The computer program may include instructions, and the processor may invoke the instructions in the computer program stored in the memory to instruct the communication device or perception device to perform any of the above-described method embodiments. Of course, the memory may not be located in the communication device or perception device.

[0278] As another possible implementation, the communication device or perception device also includes an interface circuit, which is a code / data read / write interface circuit, and the interface circuit is used to receive computer execution instructions (computer execution instructions are stored in a memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor.

[0279] As another possible implementation, the communication device or the perception device further includes a communication interface, which is used to communicate with modules outside the communication device or the perception device.

[0280] It can be understood that the communication device or perception device can be a chip or a chip system. When the communication device or perception device is a chip system, it can be composed of chips or include chips and other discrete devices. The embodiments of the present application do not specifically limit this.

[0281] The present application also provides a computer-readable storage medium having a computer program or instruction stored thereon, which implements the functions of any of the above method embodiments when executed by a computer.

[0282] The present application also provides a computer program product, which implements the functions of any of the above method embodiments when executed by a computer.

[0283] Those skilled in the art will appreciate that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and units may refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0284] It is understood that the systems, devices, and methods described in this application may also be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of devices or units, and may be electrical, mechanical, or other forms.

[0285] The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Components shown as units may or may not be physical units. Some or all of these units may be selected to achieve the objectives of this embodiment as needed.

[0286] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0287] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state drive (SSD)). In the embodiment of the present application, the computer may include the aforementioned device.

[0288] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0289] Although the present application has been described with reference to specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely illustrative of the present application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, the present application is intended to include such modifications and variations as fall within the scope of the claims of the present application and their equivalents.

Claims

1. A signal receiving method, characterized in that: The method comprises: Receive a first signal, where the first signal includes a target signal, where the target signal occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1; Down-converting the first signal to obtain a second signal; A third signal is determined according to the second signal, wherein the third signal comprises a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; The third signal is sampled to determine the target signal.

2. The method according to claim 1, characterized in that The frequency of the down-conversion is related to the carrier frequency of the first signal and / or the position of the target signal.

3. The method according to claim 1 or 2, characterized in that: Determining a third signal according to the second signal includes: The second signal is delayed K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The K delayed signals are superimposed to obtain the third signal.

4. The method according to claim 1 or 2, characterized in that: Determining a third signal according to the second signal includes: determining the third signal by an X-level circuit, wherein: The output signal of the i-th stage circuit is: a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, i=1, 2, ..., X, where X is a positive integer greater than 1; Among them, when i=1, the input signal of the i-th stage circuit is the signal after the second signal is delayed by δ, when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit, the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

5. The method according to claim 4, characterized in that K＝2 X ； The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after superposition of the signals.

6. The method according to claim 4, characterized in that The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed respectively. The signal after the signal is superimposed, П represents the cumulative multiplication, K i Is a positive integer.

7. The method according to any one of claims 1 to 6, characterized in that: K=M, sampling the third signal, including: In time range The third signal is sampled within a time range, and the reference point of the time range is the starting time of the first signal.

8. The method according to any one of claims 1 to 6, characterized in that: K=M, sampling the third signal, including: The third signal is delayed A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δa is greater than or equal to 0, a=1,2,...,A; In time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the starting time of the first signal.

9. The method according to claim 8, characterized in that The sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

10. The method according to claim 8 or 9, characterized in that: Among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

11. The method according to any one of claims 1 to 6, characterized in that: K=M-1+C, where C is a positive integer.

12. The method according to claim 11, characterized in that Sampling the third signal includes: Performing C-segment sampling on the third signal; The c-th sampling corresponds to a signal in which the third signal is within a time range c, c=1, 2, ..., C, and the time range c is: The reference point of the time range c is the start time of the first signal.

13. The method according to claim 12, characterized in that The sampling frequency used when performing C-segment sampling on the third signal is greater than or equal to NΔf C / C, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

14. The method according to claim 12 or 13, characterized in that In the C-segment sampling of the third signal, the sampling positions in any two segments are different.

15. The method according to any one of claims 1 to 14, characterized in that: Sampling the third signal to determine the target signal includes: The third signal is sampled to obtain a first time domain sequence, and an N / M-point discrete Fourier transform DFT is performed on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

16. A device, characterized in that: The device comprises: a first circuit; The first circuit is used to determine a third signal according to the second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Among them, the second signal is a signal after down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k=1,2,…,K, δ is greater than or equal to 0, K is a positive integer greater than or equal to M; the third signal is the input signal of the analog-to-digital converter.

17. The device according to claim 16, characterized in that The first circuit includes K delays and an adder; The kth delay device among the K delay devices is used to delay the second signal Obtaining a kth delayed signal of the second signal; The adder is used to superimpose K delayed signals of the second signal to obtain the third signal.

18. The device according to claim 16, characterized in that The first circuit includes an X-level circuit, wherein: The output signal of the i-th stage circuit is: a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, i=1, 2, ..., X, where X is a positive integer greater than 1; Among them, when i=1, the input signal of the i-th stage circuit is the signal after the second signal is delayed by δ, when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit, the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

19. The device according to claim 18, characterized in that K=2 X ; The i-th stage circuit includes a delay device and an adder; The delay device is used to delay the input signal of the i-th stage circuit The adder is used to superimpose the input signal of the i-th stage circuit and the output signal of the delay device in the i-th stage circuit.

20. The device according to claim 18, characterized in that The i-th stage circuit includes K i -1 delay and one adder; The K i - 1 delay device, used to delay the input signal of the i-th circuit The adder is used to superimpose the input signal of the i-th circuit and the K in the i-th circuit. i -1 delay output signal.

21. The device according to any one of claims 16 to 20, characterized in that: K=M; the device also includes an analog-to-digital converter; The analog-to-digital converter is used in the time range The third signal is sampled within a time range, and the reference point of the time range is the starting time of the first signal.

22. The device according to any one of claims 16 to 20, characterized in that K=M; the device also includes an analog-to-digital converter and a second circuit; The second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A; The analog-to-digital converter is used in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the starting time of the first signal.

23. The device according to claim 22, characterized in that The sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

24. The device according to claim 22 or 23, characterized in that Among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

25. The device according to any one of claims 16 to 20, characterized in that K=M-1+C, where C is a positive integer.

26. The device according to claim 25, characterized in that The device also includes an analog-to-digital converter; The analog-to-digital converter is used to perform X-segment sampling on the third signal; wherein the c-th segment sampling corresponds to the signal of the third signal being within a time range c, c=1, 2, ..., C, and the time range c is: The reference point of the time range c is the start time of the first signal.

27. The device according to any one of claims 16 to 26, characterized in that The device also includes: a discrete Fourier transform module; The discrete Fourier transform module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, and the first time domain sequence is a sampling result corresponding to the third signal.

28. A chip, characterized in that: The chip comprises: a first circuit; The first circuit is used to determine a third signal according to the second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Among them, the second signal is a signal after down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k=1,2,…,K, δ is greater than or equal to 0, K is a positive integer greater than or equal to M; the third signal is the input signal of the analog-to-digital converter.

29. The chip according to claim 28, characterized in that The chip also includes the analog-to-digital converter; The analog-to-digital converter is used to sample the third signal.

30. The chip according to claim 28 or 29, characterized in that: The chip also includes a discrete Fourier transform module; The discrete Fourier transform module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein the first time domain sequence is a sampling result corresponding to the third signal, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

31. A device, characterized in that: The device comprises a processor; the processor is used to run a computer program or instruction so that the device executes the method according to any one of claims 1-15.

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