Analog-digital scheme for joint clock recovery and frame alignment

Abstract

A receiver (20) includes (i) circuitry including a Clock and Data Recovery (CDR) loop and (ii) a frame aligner (84). The circuitry is configured to apply CDR to a signal using the CDR loop, and to buffer the signal that underwent CDR in a memory buffer (60). The frame aligner is configured to align the signal buffered in the memory buffer to frame boundaries between successive frames of the signal, by applying to the CDR loop one or more shifts, each equivalent to a symbol duration of the signal.

Description

[0001] ANALOG-DIGITAL SCHEME FOR JOINT CLOCK RECOVERY AND FRAME ALIGNMENT

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application 63 / 581,007, filed September 7, 2023, whose disclosure is incorporated herein by reference.

[0004] FIELD OF THE INVENTION

[0005] The present invention relates generally to communication receivers, and particularly to methods and systems for joint clock recovery and frame alignment.

[0006] BACKGROUND OF THE INVENTION

[0007] Communication receivers often perform tasks such as Clock and Data Recovery (CDR) and frame alignment. CDR typically involves recovering a clock signal from a received signal in order to set the appropriate timing for sampling the signal. Frame alignment typically involves identifying the timing of signal frames, and aligning the storage of the received signal in memory to frame boundaries for further processing.

[0008] SUMMARY OF THE INVENTION

[0009] An embodiment of the present invention that is described herein provides a receiver including (i) circuitry including a Clock and Data Recovery (CDR) loop and (ii) a frame aligner. The circuitry is configured to apply CDR to a signal using the CDR loop, and to buffer the signal that underwent CDR in a memory buffer. The frame aligner is configured to align the signal buffered in the memory buffer to frame boundaries between successive frames of the signal, by applying to the CDR loop one or more shifts, each equivalent to a symbol duration of the signal.

[0010] In some embodiments, the circuitry includes a processing chain configured to sample the signal in accordance with a sampling clock, re-sample the sampled signal in accordance with a re-sampling phase, and buffer the re-sampled signal in the memory buffer; the CDR loop includes (i) a first CDR loop configured to adjust the sampling clock and (ii) a second CDR loop configured to adjust the re-sampling phase; and the frame aligner is configured to align the signal buffered in the memory buffer to the frame boundaries by applying the one or more shifts to both the first CDR loop and the second CDR loop.

[0011] In a disclosed embodiment, the first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth that is larger than the first loop bandwidth. In an example embodiment, the circuitry includes a Numerically-Controlled Oscillator (NCO) configured to adjust sampling phases of the first and second CDR loops, and the frame aligner is configured to apply the shifts by controlling the NCO.

[0012] Typically, the circuitry is configured to detect a frame synchronization sequence in the signal when the signal buffered in the memory buffer to the frame boundaries, and the frame aligner is configured to continue applying the shifts until the frame synchronization sequence is detected. In an embodiment, the frame aligner is configured to apply each of the shifts during a different frame of the signal. In an embodiment, the frame aligner is configured to insert a waiting period after every N shifts, N being a defined integer.

[0013] There is additionally provided, in accordance with an embodiment of the present invention, a method including applying Clock and Data Recovery' (CDR) to a signal using a CDR loop. The signal that underwent CDR is buffered in a memory buffer. The signal buffered in the memory buffer is aligned to frame boundaries between successive frames of the signal, by applying to the CDR loop one or more shifts, each equivalent to a symbol duration of the signal. Further processing is applied to the aligned signal in the memory buffer.

[0014] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Fig. 1 is a block diagram that schematically illustrates a receiver that uses joint CDR and frame alignment, in accordance with an embodiment of the present invention;

[0017] Fig. 2 is a block diagram that schematically illustrates a buffer in the receiver of Fig. 1, before and after frame alignment, in accordance with an embodiment of the present invention;

[0018] Fig. 3 is a state diagram that schematically illustrates a frame alignment process, in accordance with an embodiment of the present invention; and

[0019] Figs. 4 and 5 are graphs of simulation results showing the behavior of CDR loops in the receiver of Fig. 1 during joint CDR and frame alignment, in accordance with an embodiment of the present invention.

[0020] DETAILED DESCRIPTION OF EMBODIMENTS

[0021] OVERVIEW

[0022] Embodiments of the present invention that are described herein provide methods and apparatus for joint Clock and Data Recovery (CDR) and frame alignment in communication receivers. In disclosed embodiments, a receiver receives a signal comprising a sequence of signal frames. The receiver processes the signal, including, among other tasks, recovering the signal clock using a CDR loop. The receiver buffers the signal that underwent CDR in a memory buffer for further processing (e.g.. carrier phase recovery and / or bit decoding).

[0023] Each frame of the signal comprises a frame synchronization sequence, e g., a Start-Of- Frame (SOF) sequence, which is used by the receiver to detect the frame boundaries. To simplify subsequent processing of the signal, the signal is required to be aligned in the buffer to the frame boundaries. In other words, the signal needs to be stored in the buffer such that the frame synchronization sequence is positioned at a fixed predefined position ("target position”) in the buffer.

[0024] To meet this requirement, the receiver further comprises a frame aligner that aligns the signal in the buffer by controlling the CDR loop. Typically, although not necessarily, the frame aligner is implemented in software. The frame aligner carries out an iterative process that shifts the timing of the signal by one symbol duration (one Unit Interval - UI) from one frame to another. As a result of the timing shifts, the position of the frame synchronization sequence in the buffer moves by one symbol-position from frame to frame. The process continues until the frame synchronization sequence reaches the target position in the buffer.

[0025] In a given iteration of the process, the frame aligner shifts the timing of the signal by 1-UI by controlling the CDR loop to apply an additional phase shift equivalent to one symbol duration. In an example implementation that is described herein in detail, the CDR loop is a dual loop that comprises (i) a slower CDR loop that adapts a sampling clock used for sampling the signal, and (ii) a faster CDR loop that adapts a resampling phase used for resampling of the signal. A Numerically-Controlled Oscillator (NCO) generates a digital phase correction word specifying the resampling phase, which in turn, after additional processing, generates the sampling clock. The NCO is thus considered as belonging to both CDR loops. The frame aligner controls the NCO to apply an additional phase bias that is equivalent to a 1-UI timing shift per iteration.

[0026] When using the disclosed technique, the same CDR loop is used both for clock recovery (at sub-UI resolution and with 1-UI ambiguity) and for frame alignment (at integer multiples of 1-UI). As will be explained and demonstrated herein, the two operations are performed simultaneously, with little or no cross-effects on one another. This solution minimizes the additional hardware needed for frame alignment. As a result, power consumption is reduced considerably, especially in highly-parallelized receiver configurations. The disclosed technique can also be viewed as circuitry that converges to sample the received signal at the appropriate phase, with two different resolutions: (i) sub-UI resolution with 1 UI ambiguity, based on timing error estimation, and (ii) at integer multiples of 1-UI, based on frame synchronization detection.

[0027] The disclosed techniques are demonstrated below using a receiver configuration that performs frequency-domain processing. Receiver operations such as Frame Detection (FD) and buffering are performed in multiple parallel branches. Example simulation results of the disclosed techniques in such a receiver are also provided.

[0028] SYSTEM DESCRIPTION

[0029] Fig. 1 is a block diagram that schematically illustrates a receiver 20 that uses joint CDR and frame alignment, in accordance with an embodiment of the present invention. Receiver 20 may be used for signal reception in any suitable communication system. In an example embodiment, receiver 20 implements the 800ZR Coherent optical communication protocol.

[0030] Receiver 20 receives and processes an analog input signal, e.g., at baseband or some low intermediate Frequency (IF). The input signal comprises a sequence of symbols modulated in accordance with a certain modulation scheme. The symbol rate is denoted Rs. The symbol duration (1 / Rs) is also referred to as Unit Interval (UI). In an example implementation relating to the 800ZR Coherent protocol, Rs=120 GBaud, although any other suitable rate can be used.

[0031] The symbols of the received signal are formatted in a sequence of frames. Each frame comprises a frame synchronization sequence - A sequence of several predefined symbols whose position is indicative of the boundaries of the frame. The frame synchronization sequence may comprise, for example, a Start-Of-Frame (SOF) sequence, an End-Of-Frame (EOF) sequence, or any other suitable frame synchronization sequence located at any suitable location in the frame.

[0032] The description that follows refers mainly to an example 800ZR Coherent implementation in which each frame comprises 7296 symbols and the frame synchronization sequence is an 11 -symbol SOF sequence. Alternatively, any other suitable frame and frame synchronization sequence sizes can be used.

[0033] In the example of Fig. 1, receiver 20 comprises a processing chain 24 comprising the following modules: ■ An Analog-to-Digital Converter (ADC) 28 that samples (digitizes) the analog input signal. ADC 28 samples the input signal in accordance with a sampling clock 32. The sampling rate of ADC 28 (i.e., the rate of sampling clock 32) is higher than the symbol rate Rs by a factor of m / k (wherein m and k are integers, and m>k). In other words. ADC 28 samples the signal with an over-sampling rate of (m / k)>l.

[0034] ■ A first Digital Signal Processing (DSP1) block 36 that processes the digital signal produced by ADC 28. The processing tasks of the DSP1 block may include, for example, compensation for In-phase / Quadrature (I / Q) imbalance and filtering.

[0035] ■ A digital resampler 40 that resamples the output of DSP1 block 36. Resampler 40 resamples the signal in accordance with a phase correction word 44 that specifies the resampling phase. In the present example the resampling rate is equal to the original sampling rate, i.e., (m / k)Rs. The timing of the resampled signal (the output of resampler 40), however, may vary relative to the timing of the originally sampled signal (the output of ADC 28).

[0036] ■ A second DSP (DSP2) block 48 that processes the resampled signal produced by resampler 40.

[0037] ■ An equalizer (EQ) 52 that filters the output of DSP2 block 48 and down-samples it from the oversampled rate of (m / k)Rs to a rate of Rs (i.e., to one sample-per-symbol).

[0038] ■ A Frame Detector (FD) 56 that detects frame synchronization sequences (in the present example SOF) in the signal. In a typical embodiment, FD 56 comprises a correlator that correlates the received symbols with the known sequence of the SOF. The output of processing chain 24 is buffered in a memory buffer 60 for further processing.

[0039] In addition to processing chain 24, receiver 20 comprises two CDR loops. One CDR loop (referred to herein as “fast CDR loop”) comprises a Timing Error Detector (TED) 64, a loop filter 68, and a Numerically Controlled Oscillator (NCO) 72. The other CDR loop (referred to as “slow' CDR loop”) comprises (in addition to TED 64, LF 68 and NCO 72) an additional loop filter 76 and a Voltage Controlled Oscillator (VCO) 80. TED 64, LF 68 and NCO 72 are thus considered as belonging to both CDR loops.

[0040] In the fast CDR loop, TED 64 outputs a phase error signal within the interval [0,1 / Rs), i.e., with an ambiguity of one Unit Interval (UI). Loop filter 68 filters the phase error signal. NCO 72 generates, based on the filtered phase error signal, a digital phase correction word 44 that controls the resampling phase. In the slow CDR loop, loop filter 76 filters the output of NCO 72. VCO 80 generates, based on the output of loop filter 76, a control signal that adjusts the phase of sampling clock 32.

[0041] In an example implementation, the loop bandwidth of the fast CDR loop is on the order of 100 kHz. whereas the loop bandwidth of the slow CDR loop is on the order of 5 MHz. Generally, however, any other suitable bandwidths can be used.

[0042] The slow CDR loop adapts the phase of sampling clock 32, with which ADC 28 samples the signal. In parallel, the fast CDR loop adapts phase correction word 44, with which resampler 40 resamples the signal. In other words, resampler 40 can be viewed as interpolating between the samples of ADC 28, and the fast CDR loop can be viewed as setting the interpolation phase. Both loops aim to minimize the timing error detected by TED 64.

[0043] This dual-loop configuration achieves high loop bandwidth and high tracking performance using the fast CDR loop. At the same time, the slow CDR loop removes the average timing error and centers the phase corrections produced by NCO 72 around zero.

[0044] To simplify processing of the signal buffered in buffer 60, the buffered signal needs to be aligned in the buffer to the frame boundaries. In other words, the signal needs to be stored in buffer 60 such that the SOF is positioned at a fixed predefined position in the buffer. In some embodiments, receiver 20 further comprises a frame aligner 84 that performs this alignment. As will be explained in detail below; frame aligner 84 aligns the buffered signal to frame boundaries by controlling phase correction word 44 produced by NCO 72, which in turn impacts the fast and slow CDR loops of the receiver.

[0045] Frame aligner 84 performs frame alignment in response to a “SOF detection" signal produced by FD 56. FD 56 is configured to assert the “SOF detection” signal if the SOF of the currently buffered frame is positioned at the desired predefined position in buffer 60 (i.e., if the buffered signal is aligned to the frame boundaries). If the buffered frame is not positioned at the desired predefined position in the buffer (i.e., if the buffered signal is not aligned to the frame boundaries) the “SOF detection” signal is de-asserted.

[0046] In an example implementation, DSP1 block 36 performs Fast-Fourier Transformation (FFT), and DSP2 block 48 performs Inverse FFT (IFFT). TED 64 may comprise, for example, a Godard frequency -domain phase detector. Resampler 40 may comprise, for example, a Frequency -Domain Equalizer (FDE) that modifies the linear slope of the samples according to the phase correction word generated by NCO 72. This implementation is suitable, for example, for receivers that process signals in the frequency domain, such as in optical links with high Chromatic Dispersion (CD) distortion. In such receivers the FDE can compensate for CD and timing jointly, by changing the phase of the frequency -domain samples. Alternatively, DSP blocks 36 and 48 and TED 64 can be implemented in any other suitable way.

[0047] EXAMPLE BUFFER CONFIGURATION

[0048] After the timing error has been corrected by the CDR loops, and down-sampling equalization has been performed by equalizer 52, the signal buffered in buffer 60 comprises detectable symbols. In particular, the known symbols of the SOF sequence are detectable. At this stage, the correlator in FD 56 is able to identify correctly whether the buffered signal is aligned to the frame boundary' (i.e., whether the SOF is located at the correct position in buffer 60).

[0049] Fig. 2 is a block diagram that schematically illustrates buffer 60 of receiver 20. in accordance with an embodiment of the present invention. The top of the figure shows the state of buffer 60 before frame alignment, and the bottom of the figure shows the buffer state after frame alignment.

[0050] In the present example, some or all processing of the signal in receiver 20 is performed in parallel. In particular, equalizer 52 outputs the equalized signal over P parallel branches. The size of buffer 60 is P symbols. The buffer comprises P symbol-positions numbered 0... (P- 1). The P branches write P respective symbols to the P respective symbol-positions in buffer 60, in parallel. In an example embodiment, P=128, although any other suitable value can be used.

[0051] The frame size should therefore be greater than or equal to P. Typically, the frame size is set to be an integer multiple of P (K-P wherein K is integer). With this implementation, a SOF appears every K cycles of P symbols in the signal. This property is used below.

[0052] For a buffer of size P, there are P possible positions for the SOF sequence (i.e., FD 56 has an ambiguity of P symbols). One of these positions is predefined as a “target position” in which the signal is considered aligned. In some embodiments, FD 56 asserts the “SOF detection” signal in response to detecting a SOF at the target position in the buffer. Without loss of generality, the description herein assumes that the target position is the beginning of the buffer (i.e., the first symbol of the SOF is stored in the first symbol-position in buffer 60).

[0053] The beginning and end of the disclosed frame alignment process are demonstrated in Fig. 2. As seen, before frame alignment (top of the figure) the SOF is positioned at some arbitrary position in buffer 60. After frame alignment (bottom of the figure) the SOF begins at the first symbol-position of the buffer. In the examples given herein, the frame synchronization sequence (e.g., SOF) is contiguous, i.e., made-up of a sequence of successive symbols. This choice, however, is in no way mandatory. In alternative embodiments, the known symbols of the frame synchronization sequence may be spread across the frame in any suitable way (e.g., with uniform spacing between symbols). In these embodiments, the known symbols of the frame synchronization sequence are interleaved with the other symbols of the frame. In this context, “aligning the frame synchronization sequence in the buffer to frame boundaries’" may comprise aligning any of the symbols of the frame synchronization sequence (e.g., the first symbol) to any target position in the buffer (e.g., the first position).

[0054] The configurations of receiver 20 and its various components, as shown in Figs. 1 and 2, are example configurations that are chosen purely for the sake of conceptual clarity. In alternative embodiments, any other suitable configuration can be used. Elements that are not necessary for understanding the principles of the present invention have been omitted from the figures for clarity.

[0055] The various elements of receiver 20 may be implemented in hardware, e.g., in one or more Application-Specific Integrated Circuits (ASICs) or FPGAs, in software, or using a combination of hardware and software elements. Buffer 60 may be implemented in any suitable memory, e.g., Random-Access Memory (RAM).

[0056] In some embodiments, certain functions of receiver 20, for example some or all the functions of frame aligner 84, may be implemented in a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and / or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.

[0057] JOINT CDR AND FRAME ALIGNMENT

[0058] In some embodiments, frame aligner 84 carries out an iterative process that controls phase correction word 44 produced by NCO 72, in a manner that causes the signal buffered in buffer 60 to align with frame boundaries. Typically, each iteration is performed on a newly received frame. In each iteration, frame aligner 84 instructs NCO 72 to add a bias of m / k to phase correction word 44 it produces. This bias comes in addition to the error signal produced by loop filter 68. The additional bias of m / k is equivalent to a timing shift of one symbol duration (LUI) in the resampling phase specified by phase correction word 44. Thus, in each iteration, frame aligner 84 causes the resampling phase specified by control word 44 to shift by another 1-UI. As a result, the position of the SOF sequence in buffer 60 shifts by one symbol-position from one frame to the next. Frame aligner 84 continues this process until FD 56 detects that the SOF sequence has reached the target position in the buffer.

[0059] It is important to note that the frame alignment process is smooth and hitless. Since TED 64 has an ambiguity of 1-UI, timing jumps of integer multiples of 1-UI have no effect on the estimated timing error. Equalizer 52, too, suffers little or no degradation due to the timing jumps.

[0060] In some embodiments, frame aligner 84 inserts a waiting period after every N iterations (after N UI timing shifts), in order to allow the slow CDR loop to converge. This feature reduces the required dynamic range of NCO 72, at the expense of slightly slowing down the frame alignment process. In one example embodiment N=5, but any other suitable value can be used. The setting of N enables trading-off between frame alignment time and NCO dynamic range.

[0061] Fig. 3 is a state diagram that schematically illustrates the disclosed frame alignment process, in accordance with an embodiment of the present invention. The process of Fig. 3 is carried out by frame aligner 84. As seen in the figure, the frame alignment begins after both CDR loops have converged (a state denoted “CDR CONVERGENCE”) and after equalizer 52 has converged (a state denoted “EQ CONVERGENCE”).

[0062] The frame alignment begins with frame aligner 84 instructing NCO 72 to add a bias of m / k to the digital phase correction word it produces (a state denoted “UI SHIFT”). This bias causes the timing of the resampling (and therefore the timing of the signal buffered in buffer 60) to shift by 1 -UI.

[0063] After applying the shift, frame aligner 84 checks whether SOF is detected by FD 56. If SOF is detected, meaning the signal is frame-aligned, the process terminates (a state denoted “FINISH”). If SOF is not detected, the process proceeds.

[0064] Frame aligner 84 then checks whether a sequence of N iterations (applying a total timing shift of N-UI) has been completed. If so, frame aligner 84 waits for a certain wait period to allows NCO 72 to converge (a state denoted “NCO WAIT”). Alternatively to waiting a predefined wait period, frame aligner 84 may monitor the value of phase correction word 44 and wait until the value drops below a defined low threshold.

[0065] If a sequence of N iterations is not yet completed, or after waiting the “NCO WAIT” period, frame aligner 84 waits for the next frame to be received and buffered (a state denoted “WAIT FRAME”). As explained above, in some embodiments the frame size is set to K-P symbols. In such a case waiting a frame (K-P symbols) ensures that a SOF is not missed. The process then returns to the “UI SHIFT” state, in which frame aligner 84 applies another 1-UI shift for the next iteration. Iterations continue until SOF is detected successfully.

[0066] Figs. 4 and 5 are graphs of simulation results showing the behavior of the slow and fast CDR loops during joint CDR and frame alignment, in accordance with an embodiment of the present invention. The simulation used for producing these examples implemented the frequency -domain receiver implementation described above.

[0067] In both graphs, the horizontal axis denotes sample number (proportional to time), and the vertical axis denotes relative timing (in UI units). A curve 90 shows the phase of sampling clock 32 (the phase of VCO 80 and ADC 28). i.e., the phase of the slow CDR loop. A curve 94 shows the phase specified by control word 44 (the phase of resampler 40), i.e., the phase of the fast CDR loop. A curve 98 show's the total phase applied to the received signal.

[0068] Fig. 4 shows an example of a sequence of N=5 iterations (five 1-UI timing jumps) applied to the received signal. A short time gap is inserted between adjacent iterations. An inset at the bottom-right of the figure focuses on the time vicinity of the five timing jumps.

[0069] As seen, each 1-UI timing jump applied by NCO 72 is reflected immediately to the output of resampler 40 (see curve 94). The slow CDR loop of ADC 28 responds to the jump and begins to converge slowly to reduce the bias (see curve 90). The convergence speed and overshoot can be controlled by proper setting of the loop bandwidth and damping factor of the slow CDR loop. The fast CDR loop (curve 94) responds to the adaptation of the slow' CDR loop (curve 90) and compensates for it in the opposite direction.

[0070] The overall effect is that the 1-UI bias step is transferred slowly from digital sampling (by resampler 40) to analog sampling (by ADC 28). At the same time, the total timing phase (curve 98) is smooth and transparent to equalizer 52 and FD 56 (see sharp steps in curv e 98).

[0071] Fig. 5 shows an example of a sequence of thirty-two iterations applied to the received signal (achieving a total timing correction of 32-UI) with a “WAIT NCO” waiting period inserted after every N=5 iterations. Curve 94 shows how' the “WAIT NCO” period allows NCO 72 to converge almost to zero, before starting the next sequence of N=5 iterations.

[0072] Note that the dynamic range of NCO 72 remains below m / k*N throughout the process. After finding the correct shift and allowing the second order loop to fully converge, the output of NCO 72 depends on the overshoot, which in turn depends on the configured loop damping factor. Unlike the example of Fig. 4, in the present example the overshoot is small due to overdamped loop configuration. Finally, after completing the sequence of 32 iterations, the slow CDR loop converges and the analog signal is ideally sampled at the correct phase that also yields frame alignment.

[0073] It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

CLAIMS1. A receiver, comprising: circuitry comprising a Clock and Data Recovery (CDR) loop, the circuitry configured to apply CDR to a signal using the CDR loop, and to buffer the signal that underwent CDR in a memory buffer; and a frame aligner, configured to align the signal buffered in the memory buffer to frame boundaries between successive frames of the signal, by applying to the CDR loop one or more shifts, each equivalent to a symbol duration of the signal.

2. The receiver according to claim 1, wherein: the circuitry comprises a processing chain configured to sample the signal in accordance with a sampling clock, re-sample the sampled signal in accordance with a resampling phase, and buffer the re-sampled signal in the memory buffer; the CDR loop comprises (i) a first CDR loop configured to adjust the sampling clock and (ii) a second CDR loop configured to adjust the re-sampling phase; and the frame aligner is configured to align the signal buffered in the memory buffer to the frame boundaries by applying the one or more shifts to both the first CDR loop and the second CDR loop.

3. The receiver according to claim 2, wherein the first CDR loop has a first loop bandwidth, and wherein the second CDR loop has a second loop bandwidth that is larger than the first loop bandwidth.

4. The receiver according to claim 2, wherein the circuitry comprises a Numerically- Controlled Oscillator (NCO) configured to adjust sampling phases of the first and second CDR loops, and wherein the frame aligner is configured to apply the shifts by controlling the NCO.

5. The receiver according to any of claims 1-4, wherein the circuitry is configured to detect a frame synchronization sequence in the signal when the signal buffered in the memory buffer to the frame boundaries, and wherein the frame aligner is configured to continue applying the shifts until the frame synchronization sequence is detected.

6. The receiver according to any of claims 1-4, wherein the frame aligner is configured to apply each of the shifts during a different frame of the signal.

7. The receiver according to any of claims 1-4, wherein the frame aligner is configured to insert a waiting period after every N shifts, N being a defined integer.

8. A method, comprising: applying Clock and Data Recovery7(CDR) to a signal using a CDR loop; buffering the signal that underwent CDR in a memory buffer; aligning the signal buffered in the memory buffer to frame boundaries between successive frames of the signal, by applying to the CDR loop one or more shifts, each equivalent to a symbol duration of the signal; and applying further processing to the aligned signal in the memory buffer.

9. The method according to claim 8, wherein: applying the CDR loop comprises (i) adjusting a sampling clock of the signal by a first CDR loop and (ii) adjusting a re-sampling phase of the signal by a second CDR loop; and aligning the signal comprises applying the one or more shifts to both the first CDR loop and the second CDR loop.

10. The method according to claim 9, wherein the first CDR loop has a first loop bandwidth, and wherein the second CDR loop has a second loop bandwidth that is larger than the first loop bandwidth.

11. The method according to claim 9, wherein aligning the signal comprises applying the shifts to a Numerically-Controlled Oscillator (NCO) that adjusts sampling phases of the first and second CDR loops.

12. The method according to any of claims 8-11, wherein aligning the signal comprises continuing applying the shifts until detecting a frame synchronization sequence in the signal, indicating that the signal buffered in the memory buffer is aligned to the frame boundaries.

13. The method according to any of claims 8-11, wherein aligning the signal comprises applying each of the shifts during a different frame of the signal.

14. The method according to any of claims 8-11, wherein aligning the signal comprises inserting a waiting period after every7N shifts, N being a defined integer.

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