Annular gate plasma transistor and manufacturing method therefor

Abstract

Provided are an annular gate plasma transistor and a manufacturing method therefor. The annular gate plasma transistor comprises a source electrode layer (1), a gate electrode layer (2) and a drain electrode layer (3), wherein a first insulating layer (4) is provided between the gate electrode layer (2) and the drain electrode layer (3), and a second insulating layer (5) is provided between the source electrode layer (1) and the gate electrode layer (2); several through holes (20) are formed in a gate electrode of the gate electrode layer (2), the first insulating layer (4) and the second insulating layer (5) are of a hollow structure, and the hollow structure of the first insulating layer (4) is connected to the hollow structure of the second insulating layer (5) by means of the through holes (20), so that a closed chamber is formed between the source electrode layer (1) and the drain electrode layer (3), and a source electrode of the source electrode layer (1), the gate electrode of the gate electrode layer (2) and a drain electrode of the drain electrode layer (3) are exposed in the closed chamber; when the annular gate plasma transistor works, there are carriers in the closed cavity; and the movement trajectories of the carriers are regulated, so as to regulate an on-state current of the annular gate plasma transistor. The present disclosure has a relatively strong gate control capability.

Description

Ring-gate plasma transistor and manufacturing method thereof

[0001] Related applications

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on September 12, 2023, with application number CN202311173141.9 and invention name “A Ring-Gate Plasma Transistor and Its Manufacturing Method,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of field effect switches and amplifier devices, and in particular to a ring-gate plasma transistor and a method for manufacturing the same. Background Art

[0004] Due to its advantages such as long mean free path of carriers, high mobility, and strong current-carrying capacity, low-pressure plasma is used as a carrier transport channel or medium in many important electronic devices, such as thyratrons and trigger diodes. Thyratrons are three-terminal devices with a gate electrode. Due to their high current and high power characteristics, they are widely used in scientific research, military, medical, and industrial fields, such as fast switches in lasers and radars, rectifiers, and relaxation oscillators. However, because the mesh size of the gate electrode of traditional thyratrons is much larger than the Debye length of the low-pressure plasma, changes in the gate voltage are completely shielded by the plasma, making it impossible for the gate electrode to regulate the anode current. Thyratrons can only function as switches, without power amplification.

[0005] In 2008, Eden et al. used microcavity plasma to replace the collector electrode in a bipolar junction transistor, fabricating a plasma-based transistor. This device increased the conduction current by a factor of four at a -20V operating voltage. In 2010, the same research group designed and fabricated a plasma transistor that could be turned off with a base-emitter voltage of 1V (DOI: 10.1063 / 1.2981573). In 2015, Massood Tabib-Azar et al. proposed a microcavity plasma transistor device capable of regulating the microcavity plasma concentration via a gate electrode. Testing in a high-temperature, high-radiation nuclear reactor verified the device's excellent resistance to high temperatures and radiation (U.S. Patent: US2015 / 0162158Al). In 2018, Wang Yaogong et al. proposed a microcavity plasma transistor with a similar structure and its fabrication method (Chinese Patent: ZL201811125596.2). However, all previous plasma transistors controlled the channel current via a lateral gate electrode. Because plasma has strong electric field shielding properties, it is difficult for side gate electrodes to effectively control the plasma channel current. Therefore, the gate control capability of plasma channel transistors has been poor, making it difficult to meet the needs of practical applications. In addition, plasma channel transistors have previously used DC high-voltage electric field breakdown or AC radio frequency electric field excitation to excite plasma. The DC high-voltage electric field breakdown method requires the device to have a very high operating voltage, and the AC radio frequency electric field excitation method requires the device to introduce a complex radio frequency excitation circuit. Therefore, previous plasma channel crystals also have the disadvantages of high operating voltage or complex device structure.

[0006] Summary of the Invention

[0007] In view of the technical problems existing in the prior art, the present disclosure aims to provide a ring-gate plasma transistor and a manufacturing method thereof, an electronic device and an electronic device.

[0008] The present application provides a plasma-based ring-gate transistor, which includes a source electrode layer, a drain electrode layer, a gate electrode layer, a first insulating layer, and a second insulating layer. The first insulating layer is located between the drain electrode layer and the gate electrode layer, and the second insulating layer is located between the source electrode layer and the gate electrode layer. In other words, the source electrode layer, the second insulating layer, the gate electrode layer, the first insulating layer, and the drain electrode layer are stacked in this order. A gate electrode of the gate electrode layer is provided with a plurality of through holes. The first insulating layer and the second insulating layer are hollow structures. The hollow structure of the first insulating layer is connected to the hollow structure of the second insulating layer through the through holes, thereby forming a closed chamber between the source electrode layer and the drain electrode layer, and the source electrode of the source electrode layer, the gate electrode of the gate electrode layer, and the drain electrode of the drain electrode layer are exposed in the closed chamber. When the ring-gate plasma transistor is in operation, plasma exists in the closed chamber, and the electrons and ions in the plasma serve as carriers. When the carriers are transported along the source electrode, the hollow structure of the first insulating layer, the through holes, the hollow structure of the second insulating layer, and the drain electrode, the gate electrode regulates the concentration and velocity of the carriers in the through holes and thereby regulates the current of the ring-gate plasma transistor.

[0009] In some possible implementations, in order to regulate the conduction current of the transistor, a plurality of through holes (ie, through holes) are provided in the center of the gate electrode layer, and the length of the through holes determines the effective channel length of the ring-gate plasma transistor.

[0010] In some possible implementations, the hollow structure of the first insulating layer, the through-hole of the gate electrode, and the hollow structure of the second insulating layer are coaxial to form a regular closed chamber.

[0011] In the ring-gate plasma transistor provided in the embodiment of the present application, the source electrode of the source electrode layer can be a conductive sheet electrode, or a filament cathode processed on an insulating substrate, or a micro-on-chip electron emission source prepared using micro-nano processing; the diameter of the central through hole of the gate electrode layer must match the Debye length of the plasma at a certain specific gas pressure (0.1~1000Pa), so that the carrier transport can be efficiently regulated; the thickness of the first insulating layer and the second insulating layer must match the mean free path of gas molecules at a certain specific gas pressure (0.1~1000Pa), so as to increase the probability of collision and ionization of gas molecules, thereby allowing the gas molecules to fully collide and ionize.

[0012] In the plasma transistor provided in the embodiment of the present application, the source electrode layer, the second insulating layer, the gate electrode layer, the first insulating layer, and the drain electrode layer are assembled by anodic bonding to form a microcavity, and the pressure inside the cavity is maintained at 0.1 to 1000 Pa. Compared with the micro vacuum transistors in the prior art, the structure processing technology is simpler and easier to operate, and the device processing cost is lower. At the same time, the vacuum condition required for the plasma transistor device in the present application is a rough vacuum (0.1 to 1000 Pa), which has lower requirements for device packaging. Electrons emitted by the source electrode collide with gas molecules inside the closed cavity under the action of the strong electric field of the drain electrode layer to excite plasma. Due to the high mobility and high ion concentration of the plasma, the on-state current and power of the device are much greater than those of solid-state devices. In addition, the plasma transistor has the advantages of traditional vacuum devices - radiation resistance and high temperature resistance. The diameter of the central through hole of the gate electrode layer in the ring-gate plasma transistor matches the Debye length of the plasma at a set gas pressure to avoid plasma shielding of the gate electrode. Therefore, the concentration and velocity of carriers can be efficiently controlled to control the current of the device, achieving strong gate control capability.

[0013] In some possible implementations, when the substrates of the source electrode layer, the drain electrode layer and the gate electrode layer are conductive substrates, any one of the three substrates can simultaneously serve as corresponding electrodes, wherein the conductive substrate is a doped silicon substrate.

[0014] In some possible implementations, the surface of the gate electrode exposed to the plasma is entirely or partially covered with an insulating layer.

[0015] In some possible implementations, the source electrode is an electron emission source, which is exposed in the closed chamber to emit electrons for impact ionization to excite low-pressure plasma in the closed chamber.

[0016] In some possible implementations, the electron emission source may be a yttrium oxide thermal emission source, comprising two drive electrodes and an electron emitter. The electron emitter comprises a suspended metal wire and yttrium oxide coated on the surface of the metal wire. The metal wire is composed of one or more of the following materials: iridium, platinum, tungsten, molybdenum, chromium, and gold.

[0017] In some possible implementations, the closed chamber is filled with one or more of the following low-pressure plasma gases: hydrogen, helium, nitrogen, oxygen, neon, argon, and mercury vapor, and the gas pressure is maintained at 0.1-1000 Pa.

[0018] In some possible implementations, the first insulating layer and the second insulating layer are made of the same material, and the thickness of the second insulating layer is greater than that of the first insulating layer.

[0019] In some possible implementations, the thickness of the first insulating layer is in the range of 1 mm to 3 mm, ensuring that the emitted electrons of the source electrode can be accelerated to sufficient energy under the action of the grid voltage so as to fully collide with the gas molecules and ionize them.

[0020] In some possible implementations, the thickness of the second insulating layer is in the range of 2 mm to 4 mm, ensuring that the distance is much larger than the mean free path of electrons under a certain gas pressure (0.1 to 1000 Pa), so that the electrons fully collide with gas molecules and ionize them.

[0021] In some possible implementations, the device comprises, from bottom to top, a source electrode layer, a second insulating layer, a gate electrode layer, a first insulating layer, and a drain electrode layer, and the device is packaged by anodic bonding.

[0022] In some possible implementations, the diameter of the through hole of the grid is smaller than or equal to the Debye length of the plasma at a certain pressure (0.1-1000 Pa), and the length of the through hole 20 is smaller than or equal to 1 mm.

[0023] In some possible implementations, the substrates of the source electrode layer, the drain electrode layer, and the gate electrode layer are composed of one or more of the following materials: silicon and glass.

[0024] In some possible implementations, the plasma transistor further includes a heat dissipation component, which is located below the substrate of the source electrode layer.

[0025] In some possible implementations, the plasma transistor further includes a power supply and a control module for providing voltages to the collector, the gate electrode, the first driving electrode, and the second driving electrode and regulating the voltages.

[0026] In some possible implementations, the plasma transistor further includes a base, which is an electrical connection for providing voltage and regulating voltage to the source electrode layer, the gate electrode layer, and the drain electrode layer.

[0027] In some possible implementations, the plasma transistor further includes a gas supplement therein; the gas supplement is used to maintain the gas pressure inside the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1a to 1d are schematic structural diagrams of a ring-gate plasma transistor in a first embodiment of the present disclosure; Figure 1a is a schematic three-dimensional structural diagram of the plasma transistor, Figure 1b is a cross-sectional view of the device taken along the AA' dashed line in Figure 1a, Figure 1c is a top view of the gate electrode layer in the device, and Figure 1d is an enlarged schematic diagram of the through hole of the gate electrode layer in the dashed box in Figure 1c.

[0029] FIG2 is a schematic diagram of a cross-sectional three-dimensional structure of a ring-gate plasma transistor in a second embodiment of the present disclosure.

[0030] Figures 3a to 3c are schematic structural diagrams of the ring-gate plasma transistor in Example 3 of the present disclosure; wherein Figure 3a is a cross-sectional view of the device, Figure 3b is a stereoscopic schematic diagram of the source electrode layer in the device, and Figure 3c is a stereoscopic schematic diagram of the gate electrode 21 in the device.

[0031] 4a to 4b are schematic structural diagrams of a ring-gate plasma transistor in a fourth embodiment of the present disclosure; wherein FIG4a is a schematic cross-sectional three-dimensional structural diagram of the plasma transistor; and FIG4b is a main view of the cross-sectional view of the device.

[0032] Figures 5a to 5c are schematic structural diagrams of the ring-gate plasma transistor in Example 5 of the present disclosure; Figure 5a is a three-dimensional cross-sectional view of the ring-gate plasma transistor provided in Example 5; Figure 5b is a main view of the cross-sectional portion of the device; and Figure 5c is a three-dimensional schematic diagram of the source electrode layer 1 in an embodiment of the present disclosure.

[0033] Figures 6a to 6c are schematic structural diagrams of the ring-gate plasma transistor in Example 6 of the present disclosure; Figure 6a is a three-dimensional cross-sectional view of the plasma transistor provided in an embodiment of the present disclosure; Figure 6b is a main view of the cross-sectional portion of the device; and Figure 6c is a top view of the source electrode layer 1 in an embodiment of the present disclosure.

[0034] Figures 7a to 7b are schematic structural diagrams of a ring-gate plasma transistor in a seventh embodiment of the present disclosure; Figure 7a is a three-dimensional cross-sectional view of a plasma transistor provided in an embodiment of the present disclosure; and Figure 7b is a main view of the cross-sectional portion of the device.

[0035] Figures 8a to 8b are schematic structural diagrams of a ring-gate plasma transistor in an eighth embodiment of the present disclosure; Figure 8a is a three-dimensional cross-sectional view of a plasma transistor including a heat dissipation layer provided in an embodiment of the present disclosure; and Figure 8b is a main view of the cross-sectional portion of the device.

[0036] Figures 9a to 9b are schematic structural diagrams of a ring-gate plasma transistor in a ninth embodiment of the present disclosure; Figure 9a is a schematic three-dimensional structural diagram of a ring-gate plasma transistor including a circuit base provided in an embodiment of the present disclosure; and Figure 9b is a cross-sectional view of the plasma transistor along the dotted line AA' in Figure 9a.

[0037] FIG10 is a schematic diagram of the three-dimensional structure of the ring-gate plasma transistor in the tenth embodiment of the present disclosure, including electrical connections for providing voltage and regulating circuit modules for the source electrode layer, the gate electrode layer, and the drain electrode layer.

[0038] FIG11 is a flow chart of a method for preparing a ring-gate plasma transistor provided in an embodiment of the present disclosure.

[0039] FIG12 is a schematic diagram showing a specific bonding sequence during the fabrication of a ring-gate plasma transistor. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of this application.

[0041] The terms "first", "second", etc. in the specification, embodiments, claims and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "At least one (item)" means one or more, and "more" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the front and back associated objects are in an "or" relationship. "Installation", "connection", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0042] An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB; also called a circuit board) and an electronic device electrically connected to the circuit board.

[0043] This application does not limit the application fields, scenarios, and configuration forms of the above-mentioned electronic devices. In practice, they can be configured as needed. For example, the above-mentioned electronic devices can be medical X-ray equipment, X-ray non-destructive testing equipment, X-ray fluorescence detection equipment, sterilization and disinfection equipment, vacuum measurement and leak detection equipment, ion electric propulsion equipment, electron beam detection and imaging equipment, mass spectrometers, high-power microwave sources, electric vacuum devices, etc.

[0044] In this application, the electronic devices in the electronic devices described above utilize one or more novel miniature ring-gate plasma transistors. These transistors generate plasma through the collision of electrons emitted by an electron source with gas molecules. By adjusting the voltage of the gate electrode layer, they alter the transport of carriers within the channel, thereby regulating the device's conduction current. These devices offer advantages such as low vacuum requirements, simple processing, high on-state current, high power, radiation resistance, and high-temperature resistance. The detailed structure is described below.

[0045] Example 1

[0046] The ring-gate plasma transistor constructed in this embodiment includes:

[0047] Source electrode layer 1;

[0048] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2. The diameter of the through holes should match the Debye length of the plasma under a specific gas pressure (0.1-1000 Pa) to regulate the transport of carriers in the through holes.

[0049] a drain electrode layer 3 located above the gate electrode layer 2;

[0050] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used to isolate the source electrode layer 1 from the gate electrode layer 2. The first insulating layer 4 has a through hole in the middle.

[0051] The second insulating layer 5 located between the source electrode layer 1 and the gate electrode layer 2 is used to isolate the gate electrode layer 2 from the drain electrode layer 3 . The second insulating layer 5 has a through hole in the middle.

[0052] In this embodiment, the source electrode layer substrate, the gate electrode layer substrate and the drain electrode layer substrate are doped silicon substrates. Since the substrate itself is conductive, it also serves as the corresponding electrodes, that is, it can be used as the source electrode, gate electrode and drain electrode respectively.

[0053] 1a is a schematic diagram of the three-dimensional structure of a plasma transistor provided in one embodiment of the present disclosure, FIG1b is a main view of the cross-sectional portion of the device, FIG1c is a top view of the gate electrode layer 2 of the device, and FIG1d is an enlarged schematic diagram of the through hole of the gate electrode layer.

[0054] The device operating principle of this embodiment is as follows: Under the influence of some excitation mechanism (such as a DC electric field, an AC electric field, electron beam impact ionization, or light excitation), the low-pressure gas within the device chamber is ionized to produce electrons and ions, forming a plasma (also referred to as a low-pressure plasma, which may include high-speed electrons generated by the source electrode and electrons and ions generated by collisions between high-speed electrons and gas molecules). A certain voltage difference is applied between the source electrode layer 1 and the drain electrode layer 3. The electrons and ions (collectively referred to as carriers) in the plasma within the device chamber are transported between the source and drain electrodes under the action of the electric field. Changing the voltage value of the gate electrode layer 2 can change the potential distribution near the gate electrode through-hole 20, forming a carrier depletion region 201 near the through-hole. As the depletion region 201 increases and decreases under the control of the gate electrode voltage, the non-depletion region 202 in the carrier channel correspondingly decreases and increases, further causing the plasma current in the through-hole 20 to decrease and increase, thereby achieving control of the device conduction current by the gate electrode layer 2. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0055] Example 2

[0056] The ring-gate plasma transistor constructed in this embodiment includes:

[0057] Source electrode layer 1;

[0058] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2. The diameter of the through holes should match the Debye length of the plasma under a specific gas pressure (0.1-1000 Pa) to regulate the transport of carriers in the through holes. At the same time, all surfaces of the gate electrode layer exposed to the plasma are covered with an insulating dielectric layer 22 (i.e., an insulating layer). The insulating dielectric layer is used to block the electrical contact between the gate electrode layer and the plasma, thereby suppressing the leakage current of the gate electrode;

[0059] a drain electrode layer 3 located above the gate electrode layer 2;

[0060] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used to isolate the source electrode layer 1 from the gate electrode layer 2. The first insulating layer 4 has a through hole in the middle.

[0061] The second insulating layer 5 located between the source electrode layer 1 and the gate electrode layer 2 is used to isolate the gate electrode layer 2 from the drain electrode layer 3 . The second insulating layer 5 has a through hole in the middle.

[0062] In this embodiment, the source electrode layer substrate, the gate electrode layer substrate and the drain electrode layer substrate are doped silicon substrates. Since the substrate itself is conductive, it also serves as the corresponding electrodes, that is, it can be used as the source electrode, gate electrode and drain electrode respectively.

[0063] FIG2 is a schematic diagram of a cross-sectional three-dimensional structure of a plasma transistor provided in one embodiment of the present disclosure.

[0064] The device operating principle of this embodiment is as follows: Under the influence of some excitation mechanism (such as a DC electric field, an AC electric field, electron beam impact ionization, or light excitation), the low-pressure gas inside the device chamber is ionized to produce electrons and ions, forming a plasma. A voltage difference of a certain intensity is applied between the source electrode layer 1 and the drain electrode layer 3. The electrons and ions in the plasma inside the device chamber are transported between the source and drain electrodes under the action of the electric field. Changing the voltage value of the gate electrode layer 2 can change the potential distribution near the gate electrode through hole 20, resulting in the formation of a carrier depletion region near the through hole 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depletion region in the carrier channel correspondingly decreases and increases, further causing the plasma current in the through hole 20 to decrease and increase, thereby achieving control of the device conduction current by the gate electrode layer 2. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0065] Example 3

[0066] The ring-gate plasma transistor constructed in this embodiment includes:

[0067] The source electrode layer 1 includes a substrate layer and a source electrode 10. The substrate of the source electrode layer is made of an insulating material, such as glass. The source electrode 10 of the source electrode layer 1 penetrates the substrate layer of the source electrode layer through a through hole and is exposed from the surface of the substrate layer of the source electrode layer.

[0068] A gate electrode layer 2 is located above the source electrode layer 1. The gate electrode layer 2 includes a substrate layer and a gate electrode 21. The substrate of the gate electrode layer is made of an insulating material, such as glass. The gate electrode 21 can be located in the middle of the gate electrode layer 2 and above the substrate layer of the gate electrode layer. A plurality of through holes 20 are located in the middle of the gate electrode 21. The diameter of the through holes should match the Debye length of the plasma at a specific gas pressure (0.1 to 1000 Pa) to regulate the transport of carriers in the through holes.

[0069] A drain electrode layer 3 is located above the gate electrode layer 2. The drain electrode layer 3 includes a substrate layer and a drain electrode 30. The substrate of the drain electrode layer is made of an insulating material, such as glass. The drain electrode 30 of the drain electrode layer 3 penetrates the substrate layer of the drain electrode layer through a through hole and is exposed from the surface of the substrate layer of the drain electrode layer.

[0070] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used to isolate the gate electrode layer 2 from the drain electrode layer 3. The first insulating layer 4 has a through hole in the middle.

[0071] The second insulating layer 5 is located between the source electrode layer 1 and the gate electrode layer 2 and is used to isolate the source electrode layer 1 from the gate electrode layer 2 . The second insulating layer 5 has a through hole in the middle.

[0072] FIG3 a is a cross-sectional view of a plasma transistor provided in one embodiment of the present disclosure, FIG3 b is a schematic three-dimensional structure diagram of the source electrode layer 1 of the device, and FIG3 c is a schematic three-dimensional diagram of the gate electrode 21 in the device.

[0073] The device of this embodiment operates as follows: Under the influence of some excitation mechanism (such as a DC electric field, an AC electric field, electron beam impact ionization, or light excitation), the low-pressure gas within the device chamber is ionized to produce electrons and ions, forming a plasma. A voltage difference of a certain magnitude is applied between the source electrode 10 and the drain electrode 30. The electrons and ions in the plasma within the device chamber are transported between the source and drain electrodes under the influence of the electric field. Changing the voltage value of the gate electrode 21 can change the potential distribution near the gate electrode through-hole 20, forming a carrier depletion region near the through-hole 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depletion region within the carrier channel correspondingly decreases and increases, further causing the plasma current in the through-hole to decrease and increase, thereby enabling the gate electrode 21 to control the device's conduction current. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0074] Example 4

[0075] The ring-gate plasma transistor constructed in this embodiment includes:

[0076] Source electrode layer 1, source electrode layer 1 includes a substrate layer and an electron emission source serving as a source electrode 10, wherein the source electrode layer uses doped silicon as a substrate material; the electron emission source includes a filament (also referred to as a cathode filament or filament) 101, a first drive electrode 102, and a second drive electrode 103, wherein the filament 101 is made of one of metal materials such as iridium, platinum, tungsten, molybdenum, chromium, and gold, and is covered with a layer of yttrium oxide on the surface of the filament; the first drive electrode 102 and the second drive electrode 103 are used to fix the filament 101 and provide a voltage thereto to drive the filament 101 to heat and emit electrons; the first drive electrode 102 and the second drive electrode 103 penetrate the substrate layer through a through hole and are isolated from the conductive substrate by an insulating silicon oxide material;

[0077] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2. The diameter of the through holes should match the Debye length of the plasma under a specific gas pressure (0.1-1000 Pa) to regulate the transport of carriers in the gate electrode through holes.

[0078] a drain electrode layer 3 located above the gate electrode layer 2;

[0079] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used to isolate the gate electrode layer 2 from the drain electrode layer 3. The first insulating layer 4 has a through hole in the middle.

[0080] The second insulating layer 5 located between the source electrode layer 1 and the gate electrode layer 2 is used to isolate the electron emission source from the gate electrode layer 2 . The second insulating layer 5 has a through hole in the middle.

[0081] FIG4 a is a schematic diagram of a cross-sectional three-dimensional structure of a plasma transistor provided in one embodiment of the present disclosure, and FIG4 b is a front view of a cross-sectional portion of the device.

[0082] The device operating principle of this embodiment is as follows: A voltage difference of a certain magnitude is applied between the first drive electrode 102 and the second drive electrode 103, causing current to flow through the interior of the filament 101 and heat it. When the temperature of the filament 101 reaches a certain value, electrons are emitted from the surface of the filament 101 into the surrounding low-pressure gas. A voltage difference of a certain magnitude is applied between the first or second drive electrode and the drain electrode layer 3. Driven by the electric field, the emitted electrons move toward the drain electrode layer and collide with gas molecules to generate plasma. Electrons and ions in the plasma within the device chamber are transported between the source and drain electrodes under the action of the electric field. Changing the voltage value of the gate electrode layer 2 can change the potential distribution near the gate electrode through-hole, resulting in the formation of a carrier depletion region near the through-hole 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depletion region in the carrier channel correspondingly decreases and increases, further reducing and increasing the plasma current in the through-hole, thereby enabling the gate electrode layer to control the device's conduction current. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0083] Example 5

[0084] In order to improve the airtightness of the device and reduce the difficulty of device bonding, the substrate in this embodiment uses a TGV substrate (that is, glass is embedded in the center of the silicon substrate, and two driving electrodes are introduced through the substrate in the center of the glass), and the filament of the electron emission source is fixed above the substrate by spot welding.

[0085] The plasma transistor constructed in this embodiment includes:

[0086] Source electrode layer 1, source electrode layer 1 includes a substrate layer and an electron emission source serving as source electrode 10, the source electrode layer using doped silicon as the substrate material; the electron emission source includes a filament 101, a first drive electrode 102, a second drive electrode 103, and an insulating layer 104, wherein the filament 101 is made of one of metal materials such as iridium, platinum, tungsten, molybdenum, chromium, and gold, and is covered with a layer of yttrium oxide on the surface of the filament 101; the first drive electrode 102 and the second drive electrode 103 are used to fix the filament and provide voltage to it to drive the electron emission source to heat and emit electrons; the insulating layer 104 is made of insulating glass to prevent the drive electrode from contacting the conductive substrate;

[0087] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2. The diameter of the through holes should match the Debye length of the plasma under a specific gas pressure (0.1-1000 Pa) to regulate the transport of carriers in the gate electrode through holes 20;

[0088] a drain electrode layer 3 located above the gate electrode layer 2;

[0089] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used for connecting the gate electrode layer 2 and the drain electrode layer 3. The first insulating layer 4 has a through hole in the middle.

[0090] The second insulating layer 5 located between the source electrode layer 1 and the gate electrode layer 2 is used to isolate the electron emission source from the gate electrode layer 2 . The second insulating layer 5 has a through hole in the middle.

[0091] FIG5a is a three-dimensional cross-sectional view of a ring-gate plasma transistor provided in this embodiment, FIG5b is a front view of the cross-sectional portion of the device, and FIG5c is a three-dimensional schematic view of the source electrode layer 1 in this embodiment.

[0092] The device operating principle of this embodiment is as follows: A voltage difference of a certain magnitude is applied between the first drive electrode 102 and the second drive electrode 103, causing current to flow through the filament 101 and heat it. When the filament temperature reaches a certain value, electrons are emitted from the surface of the filament 101 into the rough vacuum. A voltage difference of a certain magnitude is applied between the first or second drive electrode and the drain electrode layer 3. Driven by the electric field, the emitted electrons move toward the drain electrode layer and collide with gas molecules to generate plasma. Electrons and ions in the plasma within the device chamber are transported between the source and drain electrodes under the action of the electric field. Changing the voltage value of the gate electrode layer 2 can change the potential distribution near the gate electrode through-hole, forming a carrier depletion region near the through-hole 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depletion region in the carrier channel correspondingly decreases and increases, further reducing and increasing the plasma current in the through-hole, thereby enabling the gate electrode layer to control the device's conduction current. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0093] Therefore, this embodiment shares the same components, positional relationships, and operating principles as the fourth embodiment. The first drive electrode 102 and the second drive electrode 103 provide voltage to the filament 101, driving the electron emission source to emit electrons into the rough vacuum and ignite a plasma. This embodiment differs from the fourth embodiment in that the substrate employed in this embodiment is a silicon-glass TGV substrate, which is more conducive to device bonding and packaging.

[0094] Example 6

[0095] To meet the requirements of practical applications, this embodiment provides an electron emission source with higher current and more stable performance. This embodiment uses a filament with a larger diameter as the electron emission source, and increases the filament length by winding it in a coil, thereby improving filament life and emission current. The filament is then fixed to the source electrode layer substrate through mechanical assembly.

[0096] The ring-gate plasma transistor constructed in this embodiment includes:

[0097] The source electrode layer 1 includes a substrate layer and a source electrode 10. The source electrode layer uses glass as a substrate material and has a thickness of 5 to 6 mm. The source electrode 10 of the source electrode layer is an electron emission source. The electron emission source uses a filament with a diameter of 0.1 mm as a cathode, and the filament length is increased by winding.

[0098] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2. The diameter of the through holes should match the Debye length of the plasma under a specific gas pressure (0.1-1000 Pa) to regulate the transport of carriers in the through holes.

[0099] a drain electrode layer 3 located above the gate electrode layer 2;

[0100] The first insulating layer 4 located between the drain electrode layer 3 and the gate electrode layer 2 is used to isolate the drain electrode layer 3 from the gate electrode layer 2 . The first insulating layer 4 has a through hole in the middle.

[0101] Figure 6a is a three-dimensional cross-sectional view of a ring-gate plasma transistor provided in this embodiment, Figure 6b is a front view of the cross-sectional portion of the device, and Figure 6c is a top view of the source electrode layer 1 in this embodiment. In this embodiment, the filament cathode serves as an electron emission source and is mechanically assembled on the substrate of the source electrode layer 1. Inorganic glue can be used to fix and seal the two ends of the filament. Compared with the spot-welded filament, the filament used in this embodiment has a larger diameter (0.1 mm), and the winding method increases the length of the filament, thereby improving the ability of the filament cathode to emit electrons and the life of the filament, which is beneficial to improving the life and stability of the plasma transistor. As shown in Figure 6b, the electron emission source is fixed to the center of the source electrode layer 1, and the source electrode layer 1, the gate electrode layer 2, the first insulating layer 4 and the drain electrode layer 3 are encapsulated together by anodic bonding, and the air pressure inside the chamber is maintained at 0.1 to 1000 Pa.

[0102] The device in this embodiment operates as follows: A voltage difference of a certain magnitude is applied across the electron emission source, causing current to flow through the source and heat it. When the temperature of the electron emission source reaches a certain value, electrons are emitted from its surface into a rough vacuum. A voltage difference of a certain magnitude is applied between the electron emission source and the drain electrode layer 3. Driven by the electric field, the emitted electrons move toward the drain electrode layer and collide with gas molecules to generate plasma. Electrons and ions in the plasma within the device chamber are transported between the source and drain electrodes under the action of the electric field. Changing the voltage value of the gate electrode layer 2 can alter the potential distribution near the gate electrode via, forming a carrier depletion region near the via 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depleted region within the carrier channel correspondingly decreases and increases, further reducing and increasing the plasma current within the via, thereby enabling the gate electrode layer to control the device's conduction current. That is, when the carriers are transported in sequence through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in reverse along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0103] This embodiment shares the same components, positional relationships, and operating principles as the fourth embodiment. A voltage is applied to both ends of the electron emission source to drive the electron emission source to emit electrons into a rough vacuum and ignite a plasma. This embodiment differs from the fourth embodiment in that the source electrode layer substrate in this embodiment not only secures the cathode filament but also serves as an insulating layer to prevent contact between the gate electrode layer and the electron emission source. Furthermore, the filament used in this embodiment has superior electron emission capability and lifespan to the cathode filament in the fourth embodiment.

[0104] Example 7

[0105] In order to simplify the processing of the ring-gate plasma transistor device, this embodiment is based on the sixth embodiment, in which the source electrode layer uses conductive doped silicon, and the electron emission source is fixed on the second insulating layer.

[0106] The ring-gate plasma transistor constructed in this embodiment includes:

[0107] The source electrode layer 1 includes a substrate layer and a source electrode 10. The substrate layer of the source electrode layer 1 is made of heavily doped silicon. The source electrode is an electron emission source.

[0108] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2;

[0109] a drain electrode layer 3 located above the gate electrode layer 2;

[0110] A first insulating layer 4 is located between the drain electrode layer 3 and the gate electrode layer 2, and is used to isolate the gate electrode layer 2 from the drain electrode layer 3. The first insulating layer 4 has a through hole in the middle.

[0111] The second insulating layer 5 is located between the source electrode layer 1 and the gate electrode layer 2 and is used to isolate the source electrode layer 1 from the gate electrode layer 2 . The second insulating layer 5 has a through hole in the middle.

[0112] Figure 7a is a three-dimensional cross-sectional view of a ring-gate plasma transistor provided in one embodiment of the present disclosure, and Figure 7b is a front view of a cross-sectional portion of the device. The thickness of the second insulating layer 5 in this embodiment is 3-4 mm, which is less than the thickness of the source electrode layer 1 in Example 6. Because material thickness affects bonding quality—for example, the thinner the glass, the better the bonding quality with the silicon wafer—the device provided in this embodiment is less difficult to process than the device provided in Example 6. This embodiment shares the same components, positional relationships, and operating principles as Example 6. A voltage difference of a certain magnitude is applied across the two ends of the electron emission source, causing current to flow through the electron emission source and heat it. When the temperature of the electron emission source reaches a certain value, electrons are emitted from the surface of the electron emission source into the rough vacuum. A collection voltage is applied to the drain electrode layer 3. Driven by the external electric field, the emitted electrons move toward the drain electrode, where they collide with gas molecules within the chamber, ionizing them and generating plasma, thereby turning on the device. Changing the voltage value of the gate electrode layer 2 can change the potential distribution near the gate electrode through-hole, forming a carrier depletion region near the through-hole 20. As the depletion region increases and decreases under the control of the gate electrode voltage, the non-depletion region in the carrier channel decreases and increases accordingly, further causing the plasma current in the through-hole to decrease and increase, thereby achieving control of the device conduction current by the gate electrode layer. That is, when carriers are transported sequentially through the source electrode, the low-pressure plasma in the hollow structure of the first insulating layer, the low-pressure plasma in the gate electrode through-hole 20, the low-pressure plasma in the hollow structure of the second insulating layer, and the drain electrode, or when transported in the reverse direction along the above path, the gate electrode through-hole 20 acts as a ring gate to regulate the transport of carriers in the through-hole 20.

[0113] Example 8

[0114] Since the temperature of plasma can reach tens of thousands of degrees when excited, in order to accelerate the heat dissipation of plasma devices and prevent excessive temperature from damaging the devices, this embodiment provides a heat dissipation component under the substrate based on the fourth embodiment.

[0115] The ring-gate plasma transistor constructed in this embodiment includes:

[0116] Source electrode layer 1; source electrode layer 1 includes a substrate layer and a source electrode 10, wherein the source electrode of the source electrode layer 1 is an electron emission source, wherein the electron emission source includes a cathode filament 101, a first drive electrode 102 and a second drive electrode 103, wherein the filament cathode 101 is made of one of metal materials such as iridium, platinum, tungsten, molybdenum, chromium, gold, and the like, and the surface of the filament is covered with a layer of yttrium oxide; the first drive electrode 102 and the second drive electrode 103 are used to fix the filament and provide voltage to the filament to drive the filament to heat and emit electrons;

[0117] A gate electrode layer 2 is located above the source electrode layer 1, and a plurality of through holes 20 are present in the middle of the gate electrode layer 2;

[0118] a drain electrode layer 3 located above the gate electrode layer 2;

[0119] A first insulating layer 4 is located between the gate electrode layer 2 and the drain electrode layer 3, and is used to isolate the gate electrode layer 2 from the drain electrode layer 3. The first insulating layer 4 has a through hole in the middle.

[0120] A second insulating layer 5 located between the source electrode layer 1 and the gate electrode layer 2 is used to isolate the electron emission source from the gate electrode layer 2, and a through hole is provided in the middle of the second insulating layer 5;

[0121] The heat dissipation layer 6 is located below the source electrode layer 1 .

[0122] Figure 8a is a three-dimensional cross-sectional view of a ring-gate plasma transistor according to an embodiment of the present disclosure, and Figure 8b is a front view of a cross-sectional portion of the device. As shown in the figure, this embodiment adds a heat sink layer 6 below the substrate of the source electrode layer 1, based on the fourth embodiment. The heat sink layer is in close contact with the source electrode layer 1 to ensure good thermal conductivity between the substrate and the heat sink layer. The heat sink layer effectively facilitates the rapid dissipation of heat generated by the plasma transistor through the heat sink layer, preventing damage to the device due to excessive temperatures.

[0123] Example 9

[0124] In order to mount the ring-gate plasma transistor provided by the present disclosure as an electronic component on other devices, this embodiment adds a circuit base to the eighth embodiment for connecting the ring-gate plasma transistor to an external circuit. Figure 9a is a schematic diagram of the three-dimensional structure of a plasma transistor including a circuit base according to an embodiment of the present disclosure, and Figure 9b is a cross-sectional view of the plasma transistor along the dashed line AA' in Figure 9a. This embodiment adds a circuit base 7 below the heat dissipation layer. Circuit base 7 is provided with components (such as terminals, pins, or pinholes) that can be connected to an external circuit. The plasma transistor (including the substrate, heat dissipation layer, and other components) is mounted on circuit base 7. Connecting wires 721 (such as welding wires) connect the components (such as terminals, pins, and pinholes) on the circuit base to the various electrodes of the plasma transistor (such as the first drive electrode, the second drive electrode, the grid (i.e., the gate electrode), and the collector (i.e., the drain electrode)). This connects the plasma transistor to an external circuit, allowing it to be used on other devices.

[0125] Compared to Figure 8a in Example 8, the circuit base 7 at the bottom of this plasma transistor has a number of components 711, 712, 713, and 714 connected to the external circuit. Connecting wires 721, 722, 723, and 724 connect these components to the device's electrodes. The components on the base can be terminals, leads, or pinholes, and the connecting wires can be welding wires, which can be connected to the plasma transistor's electrodes and the base components via ultrasonic spot welding.

[0126] Example 10

[0127] To maintain the stability of the cathode filament conduction current and emission current in the plasma transistor, a circuit module 8 is required for the plasma transistor to provide voltage drive and regulation to the first drive electrode 102, the second drive electrode 103, the gate electrode layer 2, and the drain electrode layer 3. Figure 10 is a schematic diagram of the three-dimensional structure of the plasma transistor after the circuit module is introduced. This embodiment adds an external voltage and circuit module 8 to the ninth embodiment. The circuit module 8 includes a main switch 81 and voltage output terminals 821, 822, 823, and 824. Each voltage output terminal is connected to components (such as terminals, pins, pinholes, etc.) on the circuit base via connecting wires 831, 832, 833, and 834 (e.g., wires), thereby achieving voltage drive and regulation of each electrode of the device. The voltage output by each voltage output terminal should be fed back and changed in real time according to the operating requirements of the plasma transistor, thereby regulating the voltage of each electrode and ensuring the continuous and stable operation of the device.

[0128] The present application also provides a method for preparing a ring-gate plasma transistor, as shown in FIG11 , the method comprising:

[0129] S1: providing a first mother layer, a second mother layer, a third mother layer, a fourth mother layer, and a fifth mother layer.

[0130] S2: The first to fifth mother layers are bonded using an anodic bonding process, wherein the first mother layer includes N electron emission sources arranged in parallel with a period (i.e., N electron emission sources are arranged in parallel on the first mother layer), the second mother layer includes N first insulating layers with the same period as the first mother layer, the third mother layer includes N gate electrode layers with the same period as the first mother layer, the fourth mother layer includes N second insulating layers with the same period as the first mother layer, and the fifth mother layer includes N drain electrode layers with the same period as the first mother layer, N≥1; that is, the first to fifth mother layers each have multiple cyclic units, i.e., the first to fifth mother layers respectively have the same number and period of electron emission sources, first insulating layers, gate electrode layers, second insulating layers, and drain electrode layers; and when the first to fifth mother layers are bonded, the periods of each mother layer correspond, so that the cyclic units in each mother layer correspond.

[0131] S3: After bonding, cutting is performed to form the ring-gate plasma transistor. Specifically, cutting is performed according to the period of the cyclic unit in each mother layer to produce a plurality of the on-chip ring-gate plasma transistors.

[0132] As can be seen from the foregoing, the preparation method provided in this application utilizes an anodic bonding process to produce a ring-gate plasma transistor. This results in a relatively small size of the resulting ring-gate plasma transistor, allowing for integration with on-chip vacuum electronic devices, thereby providing an effective solution for the independent operation of the on-chip vacuum electronic devices. Furthermore, as can be seen from the foregoing, the method bonds the first to fifth mother layers and then cuts them to produce multiple ring-gate plasma transistors. Thus, the preparation method can be used to mass-produce the ring-gate plasma transistors, improving production efficiency and reducing production costs.

[0133] FIG12 is a schematic diagram of a specific bonding sequence during the fabrication of a ring-gate plasma transistor.

[0134] In one embodiment of the present disclosure, an electronic device is provided, which includes the ring-gate plasma transistor described in any of the above embodiments. In one embodiment of the present disclosure, an electronic device is also provided, which includes the above electronic device.

[0135] The above is only a preferred embodiment of the present application. Although the present application has disclosed the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art can use the above disclosed methods to make possible changes and modifications to the technical solutions proposed in the present application into equivalent equivalent embodiments without departing from the scope of the technical solutions of the present application. Therefore, any content that does not depart from the content of the technical solutions of the present application and makes simple changes, modifications and modifications to the above embodiments based on the technical essence of the present application still falls within the scope of protection of the technical solutions of the present application.

Claims

1. A ring-gate plasma transistor, characterized in that: The invention comprises a source electrode layer (1), a gate electrode layer (2) and a drain electrode layer (3); wherein a first insulating layer (4) is provided between the gate electrode layer (2) and the drain electrode layer (3), and a second insulating layer (5) is provided between the source electrode layer (1) and the gate electrode layer (2); a plurality of through holes (20) are provided on the gate electrode of the gate electrode layer (2); the first insulating layer (4) and the second insulating layer (5) are hollow structures; the hollow structure of the first insulating layer (4) is connected to the hollow structure of the second insulating layer (5) through the through holes (20), so that a hollow structure is formed between the source electrode layer (1) and the drain electrode layer (3); A closed chamber is formed, and the source electrode of the source electrode layer (1), the gate electrode of the gate electrode layer (2), and the drain electrode of the drain electrode layer (3) are exposed in the closed chamber; when the ring-gate plasma transistor is working, plasma exists in the closed chamber, and the electrons and ions in the plasma serve as carriers; when the carriers are transported along the source electrode, the hollow structure of the first insulating layer (4), the through hole (20), the hollow structure of the second insulating layer (5), and the drain electrode, the gate electrode regulates the concentration and speed of the carriers in the through hole (20) and thus regulates the current of the ring-gate plasma transistor.

2. The ring-gate plasma transistor according to claim 1, characterized in that: The surface of the gate electrode exposed to the plasma is entirely or partially covered with an insulating layer.

3. The ring-gate plasma transistor according to claim 1, characterized in that: The diameter of the through hole (20) matches the Debye length of the plasma under a set gas pressure; the thickness of the first insulating layer (4) and the second insulating layer (5) matches the mean free path of gas molecules under the set gas pressure.

4. The ring-gate plasma transistor according to claim 1, characterized in that: The substrates of the source electrode layer (1), the drain electrode layer (3) and the gate electrode layer (2) are composed of one or more of the following materials: silicon and glass.

5. The ring-gate plasma transistor according to claim 1, 2 or 3, characterized in that: The gas molecules in the closed chamber are one or more of the following low-pressure plasma gases: hydrogen, helium, nitrogen, oxygen, neon, argon and mercury vapor, and the gas pressure is maintained at 0.1-1000 Pa.

6. The ring-gate plasma transistor according to claim 1, 2 or 3, characterized in that: The source electrode of the source electrode layer (1) is a conductive sheet electrode, or a filament cathode processed on an insulating substrate, or a micro-chip electron emission source prepared by micro-nano processing.

7. The ring-gate plasma transistor according to claim 6, characterized in that: The filament cathode comprises a suspended metal wire and yttrium oxide coated on the surface of the metal wire, wherein the metal wire is composed of one or more of the following materials: iridium, platinum, tungsten, molybdenum, chromium and gold.

8. The ring-gate plasma transistor according to claim 1, 2 or 3, characterized in that: A gas supplement is also included for maintaining the gas pressure in the closed chamber.

9. The ring-gate plasma transistor according to claim 1, 2 or 3, characterized in that: It also includes a base for providing electrical connections for applying and regulating voltage to the source electrode layer (1), the gate electrode layer (2) and the drain electrode layer (3).

10. A method for manufacturing a ring-gate plasma transistor, characterized in that: The steps include: providing a first mother layer, a second mother layer, a third mother layer, a fourth mother layer, and a fifth mother layer; The first mother layer to the fifth mother layer are bonded by an anodic bonding process; wherein the first mother layer comprises N source electrode layers (1) arranged in parallel with a period, the second mother layer comprises N first insulating layers (4) with the same period as the first mother layer, the third mother layer comprises N gate electrode layers (2) with the same period as the first mother layer, the fourth mother layer comprises N second insulating layers (5) with the same period as the first mother layer, and the fifth mother layer comprises N drain electrode layers (3) with the same period as the first mother layer, N≥1; when the first mother layer to the fifth mother layer are bonded, the The gate electrode of the gate electrode layer (2) is provided with a plurality of through holes (20), the first insulating layer (4) and the second insulating layer (5) are hollow structures, the hollow structure of the first insulating layer (4) is connected to the hollow structure of the second insulating layer (5) through the through holes (20), thereby forming a closed chamber between the source electrode layer (1) and the drain electrode layer (3), and the source electrode of the source electrode layer (1), the gate electrode of the gate electrode layer (2) and the drain electrode of the drain electrode layer (3) are exposed in the closed chamber; The bonded structure is cut to obtain a plurality of on-chip ring-gate plasma transistors.

11. An electronic device, characterized in that: The electronic device comprises the ring-gate plasma transistor according to any one of claims 1 to 9.

12. An electronic device, characterized in that: Comprising the electronic device as claimed in claim 11.

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