An integrated vacuum electron tube device structure and a preparation method thereof

Abstract

The present invention discloses an integrated vacuum electron tube device structure and a preparation method thereof. The device structure includes a substrate, a cathode, a first insulating layer, a first grid, a second insulating layer, a second grid, a third insulating layer, and an anode; the cathode is perpendicular to the surface of the substrate; the substrate, the first insulating layer, the first grid, the second insulating layer, the second grid, the third insulating layer, and the anode are stacked without gaps from bottom to top; the first grid is an electrode with crater-shaped micropores, the second grid is an electrode with crater-shaped micropores or a tiled electrode with micropores, the height difference between the top of the second grid and the top of the first grid is 200 nm to 1000 nm, and the pore diameter of the micropores of the second grid is larger than the pore diameter of the micropores of the first grid; the cathode is located at the center of the micropores of the first grid and the second grid; the potential of the second grid is set not lower than the potential of the first grid.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-nano electronic devices, and more specifically, relates to an integrated vacuum electron tube device structure and a preparation method thereof. Background Art

[0002] An integrated vacuum electron tube is a type of field effect device that uses a micro-nano vacuum channel as a carrier transmission "medium", and has the characteristics of fast response speed, high working frequency, low device power consumption, concentrated electron energy, wide working temperature range, and strong anti-radiation interference ability, and has broad application prospects in the fields of aerospace, national defense, high-speed data processing, and high-frequency communication. The integrated vacuum electron tube device includes an electron emitter, also known as a cathode, an electron extraction grid, and an electron collector (also known as an anode). At present, according to the different relative positions of the above three types of electrodes, the integrated vacuum electron tube device structure mainly includes three types: planar back-gate type, planar side-gate type, and vertical ring-gate type. Among them, the vertical ring-gate type structure effectively enhances the gate's ability to control carriers in the vacuum channel by constructing a surrounding gate; and effectively improves the device integration density by vertically integrating the electron extraction grid and the electron collection anode. Therefore, the vertical ring-gate type structure has more application potential. However, the integrated vacuum electron tube with a vertical ring-gate structure still has the problem that the output characteristics are difficult to saturate. To solve the problem of unsaturated output characteristics, the existing technical solutions generally increase the relative height between the electron extraction grid and the top of the cathode, making the electron extraction grid higher than the top of the cathode to shield the influence of the anode electric field on the cathode surface potential, so as to obtain saturated output characteristics. However, the electron extraction grid higher than the top of the cathode is more likely to capture electrons emitted from the cathode, with a high capture rate, resulting in a large gate leakage current, which restricts the reduction of device power consumption and the improvement of power. Summary of the Invention

[0003] Aiming at the problem that the existing integrated vacuum electron tube devices are difficult to have both strong gate control ability, low gate leakage current, and saturated output characteristics, the present invention provides an integrated vacuum electron tube device structure. The provided device structure effectively improves the gate control ability through vertical integration of a double-ring gate structure; the second gate can effectively shield the influence of the anode on the cathode surface electric field to obtain saturated output characteristics; the use of the double-ring gate structure can effectively reduce the electron capture rate of the first gate and reduce the gate leakage current.

[0004] The second object of the present invention is to provide a preparation method for the integrated vacuum electron tube device structure.

[0005] The above objects of the present invention are achieved by the following technical solutions:

[0006] An integrated vacuum electron tube device structure is provided, which includes a substrate, a cathode, a first insulating layer, a first gate, a second insulating layer, a second gate, a third insulating layer and an anode; the cathode is perpendicular to the surface of the substrate; the substrate, the first insulating layer, the first gate, the second insulating layer, the second gate, the third insulating layer and the anode are stacked without gaps in sequence from bottom to top; the first gate is an electrode with crater-shaped micropores, the second gate is an electrode with crater-shaped micropores or a flat electrode with micropores, the height difference between the top of the second gate and the top of the first gate is 200 nm to 1000 nm, and the pore diameter of the micropores of the second gate is larger than that of the first gate; the cathode is located at the center of the first gate and the second gate, and the potential of the second gate is not lower than that of the first gate.

[0007] When the device structure in this solution works, the cathode is set to a low potential, the first gate is set to a high potential, the second gate is set to a potential not lower than that of the first gate to induce electron emission. The anode is set to a potential higher than that of the cathode to collect the electrons emitted from the cathode. Since the micropores of the first gate are closer to the top of the cathode than those of the second gate, the influence of the potential of the first gate on the surface electric field strength is greater. Also, because the cathode field emission current has an exponential relationship with the surface electric field strength, the electron extraction function is mainly realized by the first gate. The potential of the second gate is equal to or higher than that of the first gate, and the top of the second gate is higher than the top of the first gate. Therefore, the second gate can effectively broaden the potential region of the first gate and play a role in shielding the anode electric field, thereby weakening the influence of the anode electric field on the cathode surface electric field and ensuring that the cathode emission is controlled by the gate and a saturated output characteristic can be obtained. On the other hand, the second gate is higher than the first gate, and the pore diameter of the micropores of the second gate is larger than that of the first gate. It is difficult for the second gate to capture the electrons emitted from the cathode. Therefore, the gate leakage current of the device structure of the present invention mainly depends on the capture rate of the electrons emitted from the cathode by the first gate. However, the first gate has a small height difference from the top of the cathode, which can effectively reduce the capture rate of the electrons emitted from the cathode by the first gate and reduce the gate leakage current.

[0008] The integrated vacuum electron tube device structure provided by the present invention effectively improves the gate control ability through a vertically integrated double-ring gate structure; the second gate can effectively shield the influence of the anode on the cathode surface electric field and obtain a saturated output characteristic; the use of the double-ring gate structure can effectively reduce the electron capture rate of the first gate and reduce the gate leakage current.

[0009] Preferably, the potential of the second gate is higher than that of the first gate by within 5%.

[0010] Preferably, the anode is a flat micropore electrode or a flat plate electrode with a pore diameter of 3 to 10 μm.

[0011] Preferably, the height difference between the top of the cathode and the first gate is -100 to 100 nm.

[0012] Preferably, the height difference between the anode and the top of the second gate is 200 nm to 2000 nm.

[0013] Preferably, the first gate, the second gate, and the anode are selected from one or more of chromium, molybdenum, copper, gold, silver, aluminum, doped amorphous silicon, and indium tin oxide; the first insulating layer, the second insulating layer, and the third insulating layer are selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide.

[0014] Preferably, the cathode is a vertical micro-nano structure.

[0015] Preferably, the vertical micro-nano structure is a micro-nano cone structure, a micro-nano wire structure, a micro-nano needle structure, or a micro-nano pyramid structure.

[0016] Preferably, the material of the vertical micro-nano structure is selected from one or more of silicon, diamond, molybdenum, chromium, nickel, lanthanum hexaboride, silicon carbide, zinc oxide, titanium oxide, copper oxide, and tungsten oxide.

[0017] The present invention also provides a method for manufacturing an integrated vacuum electron tube device, including the following steps:

[0018] S1: Prepare a first insulating layer on the cathode and the substrate;

[0019] S2: Deposit a first gate on the first insulating layer obtained in S1;

[0020] S3: Spin-coat a photoresist and define a photoresist pattern;

[0021] S4: Etch and thin the photoresist until the raised first gate is exposed, and remove the first gate not covered by the photoresist;

[0022] S5: Deposit a second insulating layer and a second gate on the structure obtained in S4 in sequence;

[0023] S6: Repeat S3, etch and thin the photoresist until the raised second gate is exposed, and remove the second gate not covered by the photoresist;

[0024] S7: Deposit a third insulating layer and an anode on the structure obtained in S6 in sequence;

[0025] S8: Repeat S3, etch and thin the photoresist until the anode is exposed, and remove the anode 8 not covered by the photoresist;

[0026] S9: Etch the first insulating layer, the second insulating layer, and the third insulating layer until the top of the cathode is exposed.

[0027] Preferably, the following steps are further included:

[0028] S10: Transfer a conductive material on the structure obtained in S9 to cover the anode holes or evaporate a metal material to close the anode holes.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention discloses an integrated vacuum electron tube device, and the device structure includes a substrate, a cathode, a first insulating layer, a first gate, a second insulating layer, a second gate, a third insulating layer, and an anode; the cathode is perpendicular to the surface of the substrate; the substrate, the first insulating layer, the first gate, the second insulating layer, the second gate, the third insulating layer, and the anode are stacked without gaps from bottom to top in sequence; the first gate is an electrode with crater-shaped micropores, the second gate is an electrode with crater-shaped micropores or a flat electrode with micropores, the height difference between the top of the second gate and the top of the first gate is 200 nm to 1000 nm, and the pore diameter of the micropores of the second gate is larger than the pore diameter of the micropores of the first gate; the cathode is located at the center of the micropores of the first gate and the second gate; when the device structure works, the potential of the second gate is set to be equal to the potential of the first gate or 5% higher than the potential of the first gate at most.

[0031] The integrated vacuum electron tube device structure provided by the present invention effectively improves the gate control ability through a vertically integrated double-ring gate structure; the second gate can effectively shield the influence of the anode on the electric field on the cathode surface and obtain a saturated output characteristic; the use of the double-ring gate structure can effectively reduce the electron capture rate of the first gate and reduce the gate leakage current. The vertically integrated double-ring gate integrated vacuum electron tube device structure of the present invention has practical and wide application value in the field of micro-nano vacuum information electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic structural diagram of the integrated vacuum electron tube device structure of Embodiment 1 of the present invention;

[0033] Figure 2 is a curve graph of the output characteristics obtained by numerical simulation calculation based on the finite element method, the electrostatic field theory, and the Fowler-Nordheim theory for the integrated vacuum electron tube device structure of Embodiment 1 of the present invention;

[0034] Figure 3 is a curve graph of the transfer characteristics obtained by numerical simulation calculation based on the finite element method, the electrostatic field theory, and the Fowler-Nordheim theory for the integrated vacuum electron tube device structures of Embodiment 1, Comparative Example 2, and Comparative Example 3 of the present invention;

[0035] Figure 4 is a curve graph of the output characteristics obtained by numerical simulation calculation based on the finite element method, the electrostatic field theory, and the Fowler-Nordheim theory for the integrated vacuum electron tube device structure of Comparative Example 1 of the present invention;

[0036] Figure 5 is a schematic structural diagram of the integrated vacuum electron tube device structure of Embodiment 6 of the present invention;

[0037] Figure 6 It is a schematic structural diagram of the integrated vacuum electron tube device structure in Embodiment 7 of the present invention. Specific embodiments

[0038] The present invention will be further described below in conjunction with specific embodiments.

[0039] In the drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only for illustrative purposes and cannot be construed as a limitation of this patent.

[0040] In addition, terms such as "first" and "second" are only used for descriptive purposes, mainly to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components, and cannot be construed as indicating or implying relative importance.

[0041] The raw materials in the embodiments can all be obtained commercially;

[0042] Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in the technical field of the present invention.

[0043] The technical solution of the present invention will be further specifically described below through specific embodiments and in conjunction with the drawings:

[0044] Embodiment 1:

[0045] As Figures 1 to 3Shown is an embodiment of an integrated vacuum electron tube device structure, including a substrate 1, a cathode 2, a first insulating layer 3, a first gate 4, a second insulating layer 5, a second gate 6, a third insulating layer 7, and an anode 8; the cathode 2 is perpendicular to the surface of the substrate 1; the substrate 1, the first insulating layer 3, the first gate 4, the second insulating layer 5, the second gate 6, the third insulating layer 7, and the anode 8 are stacked without gaps from bottom to top in sequence; the first gate 4 and the second gate 6 are electrodes with crater-shaped micropores, the top of the cathode 2 is flush with the first gate 4, the height difference between the top of the second gate 6 and the top of the first gate 4 is 200 nm, and the pore diameter of the micropores of the second gate 6 is larger than that of the first gate 4; the anode 8 is a tiled electrode with micropores, the height difference between the anode 8 and the top of the second gate 6 is 200 nm, and the cathode 2 is located at the center of the first gate 4 and the second gate 6; when the integrated vacuum electron tube device structure works, the second gate 6 is short-circuited with the first gate 4.

[0046] Among them, the pore diameter of the micropores of the second gate 6 in this embodiment is 1 μm, and the pore diameter of the micropores of the first gate 4 is 450 nm. Of course, this is only a preferred implementation manner and should not be construed as a limitation to this solution.

[0047] In addition, the pore diameter of the micropores on the anode 8 in this solution is 3.2 μm. Of course, this is only a reference implementation manner and should not be construed as a limitation to this solution. In the specific implementation process, the optional range of the pore diameter of the micropores of the anode 8 is 3 - 10 μm.

[0048] The cathode 2 in this embodiment is a micro-nano silicon cone structure, the material of the substrate 1 is silicon, the first insulating layer 3, the second insulating layer 5, and the third insulating layer 7 are silicon dioxide thin film structures, and the first gate 4, the second gate 6, and the anode 8 are chromium metal thin film structures. It should be noted that the materials of the cathode 2, the first insulating layer 3, the second insulating layer 5, the third insulating layer 7, the first gate 4, the second gate 6, and the anode 8 in this embodiment are all reference implementation manners and should not be construed as a limitation to this solution.

[0049] The above integrated vacuum electron tube device structure is prepared by the following method:

[0050] S1: On the cathode 2 and the substrate 1, silicon dioxide with a thickness of 200 - 1000 nm is deposited on its surface by using a chemical vapor deposition system as the first insulating layer 3;

[0051] S2: On the basis of S1, a chromium electrode layer with a thickness of 200 - 300 nm is deposited on its surface by using magnetron sputtering as the first gate 4;

[0052] S3: Spin-coat photoresist; use an optical lithography system to expose the photoresist, and develop the exposed sample, and the diameter or width of the obtained pattern is 50 - 200 μm;

[0053] S4: Use oxygen plasma etching to thin the photoresist to 700 - 1000 nm until the top of the first gate 4 is exposed; use a mixed solution of perchloric acid, ammonium cerium nitrate, and water to etch the exposed first gate 4, and use acetone and ethanol to remove the surface photoresist;

[0054] S5: Deposit a second insulating layer 5 with a thickness of 200 - 300 nm and a second gate 6 with a thickness of 200 - 300 nm successively on the structure described in S4;

[0055] S6: Repeat S3, use oxygen plasma etching to thin the photoresist to 500 - 1000 nm until the second gate 6 is exposed; use a mixed solution of perchloric acid, ammonium cerium nitrate, and water to etch the second gate 6, and use acetone and ethanol to remove the surface photoresist;

[0056] S7: Deposit a third insulating layer 7 with a thickness of 600 nm - 2000 nm and an anode 8 with a thickness of 200 - 300 nm successively on the structure described in S6;

[0057] S8: Repeat S3, use oxygen plasma dry etching to thin the photoresist to 100 - 300 nm until the anode 8 is exposed; use a mixed solution of perchloric acid, ammonium cerium nitrate, and water to etch the anode 8, and use acetone and ethanol to remove the surface photoresist;

[0058] S9: Use plasma dry etching to etch the first, second, and third insulating layers 7 until the remaining silicon dioxide has a thickness of 200 - 400 nm, and then use a mixed solution of deionized water and hydrofluoric acid with a mass ratio of 9:1 to etch the silicon dioxide until the top of the cathode 22 is exposed;

[0059] S10: Transfer a conductive material to cover the holes in the anode 8 or evaporate a metal material on the structure obtained in S9 to close the holes in the anode 8, thereby obtaining the integrated vacuum electron tube device structure.

[0060] It should be noted that when the anode 8 is a flat electrode, the integrated vacuum electron device structure can be obtained until step S9, and step S10 is unnecessary.

[0061] The transfer output characteristics and gate capture rate of the integrated vacuum electron tube device structure in this embodiment are obtained by numerical simulation calculations based on the finite element method, electrostatic field theory, and Fowler-Nordheim theory. The calculation process is as follows: First, a two-dimensional rotationally symmetric numerical calculation model of the integrated vacuum electron tube is constructed according to the corresponding geometric parameters; Second, the potential parameters of each electrode of the device are set, and the spatial potential distribution and the electric field intensity on the tip surface of the cathode 2 are calculated; Third, the field emission current of the cathode 2 is calculated based on the electric field intensity on the tip surface of the cathode 2; Fourth, 1000 free electrons with an initial velocity of 0 are set at the top of the cathode 2, and the density distribution of the released electrons at the top of the cone is proportional to the magnitude of the field emission current at that place. By solving the motion trajectories of the particles under the corresponding spatial potential distribution, the number of particles collected by the anode 8 and the gate is statistically calculated, and the anode 8 current and the gate leakage current are calculated respectively. The calculation methods for the anode 8 current and the gate leakage current are: Anode 8 current = Cathode 2 field emission current × Number of charges collected by the anode 8 / Total number of charges, Gate leakage current = Cathode 2 field emission current × Number of charges collected by the gate / Total number of charges; Fifth, the anode 8 current of the device is calculated one by one under different gate voltages and anode 8 voltages to obtain the transfer and output characteristics of the integrated vacuum electron tube device.

[0062] According to the above numerical calculation method, the output characteristic curve of this embodiment is as Figure 2 shown, and the transfer characteristic curve is as Figure 3 shown. When the voltage of the first gate 4 Vg = 45V and the voltage of the anode 8 Va = 40V, the anode 8 current of this device is 60.3 μA, the cathode 2 current is 90.3 μA, and its gate capture rate is about 33.2%.

[0063] Therefore, it shows that the integrated vacuum electron tube device structure in this embodiment has the characteristics of low gate leakage current, saturated output characteristics, and low drive voltage.

[0064] Embodiment 2:

[0065] The difference between this embodiment and Embodiment 1 is only that the materials of the first gate 4, the second gate 6, and the anode 8 in this embodiment are one or more of molybdenum, copper, gold, silver, aluminum, and indium tin oxide.

[0066] Embodiment 3:

[0067] The difference between this embodiment and Embodiment 1 or Embodiment 2 is only that the first insulating layer 3, the second insulating layer 5, and the third insulating layer 7 in this embodiment are one or more of silicon nitride, aluminum oxide, and hafnium oxide.

[0068] Embodiment 4:

[0069] The difference between this embodiment and any one of Embodiments 1 to 3 is only that the cathode 2 in this embodiment is a micro-nano wire structure, a micro-nano needle structure, or a micro-nano pyramid structure.

[0070] Embodiment 5:

[0071] The difference between this Embodiment 1 and any one of Embodiments 1 to 4 is only that the cathode 2 material in this embodiment is one or more of diamond, molybdenum, chromium, nickel, lanthanum hexaboride, silicon carbide, zinc oxide, titanium oxide, copper oxide, and tungsten oxide.

[0072] Embodiment 6:

[0073] As Figure 5 shown, the difference between this embodiment and any one of Embodiments 1 to 5 is only that the second gate 6 in this embodiment is a flat microporous electrode.

[0074] Embodiment 7:

[0075] As Figure 6 shown, the difference between this embodiment and any one of Embodiments 1 to 5 is only that the anode 8 in this embodiment is a flat plate electrode.

[0076] Embodiment 8:

[0077] The difference between this embodiment and any one of Embodiments 1 to 7 is only that the height difference between the top of the second gate 6 and the top of the first gate 4 is 600 nm; the height difference between the anode 8 and the top of the second gate 6 is 600 nm; the height difference between the top of the cathode 2 and the first gate 4 is -100 nm.

[0078] Embodiment 9:

[0079] The difference between this embodiment and any one of Embodiments 1 to 8 is only that the height difference between the top of the second gate 6 and the top of the first gate 4 is 1000 nm; the height difference between the anode 8 and the top of the second gate 6 is 2000 nm; the height difference between the top of the cathode 2 and the first gate 4 is 100 nm.

[0080] Comparative Example 1:

[0081] In this comparative example, the second gate 6 and the first gate 4 are flush with each other, and the others are the same as any one of Embodiments 1 to 7. The output characteristic curve is shown in Figure 2 , and it can be seen that the anode 8 current increases as the anode 8 voltage increases, and the saturation characteristic no longer appears.

[0082] Comparative Example 2:

[0083] In this comparative example, the top of the cathode 2 is 400 nm lower than the first gate 4, and the others are the same as any one of Embodiments 1 to 7. The transfer characteristic curve is shown in Figure 3, when the voltage of the first gate 4, Vg = 45V and the voltage of the anode 8, Va = 40V, the anode current of the device is 25.6 μA and the cathode current is 50.5 μA. Its gate capture rate is about 49.3%. Therefore, the gate leakage current of the device in this comparative example is higher.

[0084] Comparative Example 3:

[0085] In this comparative example, the top of the cathode 2 is 400 mn higher than the first gate 4, and the others are the same as any one of Embodiments 1 to 7. The transfer characteristic curve is shown in Figure 3 , when the voltage of the first gate 4, Vg = 45V and the voltage of the anode 8, Va = 40V, the anode current of the device is 42.5 μA and the cathode current is 64.4 μA. Therefore, the device in this comparative example has a higher driving voltage.

[0086] The present invention is described with reference to the flowcharts or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process or block in the flowchart or block diagram, and the combination of processes or blocks in the flowchart or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0087] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0088] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. An integrated vacuum electron tube device structure, characterized in that, it includes a substrate (1), a cathode (2), a first insulating layer (3), a first grid (4), a second insulating layer (5), a second grid (6), a third insulating layer (7) and an anode (8); the cathode (2) is perpendicular to the surface of the substrate (1); the substrate (1), the first insulating layer (3), the first grid (4), the second insulating layer (5), the second grid (6), the third insulating layer (7) and the anode (8) are stacked without gaps in sequence from bottom to top; the first grid (4) is an electrode with crater-shaped micropores, the second grid (6) is an electrode with crater-shaped micropores or a tiled electrode with micropores, the height difference between the top of the second grid (6) and the top of the first grid (4) is 200 nm to 1000 nm, and the pore diameter of the second grid (6) is larger than the pore diameter of the first grid (4); the cathode (2) is located at the center of the first grid (4) and the second grid (6), and the potential of the second grid (6) is not lower than the potential of the first grid (4).

2. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the potential of the second grid (6) is 0 - 5% higher than the potential of the first grid (4).

3. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the anode (8) is a tiled micropore electrode or a flat plate electrode with a pore diameter of 3 - 10 μm.

4. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the height difference between the top of the cathode (2) and the first grid (4) is -100 to 100 nm.

5. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the height difference between the anode (8) and the top of the second grid (6) is 200 nm to 2000 nm.

6. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the first grid (4), the second grid (6), and the anode (8) are selected from one or more of chromium, molybdenum, copper, gold, silver, aluminum, doped amorphous silicon, and indium tin oxide; the first insulating layer (3), the second insulating layer (5), and the third insulating layer (7) are selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide.

7. The integrated vacuum electron tube device structure according to claim 1, characterized in that, the cathode (2) is an upright micro-nano structure, and the upright micro-nano structure is one of a micro-nano cone structure, a micro-nano wire structure, a micro-nano needle structure, and a micro-nano pyramid structure.

8. The integrated vacuum electron tube device structure according to claim 7, characterized in that, the material of the upright micro-nano structure is selected from one or more of silicon, diamond, molybdenum, chromium, nickel, lanthanum hexaboride, silicon carbide, zinc oxide, titanium oxide, copper oxide, and tungsten oxide.

9. A preparation method of the integrated vacuum electron tube device according to any one of claims 1 to 8, characterized in that, It includes the following steps: S1: Prepare a first insulating layer (3) on the cathode (2) and the substrate (1); S2: Deposit a first gate (4) on the first insulating layer (3) described in S1; S3: Spin-coat a photoresist and define a photoresist pattern; S4: Etch and thin the photoresist until the protruding first gate (4) is exposed, and remove the first gate (4) not covered by the photoresist; S5: Deposit a second insulating layer (5) and a second gate (6) successively on the structure obtained in S4; S6: Repeat S3, etch and thin the photoresist until the protruding second gate (6) is exposed, and remove the second gate (6) not covered by the photoresist; S7: Deposit a third insulating layer (7) and an anode (8) successively on the structure described in S6; S8: Repeat S3, etch and thin the photoresist until the anode (8) is exposed, and remove the anode (8) not covered by the photoresist; S9: Etch the first, second, and third insulating layers (7) until the top of the cathode (2) is exposed.

10. The method for manufacturing an integrated vacuum electron tube device according to claim 9, wherein, it further includes the following step: S10: Transfer a conductive material on the structure obtained in S9 to cover the holes of the anode (8) or evaporate a metal material to close the holes of the anode (8).

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