Semiconductor device, and manufacturing method for same

Abstract

A semiconductor device comprising: a substrate; a gallium nitride layer that is provided on a non-polar surface of the substrate and has a plurality of fin parts that are positioned apart from each other in a first direction parallel to the c-axis direction, and extend in a second direction orthogonal to the first direction; an electron supply layer provided on the Ga-surface of the fin parts; a gate electrode positioned between the source finger part and the drain finger part in the second direction, and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.

Description

Semiconductor device and manufacturing method thereof

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof.

[0002] In lateral GaN-HEMTs (High Electron Mobility Transistors), a GaN layer is generally grown on the c-plane of a substrate, so a two-dimensional structure is prevalent, and the degree of freedom in device structure is limited.

[0003] JP 2023-502631 A JP 2022-29220 A

[0004] The embodiments provide a semiconductor device capable of reducing the specific on-resistance RonA and improving the breakdown voltage, and a method for manufacturing the same.

[0005] According to an embodiment, a semiconductor device includes: a substrate; a gallium nitride layer provided on a non-polar surface of the substrate, the gallium nitride layer having a plurality of fin portions spaced apart from each other in a first direction parallel to a c-axis direction and extending in a second direction perpendicular to the first direction; an electron supply layer provided on a Ga surface of the fin portion; source finger portions extending in the first direction and in contact with the electron supply layer; drain finger portions extending in the first direction, spaced apart from the source finger portions in the second direction and in contact with the electron supply layer; a gate electrode located between the source finger portions and the drain finger portions in the second direction and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.

[0006] 1 is a schematic plan view of a semiconductor device according to an embodiment; FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1; FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1; (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment; (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment; (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment; (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment; (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment;

[0007] Hereinafter, embodiments will be described with reference to the drawings, in which the same components are denoted by the same reference numerals.

[0008] A semiconductor device 1 according to an embodiment will be described with reference to FIGS.

[0009] The semiconductor device 1 of the embodiment includes a substrate 10 and a gallium nitride layer 20. In this specification, a direction parallel to the c-axis direction perpendicular to the c-plane, which is the polar plane of the gallium nitride layer 20, is referred to as a first direction Y. A direction perpendicular to the first direction Y is referred to as a second direction X. A direction perpendicular to the first direction Y and the second direction X is referred to as a third direction Z. The third direction Z is a direction parallel to the m-axis direction or a-axis direction of the gallium nitride layer 20. The gallium nitride layer 20 is also referred to as a GaN layer 20. The gallium nitride layer (GaN layer) 20 contains nitrogen (N) and gallium (Ga) and may further contain additives other than nitrogen and gallium. The composition ratio of the additive in the gallium nitride layer 20 is lower than the composition ratio of nitrogen and the composition ratio of gallium.

[0010] The substrate 10 is, for example, a gallium nitride substrate. As shown in Figures 2 and 3, the GaN layer 20 is provided on a nonpolar plane (m-plane or a-plane) 10A of the substrate 10. The substrate 10 may be a sapphire substrate or a silicon substrate with a controlled off-angle.

[0011] 2, the GaN layer 20 has a plurality of fin portions 21 that are provided in a convex shape in a cross-sectional view. As shown in Fig. 1, the plurality of fin portions 21 are spaced apart from each other in the first direction Y and extend in the second direction X. Of the two side surfaces of the fin portion 21 that extend in the second direction X, the side surface facing the +c-axis direction is a Ga-face 21A that is terminated with Ga, and the side surface facing the -c-axis direction is an N-face 21B that is terminated with N.

[0012] As shown in FIG. 2 , the semiconductor device 1 includes an electron supply layer 30 provided on the Ga face 21A of the fin portion 21. The electron supply layer 30 extends in the second direction X along the fin portion 21. The band gap of the electron supply layer 30 is wider than the band gap of the GaN layer 20. The electron supply layer 30 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron supply layer 30 may also be an aluminum nitride (AlN) layer. Due to the piezoelectric polarization effect, two-dimensional electron gas 40 is distributed in the GaN layer 20 near the interface (Ga face 21A) with the electron supply layer 30. The two-dimensional electron gas 40 is distributed along the third direction Z and extends along the second direction X.

[0013] 1, the semiconductor device 1 includes a source electrode 100, a drain electrode 200, and a gate electrode 50. In the semiconductor device 1, the structure shown in FIG.

[0014] The source electrode 100 has a source pad portion 101 extending in the second direction X and a plurality of source finger portions 102 arranged and spaced apart from each other in the second direction X. The plurality of source finger portions 102 extend in the first direction Y from the source pad portion 101.

[0015] The drain electrode 200 has a drain pad portion 201 extending in the second direction X and a plurality of drain finger portions 202 arranged and spaced apart from each other in the second direction X. The drain finger portions 202 are located apart from the source finger portions 102 in the second direction X. The plurality of drain finger portions 202 extend in the first direction Y from the drain pad portion 201 toward the source pad portion 101.

[0016] The source finger portion 102 and the drain finger portion 202 are in contact with, for example, the upper end portion of the electron supply layer 30 and are electrically connected to the electron supply layer 30. The source finger portion 102 and the drain finger portion 202 may be in contact with the GaN layer 20. A current flows between the drain electrode 200 and the source electrode 100 through the two-dimensional electron gas 40.

[0017] The gate electrode 50 is located between the source finger portion 102 and the drain finger portion 202 adjacent to each other in the second direction X. The multiple gate electrodes 50 are arranged side by side and spaced apart from each other in the first direction Y. Each gate electrode 50 is located between adjacent fin portions 21 in the first direction Y. The multiple gate electrodes 50 are connected to a first gate wiring 51 extending in the first direction Y. The first gate wiring 51 is connected to a second gate wiring 52 extending in the second direction X. A gate voltage is applied to the gate electrode 50 via the second gate wiring 52 and the first gate wiring 51. The multiple first gate wirings 51 extend from the second gate wiring 52 in the first direction Y. The multiple first gate wirings 51 are connected to the multiple gate electrodes 50 arranged side by side in the first direction Y, respectively. One source finger portion 102 is located between the gate electrodes 50 adjacent to each other in the second direction X and between the first gate wirings 51 adjacent to each other in the second direction X. The distance in the second direction X between the drain finger portion 202 and the gate electrode 50 (drift length) is longer than the distance in the second direction X between the source finger portion 102 and the gate electrode 50. This improves the breakdown voltage.

[0018] 2, the semiconductor device 1 further includes a first insulating film 61 provided between the gate electrode 50 and the electron supply layer 30. The gate electrode 50 faces the electron supply layer 30 in the first direction Y via the first insulating film 61.

[0019] According to this embodiment, a two-dimensional electron gas 40 can be formed in the multiple fin portions 21 provided on the gallium nitride layer 20, distributing in the height direction of the fin portions 21 (third direction Z), thereby reducing the specific on-resistance RonA. The specific on-resistance RonA represents the product of the on-resistance Ron and the effective area A related to current conduction.

[0020] RonA decreases as the aspect ratio (ratio of height to width) of the fin portion 21 increases and as the pitch of the multiple fin portions 21 decreases. Therefore, if the width of the fin portion 21 in the first direction Y is A, the distance (or pitch) between adjacent fin portions 21 in the first direction Y is B, and the height of the fin portion 21 in the third direction Z is C, it is preferable that C > A + B. For example, A and B are approximately 100 nm, and C can be greater than A + B and equal to or less than 1 μm.

[0021] As a comparative example, a structure can be considered in which a gate electrode is provided facing the side surface of the fin portion, a source electrode is provided at the bottom of the recess between adjacent fin portions, and a drain electrode is provided on the top surface of the fin portion. According to this comparative example, in order to increase the distance between the gate electrode and the drain finger portion, it is necessary to increase the height of the fin portion. According to this embodiment, the distance (drift length) between the gate electrode 50 and the drain finger portion 202 can be increased as shown in FIG. 1 , regardless of the height of the fin portion 21. This improves the breakdown voltage.

[0022] 2 , the semiconductor device 1 may further include a p-type layer 70 provided on the N-face 21B of the fin portion 21. The p-type layer 70 is, for example, a p-type GaN layer containing magnesium (Mg). The p-type layer 70 is in contact with the gate electrode 50, for example. Alternatively, an insulating film may be provided between the p-type layer 70 and the gate electrode 50, and the p-type layer 70 may not be in contact with the gate electrode 50.

[0023] The potential of the gate electrode 50 can be applied to the fin portion 21 from the N-face 21B side via the p-type layer 70. This back-gate effect makes it possible to control the concentration of the two-dimensional electron gas 40. This makes it possible to control the threshold voltage and also enables normally-off operation.

[0024] The p-type layer 70 may be supplied with any potential, not limited to the gate potential, by an independent electrode. Also, the p-type layer 70 may be supplied with a source potential (for example, ground potential).

[0025] The semiconductor device 1 may further include a second insulating film 62. The second insulating film 62 is provided between the lower end of the electron supply layer 30 and the GaN layer 20, between the lower end of the gate electrode 50 and the GaN layer 20, between the lower end of the p-type layer 70 and the GaN layer 20, and between the lower end of the first insulating film 61 and the GaN layer 20. The second insulating film 62 is also provided on the upper surface of the fin portion 21.

[0026] The semiconductor device 1 may further include a third insulating film 63. The third insulating film 63 covers the second insulating film 62 provided on the upper surface of the fin portion 21, the upper end of the electron supply layer 30, the upper end of the gate electrode 50, the upper end of the p-type layer 70, and the upper end of the first insulating film 61.

[0027] The source finger portion 102 and the drain finger portion 202 may be in contact with the upper end portion of the electron supply layer 30 through, for example, openings formed in the third insulating film 63. In addition, the source finger portion 102 and the drain finger portion 202 may be in contact with the upper surface of the fin portion 21 through, for example, openings formed in the third insulating film 63 and the second insulating film 62.

[0028] As shown in FIGS. 1 and 3 , the semiconductor device 1 may further include a field plate electrode 80. The field plate electrode 80 is located between the gate electrode 50 and the drain finger portion 202 in the second direction X, and between adjacent fin portions 21 in the first direction Y. The field plate electrodes 80 are arranged spaced apart from one another in the first direction Y. The field plate electrodes 80 are connected to a first wiring 81 extending in the first direction Y. The first wiring 81 is electrically connected to the source finger portion 102 via a second wiring 82 extending in the second direction X. A source potential is applied to the field plate electrode 80 via the second wiring 82 and the first wiring 81. The source potential is, for example, ground potential. This reduces the electric field applied to the GaN layer 20 between the drain finger portion 202 and the gate electrode 50, thereby improving the breakdown voltage.

[0029] Hereinafter, the method for manufacturing the semiconductor device according to the embodiment will be described with reference to FIGS.

[0030] 4A, the method for manufacturing a semiconductor device according to the embodiment includes a step of forming a gallium nitride layer (GaN layer) 20 on the nonpolar surface 10A of the substrate 10. For example, the GaN layer 20 is grown on the m-plane or a-plane of the gallium nitride substrate by MOCVD (metal organic chemical vapor deposition).

[0031] The method for manufacturing a semiconductor device according to the embodiment includes a step of forming a plurality of fin portions 21 and recesses 22 located between the plurality of fin portions 21 in the GaN layer 20, as shown in FIG. 5B. For example, as shown in FIG. 4B, a mask 91 is formed on the upper surface of the GaN layer 20. For example, a silicon oxide film can be used as the mask 91. With the mask 91 formed, GaN is grown by MOCVD on the upper surface of the GaN layer 20 exposed through the mask 91 (FIG. 5A). Thereafter, the mask 91 is removed by, for example, wet etching.

[0032] 5(b), the multiple fin portions 21 are spaced apart from one another in a first direction Y that is parallel to the c-axis direction. The recesses 22 are located between adjacent fin portions 21 in the first direction Y. The multiple fin portions 21 and the multiple recesses 22 are arranged alternately in the first direction Y. The fin portions 21 and the recesses 22 extend in the second direction X.

[0033] 6A, an insulating film 60 is buried in the recess 22. The insulating film 60 also covers the upper surface of the fin portion 21. As the insulating film 60, for example, a silicon nitride film can be formed by plasma CVD (Chemical Vapor Deposition).

[0034] When manufacturing a semiconductor device having a p-type layer 70, a first opening 60a is formed in the insulating film 60 as shown in FIG. 6B. The first opening 60a includes a portion of the recess 22 adjacent to the N-face 21B of the fin portion 21. The N-face 21B of the fin portion 21 is exposed in the first opening 60a. The first opening 60a can be formed by, for example, reactive ion etching (RIE).

[0035] 7A, after forming a second mask 92 on the upper surface of the insulating film 60, a p-type layer (e.g., a p-type GaN layer) 70 is grown by MOCVD from the N-face 21B exposed in the first opening 60a. The p-type layer 70 is formed in the first opening 60a. Alternatively, after growing a GaN layer from the N-face 21B, p-type impurities (e.g., Mg) may be ion-implanted into the GaN layer and activated by heat treatment to form the p-type layer 70. For example, a silicon oxide film may be used as the second mask 92.

[0036] After the p-type layer 70 is formed, the second mask 92 is removed and / or the upper surfaces of the p-type layer 70 and the insulating film 60 are planarized by CMP (Chemical Mechanical Polishing) (FIG. 7B).

[0037] Thereafter, the method for manufacturing a semiconductor device according to the embodiment includes a step of forming an electron supply layer 30 on the Ga face 21A of the fin portion 21.

[0038] 8A, a second opening 60b is formed in the insulating film 60 by, for example, RIE. The second opening 60b includes a part of the recess 22 adjacent to the Ga face 21A of the fin portion 21. The Ga face 21A of the fin portion 21 is exposed in the second opening 60b. At this time, the insulating film 60 remaining on the bottom surface of the recess 22 and the upper surface of the fin portion 21 becomes the second insulating film 62 described above.

[0039] As shown in FIG. 8B , a third mask 93 is formed in the second opening 60b. The third mask 93 may be, for example, a silicon oxide film. The Ga surface 21A is exposed in the second opening 60b without being covered by the third mask 93. With the third mask 93 formed, an electron supply layer 30 is grown on the exposed Ga surface 21A by, for example, MOCVD or ALD (Atomic Layer Deposition). The electron supply layer 30 may be, for example, an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer. Due to the piezoelectric polarization effect, two-dimensional electron gas 40 is distributed in the GaN layer 20 near the interface (Ga surface 21A) with the electron supply layer 30.

[0040] After forming the electron supply layer 30, the third mask 93 is removed and / or the upper surfaces of the second insulating film 62, the p-type layer 70, and the electron supply layer 30 are planarized by CMP (FIG. 9A).

[0041] Thereafter, as shown in FIG. 9B, the method for manufacturing the semiconductor device of the embodiment includes a step of forming a gate electrode 50 in the second opening 60b so as to face the electron supply layer 30 with the first insulating film 61 interposed therebetween.

[0042] First, a first insulating film 61 is formed on the surface opposite to the surface in contact with the Ga face 21A of the electron supply layer 30. As the first insulating film 61, for example, a silicon nitride film can be formed by CVD.

[0043] After forming the first insulating film 61, the gate electrode 50 is formed in the second opening 60b so as to contact the p-type layer 70 and the first insulating film 61. For example, a conductive film containing at least one selected from the group consisting of TiN, TiW, and polycrystalline silicon is formed as the gate electrode 50. The TiN film and the TiW film can be formed by, for example, a sputtering method. The polycrystalline silicon film can be formed by, for example, a CVD method. After forming the conductive film, the conductive film formed on the upper surfaces of the second insulating film 62, the p-type layer 70, the first insulating film 61, and the electron supply layer 30 is removed by, for example, a CMP (Chemical Mechanical Polishing) method.

[0044] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0045] DESCRIPTION OF SYMBOLS 1...Semiconductor device, 10...Substrate, 10A...Nonpolar surface, 20...Gallium nitride layer, 21...Fin portion, 21A...Ga surface, 21B...N surface, 22...Recess, 30...Electron supply layer, 40...Two-dimensional electron gas, 50...Gate electrode, 51...First gate wiring, 52...Second gate wiring, 70...P-type layer, 80...Field plate electrode, 100...Source electrode, 101...Source pad portion, 102...Source finger portion, 200...Drain electrode, 201...Drain pad portion, 202...Drain finger portion

Claims

1. A semiconductor device comprising: a substrate; a gallium nitride layer provided on a non-polar surface of the substrate, the gallium nitride layer having a plurality of fin portions spaced apart from each other in a first direction parallel to a c-axis direction and extending in a second direction perpendicular to the first direction; an electron supply layer provided on a Ga surface of the fin portion; a source finger portion extending in the first direction and in contact with the electron supply layer; a drain finger portion extending in the first direction, spaced apart from the source finger portion in the second direction and in contact with the electron supply layer; a gate electrode located between the source finger portion and the drain finger portion in the second direction and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.

2. The semiconductor device according to claim 1, further comprising a p-type layer provided on the N-face of the fin portion.

3. The semiconductor device according to claim 2, wherein the p-type layer is in contact with the gate electrode.

4. The semiconductor device according to claim 2 or 3, wherein the p-type layer is a p-type GaN layer.

5. A semiconductor device according to any one of claims 1 to 3, further comprising a field plate electrode located between the gate electrode and the drain finger portion in the second direction and between adjacent fin portions in the first direction.

6. The semiconductor device according to claim 5, wherein said field plate electrode is electrically connected to said source finger portion.

7. A semiconductor device according to any one of claims 1 to 3, wherein, when the width of the fin portion in the first direction is A, the distance between adjacent fin portions in the first direction is B, and the height of the fin portion is C, C>A+B.

8. The semiconductor device according to any one of claims 1 to 3, wherein the electron supply layer is an aluminum gallium nitride layer or an aluminum nitride layer.

9. A semiconductor device according to any one of claims 1 to 3, wherein the distance in the second direction between the drain finger portion and the gate electrode is longer than the distance in the second direction between the source finger portion and the gate electrode.

10. A method for manufacturing a semiconductor device, comprising the steps of: forming a gallium nitride layer on a non-polar surface of a substrate; forming, in the gallium nitride layer, a plurality of fin portions spaced apart from each other in a first direction parallel to the c-axis direction and extending in a second direction perpendicular to the first direction, and recesses positioned between the plurality of fin portions; forming an electron supply layer on the Ga surface of the fin portion; and forming a gate electrode in the recess, facing the electron supply layer via a first insulating film.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a p-type layer on the N-face of the fin portion.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising the steps of: forming said p-type layer; forming said gate electrode in said recess so as to be in contact with said p-type layer and said first insulating film.

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