Insulated gate type semiconductor device

Abstract

Provided is an insulated gate type semiconductor device in which a mesa portion between trenches can be miniaturized. The insulated gate type semiconductor device comprises: a drift layer (1) of a first conduction type; base regions (3a-3d) of a second conduction type provided over the drift layer (1); contact regions (5a-5d) of the second conduction type provided in upper portions of the base regions (3a-3d); main electrode regions (4a-4h) of the first conduction type provided on the base regions (3a-3d) and the contact regions (5a-5d); gate electrodes (8a, 8c, 8e) filled in gate trenches (6a, 6c, 6e); dummy electrodes (8b, 8d) filled in dummy trenches (6b, 6d); and contact parts (9a-9d) filled in contact trenches (10a-10d). The contact trenches (10a-10d) are each located further toward the dummy trench (6b, 6d) side than a position equidistant from the gate trench (6a, 6c, 6e) and the dummy trench (6b, 6d).

Description

Insulated gate semiconductor device

[0001] The present disclosure relates to an insulated gate semiconductor device.

[0002] 17 of Patent Document 1 discloses a configuration in which a contact hole provided in an interlayer insulating film is shifted toward the dummy trench from the center of the gate trench and the dummy trench. Figures 4 and 5 of Patent Document 2 disclose a configuration in which a contact trench deeper than the emitter region is provided in a mesa portion.

[0003] 2 of Patent Document 3 discloses a configuration in which a contact trench is provided that is deeper than the emitter region and a base contact region is provided at the bottom of the contact trench. Fig. 16(c) of Patent Document 4 discloses a configuration in which an emitter electrode is formed on an insulating film and a contact region so as to contact a p-type base layer, an n-type emitter layer, and a conductor.

[0004] JP 2019-186261 A International Publication No. 2020 / 213254 JP 2014-60387 A JP 2001-16833 A

[0005] In conventional insulated gate semiconductor devices with a gate trench structure, contact trenches are formed in the center of the mesa, equidistant from adjacent trenches, to improve latch-up resistance. However, this requires increasing the distance between the contact trenches, making it difficult to miniaturize the mesa.

[0006] In view of the above problems, an object of the present disclosure is to provide an insulated gate semiconductor device that allows miniaturization of mesa portions between trenches.

[0007] One aspect of the present disclosure is an insulated gate semiconductor device comprising: a drift layer of a first conductivity type; a base region of a second conductivity type provided on the drift layer; a contact region of the second conductivity type provided above the base region and having a higher impurity concentration than the base region; a main electrode region of the first conductivity type provided on the base region and the contact region; a gate electrode embedded, via a first gate insulating film, in a gate trench provided in contact with the main electrode region and the base region; a dummy electrode embedded, via a second gate insulating film, in a dummy trench provided at a distance from the gate trench; and a contact portion embedded in the contact trench in contact with the main electrode region and the contact region, wherein the contact trench is located closer to the dummy trench than a position equidistant from the gate trench and the dummy trench.

[0008] According to the present disclosure, it is possible to provide an insulated gate semiconductor device that allows miniaturization of the mesa portion between trenches.

[0009] 1A is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to the first embodiment; FIG. 1B is a cross-sectional view enlarging a region A of FIG. 1A; FIG. 1C is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to the first embodiment; FIG. 1D is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to the first embodiment; FIG. 1E is a cross-sectional view illustrating a process for explaining an example of a method for manufacturing an insulated gate semiconductor device according to the first embodiment; FIG. 1F is a cross-sectional view illustrating a process for explaining an example of a method for manufacturing an insulated gate semiconductor device according to the first embodiment; FIG. 1G is a cross-sectional view illustrating a process for explaining an example of a method for manufacturing an insulated gate semiconductor device according to the first embodiment; FIG. 1H is a cross-sectional view illustrating a process for explaining an example of a method for manufacturing an insulated gate semiconductor device according to the first embodiment; 22 is a vertical cross-sectional view of an insulated gate semiconductor device according to a comparative example. FIG. 23 is a horizontal cross-sectional view of an insulated gate semiconductor device according to a comparative example. FIG. 24 is a graph showing the relationship between on-voltage and turn-off loss of the insulated gate semiconductor device according to the first embodiment. FIG. 25 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a second embodiment. FIG. 26 is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to the second embodiment. FIG. 27 is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to a third embodiment. FIG. 28 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a fourth embodiment. FIG. 29 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a fifth embodiment. FIG. 29 is an enlarged cross-sectional view of region A in FIG. 22. FIG. 29 is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to the fifth embodiment.Fig. 10 is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to a sixth embodiment; Fig. 11 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a seventh embodiment; Fig. 12 is a horizontal cross-sectional view of an example of an insulated gate semiconductor device according to an eighth embodiment; Fig. 13 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a ninth embodiment; and Fig. 14 is a vertical cross-sectional view of an example of an insulated gate semiconductor device according to a tenth embodiment.

[0010] Hereinafter, first to tenth embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] In the following description, a "first main electrode region" and a "second main electrode region" refer to main electrode regions of a semiconductor element into which a main current flows. The "first main electrode region" refers to a semiconductor region that becomes either an emitter region or a collector region in an insulated gate bipolar transistor (IGBT). The "first main electrode region" refers to a semiconductor region that becomes either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). The "second main electrode region" refers to a semiconductor region that becomes either an anode region or a cathode region in a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO). The "second main electrode region" refers to a region that becomes either an emitter region or a collector region, which does not become the first main electrode region, in an IGBT. The "second main electrode region" refers to a semiconductor region that becomes either a source region or a drain region, which does not become the first main electrode region, in an FET or an SIT. The "second main electrode region" refers to a region that becomes either an anode region or a cathode region, which does not become the first main electrode region, in an SI thyristor or a GTO. That is, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. Note that when the term "main electrode region" is simply used, it comprehensively means either the first main electrode region or the second main electrode region, whichever is appropriate from a technical and contextual perspective.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if it is rotated 180 degrees and observed, up and down are read as being reversed. Furthermore, "top surface" may be read as "front surface," and "bottom surface" may be read as "rear surface" or "bottom surface."

[0013] In the following description, an example will be given in which the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the "+" or "-" attached to "n" or "p" indicates a semiconductor region with a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the same "n" and "n" are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0014] First Embodiment <Structure of Semiconductor Device> An IGBT will be described as an example of a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device according to the first embodiment has a first conductivity type (n － The semiconductor device includes a n-type (n-type) drift layer 1. On the upper surface side of the drift layer 1, n-type accumulation layers 2a to 2d having a higher impurity concentration than the drift layer 1 are provided. The lower surfaces of the accumulation layers 2a to 2d are in contact with the upper surface of the drift layer 1. By providing the accumulation layers 2a to 2d, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced. Note that the accumulation layers 2a to 2d are not necessarily provided.

[0015] The upper surface of the accumulation layers 2a to 2d is provided with a second conductivity type (p － The base regions 3a to 3d are provided with a MOSFET (type) having a lower surface contacting the upper surface of the accumulation layers 2a to 2d. If the accumulation layers 2a to 2d are not provided, the lower surfaces of the base regions 3a to 3d are in contact with the upper surface of the drift layer 1.

[0016] A second conductivity type (p) dopant having a higher impurity concentration than the base regions 3a to 3d is provided in a part of the upper part of the base regions 3a to 3d. ＋ The base regions 3a to 3d and the contact regions 5a to 5d are selectively provided on the upper surface side thereof with n-type contact regions. ＋The first main electrode regions (emitter regions) 4 a to 4 d are provided on the semiconductor substrate 1. The lower surfaces of the emitter regions 4 a to 4 h are in contact with the upper surfaces of the base regions 3 a to 3 d and the contact regions 5 a to 5 d. The impurity concentrations of the emitter regions 4 a to 4 h are higher than the impurity concentrations of the drift layer 1 and the accumulation layers 2 a to 2 d.

[0017] A plurality of trenches 6a-6e are provided in parallel and spaced apart from one another in the depth direction, which is perpendicular to the upper surfaces of the emitter regions 4a-4h, from the upper surfaces of the emitter regions 4a-4h. The plurality of trenches 6a-6e have the same width and depth. The plurality of trenches 6a-6e penetrate the emitter regions 4a-4h, base regions 3a-3d, and accumulation layers 2a-2d to reach the drift layer 1. The side surfaces (sidewalls) of the plurality of trenches 6a-6e are in contact with the side surfaces of the emitter regions 4a-4h, base regions 3a-3d, and accumulation layers 2a-2d. The contact regions 5a-5d are spaced apart from the plurality of trenches 6a-6e.

[0018] A mesa portion is provided between adjacent trenches 6a to 6e. The mesa portion is a region sandwiched between adjacent trenches 6a to 6e and located above the deepest positions of the trenches 6a to 6e. The mesa portions between the multiple trenches 6a to 6e have the same width. The mesa portion includes an upper portion of the drift layer 1, accumulation layers 2a to 2d, base regions 3a to 3d, contact regions 5a to 5d, and emitter regions 4a to 4h.

[0019] The multiple trenches 6a to 6e include trenches 6a, 6c, and 6e that function as gates of the IGBT (hereinafter referred to as "gate trenches"), and trenches 6b and 6d that do not function as gates of the IGBT (hereinafter referred to as "dummy trenches"). The dummy trenches 6b and 6d have the function of reducing the capacitance between the gate and the collector. FIG. 1 illustrates an example in which the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are alternately arranged, but this is not limiting. For example, two or more gate trenches may be adjacent to each other, and two or more dummy trenches may be adjacent to each other. Furthermore, the number of gate trenches 6a, 6c, and 6e and the number of dummy trenches 6b and 6d are not particularly limited.

[0020] A gate insulating film 7 is provided so as to cover the bottom and side surfaces of the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d. The gate insulating film 7 is, for example, a silicon dioxide film (SiO ２ film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si ３ N ４ ) film, aluminum oxide (Al ２ O ３ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ２ O ３ ) film, hafnium oxide (HfO ２ ) film, zirconium oxide (ZrO ２ ) film, tantalum oxide (Ta ２ O ５ ) film, bismuth oxide (Bi ２ O ３ ) membranes or composite membranes in which a plurality of these membranes are laminated can be used.

[0021] Gate electrodes 8a, 8c, and 8e are buried inside the gate trenches 6a, 6c, and 6e with a gate insulating film 7 interposed therebetween. The gate insulating film 7 and the gate electrodes 8a, 8c, and 8e form insulated gate electrode structures (7, 8a), (7, 8c), and (7, 8e). The gate electrodes 8a, 8c, and 8e are electrically connected to a gate runner (not shown). Dummy electrodes 8b and 8d are buried inside the dummy trenches 6b and 6d with the gate insulating film 7 interposed therebetween. The dummy electrodes 8b and 8d are not connected to the gate runner (not shown) but are electrically connected to an emitter electrode 31 (described later). The gate electrodes 8a, 8c, and 8e and the dummy electrodes 8b and 8d can be made of a polysilicon film (doped polysilicon film) doped with a high impurity concentration of, for example, n-type impurities such as phosphorus (P) or p-type impurities such as boron (B).

[0022] An interlayer insulating film 20 is provided on the upper surfaces of the emitter regions 4a to 4h, the gate insulating film 7, the gate electrodes 8a, 8c, and 8e, and the dummy electrodes 8b and 8d. The interlayer insulating film 20 is, for example, a non-doped silicon oxide film (SiO ２film), silicon oxide film doped with phosphorus (PSG film), silicon oxide film doped with boron (BSG film), silicon oxide film doped with boron and phosphorus (BPSG film), silicon nitride film (Si ３ N ４ The insulating film may be a single layer such as a silicon oxide film (SiO 2 film), a high temperature oxide film (HTO film), or a laminated film of these.

[0023] Contact holes 20a to 20d penetrating the interlayer insulating film 20 are provided at positions on the mesa portion of the interlayer insulating film 20. Trenches (contact trenches) 10a to 10d are provided in the mesa portion so as to be continuous with the contact holes 20a to 20d. The contact trenches 10a to 10d are provided from the top surface of the mesa portion in a depth direction that is perpendicular to the top surface of the mesa portion. The upper portions of the side surfaces (sidewalls) of the contact trenches 10a to 10d are in contact with the emitter regions 4a to 4h. The lower surfaces (bottom surfaces) and lower portions of the side surfaces (sidewalls) of the contact trenches 10a to 10d are in contact with the contact regions 5a to 5d. Contact portions 9a to 9d are embedded in the contact trenches 10a to 10d and the contact holes 20a to 20d. By providing contact trenches 10a to 10d, contact can be made below emitter regions 4a to 4h, thereby reducing the effect of the potential created by the hole current on emitter regions 4a to 4h and improving latch-up resistance.

[0024] A surface electrode (emitter electrode) 31 is provided on the interlayer insulating film 20. The emitter electrode 31 is electrically connected to the emitter regions 4a to 4h and the contact regions 5a to 5d via contact portions 9a to 9d. The emitter electrode 31 can be made of metal such as aluminum (Al), an Al alloy, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu.

[0025] An n-type field stop (FS) layer 11 having a higher impurity concentration than the drift layer 1 is provided on the lower surface side of the drift layer 1. The upper surface of the FS layer 11 is in contact with the lower surface of the drift layer 1. The FS layer 11 prevents a depletion layer spreading from the lower surface sides of the base regions 3a to 3d from reaching a second main electrode region (collector region) 12, which will be described later.

[0026] The lower surface of the FS layer 11 is ＋ A collector region 12 is provided. The upper surface of the collector region 12 is in contact with the lower surface of the FS layer 11. The impurity concentration of the collector region 12 is higher than the impurity concentration of the base regions 3a to 3d.

[0027] The semiconductor region from the upper surface of the emitter regions 4a to 4h to the lower surface of the collector region 12 is made up of a semiconductor substrate. The semiconductor substrate is made up of, for example, a silicon (Si) substrate. The semiconductor substrate is not limited to a Si substrate, and may be made of, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ ), diamond (C) or aluminum nitride (AlN), or the like, may be a semiconductor substrate made of a semiconductor (wide bandgap semiconductor) having a wider bandgap than Si.

[0028] A back surface electrode (collector electrode) 32 is provided on the lower surface side of the collector region 12. The collector electrode 32 can be formed, for example, from a single layer film made of gold (Au) or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au).

[0029] FIG. 2 shows an enlarged view of the dashed-line region A surrounding the contact trench 10a in FIG. 1. As shown in FIG. 2, in the cross section where the emitter regions 4a and 4b appear, the contact trench 10a penetrates the emitter regions 4a and 4b and reaches the contact region 5a. The depth of the contact trench 10a is deeper than the depth of the emitter regions 4a and 4b. Because the depth of the contact trench 10a is deeper than the depth of the emitter regions 4a and 4b, the contact region 5a can be more easily expanded laterally, thereby improving the latch-up resistance. The depth of the contact trench 10a may be the same as the depth of the emitter regions 4a and 4b, or may be shallower than the depth of the emitter regions 4a and 4b.

[0030] The side surface of the contact trench 10a has a tapered shape (forward tapered shape) that narrows from the opening toward the bottom surface. The side surface of the contact trench 10a may be approximately perpendicular to the bottom surface of the contact trench 10a, or may have a tapered shape (inverse tapered shape) that widens from the opening toward the bottom surface. The bottom surface of the contact trench 10a is flat, but is not limited to this and may be a downwardly convex curved surface, etc.

[0031] A contact portion 9a is buried in the contact trench 10a and the contact hole 20a. The upper portion of the side surface of the contact portion 9a is in contact with the emitter regions 4a, 4b and the interlayer insulating film 20. The lower portion of the side surface and the lower surface of the contact portion 9a are in contact with the contact region 5a. Because the lower portion of the side surface and the lower surface of the contact portion 9a are in contact with the contact region 5a, it is easier to ensure latch-up resistance compared to a case where only the lower surface of the contact portion 9a is in contact with the contact region 5a. The contact portion 9a is in ohmic contact with the emitter regions 4a, 4b and the contact region 5a.

[0032] The contact portion 9a is composed of, for example, a barrier metal film and a contact plug. The barrier metal film may be, for example, a single layer film of titanium (Ti) or titanium nitride (TiN), or a laminated film of Ti and TiN. The contact plug may be made of a metal such as tungsten (W). A metal silicide layer may be formed between the contact portion 9a and the emitter regions 4a to 4h and the contact region 5a.

[0033] The contact portion 9a may be made of the same material as the emitter electrode 31, or may be formed integrally with the emitter electrode 31. The contact portion 9a may be made of a material different from the emitter material.

[0034] The contact portion 9a includes a buried portion 91 and a plug portion 92. The buried portion 91 and the plug portion 92 may be formed integrally with each other or may be formed separately. The buried portion 91 is a lower portion of the contact portion 9a that is buried in the contact trench 10a. The plug portion 92 is an upper portion of the contact portion 9a that is provided in the contact hole 20a.

[0035] On the gate electrode 8a side, in order to prevent an increase in the gate threshold voltage due to the contact region 5a approaching the gate electrode 8a, it is necessary to ensure a large distance d5 between the gate insulating film 7 in contact with the gate electrode 8a and the contact region 5a. On the other hand, on the dummy electrode 8b side, it is not necessary to ensure a distance d6 between the gate insulating film 7 in contact with the dummy electrode 8b and the contact region 5a, and the distance d6 may be 0. Therefore, in the semiconductor device according to the first embodiment, the positions of the contact trench 10a and the contact portion 9a are asymmetrical with respect to the center of the mesa portion, which is equidistant from the gate trench 6a and the dummy trench 6b, and are closer (shifted) to the dummy trench 6b than the center of the mesa portion.

[0036] The horizontal distance d1 from the end of the upper surface of the contact portion 9a on the gate electrode 8a side (left side) or the end of the opening of the contact hole 20a on the gate electrode 8a side (left side) to the gate insulating film 7 in contact with the side surface of the gate electrode 8a (in other words, the width of the overhang of the upper surface of the interlayer insulating film 20 on the gate electrode 8a side) is greater than the horizontal distance d2 from the end of the upper surface of the contact portion 9a on the dummy electrode 8b side (right side) or the end of the opening of the contact hole 20a on the dummy electrode 8b side (right side) to the gate insulating film 7 in contact with the side surface of the dummy electrode 8b (in other words, the width of the overhang of the upper surface of the interlayer insulating film 20 on the dummy electrode 8b side). For example, the distance d1 may be approximately 1.5 to 10 times the distance d2.

[0037] When the contact trench 10a has a forward tapered shape, the end of the upper surface of the contact portion 9a on the gate electrode 8a side is located closer to the gate electrode 8a than the side surface of the contact portion 9a on the gate electrode 8a side in the horizontal direction on the lower surface of the interlayer insulating film 20. A horizontal distance d1 from the end of the upper surface of the contact portion 9a on the gate electrode 8a side to the gate insulating film 7 in contact with the side surface of the gate electrode 8a is smaller than a horizontal distance d3 from the side surface of the contact portion 9a on the gate electrode 8a side at a position in the horizontal direction on the lower surface of the interlayer insulating film 20 or from the end of the upper surface of the emitter region 4a on the contact portion 9a side (right side) to the gate insulating film 7 in contact with the side surface of the gate electrode 8a (in other words, the protrusion width of the lower surface side of the interlayer insulating film 20 on the gate electrode 8a side).

[0038] The end of the upper surface of contact portion 9a facing the dummy electrode 8b is located closer to the dummy electrode 8b than the side surface of the upper surface of contact portion 9a facing the dummy electrode 8b in the horizontal direction on the lower surface of interlayer insulating film 20. A horizontal distance d2 from the end of the upper surface of contact portion 9a facing the dummy electrode 8b to the gate insulating film 7 in contact with the side surface of dummy electrode 8b is smaller than a horizontal distance d4 from the side surface of contact portion 9a facing the dummy electrode 8b at a position on the lower surface of interlayer insulating film 20 in the horizontal direction or from the end of the upper surface of emitter region 4b on the contact portion 9a side (left side) to the gate insulating film 7 in contact with the side surface of dummy electrode 8b (in other words, the protrusion width of the lower surface of interlayer insulating film 20 on the dummy electrode 8b side).

[0039] A horizontal distance d3 from the side surface of the contact portion 9a on the gate electrode 8a side of the lower surface of the interlayer insulating film 20 or the end portion of the upper surface of the emitter region 4a on the contact portion 9a side to the gate insulating film 7 in contact with the side surface of the gate electrode 8a is greater than a horizontal distance d4 from the side surface of the contact portion 9a on the dummy electrode 8b side of the lower surface of the interlayer insulating film 20 or the end portion of the upper surface of the emitter region 4b on the contact portion 9a side to the gate insulating film 7 in contact with the side surface of the dummy electrode 8b. For example, the distance d3 may be approximately 1.5 to 10 times the distance d4.

[0040] 1, the contact trench 10b and contact portion 9b between the dummy trench 6b and the gate trench 6c are located closer to the dummy trench 6b than a position equidistant from the dummy trench 6b and the gate trench 6c. The contact trench 10c and contact portion 9c between the gate trench 6c and the dummy trench 6d are located closer to the dummy trench 6d than a position equidistant from the gate trench 6c and the dummy trench 6d. The contact trench 10d and contact portion 9d between the dummy trench 6d and the gate trench 6e are located closer to the dummy trench 6d than a position equidistant from the dummy trench 6d and the gate trench 6e.

[0041] 3 shows a horizontal cross section passing through the upper surfaces of the emitter regions 4a to 4h, the upper surface of the gate insulating film 7, the upper surfaces of the gate trenches 6a, 6c, and 6e, the upper surfaces of the dummy trenches 6b and 6d, and the contact trenches 10a to 10d, as viewed from the B-B direction on the upper surface side of the semiconductor device according to the first embodiment shown in Fig. 1. The horizontal cross section as viewed from the A-A direction in Fig. 3 corresponds to Fig. 1.

[0042] 3, the gate trenches 6a, 6c, and 6e, the dummy trenches 6b and 6d, and the contact trenches 10a to 10d have a linear (striped) planar pattern extending parallel to one another in one direction (the vertical direction in FIG. 3). The emitter regions 4a to 4h have a planar pattern provided intermittently in one direction (the vertical direction in FIG. 3).

[0043] The emitter region 4a and the contact region 5a are in contact with one side surface (left side) of the contact trench 10a. The emitter region 4a and the contact region 5a are in contact with each other and are alternately and periodically arranged in one direction (the vertical direction in FIG. 3). The emitter region 4b and the contact region 5a are in contact with the other side surface (right side) of the contact trench 10a. The emitter region 4b and the contact region 5a are in contact with each other and are alternately and periodically arranged in one direction (the vertical direction in FIG. 3). Here, the one direction (the vertical direction in FIG. 3) refers to the direction in which the gate trenches 6a, 6c, and 6e, the dummy trenches 6b and 6d, and the contact trenches 10a to 10d extend parallel to each other. Note that the one side surface (left side) and the other side surface (right side) are perpendicular to the one direction (the vertical direction in FIG. 3).

[0044] The emitter region 4c and the contact region 5b are in contact with one side surface (left side) of the contact trench 10b. The emitter region 4c and the contact region 5b are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3). The emitter region 4d and the contact region 5b are in contact with the other side surface (right side) of the contact trench 10b. The emitter region 4d and the contact region 5b are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3).

[0045] The emitter region 4e and the contact region 5c are in contact with one side surface (left side) of the contact trench 10c. The emitter region 4e and the contact region 5c are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3). The emitter region 4f and the contact region 5c are in contact with the other side surface (right side) of the contact trench 10c. The emitter region 4f and the contact region 5c are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3).

[0046] The emitter region 4g and the contact region 5d are in contact with one side surface (left side) of the contact trench 10d. The emitter region 4g and the contact region 5d are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3). The emitter region 4h and the contact region 5d are in contact with the other side surface (right side) of the contact trench 10d. The emitter region 4h and the contact region 5d are in contact with each other and are provided alternately and periodically in one direction (the vertical direction in FIG. 3).

[0047] 4 is a vertical cross-sectional view taken along the line B-B in FIG. 3, taken at a position not passing through the emitter regions 4a-4h. As shown in FIG. 4, in the cross section where the emitter regions 4a-4h do not appear, the upper surfaces of the contact regions 5a-5d are in contact with the interlayer insulating film 20. Because the entire side surfaces and lower surfaces of the contact portions 9a-9d are in contact with the contact regions 5a-5d, it is easier to ensure latch-up resistance compared to when only the lower surfaces of the contact portions 9a-9d or only the lower surfaces and lower portions of the side surfaces of the contact portions 9a-9d are in contact with the contact regions 5a-5d.

[0048] During operation of the semiconductor device according to the first embodiment, when the emitter electrode 31 is at ground potential, a positive voltage is applied to the collector electrode 32, and a positive voltage equal to or greater than a threshold value is applied to the gate electrodes 8a, 8c, and 8e, inversion layers (channels) are formed on the side surfaces of the gate trenches 6a, 6c, and 6e in the base regions 3a to 3d, resulting in an ON state. In the ON state, current flows from the collector electrode 32 to the emitter electrode 31 via the collector region 12, the FS layer 11, the drift layer 1, the accumulation layers 2a to 2d, the inversion layers in the base regions 3a to 3d, and the emitter regions 4a, 4d, 4e, and 4h. Since the dummy trenches 6b and 6d are provided adjacent to the gate trenches 6a, 6c, and 6e, a portion of the gate-collector capacitance (feedback capacitance) is replaced with collector-emitter capacitance, thereby reducing the feedback capacitance and improving switching speed. On the other hand, when the voltage applied to the gate electrodes 8a, 8c, and 8e is less than the threshold voltage, no inversion layer is formed in the base regions 3a to 3d, resulting in an off state and no current flowing from the collector electrode 32 to the emitter electrode 31.

[0049] <Method of Manufacturing Semiconductor Device> Next, an example of a method of manufacturing a semiconductor device according to the first embodiment will be described with reference to Figures 5 to 14, which correspond to the cross sections of Figure 1. Note that the method of manufacturing a semiconductor device described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used as long as they fall within the scope of the spirit of the claims.

[0050] First, the first conductivity type (n － A semiconductor substrate made of a silicon (Si) wafer or the like (type) is prepared. This semiconductor substrate functions as drift layer 1. Next, a portion of the upper part of drift layer 1 is selectively removed by photolithography and dry etching. As a result, as shown in FIG. 5, a plurality of trenches 6a to 6e are formed in the upper part of drift layer 1. The plurality of trenches 6a to 6e includes gate trenches 6a, 6c, and 6e and dummy trenches 6b and 6d.

[0051] Next, a gate insulating film 7 is formed on the bottom and side surfaces of the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d by thermal oxidation, chemical vapor deposition (CVD), or the like. Next, a polysilicon film (doped polysilicon film) doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD or the like so as to fill the insides of the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d via the gate insulating film 7. Thereafter, the polysilicon film and gate insulating film 7 on the drift layer 1 are selectively removed by photolithography and dry etching. As a result, as shown in FIG. 6 , insulated gate electrode structures (7, 8a), (7, 8c), and (7, 8e) each consisting of the gate insulating film 7 and polysilicon gate electrodes 8a, 8c, and 8e are formed inside the gate trenches 6a, 6c, and 6e. Furthermore, the gate insulating film 7 and dummy electrodes 8b and 8d are formed inside the dummy trenches 6b and 6d.

[0052] Next, p －P-type impurities such as boron (B) are ion-implanted to form n-type base regions 3a-3d. Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the entire upper surface of the drift layer 1 to form n-type accumulation layers 2a-2d. Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an ion-implantation mask to implant n-type impurities. ＋ To form n-type emitter regions 4a-4h, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted. The photoresist film is then removed. Note that the order of the ion implantation to form accumulation layers 2a-2d, the ion implantation to form base regions 3a-3d, and the ion implantation to form emitter regions 4a-4h is not particularly limited, and the order may be reversed.

[0053] Next, the implanted impurity ions are activated by heat treatment, resulting in the formation of n-type accumulation layers 2a to 2d and p-type accumulation layers 2b to 2c on the upper part of the drift layer 1, as shown in FIG. － The base regions 3a to 3d and n ＋ 7. The emitter regions 4 are formed in the mold. The emitter regions 4 are formed intermittently in the depth direction of FIG.

[0054] Next, as shown in FIG. 8 , an interlayer insulating film 20 is formed on the upper surfaces of the gate insulating film 7, gate electrodes 8a, 8c, and 8e, dummy electrodes 8b and 8d, and emitter region 4 by CVD or the like. Next, a photoresist film is applied to the upper surface of the interlayer insulating film 20, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, portions of the interlayer insulating film 20 are selectively removed by dry etching. The photoresist film is then removed. As a result, as shown in FIG. 9 , contact holes 20a to 20d are opened in the interlayer insulating film 20, exposing portions of the upper surfaces of the emitter regions 4.

[0055] In this case, the contact holes 20a to 20d are opened so that the horizontal distance d1 from the end of the opening of the contact holes 20a to 20d on the gate electrode 8a, 8c, 8e side to the gate insulating film 7 on the gate electrode 8a, 8c, 8e side (the protruding width on the upper surface of the interlayer insulating film 20 on the gate electrode 8a, 8c, 8e side) is larger than the horizontal distance d2 from the end of the opening of the contact holes 20a to 20d on the dummy electrode 8b, 8d side to the gate insulating film 7 on the dummy electrode 8b, 8d side (in other words, the protruding width on the upper surface of the interlayer insulating film 20 on the dummy electrode 8b, 8d side).

[0056] Next, using the interlayer insulating film 20 as an etching mask, the emitter region 4 of the mesa portion and a portion of the base regions 3a to 3d are selectively removed by dry etching such as reactive ion etching (RIE). As a result, contact trenches 10a to 10d are formed that penetrate the emitter regions 4a to 4h and reach the base regions 3a to 3d so as to be continuous with the contact holes 20a to 20d, as shown in FIG.

[0057] Next, using the interlayer insulating film 20 as an ion implantation mask, p-type impurities such as boron (B) are ion-implanted. After that, the implanted p-type impurities are activated by heat treatment. As a result, as shown in FIG. 11, p-type impurities are formed in the upper portions of the base regions 3a to 3d, in contact with the lower surfaces and lower portions of the side surfaces of the contact trenches 10a to 10d. ＋ Mold contact regions 5a-5d are formed.

[0058] Next, a barrier metal film such as titanium (Ti) and titanium nitride (TiN) is formed in the contact trenches 10a-10d and the contact holes 20a-20d by sputtering, vapor deposition, dry etching, etc. Next, contact plugs such as tungsten (W) are embedded in the contact trenches 10a-10d and the contact holes 20a-20d via the barrier metal film by CVD, etch-back, etc. As a result, as shown in FIG. 12 , contact portions 9a-9d made of the barrier metal film and contact plugs are embedded in the contact trenches 10a-10d and the contact holes 20a-20d.

[0059] Next, as shown in FIG. 13, an emitter electrode 31 is deposited on the upper surfaces of the contact portions 9a to 9d and the interlayer insulating film 20 by sputtering or vapor deposition.

[0060] Next, the drift layer 1 is ground from the bottom side by grinding or chemical mechanical polishing (CMP), etc., to adjust the thickness of the drift layer 1 to the product thickness. Next, n-type impurities such as phosphorus (P) or selenium (Se) are ion-implanted over the entire bottom surface of the drift layer 1 to form an n-type FS layer 11. Next, p-type impurities such as phosphorus (P) or selenium (Se) are ion-implanted over the entire bottom surface of the drift layer 1 at an acceleration voltage lower than the acceleration voltage of the ion implantation to form the n-type FS layer 11. ＋ 14, p-type impurities such as boron (B) are implanted into the drift layer 1 to form the n-type collector region 12. Next, the implanted impurity ions are activated by heat treatment. As a result, an n-type FS layer 11 and a p-type FS layer 12 are formed under the drift layer 1. ＋ A collector region 12 of the mold is formed.

[0061] Next, a collector electrode 32 made of gold (Au) or the like is formed by sputtering, vapor deposition, or the like over the entire lower surface of the collector region 12. Thereafter, the semiconductor substrate is cut (diced) into individual pieces, thereby completing the semiconductor device according to the first embodiment shown in FIGS.

[0062] <Comparative Example> A semiconductor device according to a comparative example will now be described. Fig. 15 is a vertical cross-sectional view of the semiconductor device according to the comparative example, which corresponds to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in Fig. 1. Fig. 16 is a horizontal cross-sectional view of the semiconductor device according to the comparative example, which corresponds to the horizontal cross-sectional view of the semiconductor device according to the first embodiment shown in Fig. 2.

[0063] As shown in FIGS. 15 and 16 , the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 in that contact trenches 10a to 10d and contact portions 9a to 9d are provided in the center of the mesa portion, which is equidistant from the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d.

[0064] As shown in FIG. 15, the horizontal distance d11 from the end of the upper surface of the contact portions 9a to 9d on the side of the gate electrodes 8a, 8c, and 8e to the gate insulating film 7 on the side of the gate electrodes 8a, 8c, and 8e is equal to the horizontal distance d11 from the end of the upper surface of the contact portions 9a to 9d on the side of the dummy electrodes 8b and 8d to the gate insulating film 7 on the side of the dummy electrodes 8b and 8d.

[0065] As shown in FIG. 16, the horizontal distance d12 from the end of the upper surface of the emitter regions 4a, 4d, 4e, 4h on the side of the gate electrodes 8a, 8c, 8e to the gate insulating film 7 on the side of the gate electrodes 8a, 8c, 8e is equal to the horizontal distance d12 from the end of the upper surface of the emitter regions 4b, 4c, 4f, 4g on the side of the dummy electrodes 8b, 8d to the gate insulating film 7 on the side of the dummy electrodes 8b, 8d.

[0066] In the semiconductor device according to the comparative example, since the contact trenches 10a to 10d and the contact portions 9a to 9d are provided in the center of the mesa portion, the distances d11 and d12 need to be large, which makes it difficult to narrow the width w2 of the mesa portion sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d (mesa width).

[0067] In contrast, in the semiconductor device according to the first embodiment, the contact trenches 10a-10d and the contact portions 9a-9d sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are positioned closer to the dummy trenches 6b and 6d than to the center of the mesa portion. This allows the distances d2 and d4 on the dummy trenches 6b and 6d sides to be reduced while maintaining the distances d1 and d3 on the gate trenches 6a, 6c, and 6e sides, thereby narrowing the width w1 of the mesa portion (mesa width). This enhances the IE effect and improves the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0068] 17 shows the results of a simulation of the relationship between on-state voltage Von (on-state voltage drop) and turn-off loss Eoff (turn-off energy) when mesa widths A, B, and C are varied within a range of 1 μm or less in the semiconductor device according to the first embodiment. It can be seen from FIG. 17 that the trade-off characteristics between on-state voltage Von and turn-off loss Eoff can be improved as the mesa widths A, B, and C are narrowed.

[0069] Second Embodiment Fig. 18 is a vertical cross-sectional view of an insulated gate semiconductor device according to a second embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in Fig. 1. Fig. 19 is a horizontal cross-sectional view of an insulated gate semiconductor device according to the second embodiment, which corresponds to the horizontal cross-sectional view of the semiconductor device according to the first embodiment shown in Fig. 2.

[0070] As shown in FIGS. 18 and 19 , the insulated gate semiconductor device according to the second embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in FIGS. 1 and 2 in that only emitter regions 4a, 4d, 4e, and 4h are provided on the gate trenches 6a, 6c, and 6e sides, and no emitter regions are provided on the dummy trenches 6b and 6d sides.

[0071] 18, the upper surfaces of the base regions 3a to 3d and the contact regions 5a to 5d are in contact with the interlayer insulating film 20 on the side of the dummy trenches 6b and 6d. As shown in Fig. 19, the base regions 3a to 3d and the contact regions 5a to 5d extend in stripes along the contact trenches 10a to 10d and the dummy trenches 6b and 6d. The other configuration of the insulated gate semiconductor device according to the second embodiment is substantially the same as that of the insulated gate semiconductor device according to the first embodiment, and therefore a duplicated description will be omitted.

[0072] According to the insulated gate semiconductor device of the second embodiment, similarly to the insulated gate semiconductor device of the first embodiment, the contact trenches 10a to 10d and the contact portions 9a to 9d sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are positioned closer to the dummy trenches 6b and 6d than to the center of the mesa portion. This allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0073] Third Embodiment A vertical cross-sectional view of an insulated gate semiconductor device according to a third embodiment is similar to the vertical cross-sectional view of the semiconductor device according to the second embodiment shown in Fig. 18. The insulated gate semiconductor device according to the third embodiment is similar to the insulated gate semiconductor device according to the second embodiment shown in Fig. 19 in that only emitter regions 4a, 4d, 4e, and 4h are provided on the gate trenches 6a, 6c, and 6e sides, and no emitter regions are provided on the dummy trenches 6b and 6d sides.

[0074] Fig. 20 is a horizontal cross-sectional view of an insulated gate semiconductor device according to the third embodiment, and corresponds to the horizontal cross-sectional view of the semiconductor device according to the second embodiment shown in Fig. 19. The insulated gate semiconductor device according to the third embodiment differs from the insulated gate semiconductor device according to the second embodiment shown in Fig. 19 in that emitter regions 4a, 4d, 4e, and 4h have a planar pattern extending in stripes in one direction (the vertical direction in Fig. 20), as shown in Fig. 20. Other configurations of the insulated gate semiconductor device according to the third embodiment are substantially similar to those of the insulated gate semiconductor device according to the second embodiment, and therefore redundant description will be omitted.

[0075] According to the insulated gate semiconductor device of the third embodiment, similarly to the insulated gate semiconductor device of the first embodiment, the contact trenches 10a to 10d and the contact portions 9a to 9d sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are positioned closer to the dummy trenches 6b and 6d than to the center of the mesa portion. This allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0076] Fourth Embodiment FIG. 21 is a vertical cross-sectional view of an insulated gate semiconductor device according to a fourth embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the second embodiment shown in FIG.

[0077] 21, the insulated gate semiconductor device according to the fourth embodiment is similar to the insulated gate semiconductor device according to the second embodiment shown in FIG. 18 in that only emitter regions 4a, 4d, 4e, and 4h are provided on the gate trenches 6a, 6c, and 6e sides, and no emitter regions are provided on the dummy trenches 6b and 6d sides. However, the insulated gate semiconductor device according to the fourth embodiment differs from the insulated gate semiconductor device according to the second embodiment in that contact regions 5a to 5d are in contact with dummy trenches 6b and 6d. Other configurations of the insulated gate semiconductor device according to the fourth embodiment are substantially similar to those of the insulated gate semiconductor device according to the second embodiment, and therefore, redundant description will be omitted.

[0078] According to the insulated gate semiconductor device of the fourth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, the contact trenches 10a to 10d and the contact portions 9a to 9d sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are positioned closer to the dummy trenches 6b and 6d than to the center of the mesa portion. This allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0079] Fifth Embodiment FIG. 22 is a vertical cross-sectional view of an insulated gate semiconductor device according to a third embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in FIG.

[0080] As shown in FIG. 22, the insulated gate semiconductor device according to the fifth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in FIG. 1 in that contact holes 20 a, 20 c and contact trenches 10 a, 10 c are provided above dummy trenches 6 b, 6 d.

[0081] The upper part of the side surface of the contact trench 10a is in contact with the interlayer insulating film 20 and the emitter regions 4a and 4d. The lower part and bottom surface of the side surface of the contact trench 10a are in contact with the contact regions 5a and 5b. The upper part of the side surface of the contact trench 10c is in contact with the interlayer insulating film 20 and the emitter regions 4e and 4h. The lower part and bottom surface of the side surface of the contact trench 10c are in contact with the contact regions 5c and 5d.

[0082] The contact portions 9a and 9c embedded in the contact holes 20a and 20c and the contact trenches 10a and 10c are in contact with the dummy electrodes 8b and 8d embedded in the dummy trenches 6b and 6d.

[0083] If the dummy electrodes 8b and 8d are made of polysilicon doped with n-type impurities, a p-layer may also be formed on the surface of the dummy electrodes 8b and 8d during ion implantation to form the contact regions 5a to 5d after the contact trenches 10a and 10c are formed, resulting in the formation of a p-n junction in the dummy electrodes 8b and 8d. In this case, if the underside of the dummy trenches 6b and 6d becomes a high voltage, the potential of the dummy electrodes 8b and 8d becomes a floating potential, resulting in a decrease in breakdown voltage. On the other hand, if the dummy electrodes 8b and 8d are made of polysilicon doped with p-type impurities, a p-n junction is not formed in the dummy electrodes 8b and 8d during ion implantation to form the contact regions 5a to 5d. However, the gate electrodes 8a, 8c, and 8e, which are formed simultaneously with the dummy electrodes 8b and 8d, are also made of polysilicon doped with p-type impurities, resulting in a decrease in conductivity.

[0084] Therefore, it is preferable that the dummy electrodes 8b, 8d be made of highly doped polysilicon containing n-type impurities such as phosphorus (P) up to the solid solubility limit. This prevents the formation of a p-type layer on the surface of the dummy electrodes 8b, 8d during ion implantation to form the contact regions 5a-5d, and also prevents a decrease in conductivity. Alternatively, when the dummy electrodes 8b, 8d are made of polysilicon doped with n-type impurities, the impurity concentration of the contact regions 5a-5d may be adjusted to a level that prevents the formation of a p-type layer on the surface of the dummy electrodes 8b, 8d during ion implantation to form the contact regions 5a-5d.

[0085] FIG. 23 shows an enlarged view of the dashed-line region A surrounding the contact trench 10a in FIG. 22. As shown in FIG. 23, the depth of the contact trench 10a is deeper than the depth of the emitter region 4a. By making the depth of the contact trench 10a deeper than the depth of the emitter region 4a, the contact region 5a can be more easily expanded in the lateral direction, thereby improving the latch-up resistance. The depth of the contact trench 10a may be the same as the depth of the emitter region 4a, or may be shallower than the depth of the emitter region 4a.

[0086] The side surface of the contact trench 10a has a tapered shape (forward tapered shape) that narrows from the opening toward the bottom surface. The side surface of the contact trench 10a may be approximately perpendicular to the bottom surface of the contact trench 10a, or may have a tapered shape (inverse tapered shape) that widens from the opening toward the bottom surface. The bottom surface of the contact trench 10a is flat, but is not limited to this and may be a downwardly convex curved surface, etc.

[0087] A contact portion 9a is buried in the contact trench 10a and the contact hole 20a. The upper portion of the side surface of the contact portion 9a is in contact with the emitter region 4a and the interlayer insulating film 20. The lower portion of the side surface and the undersurface of the contact portion 9a are in contact with the contact region 5a. The contact portion 9a includes a buried portion 91 that is buried in the contact trench 10a and a plug portion 92 that is provided in the contact hole 20a.

[0088] On the gate electrode 8a side, in order to prevent an increase in gate threshold voltage due to the influence of the contact region 5a, it is necessary to increase the distance d5 between the gate insulating film 7 in contact with the gate electrode 8a and the contact region 5a. On the other hand, on the dummy electrode 8b side, it is not necessary to increase the distance between the gate insulating film 7 in contact with the dummy electrode 8b and the contact region 5a. Therefore, in the semiconductor device according to the fifth embodiment, the contact trench 10a and the contact portion 9a are provided closer to the dummy trench 6b than positions equidistant from the gate trench 6a and the dummy trench 6b, and at a position including the upper side of the dummy trench 6b.

[0089] Figure 24 shows a horizontal cross section passing through the emitter regions 4a, 4d, 4e, and 4h, the upper surfaces of the gate insulating film 7, the upper surfaces of the gate trenches 6a, 6c, and 6e, and the contact trenches 10a and 10c, as viewed from the B-B direction on the top surface of the semiconductor device according to the fifth embodiment shown in Figure 22. The horizontal cross section as viewed from the A-A direction in Figure 24 corresponds to Figure 22. In Figure 24, the dummy trenches 6b and 6d, the gate insulating film 7, and the dummy electrodes 8b and 8d hidden below the contact trenches 10a and 10c are schematically shown by dashed lines.

[0090] 24, the gate trenches 6a, 6c, and 6e, the dummy trenches 6b and 6d, and the contact trenches 10a to 10d have linear (striped) planar patterns extending parallel to one another in one direction (the vertical direction in FIG. 24). The emitter regions 4a to 4h have planar patterns that are intermittently provided in one direction (the vertical direction in FIG. 24). Other configurations of the insulated gate semiconductor device according to the fifth embodiment are substantially similar to those of the insulated gate semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0091] According to the insulated gate semiconductor device of the fifth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, contact trenches 10 a, 10 c and contact portions 9 a, 9 c are positioned closer to dummy trenches 6 b, 6 d than the center of the mesa portion, which allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between on-voltage Von and turn-off loss Eoff.

[0092] Furthermore, in the insulated gate semiconductor device according to the fifth embodiment, by providing contact holes 20 a, 20 c and contact trenches 10 a, 10 c above dummy trenches 6 b, 6 d, it is possible to make the mesa width w1 narrower than in the insulated gate semiconductor device according to the first embodiment.

[0093] Sixth Embodiment A vertical cross-sectional view of an insulated gate semiconductor device according to a sixth embodiment is similar to the vertical cross-sectional view of the semiconductor device according to the fifth embodiment shown in Fig. 22. The insulated gate semiconductor device according to the sixth embodiment is similar to the insulated gate semiconductor device according to the fifth embodiment shown in Fig. 22 in that contact holes 20a, 20c and contact trenches 10a, 10c are provided above dummy trenches 6b, 6d.

[0094] Fig. 25 is a horizontal cross-sectional view of an insulated gate semiconductor device according to the sixth embodiment, and corresponds to the horizontal cross-sectional view of the semiconductor device according to the fifth embodiment shown in Fig. 24. The insulated gate semiconductor device according to the sixth embodiment differs from the insulated gate semiconductor device according to the fifth embodiment shown in Fig. 24 in that emitter regions 4a, 4d, 4e, and 4h have a planar pattern extending in stripes in one direction (the vertical direction in Fig. 25), as shown in Fig. 25. Other configurations of the insulated gate semiconductor device according to the sixth embodiment are substantially similar to those of the insulated gate semiconductor device according to the fifth embodiment, and therefore redundant description will be omitted.

[0095] According to the insulated gate semiconductor device of the sixth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, contact trenches 10 a, 10 c and contact portions 9 a, 9 c are positioned closer to dummy trenches 6 b, 6 d than the center of the mesa portion, which allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between on-voltage Von and turn-off loss Eoff.

[0096] Furthermore, in the insulated gate semiconductor device according to the sixth embodiment, by providing contact holes 20 a, 20 c and contact trenches 10 a, 10 c above dummy trenches 6 b, 6 d, it is possible to make the mesa width w1 narrower than in the insulated gate semiconductor device according to the first embodiment.

[0097] Seventh Embodiment FIG. 26 is a vertical cross-sectional view of an insulated gate semiconductor device according to a seventh embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in FIG.

[0098] 26 , the insulated gate semiconductor device according to the seventh embodiment differs from the insulated gate semiconductor device according to the first embodiment in that dummy trenches 6 b, 6 d are provided adjacent to each other and that contact holes 20 a and contact trenches 10 a are provided above dummy trenches 6 b, 6 d. Contact portions 9 a embedded in contact holes 20 a and contact trenches 10 a are in contact with dummy electrodes 8 b, 8 d embedded in dummy trenches 6 b, 6 d. Other configurations of the insulated gate semiconductor device according to the seventh embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0099] According to the insulated gate semiconductor device of the seventh embodiment, similarly to the insulated gate semiconductor device of the first embodiment, the contact trench 10 a and the contact portion 9 a are positioned closer to the dummy trenches 6 b and 6 d than the center of the mesa portion, which allows the mesa width to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0100] Furthermore, in the insulated gate semiconductor device according to the seventh embodiment, by providing contact hole 20 a and contact trench 10 a above dummy trenches 6 b and 6 d, the mesa width can be made narrower than in the insulated gate semiconductor device according to the first embodiment.

[0101] Eighth Embodiment A vertical cross-sectional view of an insulated gate semiconductor device according to an eighth embodiment is similar to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in FIG.

[0102] Figure 27 is a horizontal cross-sectional view of an insulated gate semiconductor device according to the eighth embodiment, and corresponds to the horizontal cross-sectional view of the semiconductor device according to the first embodiment shown in Figure 3. The insulated gate semiconductor device according to the eighth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 3 in that, as shown in Figure 27, emitter regions 4a to 4h have a planar pattern extending in stripes in one direction (the vertical direction in Figure 27). Other configurations of the insulated gate semiconductor device according to the eighth embodiment are substantially similar to those of the insulated gate semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0103] According to the insulated gate semiconductor device of the eighth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, contact trenches 10a to 10d and contact portions 9a to 9d are positioned closer to dummy trenches 6b and 6d than the center of the mesa portion, which allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between on-voltage Von and turn-off loss Eoff.

[0104] Ninth Embodiment FIG. 28 is a vertical cross-sectional view of an insulated gate semiconductor device according to a ninth embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the first embodiment shown in FIG.

[0105] 28, the insulated gate semiconductor device according to the ninth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Fig. 1 in that no interlayer insulating film 20 is provided between emitter regions 4a to 4h and emitter electrode 31, and in that the upper surfaces of gate electrodes 8a, 8c, 8e and dummy electrodes 8b, 8d are covered with gate insulating film 7. Other configurations of the insulated gate semiconductor device according to the ninth embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0106] According to the insulated gate semiconductor device of the ninth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, the contact trenches 10a to 10d and the contact portions 9a to 9d sandwiched between the gate trenches 6a, 6c, and 6e and the dummy trenches 6b and 6d are positioned closer to the dummy trenches 6b and 6d than to the center of the mesa portion. This allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between the on-voltage Von and the turn-off loss Eoff.

[0107] Tenth Embodiment FIG. 29 is a vertical cross-sectional view of an insulated gate semiconductor device according to a tenth embodiment, which corresponds to the vertical cross-sectional view of the semiconductor device according to the fifth embodiment shown in FIG.

[0108] 29, the insulated gate semiconductor device according to the tenth embodiment differs from the insulated gate semiconductor device according to the fifth embodiment shown in Fig. 22 in that no interlayer insulating film 20 is provided between emitter regions 4a, 4d, 4e, 4h and emitter electrode 31, and that the upper surfaces of gate electrodes 8a, 8c, 8e are covered with gate insulating film 7. Other configurations of the insulated gate semiconductor device according to the tenth embodiment are substantially the same as those of the insulated gate semiconductor device according to the fifth embodiment, and therefore redundant description will be omitted.

[0109] According to the insulated gate semiconductor device of the tenth embodiment, similarly to the insulated gate semiconductor device of the first embodiment, contact trenches 10 a, 10 b and contact portions 9 a, 9 b are positioned closer to dummy trenches 6 b, 6 d than the center of the mesa portion, which allows the mesa width w1 to be narrowed, thereby enhancing the IE effect and improving the trade-off characteristics between on-voltage Von and turn-off loss Eoff.

[0110] Although the first to tenth embodiments have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0111] For example, although an IGBT has been exemplified as the semiconductor device according to the first to tenth embodiments, the present invention can also be applied to a reverse conducting IGBT (RC-IGBT) or a reverse blocking insulated gate bipolar transistor (RB-IGBT). ＋ The collector region 12 is ＋ The present invention can also be applied to a MOSFET having a drain region of the same type.

[0112] Furthermore, the configurations disclosed in the first to tenth embodiments can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description.

[0113] REFERENCE SIGNS LIST 1... drift layer 2a to 2d... accumulation layer 3a to 3d... base region 4, 4a to 4h... emitter region 5a to 5d... contact region 6a, 6c, 6e... trench (gate trench) 6b, 6d... trench (dummy trench) 7... gate insulating film 8a, 8c, 8e... gate electrode 8b, 8d... dummy electrode 9a to 9d... contact portion 10a to 10d... trench (contact trench) 11... FS layer 12... collector region 20... interlayer insulating film 20a to 20d... contact hole 31... emitter electrode 32... collector electrode 91... buried portion 92... plug portion

Claims

1. An insulated gate semiconductor device comprising: a drift layer of a first conductivity type; a base region of a second conductivity type provided on the drift layer; a contact region of a second conductivity type provided on an upper portion of the base region and having a higher impurity concentration than the base region; a main electrode region of a first conductivity type provided on the base region and the contact region; a gate electrode embedded, via a first gate insulating film, in a gate trench provided in contact with the main electrode region and the base region; a dummy electrode embedded, via a second gate insulating film, in a dummy trench provided at a distance from the gate trench; and a contact portion embedded in a contact trench in contact with the main electrode region and the contact region, 2. The insulated gate semiconductor device according to claim 1, wherein the contact trench is separated from the dummy trench.

3. The insulated gate semiconductor device according to claim 1 or 2, wherein the distance from the side of the contact portion on the gate electrode side to the first gate insulating film is greater than the distance from the side of the contact portion on the dummy electrode side to the second gate insulating film.

4. The insulated gate semiconductor device according to claim 1, wherein the contact trench is provided above the dummy trench, and the contact portion is in contact with the dummy electrode.

5. The insulated gate semiconductor device according to claim 1 or 2, wherein the depth of the contact trench is deeper than the depth of the main electrode region.

6. The insulated gate semiconductor device according to claim 1 or 2, wherein the contact region is separated from the dummy trench.

7. The insulated gate semiconductor device according to claim 1 or 2, wherein the contact region is in contact with the dummy trench.

8. The insulated gate semiconductor device according to claim 1 or 2, wherein the main electrode region is provided between the gate trench and the contact trench, and between the dummy trench and the contact trench.

9. The insulated gate semiconductor device according to claim 1 or 2, wherein the main electrode region is provided between the gate trench and the contact trench, and is not provided between the dummy trench and the contact trench.

10. The insulated gate semiconductor device according to claim 1 or 2, wherein each of the gate trench, the dummy trench and the contact trench has a planar pattern extending in one direction.

11. The insulated gate semiconductor device according to claim 10, wherein the main electrode region has a planar pattern that is intermittently provided in the one direction.

12. The insulated gate semiconductor device according to claim 10, wherein said main electrode region has a planar pattern extending in said one direction.

13. The insulated gate semiconductor device according to claim 4, wherein the dummy electrode is made of polysilicon containing impurities of the first conductivity type up to the solid solubility limit.

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