Semiconductor device, electronic apparatus, and method for manufacturing semiconductor device

Abstract

The present invention suppresses property variations caused by process variations. A semiconductor device according to the present invention includes a semiconductor substrate, a plurality of element isolation parts, and a field effect transistor. The field effect transistor is provided between an upper surface part of a first element isolation part and an upper surface part of a second element isolation part among the plurality of element isolation parts in a plan view. The field effect transistor includes a gate electrode, a fin part, a gate insulating film, and a protruding part. The protruding part is formed between the embedded part of the gate electrode and a side wall part of at least one of the first element isolation part or the second element isolation part, and has a narrower width than the fin part. The protruding part contains impurities of the opposite conductivity type as the fin part, and a higher concentration of impurities are distributed in the protruding part than elsewhere in the semiconductor substrate.

Description

Semiconductor device, electronic device, and method of manufacturing the semiconductor device

[0001] The present disclosure relates to a semiconductor device, an electronic device equipped with the semiconductor device, and a method for manufacturing the semiconductor device.

[0002] A solid-state imaging device (photodetector device) includes a source follower circuit that converts photoelectrically converted charges generated by a photoelectric conversion unit into pixel signals based on the charges and outputs the pixel signals. It is known that fin field effect transistors (hereinafter referred to as Fin-FETs) are often used in circuits within the device, including the source follower circuit, to improve performance.

[0003] For example, Patent Document 1 discloses a transistor having a gate electrode having a buried portion formed so as to be buried from a planar portion formed on the surface of a semiconductor substrate toward the interior of the semiconductor substrate, and a channel region (fin portion) that contacts the side surface of the buried portion via an insulating film.

[0004] Japanese Patent Application Laid-Open No. 2017-183636

[0005] Among recessed gate Fin-FETs, those with shallow recesses of around 100 nm have a small footprint, which is advantageous for miniaturization, and can be manufactured at low cost with fewer processes. On the other hand, when a sharp silicon protrusion is formed between a tapered shallow trench isolation (STI) and a silicon (Si) substrate, the protrusion is considered a tiny Fin-FET and can easily become a parasitic transistor. Furthermore, process variations cause variations in the height and width of the protrusion and the isolation, which ultimately becomes a factor in variations in the on-characteristics of the transistor.

[0006] The present disclosure has been made in view of the above circumstances, and aims to provide a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device that can suppress characteristic variations caused by process variations.

[0007] One aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, wherein the field effect transistor has a flat portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more field effect transistors embedded from the flat portion toward the interior of the semiconductor substrate. a gate insulating film disposed between the gate electrode and the fin portion; and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a narrower width than the fin portion, wherein impurities of a conductivity type opposite to that of the fin portion are distributed in the convex portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion.

[0008] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction, a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, the field effect transistor having a flat portion formed in a plane on the first surface portion of the semiconductor substrate and a sidewall portion embedded from the flat portion toward the interior of the semiconductor substrate. a gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than that of the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, wherein the convex portion insulating film is thicker than the gate insulating film covering the fin portion.

[0009] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, the field effect transistor having a flat portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the flat portion toward the interior of the semiconductor substrate. a gate insulating film disposed between the gate electrode and the fin portion; and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a narrower width than the fin portion, wherein impurities of a conductivity type opposite to that of the fin portion are distributed in the convex portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion.

[0010] Another aspect of the present disclosure includes a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction, a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, the field effect transistor having a flat portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more field effect transistors embedded from the flat portion toward the interior of the semiconductor substrate. and a gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, the convex portion insulating film being thicker than the gate insulating film covering the fin portion.

[0011] and forming a gate electrode of the field effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion, the gate electrode of the field effect transistor being formed between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion.

[0012] FIG. 1 is a plan view schematically showing a configuration example of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a second embodiment of the present disclosure. FIG. 3 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a third embodiment of the present disclosure. FIG. 4 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 5 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a sixth embodiment of the present disclosure. FIG. 6 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 7 is a cross-sectional view (part 1) showing a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 8 is a cross-sectional view (part 2) showing a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 9 is a cross-sectional view (part 3) showing a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 10 is a cross-sectional view (part 4) showing a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 11 is a cross-sectional view (part 5) showing a process procedure of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. 16 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a ninth embodiment of the present disclosure. FIG. 17 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to a tenth embodiment of the present disclosure. FIG. 18 is a diagram showing a schematic configuration of an example of a photodetector according to an eleventh embodiment of the present disclosure. FIG. 19 is a diagram showing an example of a schematic configuration of a photodetector according to a twelfth embodiment of the present disclosure. FIG. 19 is a circuit diagram showing an example of a sensor pixel and a readout circuit shown in FIG. 14. FIG. 19 is a block diagram showing an example of a configuration of an electronic device. FIG. 19 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the present technology is applied. FIG. 19 is a block diagram showing an example of a functional configuration of a camera head and a CCU shown in FIG. 17. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system to which the present technology is applied. FIG. 19 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit shown in FIG.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0014] In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type, which is different from the "first conductivity type." Furthermore, the "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the semiconductor regions have the same "n" and "n" attached, this does not mean that the impurity densities of the respective semiconductor regions are strictly the same.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Note that the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0016] First Embodiment (Configuration Example of Semiconductor Device) Fig. 1 is a plan view schematically showing a configuration example of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view schematically showing a configuration example of the semiconductor device 1 according to the first embodiment of the present disclosure. Fig. 2 shows a cross section taken along line AA' in the plan view shown in Fig. 1.

[0017] As shown in FIGS. 1 and 2 , the semiconductor device 1 according to the first embodiment includes a semiconductor substrate 2, an N-type MOS (Metal Oxide Semiconductor) transistor 3 (an example of a “field effect transistor” in the present disclosure) provided on the semiconductor substrate 2, and a plurality of element isolation portions 5 extending in a thickness direction of the semiconductor substrate 2 (the direction indicated by arrow Z in FIG. 1 ).

[0018] The semiconductor substrate 2 is made of, for example, single-crystal silicon. The semiconductor substrate 2 has a front surface 2a (an example of a "first surface" in the present disclosure) and a back surface 2b (an example of a "second surface" in the present disclosure) located opposite the front surface 2a. A MOS transistor 3 is provided on the front surface 2a side of the semiconductor substrate 2. The element isolation portion 5 is an insulating film for electrically isolating adjacent elements in the horizontal direction, and is formed, for example, of a silicon oxide film embedded in a trench. The MOS transistor 3 is provided between a first element isolation portion 51 and a second element isolation portion 52 of the multiple element isolation portions 5. The first element isolation portion 51 has a forward tapered structure and has an upper surface portion 51a on the front surface 2a side of the semiconductor substrate 2 and a sidewall portion 51b extending in the thickness direction of the semiconductor substrate 2 (the direction indicated by the arrow Z in FIG. 2 ). The second element isolation portion 52 has a forward tapered structure and has an upper surface portion 52a on the surface 2a side of the semiconductor substrate 2 and sidewall portions 52b extending in the thickness direction of the semiconductor substrate 2. Note that the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 are not at the same height as the surface 2a of the semiconductor substrate 2. Specifically, the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 may be higher than the surface 2a of the semiconductor substrate 2. The MOS transistor 3 is laid out between the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 in a plan view.

[0019] The MOS transistor 3 has a fin portion 10 in which a channel is formed, a gate insulating film 20 , a gate electrode 30 , and a source region 41 and a drain region 42 provided in the semiconductor substrate 2 .

[0020] The fin portion 10 is, for example, a part of the semiconductor substrate 2, and is made of single crystal silicon. The conductivity type of the fin portion 10 is, for example, n-type. The gate insulating film 20 is provided so as to cover the top and side surfaces of the fin portion 10. The top surface of the fin portion 10 is part of the surface 2a of the semiconductor substrate 2. The gate insulating film 20 is, for example, made of a silicon oxide film. The fin portion 10 is, for example, long in the Y-axis direction and short in the X-axis direction.

[0021] The gate electrode 30 has a planar portion 31 and at least one buried portion 32, and covers the fin portion 10 via the gate insulating film 20. For example, the gate electrode 30 is disposed so as to face the top and side surfaces of the fin portion 10 via the gate insulating film 20. This allows the gate electrode 30 to simultaneously apply a gate voltage to the top and side surfaces of the fin portion 10. In other words, the gate electrode 30 can simultaneously apply a gate voltage to the fin portion 10 from three directions: from above and both the left and right sides. This allows the gate electrode 30 to completely deplete the fin portion 10. The gate electrode 30 is made of, for example, a polysilicon (Poly-Si) film doped with impurities.

[0022] The planar portion 31 of the gate electrode 30 is formed planarly on the surface 2 a of the semiconductor substrate 2, part of the upper surface portion 51 a of the first device isolation portion 51, and part of the upper surface portion 52 a of the second device isolation portion 52. Of the multiple buried portions 32, the first buried portion 321 is located on the first device isolation portion 51 side and is buried from the planar portion 31 toward the inside of the semiconductor substrate 2. The second buried portion 322 is located on the second device isolation portion 52 side and is buried from the planar portion 31 toward the inside of the semiconductor substrate 2.

[0023] The source region 41 is provided on the surface 2a of the semiconductor substrate 2 and in its vicinity. In the Y-axis direction in Fig. 1, the source region 41 is connected to one side of the fin portion 10. The drain region 42 is provided on the surface 2a of the semiconductor substrate 2 and in its vicinity. In the Y-axis direction in Fig. 1, the drain region 42 is connected to the other side of the fin portion 10. A channel is formed between the source region 41 and the drain region 42 when the gate voltage applied to the gate electrode 30 exceeds a threshold voltage.

[0024] In the first embodiment, a dug portion 51c is formed from the upper surface 51a of the first element isolation portion 51 in the thickness direction of the semiconductor substrate 2 (the direction indicated by Z in FIG. 2 ), and a dug portion 52c is further formed from the upper surface 52a of the second element isolation portion 52 in the thickness direction of the semiconductor substrate 2. A first buried portion 321 of the gate electrode 30 is buried in the dug portion 51c. A second buried portion 322 of the gate electrode 30 is buried in the dug portion 52c. A protruding portion 621 having a width narrower than that of the fin portion 10 is formed between the dug portion 51c and the semiconductor substrate 2. Furthermore, a protruding portion 622 having a width narrower than that of the fin portion 10 is formed between the dug portion 52c and the semiconductor substrate 2. A gate insulating film 20 is arranged around the protruding portions 621 and 622. The height of the tops of the protrusions 621 and 622 is lower than the upper surface of the fin portion 10 and higher than the bottoms of the recessed portions 51c and 52c.

[0025] These protrusions 621, 622 are considered to be tiny Fin-FETs and easily become parasitic transistors. Furthermore, due to process variations, the height and width of the protrusions 621, 622 relative to the element isolation portion 5 vary, resulting in variations in the on-state characteristics of the transistors. Therefore, in the first embodiment of the present disclosure, the interior of each of the protrusions 621, 622 is doped with impurities of a second conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type) of the fin portion 10, thereby forming a high-concentration second-conductivity-type region 63 that is distributed at a higher concentration than the second-conductivity-type region 61 included in the semiconductor substrate 2 other than the protrusions 621, 622. This promotes carrier migration from the second-conductivity-type region 61 of the semiconductor substrate 2 to the fin portion 10 and suppresses carrier migration to the protrusions 621, 622. This suppresses characteristic variations due to process variations.

[0026] <Effects of First Embodiment> As described above, according to the first embodiment, the interior of each of the protruding portions 621, 622 is doped with impurities of the second conductivity type opposite to the first conductivity type of the fin portion 10, thereby forming high-concentration second conductivity type regions 63 that are distributed at a higher concentration than the second conductivity type regions 61 included inside the semiconductor substrate 2 other than the protruding portions 621, 622. This makes it possible to prevent an inversion layer from being formed preferentially in the protruding portions 621, 622 rather than in the fin portion 10, thereby promoting the movement of carriers from the second conductivity type regions 61 of the semiconductor substrate 2 to the fin portion 10 and suppressing the movement of carriers to the protruding portions 621, 622. This makes it possible to suppress characteristic variations due to process variations.

[0027] 3 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1A according to a second embodiment of the present disclosure. In FIG. 3, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0028] In the second embodiment of the present disclosure, the gate electrode 30A of the MOS transistor 3A further includes a third buried portion 323. The third buried portion 323 is formed between the first buried portion 321 and the second buried portion 322. The first fin portion 11 is formed between the first buried portion 321 and the third buried portion 323. The second fin portion 12 is formed between the second buried portion 322 and the third buried portion 323. This allows the gate electrode 30A to simultaneously apply gate voltages in three directions to the top surface and side surface portions of each of the first fin portion 11 and the second fin portion 12.

[0029] <Effects of the Second Embodiment> As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltages in three directions to the top surface and side surface of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0030] 4 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1B according to a third embodiment of the present disclosure. In FIG. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0031] In the third embodiment of the present disclosure, the first element isolation portion 51 is formed from the upper surface portion 51a in the thickness direction of the semiconductor substrate 2 (the direction indicated by the arrow Z in FIG. 4 ), and has a dug portion 51d into which the first buried portion 321 of the gate electrode 30 is buried. The second element isolation portion 52 is formed from the upper surface portion 52a in the thickness direction of the semiconductor substrate 2, and has a dug portion 52d into which the second buried portion 322 of the gate electrode 30 is buried.

[0032] The bottom of dug portion 51 d is higher than the height of the top of protrusion 621. Furthermore, the bottom of dug portion 52 d is higher than the height of the top of protrusion 622. In the third embodiment of the present disclosure, as in the first embodiment, the inside of each of protrusions 621, 622 is doped with impurities of a second conductivity type opposite to the first conductivity type of fin portion 10, thereby forming high-concentration second-conductivity-type regions 63 that are distributed at a higher concentration than second-conductivity-type regions 61 included inside semiconductor substrate 2 other than protrusions 621, 622.

[0033] <Operational Effects of Third Embodiment> As described above, the third embodiment also provides the same operational effects as the first embodiment.

[0034] 5 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1C according to a fourth embodiment of the present disclosure. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the fourth embodiment of the present disclosure, a convex insulating film 71 is disposed between the convex portion 621 and the first buried portion 321 of the gate electrode 30. Furthermore, a convex insulating film 72 is disposed between the convex portion 622 and the second buried portion 322 of the gate electrode 30. The convex insulating films 71 and 72 are at least 1 nm thicker around the entire periphery of the convex portions 621 and 622 than the gate insulating film 20 covering the fin portion 10.

[0035] <Effects of the Fourth Embodiment> As described above, according to the fourth embodiment, the convex portion insulating films 71, 72 are disposed between the convex portions 621, 622 and the gate electrode 30, and the convex portion insulating films 71, 72 are formed to be thicker than the gate insulating film 20 covering the fin portion 10, thereby preventing an inversion layer from being preferentially formed in the convex portions 621, 622 rather than in the fin portion 10. This makes it possible to suppress characteristic variations due to process variations.

[0036] 6 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1D according to a fifth embodiment of the present disclosure. In FIG. 6, the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0037] In the fifth embodiment of the present disclosure, the same effects as those of the fourth embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltage in three directions to the top and side surfaces of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0038] 7 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1E according to a sixth embodiment of the present disclosure. In FIG. 7, the same parts as those in FIG. 4 and FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0039] In the sixth embodiment of the present disclosure, the same effects as those of the third and fourth embodiments can be obtained.

[0040] 8 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1F according to a seventh embodiment of the present disclosure. In FIG. 8, the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0041] In the seventh embodiment of the present disclosure, the high-concentration second-conductivity-type region 63 or the second-conductivity-type region is not formed inside each of the protrusions 621 and 622. In addition, the height of the tops of the protrusions 621 and 622 is higher than the bottoms of the respective recessed portions 51 c and 52 c, and therefore the protrusion insulating films 71 and 72 are oxidized in all directions. This makes it easier to thicken the protrusion insulating films 71 and 72.

[0042] 9A to 9E are cross-sectional views showing the process steps of a method for manufacturing a semiconductor device 1F according to a seventh embodiment of the present disclosure. The semiconductor device 1F is manufactured using various types of equipment, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0043] 9A , a silicon single crystal semiconductor substrate 2 is prepared. As shown in FIG. 9B , a manufacturing apparatus forms a plurality of element isolation regions 5 in the semiconductor substrate 2. Next, as shown in FIG. 9C , the manufacturing apparatus forms an anti-reflection film 81 on the surface 2 a of the semiconductor substrate 2, the upper surface 51 a of the first element isolation region 51, and the upper surface 52 a of the second element isolation region 52. A resist is patterned on the anti-reflection film 81 in a lithography process, and trenches 821 and 822 are formed so as to overlap the upper surface 51 a of the first element isolation region 51 and the upper surface 52 a of the second element isolation region 52. This forms the fin portion 10 and the protrusions 621 and 622.

[0044] 9D(1), the manufacturing equipment removes the anti-reflection film 81 and resist through a dry etching process, forms a gate insulating film 20 on the upper and side surfaces of the fin portion 10, forms a convex insulating film 71 around the convex portion 621, and forms a convex insulating film 721 around the convex portion 622. At this time, as shown in FIG. 9D(2), for example, an insulating material is formed on the convex portion 622, and a resist mask is formed on the insulating material using well-known photography techniques. Then, an insulating material is deposited in the opening of the resist mask so that the thickness of the insulating material is thicker than the thickness of the gate insulating film 20. Then, the resist mask is removed.

[0045] 9E, the manufacturing equipment forms gate electrodes 30 in dug portions 51c of first element isolation portion 51, dug portions 52c of second element isolation portion 52, and on surface 2a of semiconductor substrate 2.

[0046] <Effects of Seventh Embodiment> As described above, according to the seventh embodiment, the convex portion insulating films 71, 72 are disposed between the convex portions 621, 622 and the gate electrode 30, and the convex portion insulating films 71, 72 are formed to be thicker than the gate insulating film 20 covering the fin portion 10, thereby preventing an inversion layer from being preferentially formed in the convex portions 621, 622 rather than in the fin portion 10. This makes it possible to suppress characteristic variations due to process variations.

[0047] 10 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1G according to an eighth embodiment of the present disclosure. In FIG. 8, the same parts as those in FIG. 2 and FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0048] In the eighth embodiment of the present disclosure, the same effects as those of the seventh embodiment can be obtained, and the gate electrode 30A can simultaneously apply gate voltage in three directions to the top and side surfaces of each of the first fin portion 11 and the second fin portion 12, thereby realizing a transistor with high driving capability.

[0049] 11 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1H according to a ninth embodiment of the present disclosure. In FIG. 11, the same parts as those in FIG. 4 and FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0050] In the ninth embodiment of the present disclosure, the same effects as those of the third and seventh embodiments can be obtained.

[0051] 12 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device 1I according to a tenth embodiment of the present disclosure. In FIG. 12, the same parts as those in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0052] In the tenth embodiment of the present disclosure, a convex portion insulating film 91 is disposed between the convex portion 621 and the first buried portion 321 of the gate electrode 30. Furthermore, a convex portion insulating film 92 is disposed between the convex portion 622 and the second buried portion 322 of the gate electrode 30. The convex portion insulating film 91 is configured with a first portion 911 having a maximum first thickness that is thicker than the gate insulating film 20 covering the fin portion 10 at its top, and a second portion 912 that is thinner than the first thickness. The convex portion insulating film 91 gradually becomes thicker from the second portion 912 to the first portion 911.

[0053] The protrusion insulating film 92 is composed of a first portion 921 having a maximum first thickness that is thicker than the gate insulating film 20 covering the fin portion 10 at its top, and a second portion 922 that is thinner than the first thickness. The protrusion insulating film 92 gradually becomes thicker from the second portion 922 to the first portion 921.

[0054] In the tenth embodiment of the present disclosure, the same effects as those of the seventh embodiment can be obtained.

[0055] Eleventh Embodiment (An Example of a First Photodetector) Any one of the semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the semiconductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment can be applied to a first photodetector. An example of a first photodetector to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are applied will be described below.

[0056] FIG. 13 shows a schematic configuration of an example of a photodetector according to an eleventh embodiment of the present disclosure. As shown in FIG. 13, the photodetector 1-1 of this example includes a semiconductor substrate 11-1, a pixel region (so-called imaging region) 3-1 in which pixels 2-1, each including a plurality of photoelectric conversion elements, are regularly arranged two-dimensionally on, for example, a silicon substrate, and a peripheral circuit section. The pixel 2-1 includes, for example, a photodiode serving as a photoelectric conversion element, and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors may be configured with, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Alternatively, a selection transistor may be added to configure a total of four transistors. The equivalent circuit of a unit pixel is the same as a conventional one, and therefore a detailed description thereof will be omitted. The pixel 2-1 may also have a shared pixel structure. In the third embodiment of the present disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used as one or more of the plurality of pixel transistors.

[0057] This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor each shared.

[0058] The peripheral circuit section includes a vertical drive circuit 4-1, a column signal processing circuit 5-1, a horizontal drive circuit 6-1, an output circuit 7-1, a control circuit 8-1, and the like.

[0059] The control circuit 8-1 receives an input clock and data instructing the operation mode, etc., and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8-1 generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. These signals are then input to the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc.

[0060] The vertical drive circuit 4-1 is configured, for example, by a shift register, selects pixel drive wirings, supplies pulses for driving pixels to the selected pixel drive wirings, and drives the pixels row by row. That is, the vertical drive circuit 4-1 selects and scans each pixel 2-1 in the pixel region 3-1 row by row in the vertical direction, and supplies pixel signals based on signal charges generated in accordance with the amount of light received in, for example, photodiodes serving as photoelectric conversion elements of each pixel 2-1 to the column signal processing circuit 5-1 via vertical signal lines 9-1.

[0061] The column signal processing circuit 5-1 is arranged, for example, for each column of pixels 2-1, and performs signal processing such as noise removal on signals output from one row of pixels 2-1 for each pixel column. That is, the column signal processing circuit 5-1 performs signal processing such as CDS for removing fixed pattern noise specific to the pixels 2-1, signal amplification, and AD conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5-1 and connected between it and the horizontal signal line 10-1.

[0062] The horizontal drive circuit 6-1 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5-1 in turn, causing each of the column signal processing circuits 5-1 to output a pixel signal to the horizontal signal line 10-1.

[0063] The output circuit 7-1 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5-1 through the horizontal signal line 10-1. For example, the output circuit 7-1 may only perform buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 12-1 exchanges signals with the outside.

[0064] As described above, according to the eleventh embodiment, even when applied to the photodetector 1-1, the same effects as those of the first to tenth embodiments can be obtained.

[0065] Twelfth Embodiment (Application Example to Second Photodetector) Any one of the semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the semiconductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment can be applied to a second photodetector. An example of a second photodetector to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are applied will be described below.

[0066] 14 illustrates an example of a schematic configuration of a photodetector 1-2 according to a twelfth embodiment of the present disclosure. The photodetector 1-2 includes three substrates (a first substrate 10-2, a second substrate 20-2, and a third substrate 30-2). The photodetector 1-2 has a three-dimensional structure formed by bonding together the three substrates (the first substrate 10-2, the second substrate 20-2, and the third substrate 30-2). The first substrate 10-2, the second substrate 20-2, and the third substrate 30-2 are stacked in this order.

[0067] The first substrate 10-2 has, on its semiconductor substrate 11-2, a plurality of sensor pixels 12-2 that perform photoelectric conversion. The plurality of sensor pixels 12-2 are arranged in a matrix within a pixel region 13-2 of the first substrate 10-2. The second substrate 20-2 has, on its semiconductor substrate 21-2, readout circuits 22-2 for every four sensor pixels 12-2 that output pixel signals based on the charges output from the sensor pixels 12-2. The second substrate 20-2 has a plurality of pixel drive lines 23-2 extending in the row direction and a plurality of vertical signal lines 24-2 extending in the column direction. The third substrate 30-2 has, on its semiconductor substrate 31-2, a logic circuit 32-2 that processes pixel signals. The logic circuit 32-2 has, for example, a vertical drive circuit 33-2, a column signal processing circuit 34-2, a horizontal drive circuit 35-2, and a system control circuit 36-2. The logic circuit 32-2 (specifically, the horizontal drive circuit 35-2) outputs the output voltage Vout for each sensor pixel 12-2 to the outside. In the logic circuit 32-2, for example, a low-resistance region made of silicide such as CoSi or NiSi formed using a salicide (self-aligned silicide) process may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0068] The vertical drive circuit 33-2, for example, sequentially selects a plurality of sensor pixels 12-2 row by row. The column signal processing circuit 34-2, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12-2 in the row selected by the vertical drive circuit 33-2. The column signal processing circuit 34-2, for example, performs CDS processing to extract the signal level of the pixel signal and stores pixel data corresponding to the amount of light received by each sensor pixel 12-2. The horizontal drive circuit 35-2, for example, sequentially outputs the pixel data stored in the column signal processing circuit 34-2 to the outside. The system control circuit 36-2, for example, controls the driving of each block (the vertical drive circuit 33-2, the column signal processing circuit 34-2, and the horizontal drive circuit 35-2) within the logic circuit 32-2.

[0069] Fig. 15 shows an example of a sensor pixel 12-2 and a readout circuit 22-2. Below, a case will be described in which four sensor pixels 12-2 share one readout circuit 22-2, as shown in Fig. 15. Here, "shared" means that the outputs of the four sensor pixels 12-2 are input to a common readout circuit 22-2.

[0070] The sensor pixels 12-2 have common components. In Fig. 15, in order to distinguish the components of the sensor pixels 12-2 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each sensor pixel 12-2. Hereinafter, when it is necessary to distinguish the components of each sensor pixel 12-2 from one another, an identification number is added to the end of the reference numeral of the component of each sensor pixel 12-2. However, when it is not necessary to distinguish the components of each sensor pixel 12-2 from one another, the identification number at the end of the reference numeral of the component of each sensor pixel 12-2 is omitted.

[0071] Each sensor pixel 12-2 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23-2. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0072] The floating diffusions FD of the sensor pixels 12-2 that share one readout circuit 22-2 are electrically connected to each other and to the input terminal of the common readout circuit 22-2. The readout circuit 22-2 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Note that the selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22-2) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23-2 (see FIG. 14). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22-2) is electrically connected to the vertical signal line 24-2, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23-2 (see FIG. 8).

[0073] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22-2. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34-2 via the vertical signal line 24-2. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors. In the fourth embodiment of the present disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used as one or more of the plurality of pixel transistors.

[0074] <Other Embodiments> As described above, the present technology has been described using the first to twelfth embodiments. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Once the gist of the technical content disclosed in the above-described embodiment is understood, it will be clear to those skilled in the art that various alternative embodiments, examples, and operational techniques may be included in the present technology. Furthermore, the configurations disclosed in the first to twelfth embodiments may be appropriately combined within a range that does not cause contradictions. For example, configurations disclosed in multiple different embodiments may be combined, or configurations disclosed in multiple different modified examples of the same embodiment may be combined.

[0075] <Application Examples to Electronic Devices> Furthermore, the photodetector device as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0076] Fig. 16 is a block diagram showing an example of the configuration of an electronic device. As shown in Fig. 16, an electronic device 1010 includes an optical system 1020, a photodetector 1030, and a DSP (Digital Signal Processor) 1040. The DSP 1040, a display device 1050, an operation system 1060, a memory 1080, a recording device 1090, and a power supply system 1100 are connected via a bus 1070, and the electronic device 1010 is capable of capturing still images and moving images.

[0077] The optical system 1020 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 1030 , forming an image on the light-receiving surface (sensor portion) of the photodetector 1030 .

[0078] Any of the photodetector devices having the above-described configuration examples is applied as the photodetector 1030. Electrons are accumulated in the photodetector 1030 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 1020. A signal corresponding to the electrons accumulated in the photodetector 1030 is then supplied to the DSP 1040.

[0079] The DSP 1040 performs various signal processing on the signal from the photodetector 1030 to acquire an image, and temporarily stores the image data in the memory 1080. The image data stored in the memory 1080 is recorded in the recording device 1090 or supplied to the display device 1050 to display the image. In addition, the operation system 1060 accepts various operations by the user and supplies operation signals to each block of the electronic device 1010, and the power supply system 1100 supplies the power necessary to drive each block of the electronic device 1010.

[0080] <Application Example to Endoscopic Surgery System> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0081] Fig. 17 is a diagram showing an example of the schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied. Fig. 17 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0082] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0083] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0084] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0085] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing on the image signals, such as development processing (demosaic processing), to display images based on the image signals. Under the control of the CCU 11201, the display device 11202 displays images based on the image signals that have been subjected to image processing by the CCU 11201.

[0086] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical site, etc. The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of illumination light, magnification, focal length, etc.) of the endoscope 11100.

[0087] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0088] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0089] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0090] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0091] Fig. 18 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Fig. 17. The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so as to be able to communicate with each other.

[0092] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0093] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0094] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens. The driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0095] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0096] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0097] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0098] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404. The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0099] The communication unit 11411 also transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, etc. The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data transmitted from the camera head 11102.

[0100] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0101] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0102] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these. In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0103] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the endoscope 11100, the imaging unit 11402 of the camera head 11102, the image processing unit 11412 of the CCU 11201, and the like, among the above-described configurations. Specifically, the semiconductor device 1 of FIG. 1 can be applied to the imaging unit 10402. Note that, although the endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgical system.

[0104] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0105] Fig. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0106] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0107] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0108] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0109] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0110] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0111] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0112] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0113] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0114] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0115] 20 is a diagram showing an example of the installation position of the image capturing unit 12031. In FIG. 20, a vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0116] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0117] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0118] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0119] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0120] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0121] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0122] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 of the above-described configuration. Specifically, the technology can be applied to the semiconductor device 1 shown in FIG. 1 .

[0123] The present disclosure may also be configured as follows: (1) A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction, a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side, and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate, a fin portion covered by the planar portion and the buried portion of the gate electrode and forming a channel, a gate insulating film arranged between the gate electrode and the fin portion, and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than that of the fin portion, (2) The semiconductor device according to (1), wherein the protruding portion distributes impurities of a conductivity type opposite to that of the fin portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion. (2) The semiconductor device according to (1), wherein the protruding portion is shorter in height than the fin portion. (3) The semiconductor device according to (1), wherein the protruding portion is formed between a bottom of the buried portion of the gate electrode and a sidewall portion of at least one of the first device isolation portion and the second device isolation portion. (4) The semiconductor device according to (1), wherein the gate electrode has: a first buried portion formed on the first device isolation portion side of the plurality of buried portions; a second buried portion formed on the second device isolation portion side; and a third buried portion formed between the first buried portion and the second buried portion; a plurality of fin portions are formed; and a first fin portion of the plurality of fin portions is formed between the first buried portion and the third buried portion, and a second fin portion is formed between the second buried portion and the third buried portion.(5) The semiconductor device according to (1) above, wherein the first element isolation portion and the second element isolation portion are formed from the top surface portion in the thickness direction and have recessed portions into which the embedded portions of the gate electrodes are embedded. (6) The semiconductor device according to (5) above, wherein the bottoms of the recessed portions are lower than the height of the tops of the protrusions. (7) The semiconductor device according to (5) above, wherein the bottoms of the recessed portions are higher than the height of the tops of the protrusions. (8) The semiconductor device according to (1) above, further comprising a protrusion insulating film disposed between the protrusions and the gate electrode, the protrusion insulating film being thicker than the gate insulating film covering the fin portion. (9) The semiconductor device according to (8) above, wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protrusions. (10) The semiconductor device according to (8), wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, a second thickness other than the top of the convex portion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness. (11) A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portion of the gate electrode and forming a channel; a gate insulating film arranged between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than that of the fin portion; and a convex portion insulating film arranged between the convex portion and the gate electrode, The semiconductor device, wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion.(12) The semiconductor device according to (11), wherein the protrusion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protrusion. (13) The semiconductor device according to (11), wherein the protrusion insulating film has a first thickness at the top of the protrusion, a second thickness other than the top of the protrusion that is thinner than the first thickness, and gradually becomes thicker from the second thickness to the first thickness. (14) A semiconductor substrate having a first surface portion and a second surface portion located opposite to each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portion of the gate electrode and forming a channel; a gate insulating film arranged between the gate electrode and the fin portion; and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than that of the fin portion, an electronic device comprising a semiconductor device in which impurities of a conductivity type opposite to that of the fin portion are distributed in the convex portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion;(15) A semiconductor substrate having a first surface portion and a second surface portion located opposite to each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion among the plurality of element isolation portions in a planar view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portion of the gate electrode and forming a channel; a gate insulating film arranged between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion; and a convex portion insulating film arranged between the convex portion and the gate electrode, a gate insulating film covering the fin portion and a gate electrode of the field effect transistor between the sidewall portion of the first isolation portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the ... sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the first isolation portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the first isolation portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the first isolation portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the second isolation portion, the gate insulating film covering the fin portion and the sidewall portion of the(17) A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides in a thickness direction; a step of forming a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on the first surface portion side; a step of forming a recessed portion from the first surface portion of the semiconductor substrate in the thickness direction between a first element isolation portion and a second element isolation portion of the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; and a step of covering the fin portion via a gate insulating film and covering the convex portion via a convex portion insulating film thicker than the gate insulating film, and forming a gate electrode of the field effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion.

[0124] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 11-1, 11-2, 21-2, 31-2 Semiconductor device 1-1, 1-2 Photodetector device 2 Semiconductor substrate 2-1 Pixel 2a Front surface 2b Back surface 3, 3A (Metal Oxide Semiconductor) transistor 3-1 Pixel area 4-1 Vertical drive circuit 5 Element isolation section 5-1 Column signal processing circuit 6-1 Horizontal drive circuit 7-1 Output circuit 8-1 Control circuit 9-1 Vertical signal line 10 Fin section 11 First fin section 12 Second fin section 10-1 Horizontal signal line 10-2 First substrate 12-2 Sensor pixel 13-2 Pixel area 20 Gate insulating film 20-2 Second substrate 22-2 REFERENCE SIGNS LIST 23-2 Pixel drive line 24-2 Vertical signal line 30, 30A Gate electrode 30-2 Third substrate 32-2 Logic circuit 33-2 Vertical drive circuit 34-2 Column signal processing circuit 35-2 Horizontal drive circuit 36-2 System control circuit 41 Source region 42 Drain region 51 First element isolation portion 51a, 52a Top surface portion 51b, 52b Side wall portion 51c, 52c, 51d, 52d, 641, 642 Engraved portion 52 Second element isolation portion 61 Second conductivity type region 621, 622 Convex portion 63 High concentration second conductivity type region 71, 91, 92 Convex portion insulating film 81 Antireflection film 821, 822 Trench 1010 Electronic device 1020 Optical system 1030 Photodetector 1050 Display device 1060 Operation system 1070 Bus 1080 Memory 1090 Recording device 1100 Power supply system 10402 Imaging unit 11000 Endoscopic surgery system 11100 Endoscope 11101 Optical tube 11102 Camera head 11110 Surgical tool 11111 Insufflation tube 11112 Energy treatment tool 11120 Support arm device 11131 Surgeon (doctor) 11132 Patient 11133 Patient bed 11200 Cart 11201 Camera control unit (CCU: Camera Control Unit) 11202 Display device 11203 Light source device 11204 Input device 11205 Treatment tool control device 11206 Insufflation device 11207 Recorder 11208 Printer 11400 Transmission cable 11401 Lens unit 11402,12031 Imaging unit 11403 Driving unit 11404, 11411 Communication unit 11405 Camera head control unit 11412 Image processing unit 11413 Control unit 12000 Vehicle control system 12001 Communication network 12010 Drive system control unit 12020 Body system control unit 12030 Outside vehicle information detection unit 12040 Inside vehicle information detection unit 12041 Driver state detection unit 12050 Integrated control unit 12051 Microcomputer 12052 Audio / image output unit 12061 Audio speaker 12062 Display unit 12063 Instrument panel 12100 Vehicle 12101, 12102, 12103, 12104, 12105 Imaging unit 12111, 12112, 12113, 12114 Imaging range,

Claims

1. A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides to each other in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, the field effect transistor having: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portions of the gate electrode and forming a channel; a gate insulating film disposed between the gate electrode and the fin portion; and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion, the convex portion having a width narrower than that of the fin portion, a first conductive type impurity having a conductivity type opposite to that of the fin portion is distributed in the protruding portion at a higher concentration than impurities contained inside the semiconductor substrate other than the protruding portion; 2. The semiconductor device according to claim 1, wherein the protrusion is shorter in height than the fin portion.

3. The semiconductor device according to claim 1, wherein said convex portion is formed between a bottom of said buried portion of said gate electrode and at least one of the sidewall portions of said first element isolation portion and said second element isolation portion.

4. The semiconductor device of claim 1, wherein the gate electrode has a first buried portion formed on a first element isolation portion side of the plurality of buried portions, a second buried portion formed on a second element isolation portion side, and a third buried portion formed between the first buried portion and the second buried portion, and wherein a plurality of the fin portions are formed, and a first fin portion of the plurality of fin portions is formed between the first buried portion and the third buried portion, and a second fin portion is formed between the second buried portion and the third buried portion.

5. The semiconductor device according to claim 1, wherein said first element isolation portion and said second element isolation portion are formed in said thickness direction from said upper surface portion and have a recessed portion into which said buried portion of said gate electrode is buried.

6. The semiconductor device according to claim 5, wherein the bottom of said recessed portion is lower than the height of the top of said protruding portion.

7. The semiconductor device according to claim 5, wherein the bottom of said recessed portion is higher than the top of said protruding portion.

8. The semiconductor device according to claim 1, further comprising a convex insulating film disposed between said convex portion and said gate electrode, said convex insulating film being thicker than said gate insulating film covering said fin portion.

9. The semiconductor device according to claim 8, wherein the protruding portion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protruding portion.

10. The semiconductor device described in claim 8, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, and a second thickness thinner than the first thickness outside the top of the convex portion, and gradually becomes thicker from the second thickness to the first thickness.

11. A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides to each other in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portions of the gate electrode and forming a channel; a gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, The protrusion insulating film is thicker than the gate insulating film covering the fin portion.

12. The semiconductor device according to claim 11, wherein the protruding portion insulating film is thicker than the gate insulating film covering the fin portion by at least 1 nm around the entire periphery of the protruding portion.

13. The semiconductor device according to claim 11, wherein the insulating film for the convex portion has a first thickness at the top of the convex portion, and a second thickness thinner than the first thickness outside the top of the convex portion, and gradually becomes thicker from the second thickness to the first thickness.

14. A semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portions of the gate electrode and forming a channel; a gate insulating film disposed between the gate electrode and the fin portion; and a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion, an impurity having a conductivity type opposite to that of the fin portion is distributed in the protrusion at a higher concentration than the impurity contained inside the semiconductor substrate other than the protrusion; 15. A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides to each other in a thickness direction; a plurality of element isolation portions extending in a thickness direction of the semiconductor substrate and each having an upper surface portion and a sidewall portion provided on the first surface portion side; and a field effect transistor provided between an upper surface portion of the first element isolation portion and an upper surface portion of the second element isolation portion among the plurality of element isolation portions in a plan view, wherein the field effect transistor has: a gate electrode having a planar portion formed in a planar manner on the first surface portion of the semiconductor substrate and one or more buried portions buried from the planar portion toward the inside of the semiconductor substrate; a fin portion covered by the planar portion and the buried portions of the gate electrode and forming a channel; a gate insulating film disposed between the gate electrode and the fin portion; a convex portion formed between the buried portion of the gate electrode and at least one sidewall portion of the first element isolation portion and the second element isolation portion and having a width narrower than that of the fin portion; and a convex portion insulating film disposed between the convex portion and the gate electrode, The electronic device includes a semiconductor device, wherein the protrusion insulating film is thicker than the gate insulating film that covers the fin portion.

16. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; forming a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each having a top surface portion and a sidewall portion provided on the first surface portion side; forming a recessed portion in the thickness direction from the first surface portion of the semiconductor substrate between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a width narrower than that of the fin portion; distributing impurities of a conductivity type opposite to that of the fin portion in the convex portion at a higher concentration than impurities contained inside the semiconductor substrate other than the convex portion; covering the fin portion via a gate insulating film, and forming a gate electrode of the field effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion.

17. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; forming a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each having an upper surface portion and a sidewall portion provided on the first surface portion side; forming a recessed portion from the first surface portion of the semiconductor substrate in the thickness direction between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and forming a fin portion of a field effect transistor protruding from the recessed portion and a convex portion having a narrower width than the fin portion; covering the fin portion via a gate insulating film and covering the convex portion via a convex portion insulating film thicker than the gate insulating film, and forming a gate electrode of the field effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion.

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