Semiconductor device

Abstract

Provided is a semiconductor device comprising: a plurality of trench portions arranged in a predetermined arrangement direction on a front surface side of a semiconductor substrate, the plurality of trench portions having a repeating structure in which a gate trench portion and a dummy trench portion are repeated at predetermined intervals in the arrangement direction; a first conductivity type drift region provided on the semiconductor substrate; a second conductivity type base region provided above the drift region; a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region; and a second conductivity type trench bottom region provided below the gate trench portion and having a doping concentration lower than that of the base region. The trench bottom region is provided below the emitter region, and the length of the trench bottom region in the arrangement direction is shorter than the length of the repeating structure.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes an "IGBT with dV / dt controllability." [Prior art documents] [Patent documents] [Patent document 1] JP 2019-91892 A [Patent document 2] JP 2004-6647 A [Patent document 3] JP 2015-195307 A [Patent document 4] JP 2019-110288 A [Patent document 5] WO 2022 / 158053 [Patent document 6] Japanese Patent No. 6472714 General disclosure

[0003] An aspect of the present invention provides a semiconductor device comprising: a plurality of trench portions arranged in a predetermined arrangement direction on a front surface side of a semiconductor substrate, the plurality of trench portions having a repeating structure in which gate trench portions and dummy trench portions are repeated at a predetermined period in the arrangement direction; a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; and a trench bottom region of the second conductivity type provided below the gate trench portions and having a doping concentration lower than that of the base region, wherein the trench bottom region is provided below the emitter region, and the length of the trench bottom region in the arrangement direction is shorter than the length of the repeating structure.

[0004] In the semiconductor device, the trench bottom region may be in contact with the gate trench portion.

[0005] In any of the above semiconductor devices, the trench bottom region may be in contact with the dummy trench portion adjacent to the gate trench portion.

[0006] Any of the above semiconductor devices may include a trench-bottom forming region in which the trench bottom region is formed when viewed from above. Any of the above semiconductor devices may include a trench-bottom non-forming region in which the trench bottom region is not formed when viewed from above.

[0007] In any of the above semiconductor devices, the trench bottom formation region may cover the emitter region provided in contact with the gate trench portion in a top view.

[0008] In any of the above semiconductor devices, the emitter regions and the contact regions may be repeatedly arranged in a mesa portion adjacent to the gate trench portion in an extension direction of the plurality of trench portions, and the trench bottom formation region may be provided in the mesa portion adjacent to the gate trench portion, extending in the extension direction, and may cover the emitter region provided in contact with the gate trench portion in a top view.

[0009] In any of the above semiconductor devices, when viewed from above, the distance between the end edge in the extension direction of the emitter region that is located outermost in the extension direction and the end edge in the extension direction of the trench bottom formation region may be 1.0 μm or more and 10.0 μm or less.

[0010] In any of the above semiconductor devices, the emitter region may be provided in a mesa portion adjacent to the gate trench portion, extending in the extension direction of the plurality of trench portions, in contact with the gate trench portion but not in contact with the dummy trench portion, and the trench bottom formation region may be provided in a mesa portion adjacent to the gate trench portion, extending in the extension direction, and may cover the emitter region provided in contact with the gate trench portion in top view.

[0011] In any of the above semiconductor devices, the distance between an end edge of the emitter region in the extension direction and an end edge of the trench bottom formation region covering the emitter region in the extension direction may be 1.0 μm or more and 5.0 μm or less when viewed from above.

[0012] In any of the above semiconductor devices, the emitter regions and the contact regions may be repeatedly arranged in a mesa portion adjacent to the gate trench portion in an extension direction of the plurality of trench portions. The trench bottom-forming regions and the trench bottom non-forming regions may be repeatedly arranged in the extension direction in the mesa portion adjacent to the gate trench portion. The repeatedly arranged trench bottom-forming regions may cover the repeatedly arranged emitter regions in a top view.

[0013] In any of the above semiconductor devices, the distance between an end edge of the emitter region in the extension direction and an end edge of the trench bottom formation region covering the emitter region in the extension direction may be 1.0 μm or more and 2.5 μm or less when viewed from above.

[0014] In any of the semiconductor devices described above, the plurality of trenches may include two adjacent dummy trenches, and a mesa portion sandwiched between the two dummy trenches may be the trench-bottom-free region.

[0015] In any of the above semiconductor devices, the emitter region may also be provided in a mesa portion sandwiched between the two dummy trench portions, and the trench-bottom non-forming region may cover the emitter region provided in the mesa portion sandwiched between the two dummy trench portions in top view.

[0016] In any of the above semiconductor devices, the plurality of trench portions may have the repeating structure in which the dummy trench portion, the gate trench portion, and the dummy trench portion are repeated in this order in the arrangement direction.

[0017] In any of the above semiconductor devices, the multiple trench portions may have a repeating structure in which the dummy trench portion, the dummy trench portion, the gate trench portion, the gate trench portion, the dummy trench portion, and the dummy trench portion are repeated in this order in the arrangement direction.

[0018] In any of the above semiconductor devices, the doping concentration of the trench bottom region may be 1% or more and 10% or less of the doping concentration of the base region.

[0019] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0020] 1A shows an example of the top surface of the semiconductor device 100. 1B shows an example of region R in FIG. 1. 2B shows an example of a-a' cross section in FIG. 2A. 3B shows region R in a modified example of the semiconductor device 100. 4B shows an example of a-b' cross section in FIG. 4A. 5B shows region R in a modified example of the semiconductor device 100. 6B shows region R in a modified example of the semiconductor device 100. 7B shows region R in a modified example of the semiconductor device 100. 8B shows an example of a-d-d' cross section in FIG. 8A.

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0023] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0024] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0025] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0026] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0027] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0028] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, in this specification, when P++ type or N++ type is described, it means that the doping concentration is higher than that of P+ type or N+ type, and when P-- type or N-- type is described, it means that the doping concentration is higher than that of P- type or N- type.

[0029] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in the region. When the concentration of the donor, acceptor, or net doping is approximately uniform, the average value of the concentration of the donor, acceptor, or net doping in the region may be taken as the concentration of the donor, acceptor, or net doping.

[0030] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0031] This specification uses the SI unit system. In this specification, distance and length units may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 １６ , and the display of 1E-16 is 1×10 －１６ Shows.

[0032] 1 shows an example of the top surface of a semiconductor device 100. The semiconductor device 100 of this example includes a gate wiring section 50, a gate pad 112, an active section 120, and an edge termination structure section 140.

[0033] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. In this example, the semiconductor substrate 10 is a silicon substrate. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has an edge 102. Furthermore, the semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.

[0034] The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is not shown in the figure.

[0035] The gate pad 112 is provided above the semiconductor substrate 10. A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate trench portion 40 of the active portion 120. The gate trench portion 40 will be described later.

[0036] The gate wiring section 50 is provided closer to the edge 102 of the semiconductor substrate 10 than the active section 120 in a top view. The gate wiring section 50 connects the gate pad 112 and the gate trench section 40.

[0037] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided closer to the edge 102 of the semiconductor substrate 10 than the gate wiring portion 50. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf provided in an annular shape surrounding the active portion 120.

[0038] 2A shows an example of region R in FIG. 1. The semiconductor device 100 may be configured by repeatedly arranging the configuration shown in this figure in the positive and negative directions of the X-axis. However, as shown in FIG. 1, gate wiring section 50 and edge termination structure section 140 may be provided at the ends in the positive and negative directions of the X-axis.

[0039] The semiconductor device 100 may include a transistor such as an IGBT. In this example, the semiconductor device 100 is an IGBT. The semiconductor device 100 may be a reverse blocking or reverse conducting IGBT, or may be another transistor such as a MOSFET.

[0040] The semiconductor device 100 of this example includes a dummy trench portion 30, a gate trench portion 40, a gate wiring portion 50, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example includes an emitter electrode 52 provided above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example also includes a trench bottom region 60 provided below the gate trench portion 40. The trench bottom region 60 is a region that is not exposed on the front surface 21 of the semiconductor substrate 10, but in this figure, the region where the trench bottom region 60 is provided is indicated by diagonal lines when viewed from above.

[0041] The emitter electrode 52 and the gate wiring portion 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in FIG. 2A . A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38. The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate wiring portion 50 is provided above the well region 17.

[0042] The emitter electrode 52 and the gate wiring portion 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate wiring portion 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate wiring portion 50 may have a barrier metal layer made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate wiring portion 50 are provided separately from each other.

[0043] The contact holes 54 are formed above the emitter regions 12 and the contact regions 15 in the active portion 120. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided extending in the extension direction of the multiple trench portions.

[0044] The contact hole 55 electrically connects the gate wiring portion 50 and the gate conductive portion in the active portion 120 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0045] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0046] The connection portion 25 is connected to the emitter electrode 52 or the gate wiring portion 50. In one example, the connection portion 25 is provided between the gate wiring portion 50 and the gate conductive portion. The connection portion 25 in this example may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0047] The dummy trenches 30 are provided on the front surface 21 side of the semiconductor substrate 10. The dummy trenches 30 are arranged on the front surface 21 side of the semiconductor substrate 10 in a predetermined arrangement direction (in this example, the X-axis direction). The dummy trenches 30 are trenches electrically connected to the emitter electrode 52. The dummy trenches 30 may have two extension portions 31 that extend parallel to the front surface 21 of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the Y-axis direction), and a connection portion 33 that connects the two extension portions 31.

[0048] It is preferable that at least a portion of the connection portion 33 is formed in a curved shape. By connecting the ends of the two extension portions 31 of the dummy trench portion 30, electric field concentration at the ends of the extension portions 31 can be alleviated.

[0049] The gate trench portion 40 is provided on the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 is arranged in a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 may have two extension portions 41 that extend parallel to the front surface 21 of the semiconductor substrate 10 and along an extension direction (the Y-axis direction in this example) that is perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0050] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, electric field concentration at the ends of the extension portions 41 can be alleviated.

[0051] The semiconductor device 100 of this example includes a plurality of trenches arranged in a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 side of the semiconductor substrate 10. The plurality of trenches have a repeating structure in which gate trenches 40 and dummy trenches 30 are repeated at a predetermined cycle in the arrangement direction.

[0052] The multiple trenches in this example have a repeating structure in which dummy trenches 30, gate trenches 40, and dummy trenches 30 are repeated in this order in the arrangement direction (the X-axis direction in this example). That is, the semiconductor device 100 in this example has gate trenches 40 and dummy trenches 30 in a ratio of 1:2.

[0053] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be the same as the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1, 1:5, or 3:2.

[0054] The period of the repeating structure of the multiple trench portions may be determined based on the repetition of the extension portions 41 of the gate trench portion 40 and the extension portions 31 of the dummy trench portion 30. For example, the semiconductor device 100 of this example has a repeating structure made up of a loop-shaped gate trench portion 40, a loop-shaped dummy trench portion 30 surrounded by the loop-shaped gate trench portion 40, and a loop-shaped dummy trench portion 30 not surrounded by the loop-shaped gate trench portion 40, and has a period made up of six extension portions. On the other hand, when focusing only on the extension portions, the semiconductor device 100 has a repeating structure in which the dummy trench portion 30, the gate trench portion 40, and the dummy trench portion 30 are repeated in this order, and has a period made up of three extension portions.

[0055] In this way, the period of the repeating structure of the multiple trench portions may be the minimum period of the repeating structure of the extended portions of the multiple trench portions. That is, the length of the repeating structure of the multiple trench portions in this example is the length Wp shown in the figure.

[0056] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion.

[0057] The mesa portion 71 is provided in the active portion 120 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10.

[0058] The base region 14 is a region of a second conductivity type provided above a drift region 18, which will be described later. In this example, the base region 14 is, for example, a P-type.

[0059] The emitter region 12 is a first conductivity type region provided above the base region 14 and having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions to the other. The emitter region 12 is also provided below the contact hole 54. A high-concentration portion having a doping concentration higher than other portions may be provided in the portion of the emitter region 12 exposed below the contact hole 54.

[0060] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0061] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is of P+ type, for example. The contact region 15 in this example is provided on the front surface 21. The contact region 15 may be provided in the X-axis direction from one of the two trench portions to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. A high-concentration portion having a higher doping concentration than other portions may be provided in the portion of the contact region 15 exposed below the contact hole 54.

[0062] The emitter regions 12 and the contact regions 15 may be repeatedly arranged in the extension direction of the multiple trench portions (the Y-axis direction in this example) in the mesa portion 71 adjacent to the gate trench portion 40. The emitter regions 12 and the contact regions 15 may also be repeatedly arranged in the extension direction of the multiple trench portions in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. In this example, the emitter regions 12 and the contact regions 15 are repeatedly arranged in the extension direction of the multiple trench portions in all of the mesa portions 71 shown in the figure.

[0063] The well region 17 is a region of a second conductivity type provided above the drift region 18. In this example, the well region 17 is, for example, a P+ type. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30.

[0064] The trench bottom region 60 is a second conductivity type region provided below the gate trench portion 40 and having a lower doping concentration than the base region 14. In this example, the trench bottom region 60 is, for example, P-- type. The doping concentration of the trench bottom region 60 may be 1% or more and 10% or less of the doping concentration of the base region 14. By providing the trench bottom region 60, the gate-collector capacitance can be increased, and dV / dt during switching can be reduced. This reduces the gate resistance when designed to have the same dV / dt value, thereby increasing dI / dt and reducing the switching loss of the semiconductor device 100.

[0065] The trench bottom region 60 may or may not be provided below the dummy trench portion 30. In this example, the trench bottom region 60 is also partially provided below the dummy trench portion 30.

[0066] When the collector-emitter voltage of the semiconductor device 100 increases, the electric field at the bottom of the gate trench 40 becomes stronger, which may cause avalanche breakdown. If avalanche breakdown occurs at the bottom of the gate trench 40, charges generated by the avalanche breakdown may be trapped in the gate insulating film, which may cause the threshold voltage Vth of the semiconductor device 100 to fluctuate. By providing a trench bottom region 60 below the gate trench 40 and partially providing a trench bottom region 60 below the dummy trench 30, avalanche breakdown can be preferentially generated in the region at the bottom of the dummy trench 30 where the trench bottom region 60 is not formed. This suppresses the occurrence of avalanche breakdown at the bottom of the gate trench 40, and suppresses fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0067] The trench bottom region 60 is provided below the emitter region 12. The trench bottom region 60 may or may not be provided below the contact region 15. In this example, the trench bottom region 60 is also provided below the contact region 15.

[0068] The semiconductor device 100 of this example includes a trench bottom forming region 62 in which the trench bottom region 60 is formed when viewed from above, and a trench bottom non-forming region 64 in which the trench bottom region 60 is not formed when viewed from above. That is, the region other than the trench bottom forming region 62 in which the trench bottom region 60 is formed when viewed from above may be the trench bottom non-forming region 64. The boundary between the trench bottom forming region 62 and the trench bottom non-forming region 64 may be the boundary between the trench bottom region 60 and another region (e.g., the drift region 18).

[0069] The trench bottom formation region 62 may cover the emitter region 12 provided in contact with the gate trench portion 40 in a top view. In this example, the trench bottom formation region 62 is provided in the mesa portion 71 adjacent to the gate trench portion 40, extending in the extension direction, and covers the emitter region 12 provided in contact with the gate trench portion 40 in a top view. A channel is formed in the emitter region 12 provided in contact with the gate trench portion 40 during operation of the semiconductor device 100. By having the trench bottom formation region 62 cover the emitter region 12 provided in contact with the gate trench portion 40 in a top view and providing the trench bottom region 60 below the emitter region 12 provided in contact with the gate trench portion 40, it is possible to suppress avalanche breakdown in the region where the channel is formed. This makes it possible to suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0070] In a top view, the distance L1 between the edge of the emitter region 12 located outermost in the extension direction and the edge of the trench bottom formation region 62 in the extension direction may be 1.0 μm or more and 10.0 μm or less. That is, the trench bottom formation region 62 extending in the extension direction may extend beyond the emitter region 12 located outermost in the extension direction by the distance L1. By extending the trench bottom formation region 62 beyond the emitter region 12 in this manner, the trench bottom formation region 62 can reliably cover the emitter region 12. This suppresses avalanche breakdown in the region where a channel is formed, thereby suppressing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0071] The plurality of trench portions in this example include two adjacent dummy trench portions 30. The mesa portion 71 sandwiched between the two adjacent dummy trench portions 30 may be a trench bottom non-forming region 64.

[0072] In this example, the emitter region 12 is also provided in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. In top view, the trench bottom non-forming region 64 may cover the emitter region 12 provided in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. In other words, the trench bottom region 60 does not need to be formed below the emitter region 12 provided in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30 and in which no channel is formed.

[0073] The length Wt of the trench bottom region 60 in the arrangement direction (the X-axis direction in this example) is shorter than the length Wp of the repeating structure of the multiple trench portions. That is, a trench bottom forming region 62 and a trench bottom non-forming region 64 may be provided within one period of the repeating structure of the multiple trench portions. In this way, the trench bottom forming region 62 may be provided surrounded by the trench bottom non-forming region 64.

[0074] When avalanche breakdown occurs at the bottom of the trench, a current filament may be generated due to positive feedback of the avalanche breakdown. As a result, a local temperature rise occurs, which suppresses the avalanche breakdown and causes the current filament to move. If the location where the current filament is generated is surrounded by the trench bottom formation region 62, the movement of the current filament is inhibited, leading to a further temperature rise and the risk of destroying the semiconductor device 100. In the semiconductor device 100 of this example, the trench bottom formation region 62 is surrounded by the trench bottom non-formation region 64, so the movement of the current filament is not inhibited and destruction of the semiconductor device 100 can be suppressed.

[0075] 2B shows an example of the aa' cross section in Fig. 2A. The aa' cross section is an XZ plane that passes through the emitter region 12 in the active portion 120. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0076] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0077] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 may be higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0078] The collector region 22 is provided below the buffer region 20. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0079] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. In this example, the accumulation region 16 is in contact with the dummy trench portion 30. In this example, the accumulation region 16 is, for example, an N+ type. The doping concentration of the accumulation region 16 may be higher than the doping concentration of the drift region 18. The dose of ion implantation of the accumulation region 16 is 1.0E+12 cm －２ Above, 3.0E + 13cm －２ By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the semiconductor device 100 can be reduced.

[0080] The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30. The emitter region 12 is provided between the base region 14 and the front surface 21.

[0081] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating each region does not necessarily mean that the trench portion is formed in the order of forming each region and then forming the trench portion. The trench portion penetrating each region also includes a case where the trench portion is formed first and then each region is formed between the trench portions.

[0082] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0083] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0084] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0085] The trench bottom region 60 may be in contact with the gate trench portion 40. By having the trench bottom region 60 in contact with the gate trench portion 40, it is possible to suppress the occurrence of avalanche breakdown at the bottom of the gate trench portion 40 and suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0086] The trench bottom region 60 may be in contact with the dummy trench portion 30 adjacent to the gate trench portion 40. By having the trench bottom region 60 in contact with the dummy trench portion 30, the potential of the trench bottom region 60 can be fixed to be equal to the emitter potential, thereby improving the switching loss reduction characteristics of the semiconductor device 100. The trench bottom region 60 may be in partial contact with the dummy trench portion 30. By having the trench bottom region 60 in partial contact with the dummy trench portion 30, avalanche breakdown can be preferentially generated in a region at the bottom of the dummy trench portion 30 where the trench bottom region 60 is not formed. This suppresses the occurrence of avalanche breakdown at the bottom of the gate trench portion 40 and suppresses fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0087] The trench bottom region 60 may be formed by implanting ions of the second conductivity type into the bottom of the gate trench portion 40 and thermally diffusing them. That is, the concentration of the trench bottom region 60 may be high near the bottom of the gate trench portion 40 and decrease with increasing distance from the bottom of the gate trench portion 40. However, the method for forming the trench bottom region 60 is not limited to this. The trench bottom region 60 may be formed by implanting ions of the second conductivity type at a high acceleration rate from the front surface 21 of the semiconductor substrate 10, and may have a substantially uniform concentration.

[0088] The back side lifetime control region 151 may be provided in the active portion 120. However, the back side lifetime control region 151 may be omitted. The back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons. By providing the back side lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0089] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams or protons may be used to form the lattice defects.

[0090] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0091] The back surface side lifetime control region 151 is provided closer to the back surface 23 than the center of the drift region 18 in the depth direction of the semiconductor substrate 10. The back surface side lifetime control region 151 in this example is provided in the buffer region 20. The back surface side lifetime control region 151 in this example is provided over the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The back surface side lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the back surface side lifetime control region 151 is 0.5E+10 cm －２ Above, 1.0E+14cm －２ Even if it is less than 5.0E+10cm －２ Above, 1.0E+13cm －２ It may be the following:

[0092] The back surface-side lifetime control region 151 may be formed by implantation from the back surface 23 side. This makes it easier to avoid any influence on the front surface 21 side of the semiconductor device 100. For example, the back surface-side lifetime control region 151 is formed by irradiating helium or protons from the back surface 23 side. Here, whether the back surface-side lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by acquiring the state of the front surface 21 side by the SR method or by measuring leakage current.

[0093] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 and the semiconductor substrate 10. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0094] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO) film.

[0095] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. At least a portion of the collector electrode 24 may be made of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The collector electrode 24 may have a barrier metal made of titanium or a titanium compound on the semiconductor substrate 10 side of the region made of aluminum or the like.

[0096] 3 shows a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 2A in that trench bottom forming regions 62 and trench bottom non-forming regions 64 are repeatedly arranged in the extension direction in a mesa portion 71 adjacent to the gate trench portion 40. In this example, differences from the embodiment of FIG. 2A will be particularly described, and the rest may be the same as the embodiment of FIG. 2A.

[0097] The emitter regions 12 and the contact regions 15 may be repeatedly arranged in the extension direction of the multiple trench portions (the Y-axis direction in this example) in the mesa portion 71 adjacent to the gate trench portion 40. The trench bottom forming regions 62 and the trench bottom non-forming regions 64 may be repeatedly arranged in the extension direction in the mesa portion 71 adjacent to the gate trench portion 40. The repeatedly arranged trench bottom forming regions 62 may cover the repeatedly arranged emitter regions 12 in a top view. That is, the end of the trench bottom region 60 in the Y-axis direction may be below the contact region 15. By having the trench bottom forming region 62 cover the emitter region 12 in a top view, it is possible to suppress avalanche breakdown in the region where a channel is formed, and thus to suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0098] In a top view, the distance L2 between an end edge of the emitter region 12 in the extension direction and an end edge of the trench bottom formation region 62 covering the emitter region 12 in the extension direction may be 1.0 μm or more and 2.5 μm or less. That is, the trench bottom formation regions 62 repeatedly arranged in the extension direction may be provided so as to protrude by the distance L2 from the emitter region 12 that the trench bottom formation region 62 covers. By providing the trench bottom formation region 62 so that it protrudes from the emitter region 12 in this manner, the trench bottom formation region 62 can reliably cover the emitter region 12. This suppresses avalanche breakdown in the region where a channel is formed, and suppresses fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0099] 4A shows a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 2A in that the repeated structure of the multiple trench portions is different. In this example, differences from the embodiment of FIG. 2A will be particularly described, and the rest may be the same as the embodiment of FIG. 2A.

[0100] The multiple trenches in this example have a repeating structure in which dummy trenches 30, dummy trenches 30, gate trenches 40, gate trenches 40, dummy trenches 30, and dummy trenches 30 are repeated in this order in the arrangement direction (the X-axis direction in this example). That is, the semiconductor device 100 in this example has gate trenches 40 and dummy trenches 30 in a ratio of 2:4.

[0101] The contact hole 54 in this example is also provided in the mesa portion 71 sandwiched between the two gate trench portions 40. The contact hole 54 does not have to be provided in the mesa portion 71 sandwiched between the two gate trench portions 40. When the contact hole 54 is not provided in the mesa portion 71 sandwiched between the two gate trench portions 40, the mesa portion 71 may be a floating region.

[0102] The emitter region 12 in this example is also provided in the mesa portion 71 sandwiched between the two gate trench portions 40. The emitter region 12 does not necessarily have to be provided in the mesa portion 71 sandwiched between the two gate trench portions 40.

[0103] 4B shows an example of the bb' cross section in FIG. 4A. The bb' cross section is an XZ plane passing through the emitter region 12 in the active section 120. In this example, differences from the embodiment in FIG. 2B will be particularly described, and the rest may be the same as the embodiment in FIG. 2B.

[0104] The trench bottom region 60 may be in contact with the dummy trench portion 30 adjacent to the gate trench portion 40, but may not be in contact with the dummy trench portion 30 not adjacent to the gate trench portion 40. In other words, the semiconductor device 100 may have a dummy trench portion 30 in the bottom of which the trench bottom region 60 is not formed. This allows avalanche breakdown to occur preferentially in the dummy trench portion 30 in the bottom of which the trench bottom region 60 is not formed, thereby suppressing the occurrence of avalanche breakdown at the bottom of the gate trench portion 40 and suppressing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0105] In this example, the trench bottom region 60 is provided integrally from the dummy trench portion 30a adjacent to one gate trench portion 40a of two adjacent gate trench portions 40 to the dummy trench portion 30b adjacent to the other gate trench portion 40b. That is, the trench bottom region 60 may be provided integrally by overlapping the region where the second conductivity type ions implanted into the bottom of the gate trench portion 40a undergo thermal diffusion with the region where the second conductivity type ions implanted into the bottom of the gate trench portion 40b undergo thermal diffusion. However, the two adjacent gate trench portions 40 may be provided apart by a distance equal to or greater than the diffusion length of the second conductivity type ions, so that the trench bottom region 60 is formed at the bottom of each gate trench portion 40.

[0106] 5 shows a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 4A in that trench bottom forming regions 62 and trench bottom non-forming regions 64 are repeatedly arranged in the extension direction in the mesa portion 71 adjacent to the gate trench portion 40. The rest of the semiconductor device 100 may be the same as the embodiment of FIG. 4A. Furthermore, the repeatedly arranged trench bottom forming regions 62 and trench bottom non-forming regions 64 may be the same as the embodiment of FIG. 3.

[0107] 6A shows region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 4A in that the emitter region 12 and the contact hole 54 are not provided in the mesa portion 71 sandwiched between two gate trench portions 40. In this example, differences from the embodiment of FIG. 4A will be particularly described, and the rest may be the same as the embodiment of FIG. 4A.

[0108] In this example, the mesa portion 71 sandwiched between two adjacent gate trench portions 40 does not have a contact hole 54. Therefore, in this example, the mesa portion 71 sandwiched between two adjacent gate trench portions 40 is a floating region. However, a contact hole 54 may be provided in the mesa portion 71 sandwiched between two adjacent gate trench portions 40, and the mesa portion 71 may be connected to the emitter electrode 52 via the contact hole 54, so that the mesa portion 71 has a hole extraction function. Furthermore, as shown in FIG. 4A , the mesa portion 71 may function as a region in which a channel is formed by providing an emitter region 12 and a contact hole 54.

[0109] 6B shows an example of the cc' cross section in Fig. 6A. The cc' cross section is an XZ plane passing through the emitter region 12 in the active portion 120. In this example, differences from the embodiment in Fig. 4B will be particularly described, and the rest may be the same as the embodiment in Fig. 4B.

[0110] The trench bottom region 60 in this example is also provided below a mesa portion 71 sandwiched between two adjacent gate trench portions 40 in which no emitter region 12 is provided. By providing two adjacent gate trench portions 40 at a distance equal to or greater than the diffusion length of ions of the second conductivity type, the trench bottom region 60 does not need to be provided below the mesa portion 71 sandwiched between two adjacent gate trench portions 40. In other words, no emitter region 12 is provided in the mesa portion 71 sandwiched between two adjacent gate trench portions 40 in this example, and therefore no channel is formed during operation of the semiconductor device 100, and therefore the trench bottom region 60 does not need to be provided below the mesa portion 71.

[0111] 7 shows a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 6A in that trench bottom forming regions 62 and trench bottom non-forming regions 64 are repeatedly arranged in the extension direction in the mesa portion 71 adjacent to the gate trench portion 40. The rest of the semiconductor device 100 may be the same as the embodiment of FIG. 6A. Furthermore, the repeatedly arranged trench bottom forming regions 62 and trench bottom non-forming regions 64 may be the same as the embodiments of FIGS. 3 and 5.

[0112] 8A shows region R in a modified example of semiconductor device 100. Semiconductor device 100 of this example differs from the embodiment of FIG. 2A in that emitter region 12 is provided extending in the extension direction. In this example, differences from the embodiment of FIG. 2A will be particularly described, and the rest may be the same as the embodiment of FIG. 2A.

[0113] The emitter region 12 may be provided in the mesa portion 71 adjacent to the gate trench portion 40, in contact with the gate trench portion 40, but not in contact with the dummy trench portion 30, and extending in the extension direction of the multiple trench portions (the Y-axis direction in this example). The trench bottom formation region 62 may be provided in the mesa portion 71 adjacent to the gate trench portion 40, in contact with the extension direction, and may cover the emitter region 12 provided in contact with the gate trench portion 40 in a top view. By having the trench bottom formation region 62 cover the emitter region 12 in a top view, it is possible to suppress avalanche breakdown in a region where a channel is formed, and to suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0114] In a top view, a distance L3 between an end edge of the emitter region 12 in the extension direction and an end edge of the trench bottom formation region 62 covering the emitter region 12 in the extension direction may be 1.0 μm or more and 5.0 μm or less. That is, the trench bottom formation region 62 extending in the extension direction may be provided so as to protrude by the distance L3 from the emitter region 12 also extending in the extension direction. By providing the trench bottom formation region 62 so as to protrude from the emitter region 12 in this manner, the trench bottom formation region 62 can reliably cover the emitter region 12. This suppresses avalanche breakdown in the region where a channel is formed, and suppresses fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0115] 8B shows an example of the dd' cross section in Fig. 8A. The dd' cross section is an XZ plane passing through the emitter region 12 in the active section 120. In this example, differences from the embodiment in Fig. 2B will be particularly described, and the rest may be the same as the embodiment in Fig. 2B.

[0116] In the mesa portion 71 adjacent to the gate trench portion 40, the contact hole 54 may be provided above the emitter region 12 and the contact region 15. In other words, the boundary between the emitter region 12 and the contact region 15 may be located below the contact hole 54.

[0117] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0118] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0119] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate wiring portion, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 60...Trench bottom region, 62...Trench bottom formed region, 64...Trench bottom non-formed region, 71...Mesa portion, 100...Semiconductor device, 102...Edge, 112...Gate pad, 120...Active portion, 140...Edge termination structure portion, 151...Back surface side lifetime control region

Claims

1. A semiconductor device comprising: a plurality of trench portions arranged in a predetermined arrangement direction on a front surface side of a semiconductor substrate, the plurality of trench portions having a repeating structure in which gate trench portions and dummy trench portions are repeated at a predetermined period in the arrangement direction; a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; and a trench bottom region of the second conductivity type provided below the gate trench portions and having a doping concentration lower than that of the base region, wherein the trench bottom region is provided below the emitter region, and a length of the trench bottom region in the arrangement direction is shorter than a length of the repeating structure.

2. The semiconductor device according to claim 1, wherein the trench bottom region is in contact with the gate trench portion.

3. The semiconductor device according to claim 2, wherein the trench bottom region contacts the dummy trench portion adjacent to the gate trench portion.

4. The semiconductor device according to claim 1, comprising: a trench-bottom forming region in which the trench bottom region is formed when viewed from above; and a trench-bottom non-forming region in which the trench bottom region is not formed when viewed from above.

5. The semiconductor device according to claim 4, wherein the trench bottom formation region covers the emitter region provided in contact with the gate trench portion in a top view.

6. The semiconductor device described in claim 4, wherein the emitter regions and the contact regions are repeatedly arranged in the extension direction of the multiple trench portions in a mesa portion adjacent to the gate trench portion, and the trench bottom formation region is provided extending in the extension direction in the mesa portion adjacent to the gate trench portion and covers the emitter region provided in contact with the gate trench portion in a top view.

7. The semiconductor device according to claim 6, wherein, when viewed from above, the distance between an end edge in the extension direction of the emitter region located outermost in the extension direction and an end edge in the extension direction of the trench bottom formation region is 1.0 μm or more and 10.0 μm or less.

8. The semiconductor device according to claim 4, wherein the emitter region is provided in a mesa portion adjacent to the gate trench portion, in contact with the gate trench portion, but not in contact with the dummy trench portion, and extends in the extension direction of the multiple trench portions; and the trench bottom formation region is provided in a mesa portion adjacent to the gate trench portion, extending in the extension direction, and covers the emitter region provided in contact with the gate trench portion in a top view.

9. The semiconductor device according to claim 8, wherein, when viewed from above, the distance between an end edge of the emitter region in the extension direction and an end edge of the trench bottom formation region covering the emitter region in the extension direction is 1.0 μm or more and 5.0 μm or less.

10. The semiconductor device described in claim 4, wherein the emitter regions and the contact regions are repeatedly arranged in the extension direction of the multiple trench portions in a mesa portion adjacent to the gate trench portion, the trench bottom forming regions and the trench bottom non-forming regions are repeatedly arranged in the extension direction in a mesa portion adjacent to the gate trench portion, and the repeatedly arranged trench bottom forming regions cover the repeatedly arranged emitter regions when viewed from above.

11. The semiconductor device according to claim 10, wherein, when viewed from above, the distance between an end edge of the emitter region in the extension direction and an end edge of the trench bottom formation region covering the emitter region in the extension direction is 1.0 μm or more and 2.5 μm or less.

12. The semiconductor device according to claim 4, wherein the plurality of trench portions include two adjacent dummy trench portions, and a mesa portion sandwiched between the two dummy trench portions is the trench bottom non-forming region.

13. The semiconductor device according to claim 12, wherein the emitter region is also provided in a mesa portion sandwiched between the two dummy trench portions, and the trench bottom non-forming region covers the emitter region provided in the mesa portion sandwiched between the two dummy trench portions when viewed from above.

14. A semiconductor device according to any one of claims 1 to 13, wherein the plurality of trench portions have a repeating structure in which the dummy trench portion, the gate trench portion, and the dummy trench portion are repeated in this order in the arrangement direction.

15. A semiconductor device according to any one of claims 1 to 13, wherein the plurality of trench portions have a repeating structure in which the dummy trench portion, the dummy trench portion, the gate trench portion, the gate trench portion, the dummy trench portion, and the dummy trench portion are repeated in this order in the arrangement direction.

16. The semiconductor device according to claim 1, wherein the doping concentration of the trench bottom region is 1% or more and 10% or less of the doping concentration of the base region.

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