Thin film transistor and manufacturing method therefor, and display panel

Abstract

The present disclosure provides a thin film transistor and a manufacturing method therefor, an array substrate, and a display panel. The thin film transistor comprises a substrate, and an active layer and a first gate electrode which are located on the substrate. The active layer comprises a first film layer and a second film layer which are stacked on the substrate; the second film layer is located between the first film layer and the first gate electrode; the first film layer and the second film layer are semiconductor film layers; the mobility of the second film layer is lower than that of the first film layer; and the roughness of the second film layer is less than that of the first film layer.

Description

Thin film transistor, manufacturing method thereof, and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311219272.6, filed on September 20, 2023, entitled “Thin Film Transistor, Method for Making the Same, and Display Panel,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, and a display panel. Background Art

[0004] With the development of information technology, electronic display products are increasingly used in daily life. Thin-film transistors (TFTs) are the primary switching elements in the drive circuits of these electronic display products. However, the active layers of current TFTs, limited by their structural design and fabrication processes, struggle to maintain both high mobility and stability while ensuring effective film formation. This, in turn, limits further improvements in TFT performance.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a thin film transistor is provided. The thin film transistor includes a substrate, an active layer located on the substrate, and a first gate electrode. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer being located between the first film layer and the first gate electrode. The first film layer and the second film layer are semiconductor film layers. The mobility of the second film layer is lower than that of the first film layer, and the roughness of the second film layer is lower than that of the first film layer.

[0007] In the above scheme, the first film layer has a relatively high mobility. Therefore, when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with high roughness can improve the surface to avoid surface defects, thereby reducing the leakage current of the thin film transistor and improving the performance of the thin film transistor.

[0008] A second aspect of the present disclosure provides a display panel, which includes the thin film transistor according to the first aspect.

[0009] A third aspect of the present disclosure provides a method for preparing a thin film transistor, which includes: providing a substrate; depositing a first semiconductor material film layer having a first mobility on the substrate at a first film formation rate, and depositing a second semiconductor material film layer having a second mobility at a second film formation rate, wherein the first mobility is greater than the second mobility, and the first film formation rate is greater than the second film formation rate, so that the roughness of the second semiconductor material film layer is less than the roughness of the first semiconductor material film layer; patterning the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer, respectively; depositing a first conductive material thin film on the substrate, and composing the first conductive material thin film to form a first gate electrode, wherein the second film layer is formed between the first film layer and the first gate electrode.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a cross-sectional view of a thin film transistor provided in accordance with an embodiment of the present disclosure.

[0012] FIG2 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0013] FIG3 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0014] FIG4 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0015] FIG5 is a cross-sectional view of an array substrate provided in accordance with an embodiment of the present disclosure.

[0016] FIG6 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure.

[0017] FIG. 7 is a cross-sectional view of the display panel shown in FIG. 6 along line MN.

[0018] FIG8 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0019] FIG9 is a flow chart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure.

[0020] FIG10 is a flow chart of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure.

[0021] FIG11 is a flow chart of a method for manufacturing a thin film transistor according to yet another embodiment of the present disclosure.

[0022] FIG12 is a flow chart of a method for manufacturing a thin film transistor according to yet another embodiment of the present disclosure.

[0023] FIG13 is a flow chart of a method for manufacturing a thin film transistor according to yet another embodiment of the present disclosure.

[0024] FIG14 is a flow chart of a method for manufacturing a thin film transistor provided in yet another embodiment of the present disclosure.

[0025] FIG15 is a flow chart of a method for manufacturing a thin film transistor according to yet another embodiment of the present disclosure.

[0026] 16 to 20 are process diagrams of a method for manufacturing a thin film transistor provided in one embodiment of the present disclosure.

[0027] 21A and 21B are diagrams showing the simulated effects of two manufacturing processes of a semiconductor stack provided by an embodiment of the present disclosure.

[0028] 22A and 22B are diagrams showing the simulated effects of two preparation processes on a semiconductor film layer provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In thin-film transistors, the quality of the channel surface affects the mobility. If there are defects on the channel surface, such as high roughness, it means that the channel surface flatness is poor, which means that the thickness of the channel used to circulate carriers is unevenly distributed, thereby degrading the electrical properties and reliability of the channel. In addition, the high roughness of the film layer means that the arrangement of atoms and molecules on its surface is poorly regular, its structural strength is relatively low, and its blocking effect on external substances is low. Therefore, when preparing dielectric layers in thin-film transistors, if harmful ions invade the channel, it will also affect the electrical properties and reliability of the channel.

[0030] The embodiments of the present disclosure provide a thin film transistor, a method for preparing the same, and a display panel to at least solve the above-mentioned technical problems. The thin film transistor includes a substrate and an active layer and a first gate electrode located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than the mobility of the first film layer, and the roughness of the second film layer is lower than the roughness of the first film layer. In this design, the first film layer has a relatively high mobility, so when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with a small roughness can improve the surface to avoid surface defects, thereby reducing the leakage current of the thin film transistor and improving the performance of the thin film transistor; in addition, the second film layer with a small roughness has a strong blocking effect on ions, thereby protecting the first film layer.

[0031] Below, in conjunction with the accompanying drawings, a thin film transistor and its manufacturing method, and the structures involved in the display panel according to at least one embodiment of the present disclosure are described. In these embodiments, a spatial rectangular coordinate system is established with the surface of the substrate in the thin film transistor (for example, or the display surface of the display panel) as a reference to describe the positions of various structures in the thin film transistor, array substrate, and display panel. In this spatial rectangular coordinate system, the X-axis and Y-axis are parallel to the substrate, and the Z-axis is perpendicular to the substrate.

[0032] As shown in Figure 1, a thin film transistor 100 includes an active layer 120 and a first gate electrode 131, with the first gate electrode 131 spaced apart from the active layer 120. A substrate 110 supports the active layer 120 and the first gate electrode 131. By controlling the voltage on the first gate electrode 131, a voltage fluctuation in the active layer 120 can be generated, generating carriers and forming a current channel. This allows the switching and degree of the thin film transistor 100 to be controlled.

[0033] The active layer 120 includes a first film layer 121 and a second film layer 122 stacked together. The first film layer 121 is formed of a high-mobility semiconductor material, and the second film layer 122 is formed of a low-mobility semiconductor material, so that the surface of the first film layer 121 in contact with the second film layer 122 serves as the main channel for the two-dimensional electron gas (carriers). The roughness of the second film layer 122 is less than that of the first film layer 121, and the flatness of the second film layer 122 is higher than that of the first film layer 121. During the film formation process, the surface of the second film layer 122 is highly flattened, which can improve the surface defects of the first film layer 121 to ensure the electrical properties and stability of the active layer. In addition, the highly flat second film layer 122 has a better ion blocking effect, thereby protecting the first film layer 121.

[0034] Based on the thin film transistor shown in Figure 1, the surface of the first film layer 121 in contact with the second film layer 122 serves as a channel for carrier flow. Therefore, the thickness of the channel (along the direction perpendicular to the surface of the active layer 120, that is, the direction of the Z axis in Figure 1) is very small. Accordingly, the flatness of the surface at this location will also correspond to the uniformity of the channel thickness. If the surface roughness at this location is low, then the surface flatness at this location is high, and the channel thickness is relatively more uniform. The thickness of the channel is not equal to the size of the first film layer 121 along the Z axis.

[0035] In the embodiments of the present disclosure, "roughness" represents the microscopic flatness (or undulation) of the film surface, that is, the amplitude of the undulation (e.g., the distance between the peak and the trough), and can therefore be expressed in units of length (e.g., nanometers, micrometers, etc.). High roughness indicates that the atoms, molecules, or lattice structure on the film surface are loosely arranged, with large undulations. Correspondingly, low roughness indicates that the atoms, molecules, or lattice structure on the film surface are relatively regular and densely arranged, with small undulations, resulting in a higher barrier effect against the intrusion of foreign substances.

[0036] When evaluating roughness, it can also be obtained based on characteristics such as the spacing of fluctuations (such as the spacing between undulating peaks or troughs), microscopic shape, etc. In this case, the roughness can be calculated comprehensively based on characteristics such as amplitude (height), spacing, and shape.

[0037] For example, as shown in FIG1 , the thin film transistor 100 may further include a source electrode 141 and a drain electrode 142, and the source electrode 141 and the drain electrode 142 are connected to the active layer 120. The active layer 120 may be divided into a channel region, a source region, and a drain region, wherein the channel region is located between the source region and the drain region, and the channel region corresponds to the first gate electrode 131, that is, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first gate electrode 131 on the substrate, or the orthographic projection of the channel region on the substrate coincides with the orthographic projection of the first gate electrode 131 on the substrate. The source region and the drain region may be located at both ends of the active layer 120, the source region being used to connect to the source electrode 141 (electrically connected, such as in ohmic contact), and the drain region being used to connect to the drain electrode 142 (electrically connected, such as in ohmic contact). For example, after voltage is applied to the first gate electrode 131 , the channel is opened (depending on the material of the active layer, the channel state is opposite in this case, possibly from open to closed), and the current (electrical signal) on the source electrode 141 is conducted to the drain electrode 142 through the active layer 120 .

[0038] For example, in at least one embodiment of the present disclosure, as shown in Figure 1, the thin film transistor 100 may further include a first gate insulating layer 151 and an interlayer dielectric layer 160 to define various structures in the thin film transistor 100. For example, the first gate insulating layer 151 is located between the first gate electrode 131 and the active layer 120 to separate the first gate electrode 131 and the active layer 120, and the interlayer dielectric layer 160 is located between the source-drain electrode layer (including the source electrode 141 and the drain electrode 142) and the first gate electrode 131 to separate the source-drain electrode layer and the first gate electrode 131.

[0039] For example, in at least one embodiment of the present disclosure, as shown in FIG. 1 , the thin film transistor 100 may further include a buffer layer 170 between the substrate 110 and the active layer 120 . The buffer layer 170 may block harmful ions that invade from the substrate 110 into the active layer 120 .

[0040] In the embodiments of the present disclosure, as long as the roughness of the second film layer is less than that of the first film layer and the mobility of the second film layer is greater than that of the first film layer, the specific preparation process and specific materials of the first and second film layers are not limited. The following describes exemplary thin-film transistor structures using different preparation processes and specific materials for the first and second film layers, as well as the corresponding material choices.

[0041] In some embodiments of the present disclosure, the first film layer and the second film layer are composed of semiconductor film layers deposited by physical vapor deposition, and the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the first film layer is greater than the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the second film layer, so that the roughness of the second film layer is less than the roughness of the first film layer. The film formation rate of the film layer formed by physical vapor deposition under low power is low, so that the film layer can have a lower roughness. Therefore, by controlling the power of physical vapor deposition, the roughness difference between the first film layer and the second film layer can be controlled. For example, the power of physical vapor deposition to form the first semiconductor material film layer can be 4KW to 6KW, and the power of physical vapor deposition to form the second semiconductor material film layer can be 2KW to 4KW.

[0042] In other embodiments of the present disclosure, the first film layer is formed of a semiconductor film layer deposited by physical vapor deposition, and the second film layer is formed of a semiconductor film layer deposited by atomic layer deposition, so that the roughness of the second film layer is less than that of the first film layer. For example, the first film layer is formed by physical vapor deposition at a rate of 80 angstroms / second to 120 angstroms / second, and the second film layer is formed by atomic layer deposition at a rate of 20 angstroms / second to 60 angstroms / second.

[0043] Atomic layer deposition (ALD) is a surface deposition technology that can produce high-quality nanomaterials by depositing atomically thin films layer by layer on a material's surface. ALD's technical advantages include: high-precision control; control of the thickness and composition of each layer, thereby precisely controlling the thickness and properties of the film; formation of a uniform film on the surface of the structure, thereby improving the quality and stability of the film; and operation at low temperatures, which reduces the formation of impurities and thus improves the purity of the film. As a result, films formed by ALD have good uniformity, a uniform surface, and a low risk of surface defects.

[0044] For example, the roughness of the first film layer is greater than 1 nanometer, and the roughness of the second film layer is no greater than 1 nanometer. Furthermore, for example, the roughness of the second film layer is no greater than 0.8 nanometer. The actual roughness of the first and second film layers can be designed according to specific process requirements and is not limited to the above numerical range, as long as the roughness of the second film layer can achieve the effect of improving the surface of the first film layer.

[0045] For example, in the embodiments of the present disclosure, when the first film layer has high mobility and high roughness, the material of the first film layer is not limited and can be determined based on actual process requirements. For example, the material of the first film layer includes at least one of In, Ga, Zn, and Sn. For example, optionally, the material of the first film layer is one of IGZO, IGZTO, IZO, and IGO. For example, further, the mobility of the first film layer is not less than 20 cm2 / Vs.

[0046] For example, in the embodiments of the present disclosure, when the second film layer has low mobility and low roughness, the material of the second film layer is not limited and can be determined based on actual process requirements. For example, the material of the second film layer includes at least one of In, Ga, and Zn. For example, optionally, the material of the second film layer is IGZO. For example, further, the mobility of the second film layer is no greater than 15 cm2 / Vs.

[0047] For example, as shown in Figure 1, the first film layer 121 and the second film layer 122 are in contact with each other, and the first film layer 121 and the second film layer 122 can be prepared under the same composition process to reduce the preparation process flow of the active layer 120. In this case, the patterns of the first film layer 121 and the second film layer 122 roughly overlap, that is, the orthographic projection of the first film layer 121 on the substrate 110 overlaps with the orthographic projection of the second film layer 122 on the substrate 110.

[0048] In an embodiment of the present disclosure, when the first film layer is a semiconductor layer and the thin film transistor includes only one gate electrode (first gate electrode), the thin film transistor can be set as a top-gate thin film transistor, or can be set as a bottom-gate thin film transistor, as follows.

[0049] For example, in some embodiments of the present disclosure, as shown in FIG1 , when the first film layer 121 is a semiconductor layer, the first film layer 121 is located between the second film layer 122 and the substrate 110 , that is, the thin film transistor 100 is a top-gate thin film transistor.

[0050] Both ends of the first film layer need to be doped (for example, heavily doped) to make it conductive, so as to ensure the electrical connection between the active layer and the source electrode and the drain electrode. When the thin film transistor is a top-gate thin film transistor, the design thickness of the second film layer can be reduced to ensure that the setting of the second film layer does not have an adverse effect on the doping of the first film layer. For example, the thickness of the second film layer is less than the thickness of the first film layer.

[0051] For example, the thickness of the first film layer is 50 to 500 angstroms, such as 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, etc., and / or the thickness of the second film layer is 10 to 100 angstroms, such as 20 angstroms, 40 angstroms, 60 angstroms, 80 angstroms, etc.

[0052] For example, in some other embodiments of the present disclosure, as shown in FIG2 , when the first film layer 121 is a semiconductor layer, the second film layer 122 is located between the first film layer 121 and the substrate 110 , that is, the thin film transistor 200 is a bottom-gate thin film transistor.

[0053] For example, as shown in Figure 2, when the thin film transistor 200 is a bottom-gate thin film transistor, the positive projection of the active layer 120 on the substrate 110 is located within the positive projection of the first gate electrode 131 on the substrate 110. In this way, the setting of the first gate electrode 131 can avoid adverse effects on the flatness of the active layer 120; in addition, the first gate electrode 131 can block the light passing through the side of the substrate 110 to reduce the problem of photogenerated carriers in the active layer 120; in addition, the first gate electrode 131 can block harmful ions invading from the substrate 110 to the active layer 120.

[0054] In at least one embodiment of the present disclosure, as shown in FIG3 , the active layer 120 may further include a third film layer 123. The third film layer 123 is located on a side of the first film layer 121 facing away from the first gate electrode 131, and the third film layer 123 is made of a semiconductor material. The mobility of the third film layer 123 is lower than that of the first film layer 121, and the roughness of the third film layer 123 is less than that of the first film layer 121. In this way, the third film layer 123 and the second film layer 122 can protect the first film layer 121 from both sides to prevent harmful ions in other dielectric layers (e.g., the gate insulating layer) from invading the first film layer 121.

[0055] The mobility of the third film layer is lower than that of the first film layer, so the first film layer is still used to form the channel.

[0056] In some embodiments of the present disclosure, the first and third film layers are formed from semiconductor film layers deposited by physical vapor deposition (PVD). The PVD power for the semiconductor film forming the first film layer is greater than the PVD power for the semiconductor film forming the third film layer, such that the roughness of the third film layer is less than that of the first film layer. The film layers formed by PVD at low power have a low deposition rate, resulting in a higher roughness. Therefore, by controlling the PVD power, the difference in roughness between the first and third film layers can be controlled.

[0057] In other embodiments of the present disclosure, the first film layer is composed of a semiconductor film layer deposited by physical vapor deposition, and the third film layer is composed of a semiconductor film layer deposited by atomic layer deposition, so that the roughness of the third film layer is smaller than that of the first film layer.

[0058] For example, the roughness of the third film layer is no greater than 1 nanometer. For example, further, the roughness of the third film layer is no greater than 0.8 nanometer.

[0059] For example, in the embodiments of the present disclosure, when the third film layer has low mobility and low roughness, the material of the third film layer is not limited and can be determined based on actual process requirements. For example, the material of the third film layer includes at least one of In, Ga, and Zn. For example, optionally, the material of the third film layer is IGZO. For example, further, the mobility of the third film layer is no greater than 15 cm2 / Vs.

[0060] For example, in some embodiments of the present disclosure, as shown in FIG3 , the third film layer 123 and the first film layer 121 can be prepared using the same patterning process to reduce the preparation process flow of the active layer 120. In this case, the orthographic projection of the third film layer 123 on the substrate 110 coincides with the orthographic projection of the first film layer 121 on the substrate 110. For example, further, the orthographic projections of the first film layer 121, the second film layer 122, and the third film layer 123 on the substrate 110 coincide, that is, the first film layer 121, the second film layer 122, and the third film layer 123 are formed using the same patterning process. In this way, the first film layer 121 can be prevented from coming into contact with other materials (such as photoresist) and being contaminated (such as ion intrusion).

[0061] In at least one embodiment of the present disclosure, as shown in FIG4 , the thin film transistor 400 can be designed as a dual-gate thin film transistor to improve the response speed of the thin film transistor. For example, the thin film transistor 400 can include a second gate electrode 132 , which is located on a side of the active layer 120 away from the first gate electrode 131 .

[0062] For the first gate electrode 131 and the second gate electrode 132, the area of ​​the side located between the active layer 120 and the substrate 110 is larger than the area of ​​the active layer 120 to shield the active layer 120 and ensure the flatness of the active layer 120. Exemplarily, as shown in FIG4 , the second gate electrode 132 is located between the active layer 120 and the substrate 110, and the orthographic projection of the active layer 120 on the substrate 110 is located within the orthographic projection of the second gate electrode 132 on the substrate 110.

[0063] For example, as shown in FIG. 4 , in the case where the second gate electrode 132 is provided, the thin film transistor 100 may further include a second gate insulating layer 152 located between the active layer 120 and the second gate electrode 132 .

[0064] At least one embodiment of the present disclosure provides an array substrate, as shown in Figure 5, the array substrate may include a driving circuit layer 10, the driving circuit layer includes a plurality of pixel driving circuits, each pixel driving circuit includes a plurality of thin film transistors 100, and at least one thin film transistor is the thin film transistor in the above embodiment.

[0065] For example, the pixel driving circuit may include multiple transistors TFT (thin film transistors), capacitors, etc., and may be formed in various forms such as 2T1C (i.e., two transistors (TFT) and one capacitor (C)), 3T1C, or 7T1C. The pixel driving circuit is connected to a light-emitting device (see the light-emitting device 200 in the following embodiment) to control the switching state and the light-emitting brightness of the light-emitting device.

[0066] For example, in at least one embodiment of the present disclosure, as shown in Figure 5, the array substrate may further include a planar layer 180 and an anode 210 located on the planar layer 180, a via is provided in the planar layer 180, a pixel driving circuit is provided corresponding to the anode 210, and a source electrode or a drain electrode of a thin film transistor in the pixel driving circuit is connected to the corresponding anode 210 through the via.

[0067] At least one embodiment of the present disclosure provides a display panel, as shown in Figures 6 and 7, which includes a display function layer 20 and the array substrate 10 in the above embodiment. The display panel can be divided into a display area 1 and a frame area 2 located on at least one side of the display area, and a plurality of sub-pixels R, G, and B are arranged in the display area 1. The display function layer 20 is located on the array substrate 10 and includes a plurality of light-emitting devices 200, which are physical light-emitting structures of sub-pixels R, G, and B. For example, the light-emitting devices 200 respectively located in the sub-pixels R, G, and B are respectively designed to emit red light (R), green light (G), and blue light (B). For example, the light-emitting devices 200 are connected to the pixel driving circuit in the array substrate 100.

[0068] The light-emitting device 200 may include an anode 210, a light-emitting functional layer 230, and a cathode 220 stacked in sequence on an array substrate. The light-emitting functional layer 230 may include a first common layer 231, a light-emitting layer 232, and a second common layer 233 stacked in sequence on the anode 210. For example, the first common layer 231 may include a hole injection layer, a hole transport layer, and may further include an electron blocking layer. For example, the second common layer 233 may include an electron injection layer, an electron transport layer, and may further include a hole blocking layer.

[0069] For example, as shown in FIG. 7 , the display panel may further include a pixel defining layer 300 , wherein the pixel defining layer 300 includes a plurality of openings to define positions of the light emitting devices. For example, the light emitting layer of each light emitting device 200 is located in the opening.

[0070] 7 , the display panel may further include an encapsulation layer 30 to cover the display function layer 20 to protect the light emitting device 200. For example, the encapsulation layer 30 may include a first inorganic encapsulation layer 31, an organic encapsulation layer 32, and a second inorganic encapsulation layer 33 sequentially stacked on the display function layer 20.

[0071] For example, in an embodiment of the present disclosure, the display panel may further include functional structures such as a touch function layer, a polarizer, a lens layer, and a cover plate located on the display side (eg, on the encapsulation layer).

[0072] For example, in the embodiments of the present disclosure, the display panel may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, or a navigator.

[0073] At least one embodiment of the present disclosure provides a method for manufacturing the thin film transistor mentioned in the above embodiment. As shown in FIG8 , the manufacturing method may include the following steps S100 to S300 .

[0074] S100 , providing a substrate; depositing a first semiconductor material film layer having a first mobility on the substrate at a first film formation rate, and depositing a second semiconductor material film layer having a second mobility at a second film formation rate.

[0075] The first mobility is greater than the second mobility, and the first film formation rate is greater than the second film formation rate, so that the roughness of the second semiconductor material film layer is smaller than the roughness of the first semiconductor material film layer.

[0076] S200 , patterning the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer, respectively.

[0077] S300 , depositing a first conductive material thin film on a substrate, and patterning the first conductive material thin film to form a first gate electrode, wherein a second film layer is formed between the first film layer and the first gate electrode.

[0078] In this preparation method, the first film layer has a relatively high mobility. Therefore, when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with high roughness can improve the surface to avoid surface defects, thereby improving the performance of the thin film transistor.

[0079] For example, as shown in FIG9 , in some embodiments of the present disclosure, the above step S100 may include:

[0080] S110: Forming a first semiconductor material film layer and a second semiconductor material film layer respectively by physical vapor deposition, wherein the power of the physical vapor deposition for forming the first semiconductor material film layer is greater than the power of the physical vapor deposition for forming the second semiconductor material film layer, such that the first film formation rate is greater than the second film formation rate, and the roughness of the second film layer is less than the roughness of the first film layer. In this design, the specific materials and formation environment of the first and second film layers can be found in the relevant descriptions of the aforementioned embodiments and are not further described here.

[0081] For example, as shown in FIG10 , in some other embodiments of the present disclosure, the above step S100 may include:

[0082] S120: Forming a first semiconductor material film layer by physical vapor deposition and a second semiconductor material film layer by atomic layer deposition, such that the first film formation rate is greater than the second film formation rate, and the roughness of the second film layer is less than the roughness of the first film layer. In this design, the specific materials and formation environment of the first and second film layers can be found in the relevant description of the previous embodiment and are not further described here.

[0083] For example, as shown in FIG11 , in at least one embodiment of the present disclosure, the preparation method may further include:

[0084] S250: Depositing an insulating material between the first gate electrode and the active layer to form a first gate insulating layer. The first gate insulating layer separates the first gate electrode and the active layer. The positional relationship between the first gate insulating layer, the first gate electrode, and the active layer formed in this manner can be found in the relevant description of the previous embodiment and is not further described here.

[0085] For example, as shown in FIG12 , the preparation method further includes:

[0086] S400: A conductive material film is deposited on a side of the active layer facing away from the substrate, and the conductive material film is patterned to form a source electrode and a drain electrode. The source electrode and the drain electrode are respectively connected to two ends of the active layer. The positional relationship between the source electrode, the drain electrode, the first gate electrode, and the active layer formed in this manner can be found in the description of the previous embodiment and is not further described here.

[0087] For example, as shown in FIG13 , in at least one embodiment of the present disclosure, the preparation method may further include:

[0088] S220 deposits a third semiconductor material film layer having a third mobility at a third film formation rate, wherein the first mobility is greater than the third mobility and the first film formation rate is greater than the third film formation rate, such that the roughness of the third semiconductor material film layer is less than the roughness of the first semiconductor material film layer; and the third semiconductor material film layer is patterned to form a third film layer. In this design, the specific materials and formation environment of the third film layer can be found in the relevant description of the aforementioned embodiment and are not further described here.

[0089] In the fabrication method provided in at least one embodiment of the present disclosure, the second mobility is equal to the third mobility. For example, the second film formation rate is equal to the third film formation rate, so that the roughness of the second film layer and the third film layer are equal. The mobility and roughness of the second film layer and the third film layer are equal, for example, the second film layer and the third film layer can also be made of the same material to reduce the fabrication cost of the thin film transistor.

[0090] In at least one embodiment of the present disclosure, the preparation method may further include: after depositing the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer, simultaneously patterning the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer to form a first film layer, a second film layer, and a third film layer, and making the orthographic projection of the first film layer on the substrate, the orthographic projection of the second film layer on the substrate, and the orthographic projection of the third film layer on the substrate coincide with each other. In this way, the preparation process cost of the active layer can be simplified. In addition, the second semiconductor material layer and the third semiconductor material layer can protect the first semiconductor material layer, thereby reducing the risk of contamination of the active layer, especially the first film layer, during the preparation process.

[0091] In at least one embodiment of the present disclosure, the preparation method may further include: depositing a second conductive material thin film on the substrate, and patterning the second conductive material thin film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode. Regarding the structure of the thin film transistor formed as a dual-gate thin film transistor, please refer to the relevant description in the aforementioned embodiment, which will not be repeated here. In addition, based on the different choices of whether the first gate electrode is located above or below the active layer, the preparation method of the second gate electrode can have different options, as follows.

[0092] For example, as shown in FIG14 , in some embodiments of the present disclosure, the first gate electrode is formed on a side of the active layer facing away from the substrate, and the preparation method further includes:

[0093] S70: before forming the active layer and the first gate electrode, depositing a second conductive material thin film on the substrate, and patterning the second conductive material thin film to form a second gate electrode.

[0094] For example, in some other embodiments of the present disclosure, the preparation method may further include:

[0095] S80 : before forming the active layer and the first gate electrode and after forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer to cover the second gate electrode.

[0096] In at least one embodiment of the present disclosure, as shown in FIG15 , the preparation method may further include:

[0097] S240: After forming a first gate electrode and an active layer on the substrate, depositing a second conductive material film on the substrate, and patterning the second conductive material film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode.

[0098] For example, in some other embodiments of the present disclosure, the preparation method may further include:

[0099] S230 : After forming the active layer and the first gate electrode and before forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer.

[0100] The positional relationship between the second gate insulating layer formed in this manner and other structures in the thin film transistor can be found in the relevant descriptions in the aforementioned embodiments and will not be elaborated here.

[0101] Next, the process of preparing a thin film transistor in at least one embodiment of the present disclosure is described by taking the preparation of the thin film transistor 400 shown in FIG4 as an example. For details, please refer to the process steps shown in FIG16 to FIG20 below.

[0102] As shown in FIG16 , a substrate 110 is provided and an insulating material film layer and a conductive material film (the second conductive material film mentioned above) are sequentially deposited on the substrate 110 , and the insulating material film layer forms a buffer layer 170 ; the conductive material film is patterned to form a second gate electrode 132 .

[0103] In an embodiment of the present disclosure, the patterning process may be a photolithography patterning process, which may include, for example, coating a photoresist on a structural layer to be patterned, exposing the photoresist using a mask, developing the exposed photoresist to obtain a photoresist pattern, etching the structural layer using the photoresist pattern (optionally wet etching or dry etching), and then optionally removing the photoresist pattern. In the case where the material of the structural layer includes photoresist, the structural layer may be directly exposed through the mask to form the desired pattern.

[0104] As shown in Figures 16 and 17, an insulating material film layer is deposited on the substrate 110 having the second gate electrode 132 formed thereon to form a second gate insulating layer 152. A third semiconductor material film layer 123a, a first semiconductor material film layer 121a, and a second semiconductor material film layer 122a are then sequentially deposited on the second gate insulating layer 152. The second semiconductor material film layer 122a and the third semiconductor material film layer 123a can be formed by atomic layer deposition, with a roughness of no greater than 1 nanometer and a thickness of 10 to 100 angstroms. The first semiconductor material film layer 121a can be formed by physical vapor deposition, with a roughness of greater than 1 nanometer and a thickness of 50 to 500 angstroms.

[0105] As shown in Figures 17 to 18, the first semiconductor material film layer 121a, the second semiconductor material film layer 122a and the third semiconductor material film layer 123a are subjected to a composition process to form a first film layer 121, a second film layer 122 and a third film layer 123, respectively. The first film layer 121, the second film layer 122 and the third film layer 123 stacked together constitute an active layer 120.

[0106] For example, in the step shown in FIG18 , a doping process can be performed on both ends of the first film layer 121 (the source region and the drain region connected to the source electrode and the drain electrode, respectively) through the second film layer 122 to make both ends of the first film layer 121 conductive.

[0107] In some embodiments of the present disclosure, after forming a gate electrode (eg, the first gate electrode 131 shown in FIG. 19 below) on the side of the active layer facing away from the substrate, the active layer may be doped using the gate electrode as a mask.

[0108] As shown in Figures 18 to 19, an insulating material is deposited on the active layer 120 to form a first gate insulating layer 151; then a conductive material film (the above-mentioned first conductive material film) is deposited on the first gate insulating layer 151, and the conductive material film is patterned to form a first gate electrode 131.

[0109] As shown in FIG. 19 and FIG. 20 , an insulating material film layer is deposited on the substrate 110 on which the first gate electrode 131 is formed to form an interlayer dielectric layer 160 .

[0110] As shown in Figures 20 and 4, the interlayer dielectric layer 160 is patterned to form vias; a conductive material film is deposited on the interlayer dielectric layer 160, and the conductive material film is patterned to form a source electrode 141 and a drain electrode 142. The source electrode 141 and the drain electrode 142 are connected to the active layer 120 through the vias in the interlayer dielectric layer 160.

[0111] The roughness of the film formed by atomic layer deposition is significantly smaller than that of the film formed by physical vapor deposition, as follows.

[0112] As shown in Figure 21A, atomic layer deposition is used to form the IGZO film layer and the IGO film layer. The composition ratio of In, Ga and Zn in the IGZO film layer is 1:1:1, and the composition ratio of In and Ga in the IGO film layer is 2.5:1. The surfaces of the two film layers are very flat, and the sum of their film thicknesses is in the range of 21.03 nanometers (at position A1) to 21.07 nanometers (at position A2), that is, the overall thickness of the IGZO film layer and the IGO film layer is relatively uniform.

[0113] As shown in Figure 21B, IGZO and IZO films were formed using physical vapor deposition. The ratio of In, Ga, and Zn in the IGZO film was 1:1:1, and the ratio of In to Zn in the IZO film was 5:1. The surfaces of the two films were highly undulating. At position B1, the thicknesses of the IGZO and IZO films were 18.99 nm and 20.31 nm, respectively, with a combined thickness of 39.3 nm. At position B2, the combined thickness of the IGZO and IZO films was 40.82 nm. The overall thickness difference between the IGZO and IZO films was significant, and defects were significant at the interface between the two films.

[0114] As shown in FIG22A , an IGZO film layer is formed by atomic layer deposition. The composition ratio of In, Ga, and Zn in the IGZO film layer is 1:1:1. The height difference from the highest point to the lowest point on the surface of the IGZO film layer is 2.4 nanometers, and the average height difference of the surface is 0.18 nanometers.

[0115] As shown in FIG22B , a IGZO film layer is formed by physical vapor deposition. The composition ratio of In, Ga, and Zn in the IGZO film layer is 1:1:1. The height difference from the highest point to the lowest point on the surface of the IGZO film layer is 5.1 nanometers, and the average height difference on the surface is 0.3 nanometers.

[0116] In the above embodiments of the present disclosure, the environmental conditions for physical vapor deposition may be: 5 kW power, 75% oxygen partial pressure; and atomic layer deposition is performed at 300 degrees Celsius.

[0117] For example, in one example, two IGZO film layers are formed based on atomic layer deposition, and the composition ratio of In, Ga and Zn in one IGZO film layer is 1.2:1:1, and the composition ratio of In, Ga and Zn in the other IGZO film layer is 2.5:1:1. In this case, the surface undulation of the active layer (which can be roughness or used to calculate roughness) is approximately 0.77 nanometers.

[0118] For example, in another example, an IGZO film layer and an IGO film layer are formed based on atomic layer deposition, and the composition ratio of In, Ga and Zn in the IGZO film layer is 1.2:1:1, and the composition ratio of In and Ga in the other IGZO film layer is 2.5:1. In this case, the surface undulation of the active layer (which can be roughness or used to calculate roughness) is approximately 0.78 nanometers.

Claims

1. A thin film transistor, comprising a substrate, an active layer and a first gate electrode located on the substrate, wherein: The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, and The first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than the mobility of the first film layer, and the roughness of the second film layer is smaller than the roughness of the first film layer.

2. The thin film transistor according to claim 1, wherein: The material of the first film layer includes at least one of In, Ga, Zn, and Sn, and the mobility of the first film layer is not less than 20 cm2 / Vs; and / or The material of the second film layer includes at least one of In, Ga, and Zn, and the mobility of the second film layer is not greater than 15 cm2 / Vs; The roughness of the first film layer is greater than 1 nanometer, and the roughness of the second film layer is not greater than 1 nanometer.

3. The thin film transistor according to claim 1, wherein: The orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the second film layer on the substrate; The first film layer is in direct contact with the second film layer.

4. The thin film transistor according to any one of claims 1 to 3, wherein: The active layer is located between the first gate electrode and the substrate, the thickness of the second film layer is less than the thickness of the first film layer, the thickness of the first film layer is 50 to 500 angstroms, and / or the thickness of the second film layer is 10 to 100 angstroms; or The first gate electrode is located between the active layer and the substrate, and the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate electrode on the substrate.

5. The thin film transistor according to any one of claims 1 to 3, wherein: Also includes: A first gate insulating layer is located between the first gate electrode and the active layer.

6. The thin film transistor according to any one of claims 1 to 3, wherein: Also includes: A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on a side of the active layer away from the substrate, and two ends of the active layer are connected to the source electrode and the drain electrode respectively.

7. The thin film transistor according to claim 6, wherein: The thin film transistor also includes a first gate insulating layer and an interlayer dielectric layer, wherein the first gate insulating layer is located between the first gate electrode and the active layer to separate the first gate electrode and the active layer, and the interlayer dielectric layer is located between the source electrode, the drain electrode and the first gate electrode to separate the source electrode, the drain electrode and the first gate electrode.

8. The thin film transistor according to any one of claims 1 to 3, wherein: The active layer further comprises: A third film layer, located on a side of the first film layer away from the first gate electrode, the third film layer comprising a semiconductor material; The mobility of the third film layer is lower than that of the first film layer, and the roughness of the third film layer is smaller than that of the first film layer.

9. The thin film transistor according to claim 8, wherein: The first film layer is in direct contact with the third film layer; The material of the third film layer includes at least one of In, Ga, and Zn; the mobility of the third film layer is not greater than 15cm2 / Vs; The roughness of the third film layer is not greater than 1 nanometer; The orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the third film layer on the substrate.

10. The thin film transistor according to claim 8, wherein: Also comprising a second gate electrode, wherein the second gate electrode is located on a side of the active layer away from the first gate electrode; The thin film transistor further includes a second gate insulating layer located between the second gate electrode and the active layer.

11. The thin film transistor according to any one of claims 1 to 3, wherein: The thin film transistor further includes a buffer layer located between the substrate and the active layer.

12. A display panel comprising the thin film transistor according to any one of claims 1 to 11.

13. A method for preparing a thin film transistor, comprising: providing a substrate; Depositing a first semiconductor material film layer having a first mobility on the substrate at a first film formation rate, and depositing a second semiconductor material film layer having a second mobility at a second film formation rate, wherein the first mobility is greater than the second mobility, and the first film formation rate is greater than the second film formation rate, so that the roughness of the second semiconductor material film layer is less than the roughness of the first semiconductor material film layer; performing patterning on the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer respectively; and A first conductive material film is deposited on the substrate, and the first conductive material film is patterned to form a first gate electrode, wherein the second film layer is formed between the first film layer and the first gate electrode.

14. The preparation method according to claim 13, wherein: The method of depositing a first semiconductor material film layer having a first mobility on the substrate at a first film forming rate, and depositing a second semiconductor material film layer having a second mobility at a second film forming rate, comprises: The first semiconductor material film layer and the second semiconductor material film layer are respectively formed by physical vapor deposition, wherein the power of physical vapor deposition for forming the first semiconductor material film layer is greater than the power of physical vapor deposition for forming the second semiconductor material film layer, so that the first film forming rate is greater than the second film forming rate, and the roughness of the second film layer is less than the roughness of the first film layer, the power of physical vapor deposition for forming the first semiconductor material film layer is 4KW~6KW, and the power of physical vapor deposition for forming the second semiconductor material film layer is 2KW~4KW.

15. The preparation method according to claim 13, wherein: The method of depositing a first semiconductor material film layer having a first mobility on the substrate at a first film formation rate, and depositing a second semiconductor material film layer having a second mobility at a second film formation rate, includes: forming the first semiconductor material film layer by physical vapor deposition, and forming the second semiconductor material film layer by atomic layer deposition, so that the first film formation rate is greater than the second film formation rate, and the roughness of the second film layer is less than the roughness of the first film layer, the first film formation rate is 80 angstroms / second to 120 angstroms / second, and the second film formation rate is 20 angstroms / second to 60 angstroms / second.

16. The preparation method according to claim 14 or 15, wherein: The material of the first film layer includes at least one of In, Ga, Zn, and Sn, and the mobility of the first film layer is not less than 20 cm2 / Vs; and / or the material of the second film layer includes at least one of In, Ga, and Zn, and the mobility of the second film layer is not more than 15 cm2 / Vs; The roughness of the first film layer is greater than 1 nanometer, and the roughness of the second film layer is not greater than 1 nanometer.

17. The preparation method according to any one of claims 13 to 16, further comprising: depositing an insulating material between the first gate electrode and the active layer to form a first gate insulating layer; A conductive material film layer is deposited on a side of the active layer away from the substrate, and a patterning process is performed on the conductive material film layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to two ends of the active layer.

18. The preparation method according to any one of claims 13 to 16, further comprising: Depositing a third semiconductor material film layer having a third mobility at a third film formation rate, wherein the first mobility is greater than the third mobility, and the first film formation rate is greater than the third film formation rate, so that the roughness of the third semiconductor material film layer is less than the roughness of the first semiconductor material film layer; and Performing patterning on the third semiconductor material film layer to form a third film layer; The second mobility is equal to the third mobility; The second film forming rate is equal to the third film forming rate, so that the roughness of the second film layer and the third film layer are equal; The material of the third film layer includes at least one of In, Ga, and Zn; the mobility of the third film layer is not greater than 15cm2 / Vs; The roughness of the third film layer is not greater than 1 nanometer; After depositing the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are simultaneously subjected to a patterning process to form the first film layer, the second film layer and the third film layer, and the orthographic projection of the first film layer on the substrate, the orthographic projection of the second film layer on the substrate and the orthographic projection of the third film layer on the substrate coincide with each other.

19. The preparation method according to claim 18, wherein: The first gate electrode is formed on a side of the active layer away from the substrate, and the preparation method further includes: Before forming the active layer and the first gate electrode, a second conductive material film is deposited on the substrate, and the second conductive material film is patterned to form a second gate electrode. The preparation method also includes: before forming the active layer and the first gate electrode and after forming the second gate electrode, an insulating material is deposited on the substrate to form a second gate insulating layer to cover the second gate electrode.

20. The preparation method according to claim 18, wherein: The first gate electrode is formed between the active layer and the substrate, and the preparation method further includes: After forming the first gate electrode and the active layer on the substrate, a second conductive material film is deposited on the substrate, and the second conductive material film is patterned to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode. The preparation method further includes: after forming the active layer and the first gate electrode and before forming the second gate electrode, an insulating material is deposited on the substrate to form a second gate insulating layer.

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