Semiconductor structure preparation method, semiconductor structure, semiconductor device, and device

Abstract

Provided in the present disclosure are a semiconductor structure preparation method, a semiconductor structure, a semiconductor device, and a device. The method comprises: providing a substrate, which is a wafer; forming an active structure on the substrate, wherein the active structure comprises a first part and a second part; depositing a semiconductor material on the active structure, so as to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on two sides of a third part of the dummy gate structure; flipping the wafer, and removing the substrate; forming a source structure and a drain structure of a second transistor on two sides of a fourth part of the dummy gate structure; etching the dummy gate structure, so as to form a first trench; and forming a first gate structure of the first transistor and a second gate structure of the second transistor, respectively, at the first trench, wherein the first gate structure and the second gate structure are self-aligned in a vertical direction.

Description

Semiconductor structure preparation method, semiconductor structure, device and equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311226981.7 and application date September 21, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device, and an apparatus. Background Art

[0004] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0005] In the related art, a process for manufacturing stacked transistors adopts a monolithic solution or a sequential solution, both of which have problems of high difficulty and complexity in the manufacturing process.

[0006] Summary of the Invention

[0007] The present disclosure provides a method for preparing a semiconductor structure, a semiconductor structure, a device, and an apparatus.

[0008] The first aspect of the present disclosure provides a method for preparing a semiconductor structure. The method includes: providing a substrate, which is a wafer; forming an active structure on the substrate, the active structure including a first portion and a second portion; depositing a semiconductor material on the active structure to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on both sides of a third portion of the dummy gate structure, the third portion being the portion of the dummy gate structure corresponding to the first portion; flipping the wafer and removing the substrate; forming a source structure and a drain structure of a second transistor on both sides of a fourth portion of the dummy gate structure, the fourth portion being the portion of the dummy gate structure corresponding to the second portion; etching the dummy gate structure to form a first groove; and forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, the first gate structure and the second gate structure being self-aligned in a vertical direction.

[0009] A second aspect of the present disclosure provides a semiconductor structure. The semiconductor structure is prepared by the method for preparing a semiconductor structure described in the first aspect, and includes: a first transistor; a second transistor, the second transistor being disposed opposite the first transistor; a first active structure of the first transistor and a second active structure of the second transistor being formed through the same process; and a first gate structure of the first transistor and a second gate structure of the second transistor being self-aligned in a vertical direction.

[0010] A third aspect of the present disclosure provides a semiconductor device, which includes: the semiconductor structure as mentioned in the second aspect.

[0011] A fourth aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device as mentioned in the third aspect, wherein the semiconductor device is disposed on the circuit board.

[0012] In the present disclosure, the source structure and drain structure of the first transistor and the source structure and drain structure of the second transistor are first prepared, and then the first gate structure of the first transistor and the second gate structure of the second transistor are respectively prepared at the first groove. This can simplify the preparation process and improve the thermal budget when preparing the second transistor; at the same time, since the first gate structure and the second gate structure are both formed at the first groove, the first gate structure and the second gate structure are self-aligned in the vertical direction.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0015] FIG1 is a schematic flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0016] FIG2 is a schematic diagram of a first structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0017] 3A to 3F are schematic diagrams of a first preparation process of a semiconductor structure provided by an embodiment of the present disclosure.

[0018] FIG4 is a schematic diagram of a second structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0019] FIG5 is a schematic diagram of a third structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0020] 6A to 6F are schematic diagrams of a second preparation process of a semiconductor structure provided by an embodiment of the present disclosure.

[0021] FIG7 is a schematic diagram of a fourth structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0022] FIG8 is a fifth structural schematic diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0023] 9A to 9F are schematic diagrams of a third preparation process of a semiconductor structure provided by an embodiment of the present disclosure.

[0024] FIG10 is a sixth structural schematic diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0025] Description of reference numerals:

[0026] Semiconductor structure 10; first transistor 11; second transistor 12; insulating dielectric layer 13; gate dielectric layer 14; first active structure 111; first gate structure 112; first interlayer dielectric 113; source structure and drain structure 114 in the first transistor; first metal interconnection layer 115; first insulating layer 116; carrier wafer 117; second active structure 121; second gate structure 122; second interlayer dielectric 123; source structure and drain structure 124 in the second transistor; second metal interconnection layer 125; silicon substrate 21; bottom silicon layer 211; sacrificial layer 212; top silicon layer 213; fin structure 22A; nanosheet 22B; block planar structure 22C; dummy gate structure 23; shallow trench isolation region 24; shallow trench isolation layer 241; spacer 25; gate structure 26; columnar structure 31. DETAILED DESCRIPTION

[0027] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0028] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0029] As Moore's Law continues to deepen, further scaling transistors beyond the gate-all-around FET (GAA) technology node is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing integrated circuit scaling.

[0030] In one embodiment, there are two schemes for fabricating stacked transistors. The first is a monolithic scheme, and the second is a sequential scheme.

[0031] The first solution is to fabricate N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate. This means that transistors on the same layer must be of the same type, either NFET or PFET. Furthermore, the upper and lower layers of transistors must be strictly in the same plane, with no alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex, requiring a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0032] The second solution is based on wafer bonding and layer-by-layer processing. The upper transistor is prepared by attaching a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of a high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0033] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the bottom layer devices when making the upper layer devices; (2) the performance of the top layer devices under low thermal budget; and (3) the metal interconnection of transistors between layers.

[0034] In order to solve the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce the thermal budget of manufacturing stacked transistors and simplify the process flow.

[0035] In some embodiments, the semiconductor structure described above can be applied to semiconductor devices such as memories and processors.

[0036] In one embodiment, the semiconductor structure may include at least two transistors, taking a first transistor and a second transistor as an example. The first transistor and the second transistor are arranged opposite to each other. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process. In this case, it can be understood that the first transistor and the second transistor share the same active structure. The first gate structure in the first transistor and the second gate structure in the second transistor are self-aligned in the vertical direction.

[0037] In some embodiments, the first transistor and the second transistor in the semiconductor structure are transistors of the same type, such as any one of the following: a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0038] FIG2 is a semiconductor structure composed of a fin field-effect transistor. The preparation method provided by the embodiment of the present disclosure will be described below with reference to the semiconductor structure shown in FIG2 .

[0039] FIG1 is a schematic diagram of a first implementation flow of a method for preparing a semiconductor structure according to an embodiment of the present disclosure. Referring to FIG1 , the method for preparing a semiconductor structure may include steps S101 to S108:

[0040] Step S101: providing a substrate.

[0041] In some embodiments, the substrate is a wafer made of silicon material. In one embodiment, the wafer can be a silicon (Si) wafer or a silicon-on-insulator (SOI) wafer. Accordingly, the substrate can be a Si substrate or an SOI substrate, or of course, a substrate made of other semiconductor materials, which is not limited in the present disclosure.

[0042] In some embodiments, the substrate can be a multi-layer structure. A sacrificial layer (e.g., silicon germanium (SiGe)) is epitaxially grown on a bottom silicon layer, and a top silicon layer is epitaxially grown on top of the sacrificial layer (see FIG. 3A ). The sacrificial layer is used to protect the structure of the top silicon layer, reduce external shock and vibration, improve the durability and reliability of the top silicon layer, and extend its service life.

[0043] In one embodiment, the thickness of the sacrificial layer is approximately 10 to 20 nm, and the thickness of the top silicon layer is greater than 100 nm. It should be noted that the thickness of the sacrificial layer and the top silicon layer can be selected based on actual use requirements. For example, in a fin field-effect transistor, the top silicon layer has a relatively large thickness to facilitate etching of the fin structure. In a gate-all-around transistor, the sacrificial layer and the silicon layer are stacked, and the sacrificial layer is a semiconductor material layer disposed in the stack. In this case, the thickness of the sacrificial layer and the silicon layer are both selected based on actual use requirements; this is not limited in the present embodiment.

[0044] Step S102: forming an active structure on a substrate, the active structure including a first portion and a second portion.

[0045] In some embodiments, one or more active structures may be formed on the substrate by etching the substrate. The active structure is divided into two parts, the upper part (i.e., the first part) being used as the active structure of the first transistor (i.e., the first active structure), and the lower part (i.e., the second part) being used as the active structure of the second transistor (i.e., the second active structure).

[0046] In some embodiments, when etching the substrate, the etching depth is the sum of the thicknesses of the silicon layer and the sacrificial layer in the substrate, that is, etching is performed until the connection between the sacrificial layer and the underlying silicon layer.

[0047] For example, the substrate can be etched using anisotropic etching to form active structures in the active region, such as fin structures extending in the same direction (see FIG3A(b)), parallel nanosheets (see FIG6E(b)), and block-shaped planar structures (see FIG9A(b)). In some embodiments, when the active structure is a fin structure, the transistor is a fin field effect transistor (FinFET); when the active structure is a plurality of parallel nanosheets, the transistor is a gate-all-around field effect transistor (GAAFET); and when the active structure is a block-shaped planar structure, the transistor is a planar transistor.

[0048] It should be noted that the etching process mentioned in the embodiments of the present disclosure may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, and the embodiments of the present disclosure are not limited to this.

[0049] In some embodiments, after the fin structure is formed in step S102 , ion implantation may be performed at the connection between the upper and lower halves of the fin structure to form an electrical isolation layer for electrically isolating the upper and lower halves of the fin structure.

[0050] In some embodiments, the ions implanted include P-type ions, N-type ions, or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), or aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), or antimony (Sb).

[0051] Step S103: depositing a semiconductor material on the active structure to form a dummy gate structure.

[0052] In some embodiments, after the fin structure is formed by etching the substrate, a trench is formed in the etched area. The gate region is opened by photolithography at the trench location, and a semiconductor material (such as polysilicon) is deposited in the gate region. Then, oxide is filled in the trench region except for the gate region to form a shallow trench isolation (STI) region. After the STI region is formed, the semiconductor material deposited in the gate region is removed by etching to expose the sacrificial layer in the gate region. The sacrificial layer not covered by the STI region is selectively removed by wet etching (see (c) in FIG. 3B ). Then, semiconductor material is re-deposited in the location of the etched sacrificial layer. At this point, the dummy gate structure is formed (see (a) in FIG. 3C ).

[0053] In some embodiments, the oxide forming the shallow trench isolation region may be silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon oxycarbide (SiCO).

[0054] In some embodiments, in order to facilitate subsequent processing, after step S103, the shallow trench isolation area can also be polished or chemical-mechanical planarization (CMP) treated, so that when the shallow trench isolation area is subsequently etched, the corresponding corrosion depths of the shallow trench isolation areas in different areas are the same, thereby making the top height of the exposed active structure the same.

[0055] Step S104 : forming a source structure and a drain structure of the first transistor on both sides of the third portion of the dummy gate structure.

[0056] In some embodiments, the third portion is a portion of the dummy gate structure corresponding to the first portion.

[0057] It can be understood that the dummy gate structure is also divided into two parts, the upper part (ie, the third part) is used in the first transistor, and the lower part (ie, the fourth part) is used in the second transistor.

[0058] In some embodiments, the upper half of the shallow trench isolation region is removed by etching to expose the first portion of the fin structure covered by the shallow trench isolation region, thereby exposing the upper half of the dummy gate structure. Spacers are formed on both sides of the upper half of the dummy gate structure, and the spacers are used as masks to epitaxially grow the source and drain electrodes to form the source and drain structures of the first transistor, and deposit an interlayer dielectric (such as silicon dioxide) (see (b) in Figure 3C). Then, metal contacts are made to the source and drain structures of the first transistor, and back-end processing is performed above the source and drain structures to form the first metal interconnect layer of the first transistor.

[0059] In some embodiments, the solvent used to etch the shallow trench isolation region may be a DHF solution or a BOE solution. The solvent used in the etching process can be selected according to actual conditions and is not limited to the DHF solution or the BOE solution.

[0060] Step S105: Flip the wafer and remove the substrate.

[0061] In some embodiments, after forming the source and drain structures of the first transistor, post-processing (e.g., deposition of a dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the source and drain structures to form a metal interconnect layer of the first transistor. An insulating material (e.g., silicon oxide) is deposited on the metal interconnect layer to form a first insulating layer, which is then bonded to a carrier wafer. The unfinished first transistor (i.e., wafer) is then flipped so that the substrate (i.e., bottom silicon layer) faces upward, and the substrate is then etched using the same etching method as in step S102 (see (b) in FIG. 3D ).

[0062] Step S106: forming a source structure and a drain structure of the second transistor on both sides of the fourth portion of the dummy gate structure, where the fourth portion is a portion of the dummy gate structure corresponding to the second portion.

[0063] In some embodiments, after flipping the wafer, a CMP process is used to thin the wafer until the sacrificial layer surrounded by the shallow trench isolation region is exposed (see (c) in FIG. 3D ). The sacrificial layer surrounded by the shallow trench isolation region is then selectively removed by wet etching (see (a) in FIG. 3E ). The lower half of the shallow trench isolation region is removed by etching to expose the second portion of the active structure covered by the shallow trench isolation region. The source and drain structures of the second transistor are then formed using the same method as step S104.

[0064] In some embodiments, after the source structure and drain structure of the first transistor and the metal interconnection layer are fabricated on the substrate, the first transistor is directly flipped over and the second transistor is fabricated on the back side of the first transistor. This can eliminate the need for photolithography alignment, simplify the process flow, and save costs.

[0065] Step S107 : etching the dummy gate structure to form a first trench.

[0066] In some embodiments, after forming the source structure and the drain structure of the second transistor, the dummy gate structure is removed by etching to form a trench (ie, a first trench) at the gate region (see (b) in FIG. 3E ).

[0067] Step S108 : forming a first gate structure of the first transistor and a second gate structure of the second transistor in the first trench, respectively, wherein the first gate structure and the second gate structure are self-aligned in a vertical direction.

[0068] In some embodiments, a metal material is deposited at the first groove to form a gate structure. The gate structure that wraps the second portion is removed by etching, exposing the second portion. The unetched gate structure wraps the first portion, and this portion of the gate structure is the first gate structure in the first transistor. An insulating material is deposited on the first gate structure to form an insulating dielectric layer, which is used to isolate the first gate structure from the second gate structure. A metal material is then deposited on the insulating dielectric layer to form a second gate structure of the second transistor (see (b) in FIG. 3F ).

[0069] In other embodiments, after forming the first trench, the first and second gate structures may be fabricated using the following method: depositing a metal material in the first trench to a height consistent with the height of the active structure in the first transistor, thereby forming the first gate structure in the first transistor. Subsequently, an insulating material is deposited over the first gate structure to form an insulating dielectric layer. Finally, a metal material is deposited over the insulating dielectric layer to form the second gate structure in the second transistor.

[0070] It should be noted that the above-mentioned “isolation” can be understood as physical isolation or electrical isolation.

[0071] In some embodiments, the insulating dielectric layer between the first gate structure and the second gate structure may not be provided, depending on practical circumstances. Thus, the first transistor and the second transistor can be interconnected through the contact between the first gate structure and the second gate structure, without the need for extending interconnection lines.

[0072] In some embodiments, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0073] In some embodiments, the metal materials of the first gate structure and the second gate structure may include: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), and titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0074] In some embodiments, before preparing the first gate structure and the second gate structure, the above-mentioned semiconductor preparation method also includes: depositing a gate dielectric layer on the surface of the active structure, and the gate dielectric layer is used to isolate the active structure of the first transistor (i.e., the first part) and the first gate structure and the active structure of the second transistor (i.e., the second part) and the second gate structure.

[0075] It should be noted that the material of the gate dielectric layer can be set according to actual circumstances and is not limited in this regard in the embodiments of the present disclosure. When the gate dielectric layer is made of a single material, the active structure of the first transistor and the active structure of the second transistor are both encapsulated by the gate dielectric layer of the same material. When the gate dielectric layer is made of two materials, the active structure of the first transistor is encapsulated by the first gate dielectric layer, and the active structure of the second transistor is encapsulated by the first gate dielectric layer. In some embodiments, the first gate dielectric layer and the second gate dielectric layer are made of different materials.

[0076] In some embodiments, when the gate dielectric layers of the first transistor and the second transistor are different, a method for forming the first gate dielectric layer and the second gate dielectric layer includes: depositing a layer of insulating material on the surface of the active structure to form the gate dielectric layer, removing the gate dielectric layer in a second portion of the active structure by etching to expose the second portion of the active structure, the gate dielectric layer in the unetched first portion being the first gate dielectric layer in the first transistor, and continuously depositing another insulating material on the surface of the second portion of the active structure to form the second gate dielectric layer in the second transistor.

[0077] In some embodiments, the first transistor and the second transistor in the semiconductor structure are of the same type, such as any of the following: a fin field effect transistor, a gate-all-around transistor, and a planar transistor. Therefore, the semiconductor structure can also be designed according to the different types of transistors.

[0078] Below, the semiconductor structure provided by the embodiment of the present disclosure is described by taking the first transistor and the second transistor as fin field-effect transistors as an example. Figure 2 is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present disclosure. (a) in Figure 2 is a top view of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, source structure and drain structure are shown in the top view; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and the drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0079] As shown in FIG2 , the semiconductor structure 10 includes a first transistor 11 and a second transistor 12. The active structure in the semiconductor structure 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, namely the first part and the second part. The first part serves as the first active structure 111 in the first transistor 11, and the second part serves as the second active structure 121 in the second transistor 12. An insulating dielectric layer 13 is provided between the first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12. The insulating dielectric layer 13 is used to isolate the first gate structure 112 from the second gate structure 122. In addition to the gate region, a shallow trench isolation layer 241 is provided between the first transistor 11 and the second transistor 12. The shallow trench isolation layer 241 is used to isolate the first transistor 11 from the second transistor 12.

[0080] As shown in FIG2 , the gate dielectric layer 14 wraps around the first and second portions of the fin structure. In the first transistor 11, at a position corresponding to the first portion, the first gate structure 112 wraps around the gate dielectric layer 14, and the gate dielectric layer 14 is used to isolate the fin structure from the first gate structure 112. The first interlayer dielectric 113 wraps around the first portion of the fin structure 22A, the source structure, and the drain structure 114 in the first transistor 11 at locations other than the gate region. The second interlayer dielectric 123 wraps around the second portion of the fin structure 22A, the source structure, and the drain structure 124 in the second transistor 12 at locations other than the gate region. The structure of the second transistor 12 is substantially similar to that of the first transistor 11, and the structure of the second transistor 12 will not be described in detail herein.

[0081] As shown in (c) and (d) of FIG. 2 , the source structure and the drain structure 114 of the first transistor 11 are arranged opposite to the source structure and the drain structure 124 of the second transistor 12 .

[0082] In some embodiments, the first active structure of the first transistor and the second active structure of the second transistor are formed through the same process, so that the first transistor and the second transistor can be self-aligned and the active area of ​​the first transistor and the active area of ​​the second transistor are consistent.

[0083] The following describes the preparation process of the semiconductor structure shown in Figure 2 in conjunction with the above preparation method. The semiconductor structure shown in Figure 2 can be prepared by the process shown in Figures 3A to 3F, which are schematic diagrams of the first preparation process of the semiconductor structure in the embodiment of the present disclosure.

[0084] In one example, taking the first transistor 11 and the second transistor 12 as fin field-effect transistors, a first manufacturing process of the semiconductor structure 10 may include the following steps:

[0085] Step 1: Provide a silicon substrate 21. In some embodiments, the silicon substrate 21 is composed of a bottom silicon layer 211, a sacrificial layer 212, and a top silicon layer 213 (see (a) in FIG. 3A). The sacrificial layer is made of SiGe.

[0086] Step 2: Etching the silicon substrate 21 to form a plurality of fin structures 22A (see (b) in FIG. 3A ).

[0087] In some embodiments, anisotropic etching is performed on the silicon substrate 21 to form multiple fin structures 22A extending in the same direction. The thickness of the fin structures 22A is greater than 100 nm. The thickness of the sacrificial layer 212 is 10 to 20 nm. The etching depth is the sum of the thicknesses of the top silicon layer 213 and the sacrificial layer 212.

[0088] Step 3: The gate region is opened through photolithography, and polysilicon (poly Si) is deposited in the gate region as a dummy gate structure 23 (see the AA' direction in FIG3A(c)). Then, STI is filled in the remaining areas except the gate region to form shallow trench isolation regions 24 (see the BB' direction in FIG3A(c)), and planarization is performed through CMP.

[0089] In some embodiments, the height of the dummy gate structure 23 and the shallow trench isolation region 24 are both greater than the thickness of the fin structure 22A. Referring to the CC' direction in FIG3A(c), the dummy gate structure 23 and the shallow trench isolation region 24 are alternately deposited around the fin structure 22A.

[0090] Step 4: Remove the dummy gate structure 23 by etching to expose the fin structure 22A and the sacrificial layer 212 (see (a) in FIG. 3B ).

[0091] Step 5: Use wet etching to selectively remove the exposed sacrificial layer 212 (see (b) in FIG. 3B ).

[0092] Step 6: Poly Si is deposited again in the gate region to form a dummy gate structure 23 (see (c) in FIG. 3B ).

[0093] In some embodiments, the bottom of the fin structure 22A wrapped by the dummy gate structure 23 formed the second time does not have the sacrificial layer 212 .

[0094] It should be noted that after forming the dummy gate structure 23, spacer structures (not shown in the figure) may be formed on both sides of the dummy gate structure 23. The material of the spacer structure may include, but is not limited to, silicon nitride, silicon carbide, silicon oxynitride, etc. In some embodiments, the spacer structure may be completed by a dielectric deposition and etching process.

[0095] Step 7: The upper portion of the shallow trench isolation region 24 is removed by etching to expose the first portion of the fin structure 22A (i.e., the first active structure 111) (see direction BB' in (a) of FIG. 3C). Ion implantation is performed at the boundaries between the exposed first portions and the unexposed second portions of the plurality of fin structures 22A to form an electrical isolation layer (not shown).

[0096] Step 8: Form spacers 25 on the sidewalls of the exposed dummy gate structure 23 (see the CC' direction in (b) of Figure 3C), and use the spacers 25 as a mask to epitaxially grow the source structure and drain structure 114 in the first transistor 11 (see the BB' direction and CC' direction in (b) of Figure 3C), and deposit a first interlayer dielectric 113 on the source structure and drain structure 114 and between the dummy gate structures 23 (see the BB' direction and CC' direction in (b) of Figure 3C).

[0097] In some embodiments, the material of the first interlayer dielectric 113 is SiO 2 .

[0098] Step 9: Perform a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and deposit an insulating material above the first metal interconnection layer 115 to form a first insulating layer 116. The first insulating layer 116 is bonded to the carrier wafer 117, and then the currently manufactured wafer is flipped over (see (c) in Figure 3C).

[0099] In some embodiments, the bonded carrier wafer can provide physical support for the flipped wafer after flipping, effectively preventing the wafer from being broken during the process of preparing the second transistor.

[0100] Step 10: The flipped wafer is thinned using a CMP process until the sacrificial layer 212 wrapped by the shallow trench isolation region 24 is exposed (see CC' direction in (a) of FIG. 3D ).

[0101] Step 11: selectively remove the exposed sacrificial layer 212 by wet etching (see the BB' direction and CC' direction in (b) of FIG. 3D ).

[0102] Step 12: Etch the shallow trench isolation region 24 until the second portion of the fin structure (ie, the second active structure 121 ) is exposed (see (c) in FIG. 3D ).

[0103] In some embodiments, during the etching process of the shallow trench isolation region 24, a certain thickness of the shallow trench isolation region 24 is retained as a shallow trench isolation layer 241. The shallow trench isolation layer 241 is used to isolate the first transistor 11 from the second transistor 12. The thickness of the shallow trench isolation layer 241 can be selected according to actual conditions and is not limited in the present disclosure.

[0104] Step 13: Form the source structure and drain structure 124 in the second transistor 12 (see (a) in FIG3E ). The process can be referred to step 8, and will not be described in detail in this embodiment of the disclosure.

[0105] It should be noted that the second interlayer dielectric 123 in the second transistor 12 and the first interlayer dielectric 113 in the first transistor 11 can be made of the same material or different materials, and can be selected according to actual conditions. This embodiment of the present disclosure does not limit this.

[0106] Step 14: Remove the dummy gate structure 23 by etching, and form a gate dielectric layer 14 on the surface of the fin structure 22A (see (b) in FIG3E ). Then, deposit a metal material in the gate region to form a gate structure 26 , which now wraps around the fin structure 22A.

[0107] Step 15: Etch the upper portion of the gate structure 26 to expose the second portion of the fin structure 22A. The unetched gate structure 26 is the first gate structure 112 in the first transistor 11 (see (c) in FIG. 3E ).

[0108] Step 16: Deposit a layer of insulating material on the first gate structure 112 to form an insulating dielectric layer 13 (see (a) in FIG. 3F ).

[0109] Step 17: depositing a metal material on the insulating dielectric layer 13 to form a second gate structure 122 (see FIG. 3F (b)).

[0110] In some embodiments, the insulating dielectric layer 13 is used to isolate the first gate structure 112 from the second gate structure 122 .

[0111] Step 18: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0112] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed.

[0113] It should be noted that the substrate used in Figures 3A and 3F is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 3A and 3F. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 can be electrically isolated by the BOX. The schematic diagram of the resulting semiconductor structure 10 is shown in Figure 4. Figure 4 is a schematic diagram of a second structure of the semiconductor structure in the present disclosure. In some embodiments, Figure 4 (a) is a top view of the semiconductor structure. It should be noted that for ease of understanding, the top view only shows the fin structure, gate structure, source structure, and drain structure; (b) is a cross-sectional view of the semiconductor structure taken along the fin structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the source and drain structures (i.e., BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the gate structure (i.e., CC' direction). As shown in FIG. 4 , the BOX is located between the first active structure 111 and the second active structure 121 , and the BOX can achieve electrical isolation between the first active structure 111 and the second active structure 121 .

[0114] In some embodiments, the first transistor and the second transistor may also be all-around gate transistors. As shown in Figure 5, Figure 5 is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present disclosure. In some embodiments, Figure 5 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, Figure 5 (a) only shows the nanosheet, gate structure, source structure and drain structure. Figure 5 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet (i.e., AA' direction); Figure 5 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and the drain structure (i.e., BB' direction); Figure 5 (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0115] As shown in FIG5 , the first active structure 111 in the first transistor 11 and the second active structure 121 in the second transistor 12 are multiple parallel nanosheets. The first active structure 111 and the second active structure 121 are active structures formed in the same process. The upper half of the active structure serves as the first active structure 111 in the first transistor 11, and the lower half of the active structure serves as the second active structure 121 in the second transistor 12. The semiconductor structure 10 shown in FIG5 has the same structure except that the first active structure 111 and the second active structure 121 are different from the first active structure 111 and the second active structure 121 in FIG2 , and is not further described in the present embodiment.

[0116] The following describes the preparation process of the semiconductor structure shown in Figure 5 in conjunction with the above preparation method. The semiconductor structure shown in Figure 5 can be prepared by the process shown in Figures 6A to 6F, which are schematic diagrams of the second preparation process of the semiconductor structure in the embodiment of the present disclosure.

[0117] In another example, taking the first transistor 11 and the second transistor 12 as all-around gate transistors as an example, the second preparation process of the semiconductor structure 10 may include the following steps:

[0118] Step 1: Provide a substrate 21 (see (a) in FIG6A ). In some embodiments, substrate 21 is formed by alternately depositing two semiconductor material layers (e.g., Si and SiGe) on an underlying silicon layer. In some embodiments, the SiGe layer serves as a sacrificial layer for fabricating nanosheets in gate-all-around transistors.

[0119] Step 2: Etching the substrate 21 to form a columnar structure 31 on the substrate 21 (see (b) in FIG. 6A ).

[0120] Step 3: The gate region is opened through photolithography, and polysilicon is deposited in the gate region as a dummy gate structure 23. STI is then filled in the remaining areas except the gate region to form shallow trench isolation regions 24, and planarization is performed through CMP (see (c) in FIG6A ). The process can be referred to as step 3 of the first method for preparing the semiconductor structure.

[0121] Step 4: Remove the dummy gate structure 23 by etching until the columnar structure 31 is exposed (see (a) in FIG. 6B ).

[0122] Step 5: Use wet etching to selectively remove the exposed SiGe layer (ie, the sacrificial layer at the gate region) (see (b) in FIG. 6B ).

[0123] Step 6: Poly Si is deposited again in the gate region to form a dummy gate structure 23 (see (c) in FIG. 6B ). The process can be referred to the sixth step of the first method for preparing the semiconductor structure.

[0124] Step 7: The upper half of the shallow trench isolation region 24 is removed by etching, exposing the upper half (i.e., the first portion) of the columnar structure 31 (see (a) in FIG6C ). Ion implantation is performed at the boundary between the exposed upper half of the columnar structure 31 and the unexposed lower half (i.e., the second portion) of the columnar structure 31 to form an electrical isolation layer (not shown).

[0125] Step 8: Form spacers 25 on both sides of the upper portion of the dummy gate structure 23 and use the spacers 25 as masks to form the source and drain structures 114 in the first transistor 11 (see FIG. 6C (b)).

[0126] Step 9: Deposit a first interlayer dielectric 113 on the source and drain structures 114 and between the dummy gate structures 23 (see (c) in FIG. 6C ). The process can be referred to step 8 of the first method for manufacturing a semiconductor structure.

[0127] Step 10: Perform a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and deposit an insulating material above the first metal interconnection layer 115 to form a first insulating layer 116. The first insulating layer 116 is bonded to the carrier wafer 117, and then the wafer currently manufactured is flipped over (see (a) in Figure 6D).

[0128] Step 11: Use CMP process to thin the flipped wafer and remove the bottom silicon layer until the SiGe layer at the bottom of the columnar structure 31 is exposed (see BB' direction in (b) of FIG. 6D ).

[0129] Step 12: Etch the shallow trench isolation region 24 until the second portion of the columnar structure 31 is exposed (see (c) in FIG. 6D ). The process can refer to step 12 of the first method for preparing the semiconductor structure.

[0130] Step 13: Form the source and drain structures 124 in the second transistor 12 (see (a) in FIG. 6E ), and deposit a second interlayer dielectric 123 on the source and drain structures 124 in the second transistor and between the dummy gate structures 23. For the same process, refer to step 8 of the first method for fabricating a semiconductor structure.

[0131] Step 14: Remove the dummy gate structure 23 by etching, thus forming multiple nanosheets 22B arranged in parallel within the semiconductor structure 10. A gate dielectric layer 14 is formed on the surfaces of the multiple nanosheets. Metal material is then deposited in the gate region to form a gate structure 26 (see FIG6E(b)).

[0132] Step 15: Form the first gate structure 112 and the second gate structure 122 (see FIG6F ). The formulas can be found in steps 15 to 17 of the first method for manufacturing the semiconductor structure.

[0133] Step 16: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0134] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are all-around gate transistors is completed.

[0135] It should be noted that the substrate used in Figures 6A and 6F is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 6A and 6F. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure of the first transistor and the second active structure of the second transistor can be electrically isolated by the BOX. The schematic diagram of the resulting semiconductor structure is shown in Figure 7. Figure 7 is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present disclosure. Figure 7 (a) is a top view of the semiconductor structure. It should be noted that for ease of understanding, the top view only shows the nanosheet, gate structure, source structure, and drain structure; (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the nanosheet (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source structure and drain structure (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the CC' direction). As shown in FIG7 , the BOX is located between the first active structure and the second active structure, and the BOX can achieve electrical isolation between the first active structure and the second active structure.

[0136] Below, taking the first transistor and the second transistor as planar transistors as an example, the fifth structural schematic diagram of the semiconductor structure is described. Figure 8 is a fifth structural schematic diagram of the semiconductor structure in the embodiment of the present disclosure. (a) in Figure 8 is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the block planar structure, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the block planar structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and the drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0137] 8 , the first active structure 111 in the first transistor 11 and the second active structure 121 in the second transistor 12 are block-shaped planar structures. The first active structure 111 and the second active structure 121 are block-shaped planar structures formed in the same process. The upper half of the active structure serves as the first active structure 111 in the first transistor 11, and the lower half of the active structure serves as the second active structure 121 in the second transistor 12. The semiconductor structure shown in FIG8 is identical to the first active structure 111 and the second active structure 121 in FIG2 , except that the first active structure 111 and the second active structure 121 differ from each other. This is not described in detail in the present disclosure.

[0138] The following describes the preparation process of the semiconductor structure shown in Figure 8 in conjunction with the above preparation method. The semiconductor structure shown in Figure 8 can be prepared by the process shown in Figures 9A to 9F, which are schematic diagrams of the third preparation process of the semiconductor structure in the embodiment of the present disclosure.

[0139] In another example, taking the first transistor 11 and the second transistor 12 as planar transistors as an example, the third preparation process of the semiconductor structure 10 may include the following steps:

[0140] Step 1: Provide a silicon substrate 21 (see (a) in FIG9A ). In some embodiments, the silicon substrate 21 is composed of a bottom silicon layer 211, a sacrificial layer 212, and a top silicon layer 213. The sacrificial layer 212 is made of SiGe.

[0141] Step 2: Etching both sides of the silicon substrate 21 to form a block-shaped planar structure 22C (see (b) in FIG. 9A ).

[0142] Step 3: The gate region is opened by photolithography and poly Si is deposited in the gate region as a dummy gate structure 23. Then, STI is filled in the remaining areas except the gate region to form shallow trench isolation regions 24, and planarization is performed by CMP (see (c) in Figure 9A).

[0143] Step 4: Remove the dummy gate structure 23 by etching to expose the block planar structure 22C and the sacrificial layer 212 (see (a) in FIG. 9B ).

[0144] Step 5: Use wet etching to selectively remove the exposed sacrificial layer 212 (see (b) in FIG. 9B ).

[0145] Step 6: Poly Si is deposited again in the gate region to form a dummy gate structure 23 (see (c) in FIG. 9B ). The process can be referred to the sixth step of the first method for preparing the semiconductor structure.

[0146] Step 7: The upper half of the shallow trench isolation region 24 is removed by etching to expose the first portion of the block planar structure 22C (see (a) in FIG. 9C ). Ion implantation is performed at the boundary between the exposed first portion and the unexposed second portion of the block planar structure 22C to form an electrical isolation layer (not shown).

[0147] Step 8: Forming the source structure and drain structure 114 of the first transistor 11 (see (b) in FIG9C ). The process can refer to step 8 of the first method for manufacturing a semiconductor structure.

[0148] Step 9: Perform a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and deposit an insulating material above the first metal interconnection layer 115 to form a first insulating layer 116. The first insulating layer 116 is bonded to the carrier wafer 117, and then the currently manufactured wafer is flipped over (see (c) in Figure 9C).

[0149] Step 10: The flipped wafer is thinned using a CMP process until the sacrificial layer 212 wrapped by the shallow trench isolation region 24 is exposed (see (a) in FIG. 9D ).

[0150] Step 11: selectively remove the exposed sacrificial layer 212 by wet etching (see (b) in FIG. 9D ).

[0151] Step 12: Etch the shallow trench isolation region 24 until the second portion of the block planar structure 22C is exposed (see (c) in FIG. 9D ). The process can refer to step 12 of the first method for preparing the semiconductor structure.

[0152] Step 13: Form the source structure and drain structure 124 in the second transistor 12 (see (a) in FIG9E ). The process can be referred to step 8 of the first method for preparing the semiconductor structure, which will not be described in detail in this embodiment.

[0153] Step 14: Remove the dummy gate structure 23 by etching, and form a gate dielectric layer 14 on the surface of the block planar structure 22C. Then, deposit a metal material in the gate region to form a gate structure 26 (see FIG. 9E (b)).

[0154] Step 15: Form the first gate structure 112 and the second gate structure 122 (see FIG. 9F ). The process can refer to steps 15 to 17 of the first method for manufacturing the semiconductor structure.

[0155] Step 16: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0156] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are planar transistors is completed.

[0157] It should be noted that the substrate used in Figures 9A and 9F is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 9A and 9F. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 can be electrically isolated by the BOX. The schematic diagram of the resulting semiconductor structure is shown in Figure 10. Figure 10 is a schematic diagram of the sixth structure of the semiconductor structure in the embodiment of the present disclosure. Figure 10 (a) is a top view of the semiconductor structure. It should be noted that for ease of understanding, the top view only shows the block planar structure, gate structure, source structure, and drain structure; (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the block planar structure (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source structure and drain structure (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the CC' direction). As shown in FIG. 10 , the BOX is located between the first active structure 111 and the second active structure 121 , and the BOX can achieve electrical isolation between the first active structure 111 and the second active structure 121 .

[0158] In the embodiment of the present disclosure, the source structure and drain structure of the first transistor and the source structure and drain structure of the second transistor are first prepared, and then the first gate structure of the first transistor and the second gate structure of the second transistor are respectively prepared at the first groove. This can simplify the preparation process and improve the thermal budget when preparing the second transistor. At the same time, since the first gate structure and the second gate structure are both formed at the first groove, the first gate structure and the second gate structure are self-aligned in the vertical direction.

[0159] In some embodiments, a first transistor is formed based on a first active structure, and after flipping the wafer, a second transistor is formed based on a second active structure, so that the active structures of the first transistor and the second transistor are "back-to-back" designs, thereby achieving self-alignment of the first transistor and the second transistor.

[0160] In some embodiments, the self-alignment of the gate structure and the transistors makes the active areas and gates of the first transistor and the second transistor consistent, while solving problems such as high defect density, complex process, fixed polarity and alignment difficulties.

[0161] In some embodiments, the preparation method of the above-mentioned semiconductor structure is a fusion of sequential stacking and monolithic stacking schemes. The technology is mature and has high reusability. It can avoid expensive process development to save costs and has high feasibility.

[0162] In some embodiments, the first transistor and the second transistor have independent signal and power supply networks and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (more than 60% improvement compared to the current solution), and there is huge room for collaborative optimization of process design. Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets and even vertical transistors (vertical transport field effect transistors, VTFETs) without the need for special process development for specific device architectures, making it more flexible and highly extensible from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for expansion.

[0163] The present disclosure provides a semiconductor device including the semiconductor structure described in the above embodiment. The semiconductor structure can be defined by referring to the semiconductor structures shown in FIG. 2 , FIG. 4 , FIG. 5 , FIG. 7 , FIG. 8 , and FIG. 10 .

[0164] An embodiment of the present disclosure provides an electronic device comprising: a circuit board and a semiconductor device as described in the above embodiment, the semiconductor device being disposed on the circuit board. The semiconductor device includes the above-described semiconductor structure. The semiconductor structure can be defined with reference to the semiconductor structures shown in Figures 2, 4, 5, 7, 8, and 10.

[0165] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0166] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, comprising: Providing a substrate, wherein the substrate is a wafer; forming an active structure on the substrate, the active structure comprising a first portion and a second portion; Depositing a semiconductor material on the active structure to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on both sides of a third portion of the dummy gate structure, wherein the third portion is a portion of the dummy gate structure corresponding to the first portion; Flipping the wafer and removing the substrate; forming a source structure and a drain structure of a second transistor on both sides of a fourth portion of the dummy gate structure, wherein the fourth portion is a portion of the dummy gate structure corresponding to the second portion; Etching the dummy gate structure to form a first groove; A first gate structure of the first transistor and a second gate structure of the second transistor are respectively formed at the first groove, and the first gate structure and the second gate structure are self-aligned in a vertical direction.

2. The method according to claim 1, wherein: Before flipping the wafer, the method further includes: A first insulating layer is deposited on top of the wafer and bonded to a carrier wafer.

3. The method according to claim 1, wherein: The method further comprises: A gate dielectric layer is deposited on the surface of the active structure, and the gate dielectric layer is used to isolate the first portion from the first gate structure and the second portion from the second gate structure.

4. The method according to claim 3, wherein: The forming of a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove respectively comprises: Depositing a metal material in the first groove to form a gate structure; Etching a gate structure corresponding to the second portion to form a first gate structure and expose the second portion; Depositing an insulating material on a surface of the first gate structure to form an insulating dielectric layer, wherein the insulating dielectric layer is used to isolate the first gate structure from the second gate structure; A metal material is deposited on the surface of the insulating dielectric layer to form a second gate structure.

5. The method according to claim 1, wherein: After forming a source structure and a drain structure of the first transistor on both sides of the third portion of the dummy gate structure, the method further includes: A back-end process is performed above the source structure and the drain structure of the first transistor to form a first metal interconnection layer of the first transistor.

6. The method according to claim 1, wherein: After forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first trench, respectively, the method further includes: A back-end process is performed above the source structure and the drain structure of the second transistor to form a second metal interconnection layer of the second transistor.

7. The method according to claim 1, wherein: After forming an active structure on the substrate, the method further comprises: Ion implantation is performed at a connection between the first portion and the second portion to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first portion from the second portion.

8. The method according to claim 7, wherein: The ions implanted include P-type ions, N-type ions or oxygen ions.

9. The method according to claim 1, wherein: The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

10. The method according to claim 9, wherein: The active structure includes one of the following: at least one fin-like structure; A plurality of nanosheets or nanowires arranged in parallel; Blocky planar structure.

11. A semiconductor structure, wherein the semiconductor structure is prepared by the method according to any one of claims 1 to 10, and the semiconductor structure comprises: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are formed by the same process; and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned in a vertical direction.

12. The semiconductor structure according to claim 11, wherein: An insulating dielectric layer is provided between the first gate structure and the second gate structure, and the insulating dielectric is used to isolate the first gate structure from the second gate structure.

13. The semiconductor structure according to claim 11, wherein: An electrical isolation layer is provided between the first active structure and the second active structure.

14. The semiconductor structure according to claim 11, wherein: The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

15. The semiconductor structure according to claim 14, wherein: The first active structure and the second active structure constitute an active structure, and the active structure is at least one of the following: Fin-like structure; Nanosheets; Nanowires; Blocky planar structure.

16. A semiconductor device comprising: A semiconductor structure as claimed in any one of claims 11 to 15.

17. An electronic device comprising: A circuit board and a semiconductor device as claimed in claim 16, wherein the semiconductor device is arranged on the circuit board.

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