DC power distribution and protection system

Abstract

A DC power distribution and protection system comprising: a first DC power source (21) having a positive terminal (211) and a negative terminal (212), a first load (R1), a first power bus (31, 41) connecting the first power source (21) and the first load (R01), a first solid state power controller (SSPC_A) integrated into the first power bus (31, 41) at a power source side (61) of the first power bus, and a second solid state power controller (SSPC_B) integrated into the first power bus (31, 41) at a load side (62) of the first power bus A first bypass line (51) is provided that extends between an upstream switching device (SSPC_A1) of the first solid state power controller (SSPC_A) and a downstream switching device (SSPC_B2) of the second solid state power controller (SSPC_B), the first bypass line (51) bypassing a downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and an upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B). The first bypass line (51) comprises at least one bypass switching device (SSPC_R1, SSCP_R2, CT), and is configured to be switched on only if the downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B) are switched off.

Description

[0001] DC POWER DISTRIBUTION AND PROTECTION SYSTEM

[0002] Field of the disclosure

[0003] The present disclosure relates a DC power distribution and protection system, in particular for aerospace and marine power systems.

[0004] Background

[0005] DC power distribution is a critical technology required in both aerospace and marine industries. DC power distribution and protection systems serves to connect at least one DC power source with at least one load and provide protection against fault conditions such as a short-circuit condition. To break a current, SSPCs (Solid State Power Controllers, also referred to a Solid State Protection Controllers) are preferred over electro-mechanical switches as they show a fast response time, eliminate arcing during turn-off, and have a higher reliability.

[0006] SSPC units may be implemented in the positive rail and / or the negative rail of a DC power distribution and protection systems. One limitation of using such architecture lies in that in case of a short circuit fault at the DC common bus, all basic SSPC units will trip such that critical loads will lose all power supply from the DC power source. However, this may not be acceptable for critical loads. For example, critical loads may suffer from losing power supply in case of a DC common bus short circuit fault. One solution is to provide a separate backup DC power source. Such solution, however, increases weight and costs.

[0007] There is a need to provide for a DC power distribution and protection system which allows to maintain power supply to a load even in case of a short-circuit condition, thereby avoiding the need for a separate backup DC power source, or at least provides a useful alternative to known DC power distribution and protection systems.

[0008] Summary of the disclosure

[0009] According to a first aspect of the invention, a DC power distribution and protection system is provided for, the system comprising a first DC power source having a positive terminal and a negative terminal, a first load, and a first power bus connecting the first power source and the first load, the first power bus comprising a high side voltage rail connected to the positive terminal and a low side voltage rail connected to the negative terminal. The system further comprises a first solid state power controller (SSPC) integrated into the first power bus at a power source side of the first power bus and a second solid state power controller integrated into the first power bus at a load side of the first power bus. Each solid state power controller comprises an upstream switching device and a downstream switching device connected in common source / emitter configuration in the high side voltage rail and an upstream switching device and a downstream switching device connected in common source / emitter configuration in the low side voltage rail.

[0010] A first bypass line is provided that extends between the upstream switching device of the first solid state power controller and the downstream switching device of the second solid state power controller in the high side voltage rail or in the low side voltage rail, the first bypass line bypassing the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller, wherein the first bypass line comprises at least one bypass switching device, and wherein the bypass switching device is configured to be switched on only if the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller are switched off.

[0011] Aspects of the present invention are thus based on the idea to provide for a redundant leg in the form of a bypass line to protect and maintain the power supply to a critical load in case of a common bus failure in the DC power distribution and protection system. The bypass line bypasses a downstream switching device of the first solid state power controller and an upstream switching device of the second solid state power controller and thus those elements which trip in case of a short-circuit (in particular if an additional decoupling capacitor is provided in the SSPCs as discussed below) and provides an additional, redundant connection path between a DC power source and a load. The bypass line is not operational during normal operating mode but only activated during fault conditions.

[0012] At the same time, the upstream switching device of the first solid state power controller and the downstream switching device of the second solid state power controller continue to operate and are located in series with the at least one bypass switching device in case the bypass line is activated.

[0013] The bypass line and the at least one bypass switching device located in the bypass line represent a redundant DC circuit with a potentially reduced number of switching devices to supply the first load. By providing a bypass line in case of a short-circuit condition or other fault condition, it is possible to maintain power supply to a critical load in a simple manner, without the requirement of a separate backup DC power source.

[0014] Aspects of the present invention are further based on the idea to allow maintaining power supply at a critical load with a reduced number of switching devices: while two switching devices are bypassed by the first bypass line, the at least one bypass switching device may consist of a single switching device in embodiments, such that a reduced complexity is provided for.

[0015] The present invention is based on a DC power distribution and protection system in which an SSPC architecture is implemented that allows control of the current flow between connected source and load and which also supports power transfer and protection capability to various fault conditions, wherein SSPCs are implemented both in the positive rail and in negative rail of the power bus independently, thereby allowing to isolate the positive rail and the negative rail independently in case of a short-circuit or ground fault. The SSPC architecture may be a bidirectional SSPC architecture that allows bidirectional control of the current flow between connected source and load. In such case, bidirectional SSPCs are implemented in the power buses.

[0016] There may be provided one or several bypass lines to one or several critical loads dependent on the particular architecture of the system.

[0017] In some embodiments, the at least one bypass switching device comprises a semiconductor switch. Such semiconductor switch is arranged in series between the upstream switching device of the first solid state power controller and the downstream switching device of the second solid state power controller. By providing the bypass switching device in the form of a semiconductor switch, high reliability and short switching times can be implemented.

[0018] In some embodiments, the at least one bypass switching device comprises an upstream semiconductor switching device and a downstream semiconductor switching device connected in common source / emitter configuration. In such embodiments, two switching devices are provided in series in the bypath line.

[0019] In some embodiments, the at least one bypass switching device is not a semiconductor switch but a mechanical contactor. In the normal operation mode when there is no fault the contactor is kept open and then under common bus failure condition the contactor can be closed. Implementing the at least one bypass switching device as a mechanical contactor is associated with the advantage that a full galvanic isolation can be achieved in the bypass lane.

[0020] A contactor within the meaning of the present invention is any electromechanical control device that is used to make or break an electrical connection. A contactor is controlled by a circuit which has a much lower power level than the switched circuit. A contactor knows two switching positions and is typically monostable, wherein bi-stable contactors may be provided as well. In some embodiments, a second bypass line extending between the upstream switching device of the first solid state power controller and the downstream switching device of the second solid state power controller in the other of the high side voltage rail and the low side voltage rail is provided, the second bypass line bypassing the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller, wherein the second bypass line also comprises at least one bypass switching device. In such embodiments, accordingly, a redundant leg in the form of a bypath line and at least one bypass switching element is provided both in the positive rail and in the negative rail.

[0021] The at least one bypass switching device of the second bypass line may also be a semiconductor switch. In such embodiments, both in the first bypass line and in the second bypass line a semiconductor switch may be implemented as bypass switching device. The two bypass semiconductor switches may be elements of a further SSPC.

[0022] In some embodiments, both the first and the second solid state power controllers comprise a decoupling capacitor, the respective decoupling capacitor arranged between the middle point between the upstream switching device and the downstream switching device of the high side voltage rail and the middle point between the upstream switching device and the downstream switching device of the low side voltage rail.

[0023] Such decoupling capacitor allows to decouple a downstream DC network fault from an upstream network fault. With such decoupling capacitor, it can be ensured that in case of a short-circuit or other fault in the DC common bus, only the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller trip, while the upstream switching device of the first solid state power controller and the downstream switching device of the second solid state power controller remain functioning and can participate in providing power to the critical load through the bypass line.

[0024] In addition, it may be provided that the decoupling capacitor is configured to be intermittently charged in a pre-charging mode of the system, wherein the charge of the decoupling capacitor is transferred to a capacitive load during pre-charging to avoid inrush currents when powering up the system. Accordingly, the decoupling capacitor may also be helpful when pre-charging the DC power bus.

[0025] The switching devices may be MOSFET, IGBT, JFET, and GaN transistors. The SSPC may further comprise at least one inductance which is configured to limit the rate of rise of current in case of a short-circuit fault.

[0026] In some embodiments, the power protection system of any of the present invention further comprises a controller controlling the operation of the solid state power controllers and of the at least one bypass switching device. In particular, the state of the switching devices may be controlled in that the controller controls the gate voltage of the semiconductor switching devices.

[0027] In some embodiments, the controller is configured to: switch the first and second solid state power controllers on in case of a normal operation mode of the system; switch the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller off in case of a short-circuit condition or other fault condition at the first power bus; and subsequently switch on the at least one bypass switching device to activate the first bypass line.

[0028] Accordingly, under the control of the controller, the at least one bypass switching device is only activated after some of the switching devices of the SSPCs used under normal operation mode have been deactivated.

[0029] In a refinement of such control, when a bypass line is provided both at the high side voltage rail and the low side voltage rail of the first power bus, the controller is configured to: switch all switching devices of the first and second solid state power controllers on in case of a normal operation mode of the system; switch the downstream switching devices of the first solid state power controller and the upstream switching devices of the second solid state power controller off in case of a short-circuit condition or other fault condition at the first power bus; check if the first load is a critical load that needs to be powered up; and if so, subsequently switch on the at least one bypass switching device of the first bypass line and the at least one bypass switching device of the second bypass line.

[0030] Accordingly, there may be a check if the first load is a critical load (meaning that the load is under a critical condition) and only in such case the bypass switching devices of the first and second bypass lines are activated. If the load is under a critical condition may be sensed by sensors providing their information to the controller. However, such a check is optional.

[0031] In some embodiments, the power protection system further comprises: a second DC power source having a positive terminal and a negative terminal; a second power bus connecting the second power source and the first load, the second power bus comprising a high side voltage rail connected to the positive terminal and a low side voltage rail connected to the negative terminal, wherein the high side voltage rail of the first power bus and the high side voltage rail of the second power bus are connected and wherein the low side voltage rail of the first power bus and the low side voltage rail of the second power bus are connected; and a third solid state power controller integrated into the second power bus at the DC power source side of the second power bus, the third solid state power controller comprising an upstream switching device and a downstream switching device connected in common source / emitter configuration in the high side voltage rail and an upstream switching device and a downstream switching device connected in common source / emitter configuration in the low side voltage rail.

[0032] Accordingly, in such embodiments, a further (the second) DC power source is connected to the first load, wherein the high side voltage rails and the low side voltage rails of the first and second power buses are interconnected, such that the first load is also powered by the second DC power source. The first DC power source and the second DC power source can be considered to be arranged in parallel. A further SSPC (the third SSPC) is integrated into the second power bus at the DC power source side, this SSPC protecting the second DC power source in case of a short-circuit.

[0033] In such an arrangement, a third bypass line may be provided which extends between the upstream switching device of the third solid state power controller and the downstream switching device of the second solid state power controller in the high side voltage rail, the third bypass line bypassing the downstream switching device of the third solid state power controller and the upstream switching device of the second solid state power controller, wherein the third bypass line comprises at least one bypass switching device. The third bypass line regards the high side voltage rail. In addition or alternatively, a fourth bypass line may be provided which extends between the upstream switching device of the third solid state power controller and the downstream switching device of the second solid state power controller in the low side voltage rail, the third bypass line bypassing the downstream switching device of the third solid state power controller and the upstream switching device of the second solid state power controller, wherein the fourth bypass line comprises at least one bypass switching device. The fourth bypass line regards the low side voltage rail. If the positive rail and the negative rail are arranged symmetrically, both the third bypass line and the fourth bypass line are provided.

[0034] There may be provided further DC power sources and further bypass lines to the first (critical) load.

[0035] In some embodiments, the power protection system comprises additional DC power sources and additional loads connected through an additional DC power bus, the additional DC power bus having a high side voltage rail and a low side voltage rail, wherein the high side voltage rails of the first power bus and of the additional power bus and / or the low side voltage rails of the first power bus and of the additional power bus are connected through an additional solid state power controller, and wherein the additional solid state power controller is configured to be switched off in case of a short-circuit condition or other fault condition at the first power bus. In such embodiments, a two DC power bus system is provided, wherein the two DC power buses are linked through an SSPC (the additional SSPC). Under normal operation, when the additional SSPC is switched on, the two DC power buses are interconnected and the power sources of the two DC power buses jointly provide power to the loads connected to the two power buses. However, in case of a short-circuit fault in the first DC power bus (when some of the switching devices of the SSPCs in the first DC power bus trip), the additional SSPC is switched off such that the second DC power bus is disconnected from the first DC power bus and not affected by the short circuit fault in the first DC power bus. The additional SSPC thus allows to separate the two DC power buses in case of a short-circuit in one of the DC power buses.

[0036] In some embodiments, the additional solid state power controller comprises a first additional switching device and a second additional switching device and connected in common source / emitter configuration in the high side voltage rail and a third additional switching device and a fourth additional switching device and connected in common source / emitter configuration in the low side voltage rail, wherein the controller is configured to: switch all switching devices of the first and second solid state power controllers and of the additional solid state power controller on in case of a normal operation mode of the system; switch the downstream switching devices of the first solid state power controller and the upstream switching device of the second solid state power controller and all switching devices of the additional solid state power controller off in case of a short-circuit condition or other fault condition at the first power bus (thereby disconnecting the link to the second power bus); check if the first load is a critical load that needs to be powered up; and if so, subsequently switch on the at least one bypass switching device of the first bypass line and the at least one bypass switching device of the second bypass line (thereby opening the first and second bypass lines to the first load).

[0037] In some embodiments, the additional DC power sources and the additional loads connected through the additional DC power bus include: a third DC power source having a positive terminal and a negative terminal; a third load; a third power bus connecting the third power source and the third load, the third power bus comprising a high side voltage rail connected to the positive terminal and a low side voltage rail connected to the negative terminal; a fourth solid state power controller integrated into the third power bus at a power source side of the third power bus; a fifth solid state power controller integrated into the third power bus at a load side of the third power bus; the fourth and fifth solid state power controller each comprising an upstream switching device and a downstream switching device connected in common source / emitter configuration in the high side voltage rail and an upstream switching device and a downstream switching device connected in common source / emitter configuration in the low side voltage rail; and a fifth bypass line extending between the upstream switching device of the fourth first solid state power controller and the downstream switching device of the fifth solid state power controller in the high side voltage rail or in the low side voltage rail, the fifth bypass line bypassing the downstream switching device of the fourth solid state power controller and the upstream switching device of the fifth solid state power controller, wherein the fifth bypass line comprises at least one bypass switching device.

[0038] In such embodiments, an additional, third DC power source is connected to an additional, third load through an additional, third power bus (that is connected to the first power bus through the additional SSPC), wherein similar as with the first power bus a bypass line is provided that includes another bypass switching device. The function is the same as discussed with respect to the first bypass line branching off the first power bus. There is thus provided a two-bus system with two redundant bypass lines in such embodiments.

[0039] In a further refinement of such embodiments, the power protection system may further comprise at least one additional DC power source and / or at least one additional load. The present invention is not limited to any particular number of DC power sources and loads.

[0040] Generally, the switching devices may be implemented with antiparallel diodes.

[0041] In some embodiments, the DC power sources and the loads may be connected such that each of the DC power sources powers at least two of the loads and in that each of the loads is powered by at least two of the DC power sources. Accordingly, a DC network is provided for with the ability to share energy between different lanes (power buses) and / or to provide for redundancy in case of a failure.

[0042] The first load may be or comprise a power converter circuitry, such as a three phase inverter circuitry used to drive electric motors.

[0043] According to a second aspect of the invention, a DC power distribution and protection system is provided for, the system comprising a first DC power source having a positive terminal and a negative terminal, a first load, and a first power bus connecting the first power source and the first load, the first power bus comprising a high side voltage rail connected to the positive terminal and a low side voltage rail connected to the negative terminal. The system further comprises a first solid state power controller (SSPC) integrated into the first power bus at a power source side of the first power bus and a second solid state power controller integrated into the first power bus at a load side of the first power bus. Each solid state power controller comprises an upstream switching device and a downstream switching device connected in common source / emitter configuration in the high side voltage rail and an upstream switching device and a downstream switching device connected in common source / emitter configuration in the low side voltage rail. Further, a bypass line is provided that connects the first DC power source with the first load under bypassing of the upstream switching device and the downstream switching device of the first solid state power controller and of the upstream switching device and the downstream switching device of the second solid state power controller in one of the high side voltage rail and the low side voltage rail, wherein the bypass line comprises at least one bypass switching device, and wherein the bypass switching device is configured to be switched on only if the mentioned switching devices are switched off.

[0044] According to this aspect of the invention, the bypass line bypasses the upstream and downstream switching devices of the first and second solid state power controllers in one of the lanes (and not only the downstream switching device of the first solid state power controller and the upstream switching device of the second solid state power controller as in the first aspect of the invention). Such implementation is suitable in the case that in only one of the high side voltage rail and low side voltage rail a bypass line is implemented, and not in both. If in such case the bypass line was implemented between the middle points of the first and second solid state power controllers as in the first aspect, this would lead to a short circuit on the common bus.

[0045] In some embodiments, the at least one bypass switching device comprises a semiconductor switch. By providing the bypass switching device in the form of a semiconductor switch, high reliability and short switching times can be implemented.

[0046] In some embodiments, the at least one bypass switching device comprises an upstream semiconductor switching device and a downstream semiconductor switching device connected in common source / emitter configuration.

[0047] In some embodiments, the at least one bypass switching device is not a semiconductor switch but a mechanical contactor. In the normal operation mode when there is no fault the contactor is kept open and then under common bus failure condition the contactor can be closed. Implementing the at least one bypass switching device as a mechanical contactor is associated with the advantage that a full galvanic isolation can be achieved in the bypass lane.

[0048] Further embodiments of the second aspect of the invention correspond to embodiments of the first aspect of the invention, such as the provision of a decoupling capacitor and in that the power protection system comprises additional DC power sources and / or additional loads.

[0049] The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and / or combined with any other feature or parameter described herein.

[0050] Brief description of the disclosure

[0051] The invention will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which:

[0052] FIG. 1 is a first embodiment of a DC power distribution and protection system, the DC power distribution and protection system comprising a first bypass line bypassing two semiconductor switching devices arranged in a high side voltage rail and a second bypass line bypassing two semiconductor switching devices arranged in the low side voltage rail of the DC power distribution and protection system, wherein the bypass lines provide for a backup path to provide power to a critical load;

[0053] FIG. 2 is a flowchart of a method used in the DC power distribution and protection system of FIG. 1 , the method controlling use of the bypass lines;

[0054] FIG. 3 is a second embodiment of a DC power distribution and protection system, the second DC power distribution and protection system comprising additional bypath lines, wherein the bypass lines connect several DC power sources and a critical load;

[0055] FIG. 4 is a third embodiment of a DC power distribution and protection system, the third DC power distribution and protection system comprising a single bypass line in which two semiconductor switches are arranged in series;

[0056] FIG. 5 is a fourth embodiment of a DC power distribution and protection system, the fourth DC power distribution and protection system comprising a single bypass line with a mechanical contactor as bypass switching device;

[0057] FIG. 6 is a fifth embodiment of a DC power distribution and protection system, the fifth DC power distribution and protection system comprising a first common power bus at a second common power bus each connecting DC power sources and loads, wherein the two common power buses are interconnected through an SSPC, and wherein first and second bypass lines are provided in the first common power bus;

[0058] FIG. 7 is a flowchart of a method used in the DC power distribution and protection system of FIG. 6, the method controlling use of the bypass lines; FIG. 8 is a sixth embodiment of a DC power distribution and protection system, the sixth DC power distribution and protection system comprising a first common power bus and a second common power bus each connecting DC power sources and loads, wherein the two common power buses are interconnected through an SSPC, and wherein bypass lines are provided for the first common power bus and for the second common power bus;

[0059] FIG. 9 is an example architecture of a bidirectional SSPC; and

[0060] FIG. 10 is an example of a DC power distribution and protection system not in accordance with the present invention:

[0061] Detailed description

[0062] Before discussing embodiments of the present invention with respect to FIGs. 1 to 8, the background of the invention is discussed with respect to FIGs. 9 and 10 to provide for a better understanding of the present invention.

[0063] FIG. 10 shows an example DC power distribution and protection system which comprises three DC power sources 21 , 22, 23 and two loads R1 , R2 which are connected through a DC distribution network. Such system may be used in hybrid propulsion system or marine applications.

[0064] More particularly, the system of FIG. 10 comprises a first power source 21 and a first load R1 connected through a first power bus 31, 41. The first power source 21 has a positive terminal 211 and a negative terminal 212. Between these terminals 211, 212 a constant DC voltage such as a battery voltage is present. A high side voltage rail 31 is connected to the DC positive terminal 211 and a low side voltage rail 41 is connected to the DC negative terminal 212. The high side voltage rail 31 and the low side voltage rail 41 form the first power bus.

[0065] In a similar manner, the system further comprises a second power source 22 and a second load R2 connected through a second power bus 32, 42. The second power source 22 has a positive terminal 221 and a negative terminal 222. Between these terminals 221, 222 a constant DC voltage such as a battery voltage is present. A high side voltage rail 32 is connected to the DC positive terminal 221 and a low side voltage rail 42 is connected to the DC negative terminal 222. The high side voltage rail 32 and the low side voltage rail 42 form the second power bus. The system further comprises a third power source 23 having an additive terminal 231 and a negative terminal 232 to which a high side voltage rail 33 and a low side voltage rail 43 are connected, which form a third power bus.

[0066] Further, the first, second and third power buses are interconnected, thereby forming a first common bus. To this end, the high side voltage rail 31 of the first power bus, the high side voltage rail 32 of the second power bus, and the high side voltage rail 33 of the third power bus are connected. Further, the low side voltage rail 41 of the first power bus, the low side voltage rail 42 of the second power bus, and the low side voltage rail 43 of the third power bus are connected. Accordingly, the same voltage VB+ is present at the high side voltage rails 31, 32, 33 and the same voltage VB- is present at the low side voltage rails 41, 42, 43. As the voltage rails 31, 32, 33 and 41 , 42, 43 share a common voltage, they may be referred to as a common bus.

[0067] In case one of the loads R1 , R2 fails, all three power sources 21, 22, 23 can be used to power the remaining load. Further, in case one of the power sources 21, 22, 23 fails, the remaining power sources can power both loads R1, R2. The loads R1 , R2, in principle, can be any load. In embodiments, each load R1, R2 comprises an inverter circuitry and an associated electric motor. Each such inverter circuitry may comprise six semiconductor power switches which provide for a three-phase current as is well known to the person skilled in the art.

[0068] There may be provided further power sources and loads connected to the system in the same manner.

[0069] In aerospace applications, the power sources 21 , 22, 23 may be battery energy storage systems or fuel cells or be fed from a turbo generator / active rectifier.

[0070] The system of FIG. 1 further comprises a plurality of SSPCs, wherein two SSPCs are integrated into the first power bus, two SSPCs are integrated into the second power bus and one SSPC is integrated into the third power bus.

[0071] More particularly, SSPC_A is located at the power source side 61 of the first power bus, SSPC_B is located at the load side 62 of the first power bus, SSPC_C is located at the power source side 61 of the second power bus, SSPC_D is located at the load side 62 of the second power bus, and SSPC_E is located at the power source side 61 of the third power bus.

[0072] All SSPCs are bidirectional, i.e., they provide bidirectional protection, e.g., because the loads R1 , R2 may backfeed. They provide a protection function for the respective individual lanes 31, 41 , 32, 42, 33, 43 both at the power source side 61 (SSPC_A, SSPC_C, SSPC_E) and at the load side 62 (SSPC_B, SSPC_D). FIG. 10 also depicts an example architecture of the SSPCs, which is shown in more detail in FIG. 9, wherein in each positive rail 31, 32, 33 and each negative rail 41 , 42, 43 two switching devices with antiparallel diodes are connected in common emitter configuration.

[0073] According to FIG. 9, each bidirectional SSPC comprises four semiconductor switches S1- S4, wherein two semiconductor switches S1, S3 with antiparallel diodes D are connected in common source / emitter configuration in the high side voltage rail 31 and two semiconductor switches S2, S4 with antiparallel diodes D are connected in common source / emitter configuration in the low side voltage rail 41. The antiparallel diodes D give current that flows in the opposite direction a path to flow. Without the diodes D, inductive currents would cease instantly, generating high voltage peaks.

[0074] The switches S1-S4 may be MOSFET, GaN (Gallium Nitride), SiC (Silicon Carbide), JFET (Junction Gate Field- Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) switches. They are controlled by the respective gate voltage, which is controlled by a controller 6. Each SSPC may comprise its own controller 6 or, alternatively, one controller 6 may provide control signals to all SSPCs.

[0075] The SSPC of FIG. 9 further schematically depicts a load RLOAD and a capacitive load CLOAD, wherein the load RLOAD may be formed, e.g., by a power converter and an electric motor driven by the power converter. The capacitive load CLOAD may comprise filtering capacitors (so called DC link capacitors) that serve to filter the ripples generated by the converter or loads.

[0076] The SSPC of FIG. 9 further comprises a decoupling capacitor C arranged between the middle point between the upstream switching device S1 and the downstream switching device S3 of the high side voltage rail 31 and the middle point between the upstream switching device S2 and the downstream switching device S4 of the low side voltage rail. The C has a much smaller capacity than the capacitive load CLOAD. Decoupling capacitor C may be intermittently charged by switches S1 to S4 and transfers its current to the capacitive load CLOAD during pre-charge, thereby avoiding a sudden rise of inrush current when the SSPC pre-charges the load capacitor CLOAD. Decoupling capacitor C further serves to decouple a downstream network fault from the upstream network.

[0077] The SSPC of FIG. 9 further comprises two inductances L1 , L2 in the high side voltage rail 31, one before switch S1 and one behind switch S3, wherein the inductances L1 , L2 are configured to limit the rate of rise of current in case of a short-circuit fault. In addition, The system of FIG. 10 may comprise inductances L for the same reason. It is pointed out that the system of FIG. 10 may comprise further elements not depicted as not relevant in the present context. The bidirectional SSPCs in the system of FIG. 10 (SSPC_A to SSPC_E) allow bidirectional control of the current flow between connected source 21 , 22, 23 and loads R1, R2. However, one limitation in the system of FIG. 10 lies in that in case of the short- circuit fault directly at the DC common bus, SSPC_A2, SSPC_A4, SSPC_B1 , SSCP_B3, SSPC_C2, S SSCP_C4, SSPC_D1, SSCP_D3, SSPC_E2 and SSPC_E4 will trip simultaneously to avoid excessive faulty current in the DC system.

[0078] In this respect it is to be noted that, because of the decoupling provided by decoupling capacitor C, semiconductor switches SSPC_A1 , SSPC_A3, SSPC_B2, SSCP_B4, SSPC-C1, S SSCP_C3, SSPC_D2, SSCP_D4, SSPC_E1 and SSPC_E3 do not trip in case of a short-circuit or other fault in the DC common bus.

[0079] Because of the tripping of semiconductor switches SSPC_A2, SSPC_A4, SSPC_B1, SSCP_B3, SSPC_C2, S SSCP_C4, SSPC_D1, SSCP_D3, SSPC_E2 and SSPC_E4, critical loads will lose all power supply from the DC sources, which may cause safety issues, e.g., for inflight aerospace power system. Similar demanding requirements may be present in More Electric Engine applications where generators are fed into a single common bus and critical loads such as oil pumps and fuel pumps which are electrically driven are also connected into the same distribution feeder, wherein a short circuit within the common bus will result in complete loss of power to those critical loads. Accordingly, critical DC loads may suffer from losing power supply in case of DC common bus short circuit fault.

[0080] To address this problem, a back-up DC circuit is provided that comprises a bypass line and a reduced number of bypass switching devices to supply a critical load in case of DC common bus short circuit fault, as will be discussed in several embodiments with respect to FIGs. 1 to 8. In this respect, in the following, it is assumed that load R1 is a critical load, e.g., a load which may be damaged, cause safety issues, etc., if its power supply is interrupted, while this is to be understood as an example only.

[0081] The system of FIG. 1 is similar to the system of FIG. 10 except that first and second bypass lines 51, 52 are provided for as backup.

[0082] The first bypass line 51 extends between the upstream switching device SSPC_A1 of the first bidirectional solid state power controller SSPC_A and the downstream switching device SSPC_B2 of the second bidirectional solid state power controller SSPC_B in the high side voltage rail 31, wherein the first bypass line 51 bypasses the downstream switching device SSPC_A2 and the upstream switching device SSPC_B1. In other words, the bypass line 51 extends from the output of SSPC_A1 to the input of SSPC_B2, or from the middle point between SSPC_A1 und SSPC_A2 to the middle point between SSPC_B1 and SSPC_B2. The first bypass line 51 comprises a bypass switching device SSPC_R1 formed by a semiconductor switch with antiparallel diode. The switching device SSPC_R1 is configured to be switched on only if the downstream switching device SSPC_A2 and the upstream switching device SSPC_B1 are switched off.

[0083] The second bypass line 52 extends in a similar manner between the upstream switching device SSPC_A3 of the first bidirectional solid state power controller SSPC_A and the downstream switching device SSPC_B4 of the second bidirectional solid state power controller SSPC_B in the low side voltage rail 41, wherein the second bypass line 52 bypasses the downstream switching device SSPC_A4 and the upstream switching device SSPC_B3. The second bypass line 52 also comprises at least one bypass switching device SSPC_R3 which is formed by a semiconductor switch with antiparallel diode.

[0084] In case of short circuit fault on the DC common bus, SSPC_A2, SSPC_A4, SSPC_B1 , SSPC_B3, SSPC_C2, SSPC_C4, SSPC_D1, SSPC_D3, SSPC_E2, SSPC_E4 will trip simultaneously due to excessive current. The upstream devices SSPC_A1, SSPC_A3 (and also SSPC_C1, SPC_C3, SSPC_E1 , SSPC_E3 - but not relevant in FIG. 1) and the downstream devices SSPC_B2, SSPC_B4 (and also SSPC_D2, SSPC_D4 - but not relevant in FIG. 1) can still be utilized to provide power flow to critical loads (in particular due to the decoupling capacitor C).

[0085] To this end, a redundant circuit which consists of bypass lines 51, 52 and two bypass switching devices SSPC_R1 and SSPC_R3 is provided, wherein the two bypass switching devices SSPC_R1 and SSPC_R3 may or may not be switching elements of another SSPC, namely SSPC_R. SSPC_A1 , SSPC_R1, SSPC_B2 provide the power flow path over bypass line 51 to the critical load R1. SSPC_A3, SSPC_R3, SSPC_B4 provide the power flow path over bypass line 52 to the critical load R1.

[0086] In conventional SSPC topology without decoupling capacitors, all devices in SSPC_A and SSPC_B will be tripped due to excessive conduction current. Thanks to decoupling capacitors C, SSPC_A1, SSPC_B2, SSPC_A3, SSPC_B4 in FIG. 1 will remain on and become part of power flow path for the redundant DC bus. Accordingly, a redundant circuit with a reduced number of switches is provided that supplies the critical load R1 in case of DC common bus short circuit.

[0087] In this respect, it is to be noted that in each bypass line 51, 52 the total number of switching devices is reduced to one (namely, switching device SSPC_R1 in line 51 and switching device SSPC_R3 in line 52) compared to two switching devices SSPC_A2, SSPC_B1 and SSPC_A4, SSPC_B3 in the high side voltage rail 31 and the low side voltage rail 41 in normal operation mode. The SSPCs and switching device are controlled through a controller 6 which is also schematically depicted in FIG. 1. Controller 6 comprises a plurality of control lines 61 , each control line 61 controlling the gate voltage and thus the switching state of one of the switching devices SSPC_A1-A4, SSPC_B1-B4, SSPC_C1-C4, SSPC_D1-D4, SSPC_E1- E4, SSPC_R1, SSPC_R3. The controller 6 may receive input signals 62 from sensors and / or another controller.

[0088] The logic flowchart for controlling SSPC_R1 is illustrated in FIG. 2. After start 201 , all switching devices SSPC_A1-A4, SSPC_B1-B4, SSPC_C1-C4, SSPC_D1-D4, SSPC_E1- E4 are turned on, step 202, providing the normal operation mode. Accordingly, load R1 is supplied with power through power sources 21, 22, 23. In case of a DC common bus short circuit or other fault condition, decision 203, the switching devices SSPC_A2, SSPC_A4, SSPC_B1 , SSPC_B3 as well as all switching devices of SSCB_C, SSCP_D and SSCB_E are turned off, step 204, such that the power supply to load R1 is interrupted. At this point, it may be checked if the first load R1 is a critical load that needs to be powered up, decision 205. If so, subsequently, switching devices SSPC_R1 and SSPC_R3 of SSPC_R are turned on to open the bypass lines 51, 52 to provide power to the critical load R1. The process ends at 207.

[0089] Due to the existence of a decoupling capacitor C in each SSPC, pre-charging may be implemented in the embodiment of FIG. 1 as well, wherein the decoupling capacitor C is intermittently charged and transfers its current to a capacitive load during pre-charging.

[0090] More particularly, in the embodiment of FIG. 1 with bypass lines 51, 52, pre-charging can be implemented without needing additional components as follows. Under a common bus fault all switches neighboring the common bus may first be turned off the prevent the fault propagating into sources and loads. Accordingly, SSPC_A2, SSPC_A4, SSPC_C2, SSPC_C4, SSPC_E2, SSPC_E4, SSPC_B1, SSPC_B3, SSPCJD1 , SSPC_ are kept at off state as discussed before.

[0091] If it is required to pre-charge and connect the DC power source 21 source to load R1, while keeping SSPC_A2, SSPC_A4 and SSPC_B1 , SSPC_B3 at off sate to prevent fault connecting into the source or load, SSPCs SSPC_R1 and SSPC_R3 can be turned ON. This will connect both decoupling capacitors C on SSPC_A and SSPC_B. By alternatively switching ON and OFF SSPC_A1 and SSPC_B4 with short pulses, the coupling capacitor C can be charged and discharged respectively to allow pre-charging the bus.

[0092] Alternatively, SSPC_A1 can be kept in the ON state and pre-charging may be implemented by alternatively turning ON and OFF SSPC_R1 and SSPC B4. Similarly, SSPC_B4 can be kept in the ON state, wherein SSPC_A1 and SSPC_R1 are alternatively turned ON and OFF for pre-charging. FIG. 3 shows a further embodiment of a DC power distribution and protection system. The system of FIG. 3 is similar to the system of FIG. 1 except that additional bypass lines are provided for. More particularly, a third and a fourth bypass line 53, 54 are provided for connecting the middle points of SSPC_C and SSPC_B in the high side voltage rail 32 and the low side voltage rail 42 and a fifth and a sixth bypass line 55, 56 are provided for connecting the middle points of SSPC_E and SSPC_B in the high side voltage rail 33 and the low side voltage rail 43. Each of the bypass lines 51-56 comprises an SSPC (SSPC_R for bypass lines 51, 52, SSPC_Y for bypass lines 53, 53 and SSPC_Z for bypass lines 55, 56). The SSPCs in the bypass lines 51-56 may have the same architecture as SSPC_R in FIG. 1 (and as all other SSPCs in the system), such that a single switching device SSPC_R1, SSPC_R3, SSPC_Y1 , SSPC_Y2, SSPC_Z1, SSPC_Z2 is arranged in each bypass line.

[0093] By providing further bypass lines 53-56, additional redundancy is provided for in case a short circuit or other fault condition leads to the tripping of SSPCs SSPC_A2, SSPC_A4, SSPC_B1, SSPC_B3, SSPC_C2, SSPC_C4, SSPC_D1, SSPC_D3, SSPC_E2, SSPC_E4, wherein further of the DC voltage sources 22, 23 are connected to the critical load R1 through the bypass line 53-56. Accordingly, in case of short circuit fault on the DC common bus, bypass lines 51-56 with SSPCs SSPC_R, SSPC_Y, and SSPC_Z are provided which allow to feed the critical load R1 with power from multiple DC power sources 21, 22, 23.

[0094] The system may be expanded in that multiple critical loads such as both load R1 and load R2 are provided power through the back-up network, such that several critical loads are fed with power from the multiple DC power sources 21, 22, 23. To this end, bypass lines may also be provided to such further critical loads in the same manner as with bypass lines 51-56.

[0095] A further embodiment of a DC power distribution and protection system is shown in FIG. 4. The system of FIG. 4 differs from the embodiment of FIG. 1 in that, first, a bypass line 51 is implemented in the high side voltage rail 31 only, wherein two switching devices are arranged in the bypass line 51 in a series, namely, an upstream semiconductor switching device SSPC_R1 with antiparallel diode and a downstream semiconductor switching device SSPC_R2 with antiparallel diode connected in common source / emitter configuration. SSPC_R1 and SSPC_R2 may be part of an SSPC SSPC_R’. Second, the bypass line 51 bypasses both the upstream switching device SSPC_A1 and the downstream switching device SSPC_A2 of SSPC_A and further bypasses both the upstream switching device SSPC_B1 and the downstream switching device SSPC_B2 of SSPC_B in the high side voltage rail 31. Accordingly, SSPC_R’ is connected before SSPC_A1 and then to after SSPC_B2. In case of a short circuit in the high side voltage rail 31 , switching devices SSPC_A1 , SSPC_A2, SSPC_B1 , SSPC_B2 are switched off (set to the OFF state). Thereby, it is prevented that the shorted middle point between SSPC_A1 and SSPC_A2 and between SSPC_B1 and SSPC_B2 is connected through respective capacitor C to the low side voltage rail 41. Further the bypass line 51 is activated, wherein bypass switching devices SSPC_R1 and SSPC_R2 are switched on.

[0096] Such configuration allows bidirectional power follow capability of the reconfigured branch and avoids a short circuit in the common bus while keeping SSPC_A3, SSPC_A4, SSPC_B3 and SSPC_B4 in conduction state, and while further keeping SSPC_A1 , SSPC_A2, SSPC_B1 , SSPC_B2 in OFF state to prevent connection to the shorted middle point between SSPC_A1 and SSPC_A2 and between SSPC_B1 and SSPC_B2.

[0097] In the embodiment of FIG. 4, instead of keeping the switching devices in alternative paths in both the high side (positive) voltage rail and the low side (negative) voltage rail, they have been brought together into the high side voltage rail 31 in common source configuration.

[0098] A still further embodiment of a DC power distribution and protection system is shown in FIG. 5. The system of FIG. 5 differs from the embodiment of FIG. 4 in that a mechanical contactor CT is implemented as switching device in bypass line 51 instead of SSPC_R’. In the normal operation when there is no fault the contactor CT will be kept open and then under common bus failure condition the contactor CT can be closed safely while keeping SSPC_A3, SSPC_A4, SSPC_B3 and SSPC_B4 in conduction state, and while further keeping SSPC_A1, SSPC_A2, SSPC_B1, SSPC_B2 in OFF state to prevent connection to the shorted middle point between SSPC_A1 and SSPC_A2 and between SSPC_B1 and SSPC_B2.

[0099] The embodiment of FIG. 5 can be implemented in a simple manner and reduces power losses. The mechanical contactor CT can be controlled by a controller such as controller 6 of FIG.1.

[0100] A still further embodiment of a DC power distribution and protection system is shown in FIG. 6. The system of FIG. 6 differs from the embodiment of FIG. 1 in that comprises a two DC common buses power network. More particularly, the system comprises a first DC power source 21, a second DC power source 22, a first load R1 and a second load R2 connected through a first power bus 31, 41 and a second power bus 32, 42 which are interconnected in the manner discussed with respect to FIG. 10 and which form a first common power bus. In a similar manner, a third DC power source 24, a fourth DC power source 25, a third load R3 and a fourth load R4 are connected through a third power bus 34, 44 and a fifth power bus 35, 45 which are interconnected in the same manner as power buses 31, 41 and 32, 42, thereby forming a second common power bus.

[0101] The DC power buses include SSPCs SSPC_A, SSPC_B, SSPC_C, SSPC_D, SSPC_F, SSPC_G, SSPC_H, SSPC_J in the manner discussed before. Between SSPC_A and SSPC_B bypass lines 51, 52 are implemented in the same manner as a discussed with respect to FIG. 1.

[0102] Further, the high side voltage rails 31, 32, 34, 35 of the two common power buses are connected through an SSPC SSPC_M which has the same architecture as the other SSPCs previously discussed and, accordingly, comprises four switching devices SSPC_M1-4 and a middle capacitor C, wherein switching device SSPC_M1 , SSPC_M2 with antiparallel diodes are connected in common source / emitter configuration in the high side voltage rail , and switching device SSPC_M3, SSPC_M4 with antiparallel diodes are connected in common source / emitter configuration in the low side voltage rail.

[0103] SSPC_M is configured to be switched off in case of a short-circuit condition or other fault condition at the first common power bus. Switching off and on of the switching devices of SSPC_M is provided through a controller such as a controller similar to controller 6 of FIG. 1.

[0104] In case of short circuit fault on the first DC common bus, SSPC_A2, SSPC_A4, SSPC_B1, SSPC_B3, SSPC_C2, SSPC_C4, SSPC_D1, SSPC_D3, SSPC_M1 , SSPC_M2, SSPC_M3, SSPC_M4 will trip simultaneously due to excessive current. To supply power to the critical load R1 in case of first DC common bus short circuit, the back-up switch circuit which consists of bypass lines 51 , 52 and SSPC_R is provided for. Due to the turning of SSPCs_M1-4, the second DC common bus 34, 35, 44, 45 is not affected by the short circuit fault in first DC common bus. The two common buses are completely isolated. However, the critical load R1 in the first DC common may still suffer from losing power due to a short circuit fault, which is addressed by bypass lines 51, 52 and SSPC_R, wherein bypass lines 51, 52 and SSPC_R maintain the power flow path from DC power source 21 to the critical load R1 in the first DC common bus.

[0105] The logic flowchart for controlling SSPC_R in the system of FIG. 6 is illustrated in FIG. 7. After start 701, all switching devices SSPC_A1-A4, SSPC_B1-B4, SSPC_C1-C4, SSPC_D1-D4, SSPC_F1-F4, SSPC_G1-G4, SSPC_H1-H4, SSPC_J1-J4, SSPC_M1- M4 are turned (switched) on, step 702, providing the normal operation mode of the two bus system. Accordingly, load R1 (and loads R2-R4) is supplied with power through power sources 21, 22, 24, 25. In case of the first DC common bus short circuit or other fault condition, decision 503, the switching devices SSPC_A2, SSPC_A4, SSPC_B1 , SSPC_B3 and all switching devices of SSPC_C and SSPC_D in the first DC common bus and all the switching devices of two buses interconnection switching device SSPC_M are turned off, step 504, such that the power supply to load R1 is interrupted. At this point, it may be checked if the first load R1 is a critical load that needs to be powered up, decision 705. If so, subsequently, switching devices SSPC_R1 and SSPC_R3 of SSPC_R are turned on to open the bypass lines 51 , 52, thereby maintaining the provision power to the critical load R1. The process ends at 707.

[0106] Another still further embodiment of a DC power distribution and protection system in accordance with the principles of the present invention is illustrated in FIG. 8. The system is similar to the system of FIG. 6 except that additionally further bypass lines 57, 58 with an SSPC_S is provided, wherein switching devices SSPC_F2 and SSPC_G1 in the high side voltage rail 34 are bypassed by bypass line 57 and switching device SSPC_S1 and switching devices SSPC_F4 and SSPC_G3 in the low side voltage rail 44 are bypassed by bypass line 58 and switching device SSPC_S2, thereby maintaining in case of a short- circuit the provision of the power of DC power source 24 to load R3 which may be a further critical load.

[0107] The system functions in the same manner as the system of FIG. 6, except that redundancy is provided for both in the first DC common bus 31, 32, 41, 42 and in the second DC common bus 34, 35, 44, 45 by providing two redundant bypass line pairs 51, 52 and 57, 58. The interconnection switching devices SSPC_M1-M4 are turned off both in case of a short-circuit in the first DC common bus and in case of a short-circuit in the second DC common bus, thereby isolating the common buses.

[0108] It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way. Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein. Any ranges given herein include any and all specific values within the range and any and all sub-ranges within the given range.

Claims

CLAIMS1. A DC power distribution and protection system comprising: a first DC power source (21) having a positive terminal (211) and a negative terminal (212); a first load (R1); a first power bus (31, 41) connecting the first power source (21) and the first load (R01), the first power bus (31, 41) comprising a high side voltage rail (31) connected to the positive terminal (211) and a low side voltage rail (41) connected to the negative terminal (212); a first solid state power controller (SSPC_A) integrated into the first power bus (31, 41) at a power source side (61) of the first power bus; and a second solid state power controller (SSPC_B) integrated into the first power bus (31, 41) at a load side (62) of the first power bus; each solid state power controller (SSPC_A, SSPC_B) comprising an upstream switching device (SSPC_A1 , SSPC_B1) and a downstream switching device (SSPC_A2, SSPC_B2) connected in common source / emitter configuration in the high side voltage rail (31) and an upstream switching device (SSPC_A3, SSPC_B3) and a downstream switching device (SSPC_A4, SSPC_B4) connected in common source / emitter configuration in the low side voltage rail (41); wherein a first bypass line (51) extending between the upstream switching device (SSPC_A1) of the first solid state power controller (SSPC_A) and the downstream switching device (SSPC_B2) of the second solid state power controller (SSPC_B) in the high side voltage rail (31) or in the low side voltage rail (41), the first bypass line (51) bypassing the downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B), wherein the first bypass line (51) comprises at least one bypass switching device (SSPC_R1), and wherein the bypass switching device (SSPC_R1) is configured to be switched on only if the downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B) are switched off.

2. The system of claim 1, wherein the at least one bypass switching device is a semiconductor switch (SSPC_R1).

3. The system of any preceding claim, wherein a second bypass line (52) extending between the upstream switching device (SSPC_A3) of the first solid state power controller (SSPC_A) and the downstream switching device (SSPC_B4) of the second solid state power controller (SSPC_B) in the other of the high side voltage rail (31) and the low side voltage rail (41) is provided, the second bypass line (52) bypassing the downstream switching device (SSPC_A4) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B3) of the second solid state power controller (SSPC_B), wherein the second bypass line (52) also comprises at least one bypass switching device (SSPC_R3).

4. The system of claim 3, wherein the at least one bypass switching device of the second bypass line (52) is a semiconductor switch (SSPC_R3).

5. The system of any preceding claim, wherein both the first and the second solid state power controller (SSPC_A, SSPC_B) comprise a decoupling capacitor (C), the decoupling capacitor (C) arranged between the middle point between the upstream switching device (SSPC_A1 , SSPC_B1) and the downstream switching device (SSPC_A2, SSPC_B2) of the high side voltage rail (31) and the middle point between the upstream switching device (SSPC_A3, SSPC_B3) and the downstream switching device (SSPC_A4, SSPC_B4) of the low side voltage rail (41).

6. The system of claim 5, wherein the decoupling capacitor (C) is configured to be intermittently charged in a pre-charging mode of the system.

7. The system of any preceding claim, wherein the switching devices (S1-S4; SSPC_A1-A4, SSPC_B1-B4, SSPC_R1-3) are MOSFET, IGBT, JFET, or GaN transistors.

8. The system of any preceding claim, wherein a controller (6) controlling the operation of the solid state power controllers (SSPC_A, SSPC_B) and of the at least one bypass switching device (SSPC_R1), wherein the controller (6) is configured to: switch the first and second solid state power controllers (SSPC_A, SSPC_B) on in case of a normal operation mode of the system; switch the downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B) off in case of a short-circuit condition or other fault condition at the first power bus; andsubsequently switch on the at least one bypass switching device (SSPC_R1) to activate the first bypass line (51).

9. The system of any preceding claim, when dependant on claim 3 or 8, wherein the controller (6) is configured to: switch (202) all switching devices (SSPC_A1-A4, SSPC_B1-B4) of the first and second solid state power controllers (SSPC_A, SSPC_B) on in case of a normal operation mode of the system; switch (204) the downstream switching devices (SSPC_A2, SSPC_A4) of the first solid state power controller (SSPC_A) and the upstream switching devices (SSPC_B1 , SSPC_B3) of the second solid state power controller (SSPC_B) off in case of a short-circuit condition or other fault condition at the first power bus (31 , 41); check (205) if the first load (R1) is a critical load that needs to be powered up; and if so, subsequently switch on (206) the at least one bypass switching device (SSPC_R1) of the first bypass line (51) and the at least one bypass switching device (SSPC_R3) of the second bypass line (52).

10. The system of any preceding claim, wherein the power protection system further comprises: a second DC power source (22, 23) having a positive terminal (221 , 231) and a negative terminal (222, 232); a second power bus (32, 42; 33, 43) connecting the second power source (22, 23) and the first load (R01), the second power bus (32, 42; 33, 43) comprising a high side voltage rail (32, 33) connected to the positive terminal (221 , 231) and a low side voltage rail (42, 43) connected to the negative terminal (222, 232), wherein the high side voltage rail (31) of the first power bus and the high side voltage rail (32, 33) of the second power bus are connected and wherein the low side voltage rail (41) of the first power bus and the low side voltage rail (42, 43) of the second power bus are connected; and a third solid state power controller (SSPC_C, SSPC_E) integrated into the second power bus (32, 42; 33, 43) at the DC power source side (61) of the second power bus (32, 42; 33, 43), the third solid state power controller (SSPC_C, SSPC_E) comprising an upstream switching device (SSPC_C1 , SSPC_E1) and a downstream switching device (SSPC_C2, SSPC_E2) connected in common source / emitter configuration in the high side voltage rail (32, 33) and an upstream switching device (SSPC_C3,SSPC_E3 and a downstream switching device (SSPC_C4, SSPC_E4) connected in common source / emitter configuration in the low side voltage rail (42, 43).

11. The system of claim 10, wherein: a third bypass line (53, 55) extending between the upstream switching device (SSPC_C1, SSPC_E1) of the third solid state power controller (SSPC_C, SSPC_E) and the downstream switching device (SSPC_B2) of the second solid state power controller (SSPC_B) in the high side voltage rail (32, 33), the third bypass line (53, 55) bypassing the downstream switching device (SSPC_C2, SSPC_E2) of the third solid state power controller (SSPC_C, SSPC_E) and the upstream switching device (SSPC_B1) of the second solid state power controller (SSPC_B), wherein the third bypass line (51) comprises at least one bypass switching device (SSPC_Y1, SSCP_Z1), and / or a fourth bypass line (54, 56) extending between the upstream switching device (SSPC_C3, SSPC_E3) of the third solid state power controller (SSPC_C, SSPC_E) and the downstream switching device (SSPC_B4) of the second solid state power controller (SSPC_B) in the low side voltage rail (42, 43), the third bypass line (54, 56) bypassing the downstream switching device (SSPC_C4, SSPC_E4) of the third solid state power controller (SSPC_C, SSPC_E) and the upstream switching device (SSPC_B3) of the second solid state power controller (SSPC_B), wherein the fourth bypass line (51) comprises at least one bypass switching device (SSPC_Y2, SSCP_Z2).

12. The system of any preceding claim, wherein the power protection system comprises additional DC power sources (24, 25) and additional loads (R3, R4) connected through an additional DC power bus (34, 44; 35, 45), the additional DC power bus having a high side voltage rail (34, 35) and a low side voltage rail (44, 45), wherein the high side voltage rails of the first power bus (31) and of the additional power bus (34, 35) and the low side voltage rails of the first power bus (41) and of the additional power bus (44, 45) are connected through an additional solid state power controller (SSPC_M), and wherein the additional solid state power controller (SSPC_M) is configured to be switched off in case of a short-circuit condition or other fault condition at the first power bus (31, 41).

13. The system of claim 11, when dependant on claim 9, wherein the additional solid state power controller (SSPC_M) comprises a first additional switching device (SSPC_M1) and a second additional switching device (SSPC_M2) with antiparallel diodes and connected in common source / emitter configuration in the high side voltage rail and a third additional switching device (SSPC_M3) and a fourth additionalswitching device (SSPC_M4) with antiparallel diodes and connected in common source / emitter configuration in the low side voltage rail, and in that the controller (6) is configured to: switch (702) all switching devices (SSPC_A1-A4, SSPC_B1-B4, SSPC_M1-4) of the first and second solid state power controllers (SSPC_A, SSPC_B) and of the additional solid state power controller (SSPC_M) on in case of a normal operation mode of the system; switch (704) the downstream switching devices (SSPC_A2, SSPC_A4) of the first solid state power controller (SSPC_A) and the upstream switching device (SSPC_B1 , SSPC_B3) of the second solid state power controller (SSPC_B) and all switching devices (SSPC_M1-4) of the additional solid state power controller (SSPC_M) off in case of a short-circuit condition or other fault condition at the first power bus (31 , 41); check (705) if the first load (R1) is a critical load that needs to be powered up; and if so, subsequently switch on (706) the at least one bypass switching device (SSPC_R1) of the first bypass line (51) and the at least one bypass switching device (SSPC_R3) of the second bypass line (52).

14. The system of claim 12 or 13, wherein the additional DC power sources and the additional loads connected through the additional DC power bus include: a third DC power source (24) having a positive terminal and a negative terminal; a third load (R3); a third power bus (34, 44) connecting the third power source (24) and the third load (R1), the third power bus (34, 44) comprising a high side voltage rail (34) connected to the positive terminal and a low side voltage rail (44) connected to the negative terminal; a fourth solid state power controller (SSPC_F) integrated into the third power bus (34, 44) at a power source side (61) of the third power bus; a fifth solid state power controller (SSPC_G) integrated into the third power bus (34, 44) at a load side (62) of the third power bus; the fourth and fifth solid state power controller (SSPC_F, SSPC_G) each comprising an upstream switching device (SSPC_F1 , SSPC_G1) and a downstream switching device (SSPC_F2, SSPC_G2) connected in common source / emitter configuration in the high side voltage rail (34) and an upstream switching device (SSPC_F3,SSPC_G3) and a downstream switching device (SSPC_F4, SSPC_G4) connected in common source / emitter configuration in the low side voltage rail (44); a fifth bypass line (57) extending between the upstream switching device (SSPC_F1) of the fourth first solid state power controller (SSPC_F) and the downstream switching device (SSPC_G2) of the fifth solid state power controller (SSPC_G) in the high side voltage rail (34) or in the low side voltage rail (44), the fifth bypass line (57) bypassing the downstream switching device (SSPC_F2) of the fourth solid state power controller (SSPC_F) and the upstream switching device (SSPC_G1) of the fifth solid state power controller (SSPC_G), wherein the fifth bypass line (51) comprises at least one bypass switching device (SSPC_S1).

15. The system of any one of claims 10 to 14, wherein the DC power sources (21-24) and the loads (R1-R4) are connected such that each of the DC power sources (21- 24) powers at least two of the loads (R1-R4) and in that each of the loads (R1-R4) is powered by at least two of the DC power sources (21-24).

16. The system of any preceding claim, wherein the switching devices (SSPC_A1-4, SSPC_B1-4, SSPC_R1-3) are implemented with antiparallel diodes.

17. A DC power distribution and protection system comprising: a first DC power source (21) having a positive terminal (211) and a negative terminal (212); a first load (R1); a first power bus (31, 41) connecting the first power source (21) and the first load (R01), the first power bus (31, 41) comprising a high side voltage rail (31) connected to the positive terminal (211) and a low side voltage rail (41) connected to the negative terminal (212); a first solid state power controller (SSPC_A) integrated into the first power bus (31, 41) at a power source side (61) of the first power bus; and a second solid state power controller (SSPC_B) integrated into the first power bus (31, 41) at a load side (62) of the first power bus; each solid state power controller (SSPC_A, SSPC_B) comprising an upstream switching device (SSPC_A1 , SSPC_B1) and a downstream switching device (SSPC_A2, SSPC_B2) connected in common source / emitter configuration in the high side voltage rail (31) and an upstream switching device (SSPC_A3, SSPC_B3) and a downstream switching device (SSPC_A4, SSPC_B4) connected in common source / emitter configuration in the low side voltage rail (41);wherein a bypass line (51) connecting the first DC power source (21) with the first load (R1) under bypassing of the upstream switching device (SSPC_A1) and the downstream switching device (SSPC_A2) of the first solid state power controller (SSPC_A) and of the upstream switching device (SSPC_B1) and the downstream switching device (SSPC_B2) of the second solid state power controller (SSPC_B) in one of the high side voltage rail (31) and the low side voltage rail (41), wherein the bypass line (51) comprises at least one bypass switching device (SSCP_R1 , SSCP_R2, CT), and wherein the bypass switching device (SSCP_R1 , SSCP_R2, CT) is configured to be switched on only if the mentioned switching devices (SSPC_A1, SSPC_A2, SSPC_B1, SSPC_B2) are switched off.

18. The system of claim 17, wherein the at least one bypass switching device comprises an upstream semiconductor switching device (SSPC_R1) and a downstream semiconductor switching device (SSPC_R2) connected in common source / emitter configuration.

19. The system of claim 17, wherein the at least one bypass switching device comprises a mechanical contactor (CT).

20. The system of any one of claims 17 to 19, wherein both the first and the second solid state power controller (SSPC_A, SSPC_B) comprise a decoupling capacitor (C), the decoupling capacitor (C) arranged between the middle point between the upstream switching device (SSPC_A1 , SSPC_B1) and the downstream switching device (SSPC_A2, SSPC_B2) of the high side voltage rail (31) and the middle point between the upstream switching device (SSPC_A3, SSPC_B3) and the downstream switching device (SSPC_A4, SSPC_B4) of the low side voltage rail (41).

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