Semiconductor device

Abstract

Provided is a semiconductor device capable of achieving high breakdown voltage while suppressing an increase in on-resistance. A semiconductor device according to an embodiment of the present invention comprises a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a third electrode, an electrode part, and a region. The second nitride semiconductor layer is provided on the first nitride semiconductor layer, and has a band gap larger than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The electrode part is electrically connected to at least one of the first electrode, the second electrode, and the third electrode, and is disposed above the third electrode. Said region is a region in which a fixed charge of negative charge separated from the third electrode is introduced into the second nitride semiconductor layer.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] Semiconductor devices such as transistors and diodes using nitride semiconductors are known to have higher operating voltages and current densities than conventional semiconductor devices. Furthermore, the provision of field plates to alleviate the electric field is being promoted.

[0003] However, a peak of the electric field strength remains at the edge of the field plate, which may reduce the breakdown voltage.

[0004] Patent No. 5715588

[0005] The problem to be solved by the present invention is to provide a semiconductor device that can achieve a high breakdown voltage while suppressing an increase in on-resistance.

[0006] According to this embodiment, the semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a third electrode, an electrode portion, and a region. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The electrode portion is electrically connected to at least one of the first electrode, the second electrode, and the third electrode, and is located above the third electrode. The region is a region in the second nitride semiconductor layer into which negative fixed charges are introduced and which is separated from the third electrode.

[0007] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a cross-sectional view showing a detailed configuration example of a first region 32; FIG. 3 is a cross-sectional view showing a case where the manufacturing margin of the first region 32 is taken into consideration; FIG. 4 is a diagram showing the density of two-dimensional electron gas and the relaxation effect of an electric field; FIG. 5 is a schematic cross-sectional view of a semiconductor device 1 according to a second embodiment of the present invention;

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the characteristic configurations and operations of the semiconductor device will be mainly described, but the semiconductor device may have configurations and operations that are omitted from the following description.

[0009] (First embodiment)

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those already described are assigned the same reference numerals, and detailed description will be omitted as appropriate.

[0011] 1 is a schematic cross-sectional view of a semiconductor device 1 according to this embodiment. The semiconductor device 1 is a high electron mobility transistor (HEMT) using a nitride semiconductor such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). The semiconductor device 1 according to this embodiment has a lateral device structure using a nitride semiconductor.

[0012] The semiconductor device 1 includes a substrate 2, a buffer layer 4, a first nitride semiconductor layer 6, a second nitride semiconductor layer 8, a source electrode (an example of a first electrode) 10, a gate electrode (an example of a third electrode) 12, a drain electrode (an example of a second electrode) 14, a gate field plate electrode 16 (an example of a first electrode), a field plate electrode (an example of a second electrode) 18, a source field plate electrode (an example of a third electrode) 20, a drain field plate electrode 22 (an example of a fourth electrode), an insulating film 24, a first insulating layer 26, a second insulating layer 28, a third insulating layer 30, a first region 32, and a second region 34. In the embodiment, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The Z direction is the direction in which the substrate 2, the buffer layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are stacked. In addition, the upward direction of the drawings in this specification may be referred to as "up" and the downward direction of the drawings may be referred to as "down." In this specification, the concepts of "up" and "down" do not necessarily indicate a relationship with the direction of gravity.

[0013] For example, a Si (silicon) substrate or a sapphire substrate is used as the substrate 2. The buffer layer 4 is provided on the substrate 2. The buffer layer 4 reduces lattice mismatch with the substrate 2. The substrate 2 and buffer layer 4 are sometimes referred to as an underlayer.

[0014] The first nitride semiconductor layer 6 is provided on the buffer layer 4. The first nitride semiconductor layer 6 is, for example, undoped Al Ｘ Ga １－Ｘ N (0≦X<1). More specifically, the first nitride semiconductor layer 6 is, for example, undoped GaN. The first nitride semiconductor layer 6 functions as a channel layer. The film thickness of the first nitride semiconductor layer 6 is, for example, 1 μm or more and 10 μm or less.

[0015] The second nitride semiconductor layer 8 is provided on the first nitride semiconductor layer 6. The band gap of the second nitride semiconductor layer 8 is configured to be larger than the band gap of the first nitride semiconductor layer 6. The second nitride semiconductor layer 8 is made of, for example, undoped Al Ｙ Ga １－Ｙ N (0<Y≦1, X<Y). More specifically, the second nitride semiconductor layer 8 is, for example, undoped Al ０．２ Ga ０．８ The second nitride semiconductor layer 8 functions as a barrier layer. The thickness of the second nitride semiconductor layer 8 is, for example, 15 nm to 50 nm, and preferably 30 nm.

[0016] A heterojunction interface is provided between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8. When the semiconductor device 1 is in an on-state, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes carriers. The substrate 2, buffer layer 4, first nitride semiconductor layer 6, and second nitride semiconductor layer 8 are arranged parallel to a plane including an X axis parallel to the X direction and a Y axis parallel to the Y direction, i.e., an XY plane. The interface between the substrate 2 and the buffer layer 4, the interface between the buffer layer 4 and the first nitride semiconductor layer 6, and the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 are also arranged parallel to the XY plane. The Y direction is the direction in which carriers flow in the semiconductor device 1, which is a HEMT. In other words, the Y direction is the gate length direction of the semiconductor device 1. The X direction is the gate width direction of the semiconductor device 1.

[0017] The source electrode 10 is provided on the second nitride semiconductor layer 8. The source electrode 10 functions as a source electrode of the semiconductor device 1. The source electrode 10 includes, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0018] The drain electrode 14 is provided on the second nitride semiconductor layer 8. The drain electrode 14 functions as the drain electrode of the semiconductor device 1. The drain electrode 14 includes, for example, a stacked structure of titanium (Ti) and aluminum (Al). The distance between the source electrode 10 and the drain electrode 14 is, for example, not less than 5 μm and not more than 30 μm.

[0019] The insulating film 24 is provided on the second nitride semiconductor layer 8, between the source electrode 10 and the drain electrode 14. The insulating film 24 is in direct contact with the second nitride semiconductor layer 8. The insulating film 24 is configured to contain an insulating material. For example, the insulating material is silicon nitride (SiN). However, the material contained in the insulating film 24 is not limited to this. For example, silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc. may also be used. The film thickness of the insulating film 24 in the Z direction is, for example, 20 nm to 30 nm.

[0020] The gate electrode 12 is provided on the second nitride semiconductor layer 8 between the source electrode 10 and the drain electrode 14. More specifically, the gate electrode 12 is provided on the insulating film 24 between the second nitride semiconductor layer 8 and the first insulating layer 26. The gate electrode 12 includes, for example, a stacked structure of nickel (Ni) and gold (Au), titanium nitride (TiN), or polycrystalline silicon (Poly-Si). The bottom surface of the gate electrode 12 is in contact with the insulating film 24.

[0021] The first insulating layer 26 is provided on the insulating film 24 and on the gate electrode 12. The first insulating layer 26 contains, for example, silicon nitride (SiN). However, the material contained in the first insulating layer 26 is not limited to this. For example, the first insulating layer 26 may contain silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc. The film thickness of the first insulating layer 26 in the Z direction is, for example, 200 nm to 300 nm.

[0022] The gate field plate electrode portion 16 has a portion extending along the upper surface of the first insulating layer 26, and one end is electrically connected to the gate electrode 12. That is, one end of this gate field plate electrode portion 16 is electrically connected to the upper surface of the gate electrode 12. The gate field plate electrode portion 16 extends upward through the first insulating layer 26 and extends in the gate length direction above the first insulating layer 26. However, the form of the gate field plate electrode portion 16 is not limited to this. The gate field plate electrode portion 16 is used to alleviate the electric field within the semiconductor device 1. The gate field plate electrode portion 16 has a structure including, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0023] The field plate electrode 18 has a portion that extends along the upper surface of the first insulating layer 26 between the gate field plate electrode 16 and the drain electrode 14. That is, the field plate electrode 18 is provided on the first insulating layer 26 between the insulating film 24 and the second insulating layer 28. The field plate electrode 18 is electrically connected to, for example, the source electrode 10, for example, using a wiring (not shown) provided in the gate width direction. The field plate electrode 18 is used to alleviate the electric field within the semiconductor device 1. The field plate electrode 18 has a structure that includes, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0024] The second insulating layer 28 is provided on the first insulating layer 26, on the gate field plate electrode portion 16, and on the field plate electrode portion 18. The second insulating layer 28 is composed of, for example, silicon dioxide (SiO), which is a silicon oxide. Alternatively, the second insulating layer 28 may be composed of silicon oxide such as silicon monoxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), or aluminum oxide (AlO). However, the material contained in the second insulating layer 28 is not limited to these.

[0025] The source field plate electrode portion 20 has one end electrically connected to the source electrode 10 and has portions extending along the upper surface of the first insulating layer 26 on the gate field plate electrode portion 16 and on the field plate electrode portion 18. That is, one end of the source field plate electrode portion 20 is provided, for example, on the source electrode 10 and electrically connected to the source electrode 10. The source field plate electrode portion 20 is provided on the source electrode 10, the gate electrode 12, the gate field plate electrode portion 16, the field plate electrode portion 18, the insulating film 24, and the second insulating layer 28 between the first insulating layer 26 and the third insulating layer 30. The source field plate electrode portion 20 is used to alleviate the electric field within the semiconductor device 1. The source field plate electrode portion 20 has a structure including, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0026] One end of the drain wiring electrode portion 22 is electrically connected to the drain electrode 14. The drain wiring electrode portion 22 is provided, for example, on the second insulating layer 28. The drain field plate electrode portion 22 is used to alleviate the electric field within the semiconductor device 1. The drain field plate electrode portion 22 has a structure including, for example, aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or a layered structure of titanium (Ti) and aluminum (Al).

[0027] The first region 32 and the second region 34 are configured in the second nitride semiconductor layer 8 according to the positions of the ends E16, 18 of the electrode portions 16, 18 on the drain electrode 14 side, and are negatively charged regions separated from the gate electrode 12. That is, the first region 32 and the second region 34 are regions in the second nitride semiconductor layer 8 into which negative fixed charges have been introduced and which are separated from the gate electrode 12. The ranges of the first region 32 and the second region 34 in the y direction are, for example, not less than 0.3 μm and not more than 0.6 μm.

[0028] More specifically, the first region 32 is formed at the end E16 of the gate field plate electrode portion 16 of the second nitride semiconductor layer 8 on the drain electrode 14 side. The first region 32 is a region into which a halogen element has been introduced. The halogen element is, for example, fluorine (F), chlorine (Cl), or the like. That is, the first region 32 is a halogen-implanted region into which a negative fixed charge has been introduced by annealing. The annealing process diffuses the halogen element in the gate length direction (y direction), so that the charge changes gradually and the electric field change also becomes gentle. The halogen element is introduced, for example, by a CDE (Chemical Dry Etching) method using a gas containing CF4.

[0029] As described above, the gate field plate electrode portion 16 alleviates the electric field concentration at the end of the gate electrode 12. However, electric field concentration remains at the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side. Therefore, the first region 32 is used to alleviate the electric field concentration that occurs at the end E16. This further improves the breakdown voltage of the semiconductor device 1.

[0030] The second region 34 is formed at the end E18 of the field plate electrode portion 18 of the second nitride semiconductor layer 8 on the drain electrode 14 side. The second region 34 is a region into which a halogen element has been introduced. The halogen element is, for example, fluorine (F), chlorine (Cl), or the like. That is, the second region 34 is a halogen-implanted region into which a negative fixed charge has been introduced by annealing. The annealing process diffuses the halogen element in the gate length direction (y direction), so that the charge changes gradually and the electric field change also becomes gentle. The halogen element is introduced, for example, by a CDE (Chemical Dry Etching) method using a gas containing CF4.

[0031] As described above, the field plate electrode portion 18 alleviates the electric field concentration. However, the electric field concentration remains at the end E18 of the field plate electrode portion 18 on the drain electrode 14 side. Therefore, the second region 34 is used to alleviate the electric field concentration that occurs at the end E18. This further improves the breakdown voltage of the semiconductor device 1.

[0032] On the other hand, if the ranges of the first region 32 and the second region 34 are expanded, it will affect the two-dimensional electron gas and increase the on-resistance, so the ranges of the first region 32 and the second region 34 are limited to the ranges shown in FIG.

[0033] Fig. 2 is a cross-sectional view showing a detailed configuration example of the first region 32. Fig. 2 explains the example of the first region 32, but the second region 34 also has a similar configuration. As shown in Fig. 2, the first region 32 is configured to be flush with, for example, the upper surface of the second nitride semiconductor layer 8 on the insulating film 24 side.

[0034] The range in which the first region 32 is configured is set based on the peak position of the electric field generated by the gate field plate electrode portion 16. This peak position is the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side. This peak rises sharply at the end E16 and decreases while tailing toward the drain electrode 14. Therefore, the length of the first region 32 along the surface of the second nitride semiconductor layer 8 is, for example, 0.4 μm from the end E16 on the drain electrode 14 side. This width is set depending on the region in which the electric field is concentrated. Furthermore, the first region 32 is positioned away from the gate electrode 12 so that the negative fixed charges in the first region 32 do not affect the switching operation of the gate electrode 12.

[0035] Furthermore, the depth is within a range that does not reach the two-dimensional electron gas (2DEG). For example, the depth of the first region 32 is within a range that remains within the second nitride semiconductor layer 8. Furthermore, the concentration of the halogen element introduced can be changed depending on the electric field generated by the field plate electrode portion 18. For example, the concentration of the halogen element introduced in the first region 32 is set to, for example, approximately the maximum concentration of the two-dimensional electron gas (2DEG). Because the activation rates of the first region 32 and the second region 34 are 50% or less, even if a halogen element is introduced to a concentration approximately equal to the two-dimensional electron gas (2DEG) concentration, the reduction in the two-dimensional electron gas in the injected portion is 50% or less, and the effect on the on-resistance is also suppressed.

[0036] 3 is a cross-sectional view of the first region 32 taking into consideration the manufacturing margin. While FIG. 3 illustrates an example of the first region 32, the same applies to a configuration example of the second region 34. Because the electric field peak is greatest at the end E16, the distance between the first region 32 and the drain electrode 14 decreases the effect of alleviating the electric field. Therefore, the first region 32 is configured to be extended toward the gate electrode by approximately 0.2 μm to accommodate the manufacturing margin. This prevents the first region 32 from moving away from the end E16 toward the drain electrode 14.

[0037] FIG. 4 is a diagram schematically showing the density of two-dimensional electron gas and the relaxation effect of the electric field. Schematic diagram Ed is a diagram schematically showing the density of two-dimensional electron gas during operation of the semiconductor device 1. In FIG. 4, the density is shown at three levels: "low," "medium," and "high." The density of two-dimensional electron gas increases as the level increases from "low," "medium," to "high." Line L10 shows the electric field strength when the first region 32 and the second region 34 are not present. Line L12 shows the electric field strength when the first region 32 and the second region 34 are present. The vertical axis represents the electric field strength, and the horizontal axis corresponds to the Y coordinate.

[0038] 4, the density of the two-dimensional electron gas is at a "high" level between the drain-side end of the source field plate electrode portion 20 and the gate-side end of the drain field plate electrode portion 22. It is at a "medium" level between the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side and the end of the field plate electrode portion 18 on the gate electrode 12 side. Similarly, it is at a "medium" level between the end E18 of the field plate electrode portion 18 on the drain electrode 14 side and the drain-side end of the source field plate electrode portion 20. Furthermore, the density is at a "low" level below the gate electrode 12.

[0039] During operation of the semiconductor device 1, a voltage (drain voltage) is applied between the drain electrode 14 and the gate electrode 12. When the first region 32 and the second region 34 are not provided, the electric field strength tends to concentrate at the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side and at the end E18 of the field plate electrode portion 18 on the drain electrode 14 side, as shown by the line L10.

[0040] In contrast, according to the embodiment, the first region 32 and the second region 34 having negative fixed charges are formed at the ends of the end E16 and the end E18 on the drain electrode 14 side, so that, as shown by the line L12, the electric field concentrated at the end E16 and the end E18 is alleviated. In this way, the first region 32 and the second region 34 alleviate the electric field concentration occurring at the end E16 and the end E18, and the breakdown voltage of the semiconductor device 1 is further improved.

[0041] As described above, according to the present embodiment, in the semiconductor device 1 according to the present embodiment, the electrode portions 16, 18 are electrically connected to at least one of the source electrode 10, the gate electrode 12, and the drain electrode 14, are arranged above the gate electrode 12, have the ends E16, E18 at positions closer to the drain electrode 14 than the end of the gate electrode 12 on the drain electrode 14 side, and the first region 32 and the second region 34 are configured as negatively charged regions spaced apart from the gate electrode 12 according to the positions of the ends E16, E18 in the second nitride semiconductor layer 8. This reduces the influence of the negative charge on the gate electrode 12, and alleviates the concentration of the electric field generated at the ends E16 and E18, thereby further improving the breakdown voltage of the semiconductor device 1.

[0042] Second Embodiment The semiconductor device 1 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the concentration of the halogen element introduced into the region where the halogen element is introduced is changed depending on the magnitude of the peak of the electric field. The differences from the semiconductor device 1 according to the first embodiment will be described below.

[0043] 5 is a schematic cross-sectional view of the semiconductor device 1 according to the second embodiment, which differs from the semiconductor device 1 according to the first embodiment in that a third region 36 is further formed at an end E20 on the drain side of the source field plate electrode portion 20, and a fourth region 38 is further formed at an end E22 of the drain wiring electrode portion 22.

[0044] Furthermore, the introduction concentration of the halogen element in the first region 32, the second region 34, the third region 36, and the fourth region 38 is changed according to the magnitude of the peak of the electric field. For example, in the case where the first region 32, the second region 34, the third region 36, and the fourth region 38 are not provided, the magnitude of the peak of the electric field increases in the order of end E22, end E20, end E16, and end E18, and therefore the introduction concentration of the halogen element also increases in the order of fourth region 38, third region 36, first region 32, and second region 34. Note that at least one of the first region 32, second region 34, third region 36, and fourth region 38 according to this embodiment corresponds to a region.

[0045] This reduces the concentration of the electric field generated at the ends E22, E20, E16, and E18 to the same extent, and also suppresses the concentration of the halogen element introduced, thereby suppressing the effect on the on-resistance of the semiconductor device 1.

[0046] As described above, according to this embodiment, the gate field plate electrode portion 16, the field plate electrode portion 18, the source field plate electrode portion 20, and the drain wiring electrode portion 22 each have a portion extending in the direction (y direction) along the top surface of the second nitride semiconductor layer 8, and the first region 32, the second region 34, the third region 36, and the fourth region 38 are configured according to the positions of the ends E16, E18, E20, and E22 closer to the second electrode. This reduces the electric field generated at the ends E16, E18, E20, and E22, thereby enabling a high breakdown voltage of the semiconductor device 1. Furthermore, because the concentration of introduced halogen elements is changed according to the magnitude of the electric field strength generated at the ends E16, E18, E20, and E22, the introduction of halogen elements can be suppressed, thereby enabling a high breakdown voltage of the semiconductor device 1 while suppressing an increase in on-resistance.

[0047] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0048] 1: semiconductor device, 10: source electrode, 12: gate electrode, 14: drain electrode, 16: gate field plate electrode portion, 18: source field plate electrode portion, 20: source field plate electrode portion, 22: drain wiring electrode portion, 24: insulating film, 26: first insulating layer, 32: first region, 34: second region 34, 36: third region, 38: fourth region, E16, E18, E20, E22: end portion.

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode provided on the second nitride semiconductor layer; a second electrode provided on the second nitride semiconductor layer; a third electrode provided on the second nitride semiconductor layer between the first electrode and the second electrode; an electrode portion electrically connected to at least one of the first electrode, the second electrode, and the third electrode and positioned above the third electrode; and a region in the second nitride semiconductor layer into which negative fixed charges have been introduced, separated from the third electrode.

2. The semiconductor device according to claim 1, wherein the electrode portion has an end located closer to the second electrode than the end of the third electrode on the second electrode side, and the region is a region into which a halogen element has been introduced.

3. The semiconductor device according to claim 2, wherein the region is configured according to the position of a first end of the electrode portion on the second electrode side, the halogen element is at least one of fluorine (F) and chlorine (Cl), and the region is annealed after the halogen element is introduced.

4. The semiconductor device according to claim 1, wherein said region is formed flush with an upper surface of said second nitride semiconductor layer.

5. The semiconductor device described in claim 1, wherein the region is configured to include a first position where a first direction perpendicular to the top surface of the second nitride semiconductor layer along the first end intersects with the top surface of the second nitride semiconductor layer.

6. The semiconductor device described in claim 5, wherein the region is parallel to an upper surface of the second nitride semiconductor layer, and in a second direction perpendicular to the first direction, a first range from the first electrode side to the first position is narrower than a second range from the first position to the second electrode side.

7. The semiconductor device according to claim 6, wherein the distance between the first electrode and the second electrode in the second direction is not less than 5 μm and not more than 30 μm, and the range of the region in the second direction is not less than 0.3 um and not more than 0.6 um.

8. The semiconductor device according to claim 2, wherein the region is made up of a plurality of regions, and the introduction density of the halogen element varies depending on the position of the first end portion.

9. The semiconductor device according to claim 8, wherein a plurality of said regions are provided, and the density of introduction of the halogen element is configured to increase as the magnitude of the electric field to be generated increases.

10. A semiconductor device as described in any one of claims 1 to 9, further comprising: an insulating film provided on the second nitride semiconductor layer between the first electrode and the second electrode and in contact with the second nitride semiconductor layer; and a first insulating layer provided on the insulating film between the first electrode and the third electrode, on the insulating film between the third electrode and the second electrode, and on the third electrode, wherein the third electrode is provided on the insulating film between the first electrode and the second electrode.

11. The semiconductor device according to claim 10, further comprising a first electrode portion having a portion extending along the upper surface of the first insulating layer and one end electrically connected to the third electrode.

12. The semiconductor device according to claim 11, further comprising a second electrode portion having a portion extending along an upper surface of the first insulating layer between said first electrode portion and said second electrode.

13. The semiconductor device described in claim 12, further comprising a third electrode portion, one end of which is electrically connected to said first electrode, and having a portion extending along the upper surface of said first insulating layer above said first electrode portion and above said second electrode portion.

14. The semiconductor device according to claim 13, further comprising a fourth electrode portion, one end of which is electrically connected to said second electrode, and which has a portion extending along the upper surface of said first insulating layer.

15. The semiconductor device described in claim 14, wherein the region is configured according to the position of an end portion of a portion extending along an upper surface of the first insulating layer that is closer to the second electrode in at least one of the first electrode portion, the second electrode portion, the third electrode portion, and the fourth electrode portion.

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