Semiconductor device

Abstract

[Problem] To provide a semiconductor device having a small output capacity. [Solution] A semiconductor device according to the present embodiment comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, and a third electrode. The first nitride semiconductor layer is provided on the substrate. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The substrate is configured in accordance with the position of the second electrode. The substrate includes at least one of a first insulating layer and a first air layer which are each a region having a dielectric constant lower than that of the substrate.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] 2. Description of the Related Art Semiconductor devices such as transistors and diodes that use nitride semiconductors are known to have higher operating frequencies and higher current densities than conventional semiconductor devices.

[0003] JP 2011-204984 A

[0004] An object of the present invention is to provide a semiconductor device with a small output capacitance.

[0005] According to this embodiment, the semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, and a third electrode. The first nitride semiconductor layer is provided on the substrate. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and is a nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The substrate is configured according to the position of the second electrode and has at least one of a first insulating layer which is a region having a lower dielectric constant than the substrate, and a first air layer.

[0006] 1 is a schematic top view of a semiconductor device according to an embodiment; 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment; 3 is a diagram showing drain-source capacitance; 4 is a diagram showing an output charge amount; 5 is a schematic top view of a semiconductor device according to a second embodiment; 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment; 7 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; 8 is a schematic top view of a first configuration example of a semiconductor device according to a fourth embodiment; 9 is a schematic top view of a second configuration example of a semiconductor device according to the fourth embodiment; 10 is a schematic top view of a third configuration example of a semiconductor device according to the fourth embodiment;

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the characteristic configurations and operations of the semiconductor device will be mainly described, but the semiconductor device may have configurations and operations that are omitted from the following description.

[0008] (First embodiment)

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those already described are assigned the same reference numerals, and detailed description will be omitted as appropriate.

[0010] Fig. 1 is a schematic top view of a semiconductor device 1 of this embodiment. Fig. 2 is a schematic cross-sectional view of the semiconductor device 1 of this embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1. Fig. 1 is a top view taken along line BB' in Fig. 2.

[0011] The semiconductor device 1 is a high electron mobility transistor (HEMT) using a nitride semiconductor such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). The semiconductor device 1 according to this embodiment has a lateral device structure using a nitride semiconductor. The electrode structure of the semiconductor device 1 according to this embodiment is, for example, a multi-finger structure. As shown in FIG. 1 , unit cell a and unit cell b are arranged symmetrically in the y direction with line L10 as the center.

[0012] The semiconductor device 1 includes a substrate 2, a first insulating layer 4, a first nitride semiconductor layer 6, a second nitride semiconductor layer 8, a source electrode (an example of a first electrode) 10, a gate electrode (an example of a third electrode) 12, a drain electrode (an example of a second electrode) 14, a gate field plate electrode 16, a field plate electrode 18, a source field plate electrode (an example of an electrode) 20, a drain field plate electrode 22, an insulating film 24, a second insulating layer 26, a third insulating layer 28, and a fourth insulating layer 30. In the embodiment, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The Z direction is the direction in which the first insulating layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are stacked. In this specification, the upward direction in the drawings may be referred to as "upper," and the downward direction in the drawings may be referred to as "lower." In this specification, the concepts of "upper" and "lower" do not necessarily indicate a relationship with the direction of gravity.

[0013] The output capacitance Coss of the semiconductor device 1 is the sum of the drain-source capacitance Cds and the gate-drain capacitance Cgd. Here, the capacitance components between the substrate 2, the first insulating layer 4, and the drain electrode 14, and the capacitance component between the package provided under the substrate 2 and the first insulating layer 4, and the drain electrode 14 make significant contributions to the drain-source capacitance Cds.

[0014] The end line E14 is a line that runs along the end of the drain electrode 14 on the source electrode 10 side and intersects at right angles with the lower surface of the first nitride semiconductor layer 6. The end line E20 is a line that runs along the end of the source field plate electrode portion 20 on the drain electrode 14 side, extending along the third insulating layer 28, and intersects at right angles with the lower surface of the first nitride semiconductor layer 6.

[0015] The substrate 2 may be, for example, a Si (silicon) substrate or a sapphire substrate. The substrate 2 is preferably a Si (silicon) substrate. The Y-direction range of the substrate 2 is set to a range based on an edge line E20 on the drain electrode 14 side of the source field plate electrode portion 20, which will be described later. Preferably, the Y-direction range of the substrate 2 extends to a position closer to the drain electrode 14 side than the edge line E20. For example, the boundary surface between the substrate 2 and the first insulating layer 4 is formed in the range between the edge line E14 and the edge line E20. This makes it possible to maintain the electric field relaxation function of the source field plate electrode portion 20.

[0016] The first insulating layer 4 is made of a material with a lower dielectric constant than the substrate 2. The first insulating layer 4 is configured as a partial region of the substrate 2 and includes a first insulating layer 4a and a first insulating layer 4b. The first insulating layer 4a is an insulating layer made of, for example, PI, resin, or the like. More specifically, for example, organic SOG, hydrogenated silsesquioxane, polyallyl ether, or the like can be used as the coating material. Alternatively, a CVD film such as a methylsilane-based CVD film may be used. Alternatively, an organic SOG film with voids, hydrogenated silsesquioxane with voids, polyallyl ether with voids, or a methylsilane-based CVD film with voids may be used.

[0017] The first insulating layer 4b is made of a material having a smaller dielectric constant than the substrate 2. Like the first insulating layer 4a, the first insulating layer 4b may be, for example, an organic SOG, hydrogenated silsesquioxane, polyallyl ether, a methylsilane-based CVD film, or air. Alternatively, the first insulating layer 4b may be an organic SOG having voids, hydrogenated silsesquioxane having voids, polyallyl ether having voids, or a methylsilane-based CVD film having voids.

[0018] The range in the Y direction of the upper surface of the first insulating layer 4 is set to a range based on the edge line E14 on the source electrode 10 side of the drain electrode 14. As described above, the boundary surface between the substrate 2 and the first insulating layer 4 is formed in the range between the edge line E14 and the edge line E20. In other words, the range between the substrate 2 and the first insulating layer 4 is set in consideration of the electric field relaxation function of the source field plate electrode portion 20 and the reduction of the drain-source capacitance Cds.

[0019] The first insulating layer 4 has a structure in which its range in the Y direction increases with increasing distance from the bottom surface of the first nitride semiconductor layer 6. In other words, the boundary surface of the first insulating layer 4 with the substrate 2 is configured to have a sloped surface T10. This makes it possible to reduce the drain-source capacitance Cds while reducing the effect on the electric field relaxation function of the source field plate electrode portion 20. Here, the capacitance between the drain electrode 14 and the bottom surface of the first insulating layer 4 is defined as Cbd. In other words, the capacitance Cbd is included in the capacitive component of the drain-source capacitance Cds. Details of the capacitance Cbd will be described later.

[0020] The first nitride semiconductor layer 6 is provided on the substrate 2 and the first insulating layer 4. The first nitride semiconductor layer 6 is, for example, undoped Al Ｘ Ga １－Ｘ N (0≦X<1). More specifically, the first nitride semiconductor layer 6 is, for example, undoped GaN. The first nitride semiconductor layer 6 functions as a channel layer. The film thickness of the first nitride semiconductor layer 6 is, for example, 1 μm or more and 10 μm or less.

[0021] The second nitride semiconductor layer 8 is provided on the first nitride semiconductor layer 6. The band gap of the second nitride semiconductor layer 8 is configured to be larger than the band gap of the first nitride semiconductor layer 6. The second nitride semiconductor layer 8 is made of, for example, undoped Al Ｙ Ga １－Ｙ N (0<Y≦1, X<Y). More specifically, the second nitride semiconductor layer 8 is, for example, undoped Al ０．２ Ga ０．８ The second nitride semiconductor layer 8 functions as a barrier layer. The thickness of the second nitride semiconductor layer 8 is, for example, 15 nm to 50 nm, and preferably 30 nm.

[0022] A heterojunction interface is provided between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8. When the semiconductor device 1 is in an on-state, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes carriers. The substrate 2, the first insulating layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are arranged parallel to a plane including an X-axis parallel to the X direction and a Y-axis parallel to the Y direction, i.e., an XY plane. The interface between the substrate 2 and the first nitride semiconductor layer 6, the interface between the first insulating layer 4 and the first nitride semiconductor layer 6, and the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 are also arranged parallel to the XY plane. The Y direction is the direction in which carriers flow in the semiconductor device 1, which is a HEMT. In other words, the Y direction is the gate length direction of the semiconductor device 1. The X direction is the gate width direction of the semiconductor device 1.

[0023] The source electrode 10 is provided on the second nitride semiconductor layer 8. The source electrode 10 functions as a source electrode of the semiconductor device 1. The source electrode 10 includes, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0024] The drain electrode 14 is provided on the second nitride semiconductor layer 8. The drain electrode 14 functions as the drain electrode of the semiconductor device 1. The drain electrode 14 includes, for example, a stacked structure of titanium (Ti) and aluminum (Al). The distance between the source electrode 10 and the drain electrode 14 is, for example, not less than 5 μm and not more than 30 μm.

[0025] The insulating film 24 is provided on the second nitride semiconductor layer 8, between the source electrode 10 and the drain electrode 14. The insulating film 24 is in direct contact with the second nitride semiconductor layer 8. The insulating film 24 is configured to contain an insulating material. For example, the insulating material is silicon nitride (SiN). However, the material contained in the insulating film 24 is not limited to this. For example, silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc. may also be used. The film thickness of the insulating film 24 in the Z direction is, for example, 20 nm to 30 nm.

[0026] The gate electrode 12 is provided on the second nitride semiconductor layer 8 between the source electrode 10 and the drain electrode 14. More specifically, the gate electrode 12 is provided on the insulating film 24 between the second nitride semiconductor layer 8 and the second insulating layer 26. The gate electrode 12 includes, for example, a stacked structure of nickel (Ni) and gold (Au), titanium nitride (TiN), or polycrystalline silicon (Poly-Si). The bottom surface of the gate electrode 12 is preferably in contact with the insulating film 24.

[0027] The second insulating layer 26 is provided on the insulating film 24 and on the gate electrode 12. The second insulating layer 26 contains, for example, silicon nitride (SiN). However, the material contained in the second insulating layer 26 is not limited to this. For example, the second insulating layer 26 may contain silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc. The film thickness of the second insulating layer 26 in the Z direction is, for example, 200 nm to 300 nm.

[0028] The gate field plate electrode portion 16 has a portion extending along the upper surface of the second insulating layer 26, and one end is electrically connected to the gate electrode 12. That is, one end of this gate field plate electrode portion 16 is electrically connected to the upper surface of the gate electrode 12. The gate field plate electrode portion 16 extends upward through the second insulating layer 26 and extends in the gate length direction above the second insulating layer 26. However, the form of the gate field plate electrode portion 16 is not limited to this. The gate field plate electrode portion 16 is used to alleviate the electric field within the semiconductor device 1. The gate field plate electrode portion 16 has a structure including, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0029] The field plate electrode 18 has a portion that extends along the upper surface of the second insulating layer 26 between the gate field plate electrode 16 and the drain electrode 14. That is, the field plate electrode 18 is provided on the second insulating layer 26 between the insulating film 24 and the third insulating layer 28. The field plate electrode 18 is electrically connected to, for example, the source electrode 10, for example, using a wiring (not shown) provided in the gate width direction. The field plate electrode 18 is used to alleviate the electric field within the semiconductor device 1. The field plate electrode 18 has a structure that includes, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0030] The third insulating layer 28 is provided on the second insulating layer 26, on the gate field plate electrode portion 16, and on the field plate electrode portion 18. The third insulating layer 28 is composed of, for example, silicon dioxide (SiO), which is a silicon oxide. Alternatively, the third insulating layer 28 may be composed of silicon oxide such as silicon monoxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), or aluminum oxide (AlO). However, the material contained in the third insulating layer 28 is not limited to these.

[0031] The source field plate electrode portion 20 has one end electrically connected to the source electrode 10 and has portions extending along the upper surface of the second insulating layer 26 on the gate field plate electrode portion 16 and on the field plate electrode portion 18. That is, one end of the source field plate electrode portion 20 is provided, for example, on the source electrode 10 and electrically connected to the source electrode 10. The source field plate electrode portion 20 is provided on the source electrode 10, the gate electrode 12, the gate field plate electrode portion 16, the field plate electrode portion 18, the insulating film 24, and the third insulating layer 28 between the second insulating layer 26 and the fourth insulating layer 30. The source field plate electrode portion 20 is used to alleviate the electric field within the semiconductor device 1. The source field plate electrode portion 20 has a structure including, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0032] The drain field plate electrode portion 22 has one end electrically connected to the drain electrode 14 and a portion extending along the upper surface of the insulating film 24. That is, this drain field plate electrode portion 22 is electrically connected to the drain electrode 14. One end of the drain field plate electrode portion 22 is provided, for example, on the drain electrode 14 and electrically connected to the upper surface of the drain electrode 14. The drain field plate electrode portion 22 extends, for example, toward the source electrode 10. The drain field plate electrode portion 22 is provided, for example, on the third insulating layer 28. The drain field plate electrode portion 22 is used to alleviate the electric field within the semiconductor device 1. The drain field plate electrode portion 22 has a structure including, for example, a layered structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).

[0033] Here, the effect of the capacitance Cbd will be explained. The drain-source capacitance Cds including the capacitance Cbd is approximately expressed by equation (1). ｎ indicates an area having a minute width in the Y direction on the lower surface of the substrate 2 and the first insulating layer 4. ｎ is ΔSｎ and the drain electrode 14, and the distance d ｎ is ΔS ｎ and the drain electrode 14. n=1 is the distance ΔS １ and n=m is the position where ΔS ｍ That is, the distance d ｎ is d １ is the shortest, and d ｍ will be the longest.

[0034] As shown in equation (1), the capacitance Cds is a small ΔS ｎ If the distance d ｎ Therefore, in this embodiment, the distance d ｎ is a dielectric constant ε in a predetermined range, for example, n≦mb ｎ (mb≧n) is the dielectric constant ε in the range of n>mb ｎ (m≧n>mb). In other words, mb is less than m.

[0035] Again, as shown in FIG. 1, the cross section (ZY plane) of the first insulating layer 4 has a trapezoidal shape with a sloped surface T10, so that the dielectric constant ε ｎ (mb≧n) is the distance d ｎ (mb≧n), thereby enabling the capacitance Cbd to be reduced efficiently. Furthermore, since the first insulating layer 4 has a trapezoidal shape with inclined surfaces T10, the upper surface of the substrate 2 can be configured to have a wider area, and the electric field relaxation function of the source field plate electrode portion 20 can be more efficiently maintained. In this way, since the cross section (ZY plane) of the first insulating layer 4 has a trapezoidal shape with inclined surfaces T10, the drain-source capacitance Cds can be reduced more efficiently while maintaining the electric field relaxation function of the source field plate electrode portion 20.

[0036] Furthermore, the capacitance Cdb between the bottom surface of the first insulating layer 4 and the drain electrode 14 can be expressed by equation (2). As can be seen from these, the dielectric constant ε ｎ The smaller (mb≧n) is made, the more the output capacitance Coss of the semiconductor device 1 can be reduced.

[0037] Here, there is a relationship of mb<m. Although it is possible to reduce the drain-source capacitance Cds shown in formula (1) by thickening the first nitride semiconductor layer 6, warping or cracks may occur in the substrate 2, and there is a limit to how much this can be done.

[0038] FIG. 3 is a diagram showing the drain-source capacitance Cds when the first insulating layer 4 is present and when it is not present. The horizontal axis represents the voltage between the drain electrode 14 and the source electrode 10, and the vertical axis represents the logarithmically converted drain-source capacitance Cds (arbitrary units). FIG. 3 is a diagram showing the simulation results. The drain-source capacitance Cds when the first insulating layer 4 is present is shown by line L10, and the drain-source capacitance Cds when the first insulating layer 4 is not present is shown by line L12. As shown in FIG. 3, the drain-source capacitance Cds is smaller when the first insulating layer 4 is present.

[0039] FIG. 4 is a graph showing the output charge QOSS. The output charge QOSS when the first insulating layer 4 is included is indicated by R10, and the output charge QOSS when the first insulating layer 4 is not included is indicated by R12. FIG. 4 is a graph showing the results of a simulation. The output charge QOSS shown in FIG. 4 is the amount of charge required to charge the output capacitance Coss. Here, the voltage between the drain electrode 14 and the source electrode 10 is set to 400 volts. As shown in FIG. 4, the output charge QOSS when the first insulating layer 4 is included is approximately 70 percent of the output charge QOSS when the first insulating layer 4 is not included.

[0040] In high-frequency operation, as the output charge QOSS increases, the switching loss due to charging and discharging of the output capacitance Coss increases. As shown in Figures 3 and 4, the semiconductor device 1 according to this embodiment includes the first insulating layer 4, so the output charge QOSS can be reduced, and switching loss can be reduced. This makes it possible to configure a semiconductor device 1 having a higher breakdown field strength and higher electron mobility.

[0041] As described above, according to this embodiment, the substrate 2 of the semiconductor device 1 according to this embodiment is configured according to the position of the drain electrode 14 and has the first insulating layer 4, which is a region having a lower dielectric constant than the substrate 2. This makes it possible to reduce the drain-source capacitance Cds and reduce the output capacitance Coss of the semiconductor device 1.

[0042] Second Embodiment The semiconductor device 1 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the first insulating layer 4 c is configured to be separated into a plurality of regions. The differences from the semiconductor device 1 according to the first embodiment will be described below.

[0043] Fig. 5 is a schematic top view of the semiconductor device 1 according to the second embodiment. Fig. 6 is a schematic cross-sectional view of the semiconductor device 1 according to the second embodiment. Fig. 6 is a cross-section taken along line AA' in Fig. 1. Fig. 5 is a top view taken along line BB' in Fig. 2.

[0044] 5 and 6, the semiconductor device 1 according to the first embodiment differs from the semiconductor device 1 according to the first embodiment in that the first insulating layer 4c is configured in a striped pattern. The first insulating layer 4c is configured to be separated into, for example, three regions. That is, the first insulating layer 4c has a plurality of regions separated in the Y direction, which is parallel to the top surface of the substrate 2. Each of the separated regions is, for example, a rectangular parallelepiped.

[0045] The first insulating layer 4c is made of a material with a lower dielectric constant than the substrate 2. The first insulating layer 4c is an insulating layer made of, for example, PI, resin, or the like. More specifically, it is, for example, an organic SOG, hydrogenated silsesquioxane, polyallyl ether, or methylsilane-based CVD film. Alternatively, it may be an organic SOG with voids, hydrogenated silsesquioxane with voids, polyallyl ether with voids, or a methylsilane-based CVD film with voids. This reduces the drain-source capacitance Cds. Furthermore, since the substrate 2 and the first insulating layer 4c are alternately configured, a decrease in the rigidity of the substrate 2 can be suppressed. This makes it possible to maintain the flatness of the substrate 2.

[0046] Third Embodiment The semiconductor device 1 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that the first insulating layer 4d has a rectangular parallelepiped shape. The differences from the semiconductor device 1 according to the first embodiment will be described below.

[0047] 7 is a schematic cross-sectional view of the semiconductor device 1 according to the third embodiment. As shown in FIG. 7, the semiconductor device 1 differs from the semiconductor device 1 according to the first embodiment in that the first insulating layer 4d is configured in a rectangular parallelepiped shape. The first insulating layer 4c is configured to be separated into, for example, three regions.

[0048] The first insulating layer 4d is made of a material with a smaller dielectric constant than the substrate 2. The first insulating layer 4d is an insulating layer made of, for example, PI, resin, or the like. More specifically, it is, for example, an organic SOG, hydrogenated silsesquioxane, polyallyl ether, or methylsilane-based CVD film. Alternatively, it may be an organic SOG with voids, hydrogenated silsesquioxane with voids, polyallyl ether with voids, or methylsilane-based CVD film with voids. This reduces the drain-source capacitance Cds. Furthermore, because the first insulating layer 4d is made of a single material and has a rectangular parallelepiped shape, the film formation process is simplified.

[0049] (Fourth Embodiment) The semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the first to third embodiments in that the first air layers 4ba, ca, da are configured as hollow walls of the substrate 2. The differences from the semiconductor device 1 according to the first to third embodiments will be described below.

[0050] 8 is a schematic cross-sectional view of a first configuration example of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 8, the semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that the first insulating layers 4a, 4b (see FIG. 2) of the semiconductor device 1 according to the first embodiment are configured as a first air layer 4ba. That is, in the first configuration example of the semiconductor device 1 according to the fourth embodiment, the first air layer 4ba is configured as a hollow wall of the substrate 2. This makes it possible to further reduce the dielectric constant of the first air layer 4ba, thereby further reducing the output capacitance Coss of the semiconductor device 1 according to the first embodiment.

[0051] 9 is a schematic cross-sectional view of a second configuration example of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 9, the semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the second embodiment in that the first insulating layer 4c (see FIG. 6) of the semiconductor device 1 according to the second embodiment is configured as a first air layer 4ca. That is, in the second configuration example of the semiconductor device 1 according to the fourth embodiment, the first air layer 4ca is configured as a hollow wall of the substrate 2. This makes it possible to further reduce the dielectric constant of the first air layer 4ca, thereby further reducing the output capacitance Coss of the semiconductor device 1 according to the second embodiment.

[0052] 10 is a schematic cross-sectional view of a third configuration example of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 10, the semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the third embodiment in that the first insulating layer 4d (see FIG. 7") of the semiconductor device 1 according to the third embodiment is configured as a first air layer 4da. That is, in the third configuration example of the semiconductor device 1 according to the fourth embodiment, the first air layer 4da is configured as a hollow wall of the substrate 2. This makes it possible to further reduce the dielectric constant of the first air layer 4da, and further reduce the output capacitance Coss of the semiconductor device 1 according to the third embodiment.

[0053] As described above, according to this embodiment, the first air layers 4ba, ca, and da are configured as hollow walls of the substrate 2. This makes it possible to further reduce the dielectric constant of the first air layers 4ba, ca, and da, and further reduce the output capacitance Coss of the semiconductor device 1.

[0054] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0055] 1: semiconductor device, 4, 4c, 4d: first insulating layer, 4ba, 4ca, 4da: first air layer, 10: source electrode (an example of a first electrode), 12: gate electrode (an example of a third electrode), 14: drain electrode (an example of a second electrode), 20: source field plate electrode portion (an example of an electrode portion), 24: insulating film, 26: second insulating layer, E14, E20: end lines.

Claims

1. A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode provided on the second nitride semiconductor layer; a second electrode provided on the second nitride semiconductor layer; and a third electrode provided on the second nitride semiconductor layer between the first electrode and the second electrode, wherein the substrate has at least one of a first insulating layer which is a region having a lower dielectric constant than the substrate and a first air layer, the first insulating layer being configured according to the position of the second electrode.

2. The semiconductor device described in claim 1, wherein at least one of the first insulating layer and the first air layer is configured based on a first position where a first direction perpendicular to the upper surface of the first nitride semiconductor layer along the end of the second electrode on the first electrode side intersects with the lower surface of the first nitride semiconductor layer.

3. The semiconductor device described in claim 2, wherein at least one of the first insulating layer and the first air layer expands in range in a direction perpendicular to the first direction from the second electrode to the first electrode as the distance from the underside of the first nitride semiconductor layer increases along the first direction.

4. The semiconductor device according to claim 3, wherein at least one of the first insulating layer and the first air layer has a slope surface at the boundary with the substrate that is perpendicular to the first direction and slopes in a direction from the second electrode to the first electrode.

5. The semiconductor device according to claim 4, further comprising an electrode portion on said third electrode, one end of which is electrically connected to said first electrode, and having a portion extending along the upper surface of said first nitride semiconductor layer.

6. The semiconductor device according to claim 5, wherein said inclined surface is configured according to the position of a second end of said extending portion that is closer to said second electrode.

7. The semiconductor device described in claim 6, wherein at least one of the first insulating layer and the first air layer has a boundary with the substrate in a range between a second position where a second direction perpendicular to the upper surface of the first nitride semiconductor layer along the second end intersects with the lower surface of the first nitride semiconductor layer, and the first position.

8. The semiconductor device according to claim 2, wherein the first insulating layer has a plurality of separated regions in a second direction that is parallel to an upper surface of the second nitride semiconductor layer and perpendicular to the first direction.

9. The semiconductor device according to claim 8, wherein each of said plurality of isolated regions is a rectangular parallelepiped.

10. The semiconductor device according to claim 1, wherein at least one of the first insulating layer and the first air space is configured to be flush with the upper surface of the substrate.

11. The semiconductor device described in claim 7, further comprising: an insulating film provided on the second nitride semiconductor layer between the first electrode and the second electrode and in contact with the second nitride semiconductor layer; and a second insulating layer provided on the insulating film between the first electrode and the third electrode, on the insulating film between the third electrode and the second electrode, and on the third electrode, wherein the third electrode is provided on the insulating film between the first electrode and the second electrode.

12. The semiconductor device according to claim 1, further comprising an electrode portion electrically connected to at least one of said first electrode, said second electrode, and said third electrode, and disposed above said third electrode.

13. A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode provided on the second nitride semiconductor layer; a second electrode provided on the second nitride semiconductor layer; and a third electrode provided on the second nitride semiconductor layer between the first electrode and the second electrode, wherein the substrate has a first insulating layer configured according to the position of the second electrode and which is a region having a lower dielectric constant than the substrate.

14. A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode provided on the second nitride semiconductor layer; a second electrode provided on the second nitride semiconductor layer; and a third electrode provided on the second nitride semiconductor layer between the first electrode and the second electrode, wherein the substrate is configured according to a position of the second electrode and has a first air layer which is a region having a lower dielectric constant than the substrate.

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