Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of improving resistance to electrostrictive strain when a high electric field is applied.　A multilayer ceramic capacitor according to the present invention includes: a laminate including a plurality of laminated dielectric layers and having a first main surface and a second main surface which face each other in the lamination direction of the plurality of dielectric layers, a first side surface and a second side surface which face each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface which face each other in a length direction orthogonal to the lamination direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed to the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed to the second end surface; a first external electrode having a base electrode layer, which is disposed on the first end surface, and a plating layer, which is disposed on the base electrode layer; and a second external electrode having a base electrode layer, which is disposed on the second end surface, and a plating layer, which is disposed on the base electrode layer. The crystallites in dielectric particles contained in the dielectric layer are oriented along a C-axis.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known for some time. Generally, multilayer ceramic capacitors include a ceramic sintered body made of a dielectric ceramic such as barium titanate (BaTiO). A plurality of internal electrodes are arranged inside the ceramic sintered body so as to overlap with each other via dielectric layers. External electrodes are formed on one end surface and the other end surface of the ceramic sintered body so as to be electrically connected to the internal electrodes (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 8-306580

[0004] However, a typical multilayer ceramic capacitor such as that disclosed in Patent Document 1 has the following problem: when a high electric field is applied to the multilayer ceramic capacitor, the dielectric particles contained in the dielectric layer are significantly displaced in the direction of the applied electric field (C-axis), which may cause electrostriction and lead to failure.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can improve resistance to electrostriction when a high electric field is applied.

[0006] A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers stacked together, the laminate having first and second main surfaces opposing each other in a stacking direction of the dielectric layers, first side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; first external electrodes having first internal electrode layers disposed on the plurality of dielectric layers and exposed at the first end surfaces, second internal electrode layers disposed on the plurality of dielectric layers and exposed at the second end surfaces, a base electrode layer disposed on the first end surfaces, and a plating layer disposed on the base electrode layer; and a second external electrode having a base electrode layer disposed on the second end surfaces, and a plating layer disposed on the base electrode layer, wherein the crystallites in the dielectric particles contained in the dielectric layers are oriented along the C-axis.

[0007] In the multilayer ceramic capacitor according to the present invention, the crystallites in the dielectric particles contained in the dielectric layers are oriented along the C-axis. Therefore, when a high electric field is applied to the laminate, the amount of displacement of the dielectric layers is reduced, and the electrostriction resistance of the multilayer ceramic capacitor can be improved.

[0008] According to the present invention, in the multilayer ceramic capacitor, it is possible to improve resistance to electrostriction when a high electric field is applied.

[0009] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0010] 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1; 5 is a schematic cross-sectional view taken along line V-V in FIG. 1; and 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. (a) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into two; (b) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into three; and (c) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into four.

[0011] An example of a multilayer ceramic capacitor according to an embodiment of the present invention will now be described.

[0012] 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor according to an embodiment of the present invention will be described. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 4 is a cross-sectional view taken along line VI-VII in FIG. 1.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and external electrodes 30. The laminate 12 is formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 16, and is composed of an internal layer portion 15a that exhibits capacitance, and a first external layer portion 15b1 and a second external layer portion 15b2 that are arranged to sandwich the internal layer portion 15a from the upper and lower main surfaces.

[0014] Hereinafter, the configuration of each of the laminate 12, the internal electrode layer 16, and the external electrode 30 will be described in that order.

[0015] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face in a height direction x, which is the stacking direction of the plurality of dielectric layers 14; a first side surface 12c and a second side surface 12d that face in a width direction y that is perpendicular to the height direction x; and a first end surface 12e and a second end surface 12f that face in a length direction z that is perpendicular to the height direction x and the width direction y. The length direction z is also defined as the L direction, which is the direction connecting the first end surface 12e and the second end surface 12f. The width direction y is also defined as the W direction, which is the direction connecting the first side surface 12c and the second side surface 12d. The height direction x is also defined as the T direction, which is the direction connecting the first main surface 12a and the second main surface 12b.

[0016] The laminate 12 has a rectangular parallelepiped shape. The "rectangular parallelepiped shape" includes a rectangular parallelepiped with rounded corners and ridges. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. In other words, a "rectangular parallelepiped" member refers to any member having a first main surface 12a and a second main surface 12b, a first side surface 12c and a second side surface 12d, and a first end surface 12e and a second end surface 12f.

[0017] The first and second main surfaces 12a and 12b, the first and second side surfaces 12c and 12d, and the first and second end surfaces 12e and 12f may have irregularities or the like formed on some or all of them.

[0018] As shown in Figures 4 and 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an inner layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0019] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0020] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0021] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0022] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 50 to 2000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably, for example, approximately 0.5 μm to 10 μm.

[0023] The ceramic material constituting the dielectric layer 14 may be, for example, a dielectric material. In particular, in this embodiment, it is preferable to use a dielectric ceramic containing barium titanate (BaTiO) as the main component as the dielectric material. Furthermore, depending on the desired properties of the laminate, it is also possible to use a material containing a minor component, such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, in a smaller amount than the main component.

[0024] Furthermore, in this embodiment, the crystallites in the dielectric particles contained in the dielectric layer 14 are oriented along the C axis.

[0025] That is, when a high electric field is applied, the dielectric particles contained in the dielectric layer 14 are displaced in the direction of the applied electric field (C-axis), which causes electrostriction. In contrast, by orienting the crystallites in the dielectric particles in the C-axis in advance as described above, the amount of displacement of the dielectric particles contained in the dielectric layer 14 in the direction of the applied electric field (C-axis) when a high electric field is applied to the multilayer ceramic capacitor 10 is reduced. Therefore, the electrostriction resistance of the multilayer ceramic capacitor 10 is improved.

[0026] Furthermore, the degree of orientation of the crystallites in the dielectric particles contained in the dielectric layer 14 along the C-axis (C-axis orientation degree) is preferably 1.6 or more and 2.2 or less.

[0027] This further improves the resistance of the multilayer ceramic capacitor 10 to electrostriction.

[0028] The degree of C-axis orientation can be obtained based on diffraction intensity measurements using transmission XRD on the SPring-8. Specifically, the relative intensity ratio between the peak intensities of the plane orientations (400) and (040) obtained by Rietveld analysis and the data recorded on the ICDD card is calculated, and this is taken as the measured intensity ratio. Then, the ratio of the measured intensity ratio to the theoretical intensity ratio of the plane orientations (400) and (040) of BaTiO3 is calculated, and this is defined as the degree of C-axis orientation.

[0029] Since the theoretical intensity ratio of the (400) and (040) plane orientations of BaTiO3 is 2:1, if the measured intensity ratio is 2:1, the measured intensity ratio and the theoretical intensity ratio are the same, and the degree of C-axis orientation is 1, i.e., the crystallites in the dielectric particles are not oriented. On the other hand, if the intensity of the (400) plane orientation of BaTiO3 is greater than 2 when the intensity of the (040) plane orientation is 1, the degree of C-axis orientation becomes greater than 1, i.e., the crystallites are oriented.

[0030] Furthermore, in this embodiment, it is preferable that the dielectric particles have a relative dielectric constant of 1000 or more.

[0031] This is for the following reason: when the dielectric particles have a relative permittivity of 1000 or more, the amount of displacement of the dielectric particles is large when a voltage is applied to the dielectric layer 14. Therefore, by configuring such dielectric particles so that they are oriented in the C-axis in advance, as in the present embodiment, the effect of reducing the amount of displacement of the dielectric layer 14 when a voltage is applied in the multilayer ceramic capacitor 10 can be made more significant.

[0032] (Internal Electrode Layers) As shown in Figures 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0033] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 20a is led out to the first end face 12e and exposed. Specifically, the end of the first lead electrode portion 20a is slightly recessed from the second end face 12f.

[0034] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0035] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0036] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b that faces the first internal electrode layer 16a, and a second extraction electrode portion 20b that is located on one end side of the second internal electrode layer 16b and extends from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second extraction electrode portion 20b is extended to and exposed at the second end face 12f. Specifically, the end of the second extraction electrode portion 20b is slightly recessed from the first end face 12e.

[0037] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0038] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0039] The laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a of the laminate 12 formed between one ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes end portions (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between an end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f, and between an end of the second internal electrode layer 16b opposite to the second extraction electrode portion 20b and the first end surface 12e.

[0040] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 50 to 2000. The thickness of the internal electrode layers 16 is preferably about 0.2 μm to 2.0 μm.

[0041] The internal electrode layers 16 can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag—Pd alloy.

[0042] As shown in FIG. 7, the laminate 12 shown in FIG. 1 may include, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not extended to either the first end face 12e or the second end face 12f. The floating internal electrode layer 16c may divide the opposing electrode portion 26c into multiple portions. For example, the opposing electrode portion 26c may have a two-part structure as shown in FIG. 7(a), a three-part structure as shown in FIG. 7(b), a four-part structure as shown in FIG. 7(c), or a structure with more than four parts. By dividing the opposing electrode portion 26c into multiple portions, multiple capacitor components are formed between the opposing first internal electrode layer 16a, the second internal electrode layer 16b, and the floating internal electrode layer 16c, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby increasing the withstand voltage of the multilayer ceramic capacitor 10.

[0043] Furthermore, like the first internal electrode layer 16a and the second internal electrode layer 16b, the floating internal electrode layer 16c can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0044] As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0045] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0046] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0047] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on part of the first main face 12a, part of the second main face 12b, and part of the first side face 12c, part of the second side face 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0048] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0049] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0050] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0051] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0052] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0053] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0054] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0055] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrode layers 16 and dielectric layers 14 and the conductive paste applied to the laminated chip, but may also be baked after baking the laminated chip having internal electrode layers 16 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0056] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the first base electrode layer 32a located on the first end face 12e is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0057] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0058] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0059] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0060] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first side surface 12c and the second side surface 12d is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0061] Furthermore, it is preferable that the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first side surface 12c and the second side surface 12d is, for example, approximately 10 μm or more and 100 μm or less.

[0062] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0063] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0064] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the first and second end faces 12e and 12f, and extend to the first and second main faces 12a and 12b and the first and second side faces 12c and 12d, respectively. However, the first and second conductive resin layers may be disposed only on the other layers, such as baked layers, located on the first and second end faces 12e and 12f.

[0065] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0066] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0067] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0068] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0069] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0070] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0071] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0072] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0073] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0074] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0075] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layers. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layers.

[0076] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0077] The conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0078] (In the case of a thin film layer) When the base electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0079] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 and 3. FIG.

[0080] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0081] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0082] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0083] The lower plating layer made of Ni plating is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount.

[0084] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0085] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 10.0 mm, W in the width direction y is 0.1 mm to 10.0 mm, and T in the height direction x is 0.1 mm to 5.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0086] 1, the crystallites in the dielectric particles contained in the dielectric layers 14 of the laminate 12 are oriented along the C-axis. This reduces the amount of displacement of the dielectric particles contained in the dielectric layers 14 in the direction of the applied electric field (C-axis) when a high electric field is applied to the multilayer ceramic capacitor 10, thereby improving resistance to electrostriction.

[0087] In the multilayer ceramic capacitor 10, the degree of orientation of the crystallites in the dielectric particles contained in the dielectric layers 14 along the C-axis (C-axis orientation degree) is preferably 1.6 or more and 2.2 or less, thereby further improving the resistance of the multilayer ceramic capacitor 10 to electrostriction.

[0088] Furthermore, in the multilayer ceramic capacitor 10, the dielectric particles preferably have a relative dielectric constant of 1000 or more. This makes it possible to more significantly reduce the displacement of the dielectric layers 14 in the multilayer ceramic capacitor 10 when a voltage is applied.

[0089] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0090] (1) Prepare a dielectric sheet and a conductive paste for the internal electrode layers. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (for example, a known organic binder) and a solvent (for example, a known organic binder).

[0091] (2) Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheets by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode pattern corresponding to the first internal electrode layer is formed and a dielectric sheet on which a second internal electrode pattern corresponding to the second internal electrode layer is formed. Note that, with regard to the dielectric sheets, a dielectric sheet for an outer layer on which no internal electrode pattern is printed is also prepared.

[0092] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked to form a portion that will become a second outer layer portion, and a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed are stacked in this order on top of that to form a portion that will become an inner layer portion.

[0093] (4) Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the internal electrode pattern corresponding to the internal electrode layer located on the outermost surface of the inner layer portion to form a portion that will become the first outer layer portion, thereby producing a laminated sheet.

[0094] (5) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0095] (6) The laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0096] (7) The laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode layer 16 materials, but is preferably 900°C or higher and 1400°C or lower. The firing atmosphere preferably has an oxygen concentration of 1000 ppm or higher and 5000 ppm or lower, a temperature rise rate of 100°C / sec or higher from 800°C to the top temperature (1400°C), and a firing time of 4 seconds or higher and 8 seconds or lower. This allows the crystallites in the dielectric particles contained in the dielectric layer to be oriented along the C-axis.

[0097] (8) Subsequently, the base electrode layer is formed. The base electrode layer is a baked layer. A conductive paste containing a glass component and a metal component is prepared for each of the first base electrode layer and the second base electrode layer.

[0098] (9) A conductive paste is applied to the first end face and the second end face of the laminate 12 by, for example, dipping or screen printing, and then a baking process is performed to form the first and second base electrode layers. The baking temperature is preferably 700° C. or higher and 900° C. or lower.

[0099] (10) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0100] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in a N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0101] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0102] (11) Plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surfaces of the first and second base electrode layers. Specifically, a Ni plating layer is formed on the first and second base electrode layers, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0103] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 is manufactured.

[0104] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were fabricated as experimental samples according to the above-described manufacturing method, with the degree of C-axis orientation being varied, and an experiment was conducted to confirm the occurrence of cracks by electrostriction testing.

[0105] (1) Specifications of the Multilayer Ceramic Capacitors Produced as Examples Using the production method according to the above embodiment, multilayer ceramic capacitors were produced as samples of Examples 1 to 5. Dimensions of multilayer ceramic capacitor (design values): L x W x T = 1.19 mm x 0.68 mm x 0.68 mm Ceramic material: BaTiO3 Capacitance: 10 μF Material of internal electrode layer: Ni Structure of external electrode: Conductive metal (Cu) and glass component Plating layer Two layers formed: Ni plating layer and Sn plating layer Ni plating layer thickness: Approximately 3 μm Sn plating layer thickness: Approximately 5 μm

[0106] (2) Specifications of the Multilayer Ceramic Capacitor Fabricated as a Comparative Example A multilayer ceramic capacitor was fabricated as a sample of the comparative example using the manufacturing method according to the embodiment described above. However, in the manufacturing process of the sample of the comparative example, the temperature rise rate in step (7) of the manufacturing method was set to 5°C / min, and firing was performed with a lower oxygen concentration than in the experimental example. The other specifications were the same as those of the sample of the example.

[0107] (3) Electrostriction Test Method The electrostriction test of each sample of the multilayer ceramic capacitor was carried out using a breakdown voltage measuring device. The detailed conditions for the breakdown voltage measuring device were that the voltage was increased to DC 150 V at a voltage increase rate of 100 V / sec.

[0108] (4) Crack Detection Method Cracks in the samples were detected using the following method. First, the samples to which voltage was applied in the electrostrictive test were aligned so that the main surfaces of the multilayer ceramic capacitors (samples) faced upward. Next, ultrasonic waves were irradiated onto the top surfaces of the aligned multilayer ceramic capacitors using an ultrasonic probe, and scanning was performed. The reflected waves of the ultrasonic waves were observed, and the presence or absence of cracks was confirmed by detecting the reflected waves that returned earlier than the bottom waves. Samples confirmed to have cracks were counted as electrostrictive defects, and the crack occurrence rate was calculated. For each example and comparative example, 100 samples were prepared, and the crack occurrence rate was measured. The percentage of the number of cracks relative to the total number of measurements (100 samples) was defined as the crack occurrence rate. The criteria for the crack occurrence rate were as follows: 0% to 4% (good), 5% to 80% (fair), and 81% to 100% (poor).

[0109] (5) Method for Measuring the Degree of C-Axis Orientation The degree of C-axis orientation of the dielectric particles was obtained based on diffraction intensity measurement using transmission XRD of SPring-8. Specifically, as described above, the relative intensity ratio between the peak intensities of the plane orientations (400) and (040) obtained by Rietveld analysis and the data recorded on the ICDD card was calculated, and this was taken as the measured intensity ratio, and the ratio with the theoretical intensity ratio was calculated. The criteria for judging the degree of C-axis orientation were as follows: When the degree of C-axis orientation was 1, it was determined that the orientation was random, i.e., the C-axis was not oriented. When the degree of C-axis orientation was greater than 1, it was determined that the C-axis was oriented.

[0110] (6) Results Table 1 shows the degree of C-axis orientation of the dielectric particles, the crack occurrence rate, and the results of the electrostriction test for each sample of the multilayer ceramic capacitor according to Examples 1 to 5 and Comparative Example 1.

[0111]

[0112] According to Table 1, in each of the samples of Examples 1 to 5, the dielectric particles in the dielectric layer were oriented along the C axis, and therefore, a good result of 5% or less crack occurrence rate was obtained.

[0113] Furthermore, in each of the samples of Examples 2 to 5, the degree of orientation of the C-axis was 1.6 or more and 2.2 or less, and therefore the crack occurrence rate was 0%, and better results were obtained.

[0114] On the other hand, in the sample according to the comparative example, the C-axis was not oriented (the degree of C-axis orientation was 1), and therefore the crack occurrence rate was 93%.

[0115] The above results suggest that in this invention, the crystallites in the dielectric particles contained in the dielectric layers are oriented along the C-axis, thereby reducing the amount of displacement of the dielectric layers when a high electric field is applied to the laminate, and as a result, it is possible to improve the electrostriction resistance of the multilayer ceramic capacitor.

[0116] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0117] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0118] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 16c Floating internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 22a Side portion 22b End portion 26c Counter electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 plating layer 34a first plating layer 34b second plating layer x height direction (stacking direction) y width direction z length direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers stacked together, the laminate having a first main surface and a second main surface facing each other in a stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed at the second end surface; a first external electrode having a base electrode layer disposed on the first end surface and a plating layer disposed on the base electrode layer; and a second external electrode having a base electrode layer disposed on the second end surface and a plating layer disposed on the base electrode layer, wherein the crystallites in the dielectric particles contained in the dielectric layers are oriented along the C-axis.

2. The multilayer ceramic capacitor according to claim 1, wherein the degree of orientation of the crystallites in the dielectric particles along the C-axis (C-axis orientation degree) is 1.6 or more and 2.2 or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the dielectric particles have a relative dielectric constant of 1,000 or more.

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