Semiconductor device

Abstract

This semiconductor device includes: a nitride semiconductor layer; a plurality of source electrodes extending in a second direction; a plurality of drain electrodes extending in the second direction; a gate electrode provided on the nitride semiconductor layer, located between the source electrode and the drain electrode adjacent to each other in the first direction, and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a source wiring part provided on the insulating layer, the source wiring part having a plurality of source pad parts located apart from each other in the first direction and electrically connected to the source electrode, and a source connection part connecting two source pad parts adjacent to each other in the first direction. The width of the source connection part in the second direction is smaller than the width of the source pad part in the second direction.

Description

Semiconductor Devices

[0001] The embodiments relate to a semiconductor device.

[0002] A high electron mobility transistor (HEMT) using a gallium nitride material is known as a power device.

[0003] Patent No. 6827776 Patent No. 7260224 Patent No. 5884094

[0004] The embodiments provide a semiconductor device that allows for a reduction in planar size and capacitance.

[0005] and a source wiring portion provided on the insulating layer, the source wiring portion including a plurality of source pad portions located apart from each other in the first direction and electrically connected to the source electrode, and a source connection portion connecting two of the source pad portions adjacent to each other in the first direction, wherein the width of the source connection portion in the second direction is smaller than the width of the source pad portion in the second direction.

[0006] 2 is a schematic plan view of the semiconductor device of the embodiment; FIG. 3 is a schematic plan view of an active region in the semiconductor device of the embodiment; FIG. 4 is a cross-sectional view taken along line AA in FIG. 2; FIG. 5 is a schematic plan view showing a modified example of the semiconductor device of the embodiment; and FIG. 6 is a schematic plan view showing another modified example of the semiconductor device of the embodiment.

[0007] Hereinafter, embodiments will be described with reference to the drawings, in which the same components are denoted by the same reference numerals.

[0008] 1 , a semiconductor device 1 according to the embodiment includes a nitride semiconductor layer 20. Two directions intersecting each other in a plane parallel to the surface of the nitride semiconductor layer 20 are defined as a first direction X and a second direction Y. In this example, the first direction X and the second direction Y are perpendicular to each other. A direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z.

[0009] 3, the semiconductor device 1 may further include a substrate 10 that supports the nitride semiconductor layer 20. The substrate 10 may be, for example, a silicon substrate. Alternatively, the substrate 10 may be a sapphire substrate.

[0010] The nitride semiconductor layer 20 may have a first layer 21 and a second layer 22. In the third direction Z, the first layer 21 is provided on the substrate 10, and the second layer 22 is provided on the first layer 21. For example, the first layer 21 and the second layer 22 are grown in this order on the substrate 10 by MOCVD (metal organic chemical vapor deposition).

[0011] The band gap of the second layer 22 is wider than the band gap of the first layer 21. For example, the first layer 21 is a gallium nitride (GaN) layer, and the second layer 22 is an aluminum gallium nitride (AlGaN) layer. Due to the piezoelectric polarization effect, two-dimensional electron gas 25 is distributed in the first layer 21 near the interface with the second layer 22.

[0012] The nitride semiconductor layer 20 includes an active region 100 in which a two-dimensional electron gas 25 is distributed. The active region 100 is surrounded by an element isolation portion. The element isolation portion can be formed by, for example, ion implantation. FIG. 2 shows a portion of the active region 100. FIG. 3 is a cross-sectional view taken along line A-A in FIG. 2. The insulating layer 62 shown in FIG. 3 is omitted from FIG. 2. The semiconductor device 1 further includes a source electrode 31, a drain electrode 41, and a gate electrode 51 provided on the active region 100 of the nitride semiconductor layer 20.

[0013] 2 , a plurality of source electrodes 31 are spaced apart from one another in the first direction X and extend in the second direction Y. A plurality of drain electrodes 41 are spaced apart from one another in the first direction X and extend in the second direction Y. A plurality of gate electrodes 51 are spaced apart from one another in the first direction X and extend in the second direction Y. The source electrodes 31, the drain electrodes 41, and the gate electrodes 51 are spaced apart from one another in the first direction X. One gate electrode 51 is located between adjacent source electrodes 31 and drain electrodes 41 in the first direction X.

[0014] The distance in the first direction X between the drain electrode 41 and the gate electrode 51 (drift length) is longer than the distance in the first direction X between the source electrode 31 and the gate electrode 51. This improves the breakdown voltage.

[0015] 3 , a gate insulating film 61 is provided on the surface of the nitride semiconductor layer 20 between the source electrode 31 and the drain electrode 41. A gate electrode 51 is provided on the gate insulating film 61. The source electrode 31 and the drain electrode 41 are in contact with the nitride semiconductor layer 20. By controlling the gate electrode 51, a current flows between the drain electrode 41 and the source electrode 31 through the two-dimensional electron gas 25.

[0016] The semiconductor device 1 further includes an insulating layer 62 provided on the source electrode 31 , the drain electrode 41 , and the gate electrode 51 .

[0017] As shown in FIG. 1 , the semiconductor device 1 further includes a source wiring portion 32 , a drain wiring portion 42 , and a gate wiring portion 52 provided on the insulating layer 62 in the active region 100 .

[0018] 3, the source wiring portion 32 is provided on an insulating layer 62. Similarly, the drain wiring portion 42 and the gate wiring portion 52 are also provided on the insulating layer 62.

[0019] 1 and 2, the source wiring section 32 has a plurality of source pad sections 32A that are spaced apart from each other in the first direction X. The source wiring section 32 also has a source connection section 32B that connects two source pad sections 32A that are adjacent to each other in the first direction X. For example, the source pad sections 32A and the source connection sections 32B are arranged alternately in the first direction X.

[0020] 2 and 3, the source pad portion 32A is electrically connected to the source electrode 31 through a source via 33. The source via 33 is provided in the insulating layer 62 between the source pad portion 32A and the source electrode 31.

[0021] 1 , the semiconductor device 1 further includes a first lead 71, a second lead 72, and a third lead 73. For example, a source pad portion 32A located at one end of the source wiring portion 32 in the first direction X is connected to the first lead 71 via a fourth wire w4. The source electrode 31 is electrically connected to the first lead 71 via a source via 33, the source wiring portion 32, and the fourth wire w4. A source potential (e.g., ground potential) is applied to the first lead 71 from an external circuit.

[0022] 2, a plurality of source pad portions 32A and a plurality of source vias 33 are arranged in the first direction X in correspondence with a plurality of source electrodes 31 arranged in the first direction X. In the example of the plan view shown in FIG. 2, one source pad portion 32A overlaps two source electrodes 31. In the plan view, one source pad portion 32A may overlap one source electrode 31 or three or more source electrodes 31.

[0023] According to this embodiment, the source wiring portion 32 for electrically connecting the source electrode 31 to an external circuit is arranged on the active region 100, thereby making it possible to reduce the planar size (chip size) of the semiconductor device 1.

[0024] 2 , when the source wiring portion 32 is disposed on the active region 100, the source wiring portion 32 intersects with the drain electrode 41 and the gate electrode 51 in a plan view. At the intersection of the source wiring portion 32 and the drain electrode 41, a capacitance Cds is generated between the source wiring portion 32 and the drain electrode 41 in the third direction Z. At the intersection of the source wiring portion 32 and the gate electrode 51, a capacitance Cgs is generated between the source wiring portion 32 and the gate electrode 51 in the third direction Z.

[0025] According to this embodiment, the width of the source connection portion 32B in the second direction Y is smaller than the width of the source pad portion 32A in the second direction Y. The area of ​​one source connection portion 32B is smaller than the area of ​​one source pad portion 32A. This allows the capacitances Cds and Cgs to be reduced compared to when the source wiring portion 32 is formed only with the source pad portion 32A. The source connection portion 32B only needs to electrically connect adjacent source pad portions 32A, and the source via 33 does not need to be disposed below the source connection portion 32B. Therefore, the width of the source connection portion 32B in the second direction Y can be smaller than the width of the source pad portion 32A in the second direction Y, and / or the area of ​​the source connection portion 32B can be smaller than the area of ​​the source pad portion 32A. Alternatively, the source via 33 may be disposed below the source connection portion 32B.

[0026] According to this embodiment, the capacitance Cds and capacitance Cgs can be reduced by providing a source connection portion 32B that is smaller in width and / or area than the source pad portion 32A while easily ensuring electrical connection between the source electrode 31 and the first lead 71 in the source pad portion 32A.

[0027] 1 and 2 , the drain wiring portion 42 has a plurality of drain pad portions 42A that are spaced apart from each other in the first direction X. The drain wiring portion 42 also has a drain connection portion 42B that connects two drain pad portions 42A that are adjacent to each other in the first direction X. For example, the drain pad portions 42A and the drain connection portions 42B are arranged alternately in the first direction X.

[0028] 2, the drain pad portion 42A is electrically connected to the drain electrode 41 through a drain via 43. The drain via 43 is provided in the insulating layer 62 between the drain pad portion 42A and the drain electrode 41.

[0029] 1 , for example, the drain pad portion 42A located at one end of the drain wiring portion 42 in the first direction X is connected to the second lead 72 via a fifth wire w5. The drain electrode 41 is electrically connected to the second lead 72 via the drain via 43, the drain wiring portion 42, and the fifth wire w5. A drain potential is applied to the second lead 72 from an external circuit.

[0030] 2 , a plurality of drain pad portions 42A and a plurality of drain vias 43 are arranged in the first direction X in correspondence with a plurality of drain electrodes 41 arranged in the first direction X. In the example of the plan view shown in FIG. 2 , one drain pad portion 42A overlaps two drain electrodes 41. In the plan view, one drain pad portion 42A may overlap one drain electrode 41 or three or more drain electrodes 41.

[0031] By arranging the drain wiring portion 42 for electrically connecting the drain electrode 41 to an external circuit on the active region 100, the planar size (chip size) of the semiconductor device 1 can be reduced.

[0032] 2 , when the drain wiring portion 42 is disposed on the active region 100, the drain wiring portion 42 intersects with the source electrode 31 and the gate electrode 51 in a plan view. At the intersection of the drain wiring portion 42 and the source electrode 31, a capacitance Cds is generated between the drain wiring portion 42 and the source electrode 31 in the third direction Z. At the intersection of the drain wiring portion 42 and the gate electrode 51, a capacitance Cgd is generated between the drain wiring portion 42 and the gate electrode 51 in the third direction Z.

[0033] According to this embodiment, the width of the drain connection portion 42B in the second direction Y is smaller than the width of the drain pad portion 42A in the second direction Y. The area of ​​one drain connection portion 42B is smaller than the area of ​​one drain pad portion 42A. This allows the capacitances Cds and Cgd to be reduced compared to when the drain wiring portion 42 is formed only with the drain pad portion 42A. The drain connection portions 42B only need to electrically connect adjacent drain pad portions 42A, and the drain vias 43 do not need to be disposed below the drain connection portions 42B. Therefore, the width of the drain connection portion 42B in the second direction Y can be smaller than the width of the drain pad portion 42A in the second direction Y, and / or the area of ​​the drain connection portion 42B can be smaller than the area of ​​the drain pad portion 42A. Alternatively, the drain vias 43 may be disposed below the drain connection portions 42B.

[0034] According to this embodiment, the capacitance Cds and capacitance Cgd can be reduced by providing a drain connection portion 42B that is smaller in width and / or area than the drain pad portion 42A while easily ensuring electrical connection between the drain electrode 41 and the second lead 72 in the drain pad portion 42A.

[0035] As shown in FIG. 1 , the semiconductor device 1 includes a plurality of source wiring portions 32 and a plurality of drain wiring portions 42. The plurality of source wiring portions 32 and the plurality of drain wiring portions 42 include source wiring portions 32 and drain wiring portions 42 arranged alternately in the second direction Y. By arranging the source wiring portions 32 and drain wiring portions 42 alternately in the second direction Y, the source wiring portions 32 can be electrically connected to the source electrode 31 extending in the second direction Y without bias in the second direction Y, thereby reducing bias in the current distribution in the source electrode 31. Similarly, the drain wiring portions 42 can be electrically connected to the drain electrode 41 extending in the second direction Y without bias in the second direction Y, thereby reducing bias in the current distribution in the drain electrode 41. Note that the plurality of source wiring portions 32 and the plurality of drain wiring portions 42 do not have to be arranged alternately.

[0036] Furthermore, depending on the positions of the source electrode 31 and the drain electrode 41 in the first direction X, the position of the source pad portion 32A for connection to the source electrode 31 in the first direction X and the position of the drain pad portion 42A for connection to the drain electrode 41 in the first direction X are shifted in the first direction X. That is, the source pad portion 32A and the drain connection portion 42B are adjacent to each other in the second direction Y, and the drain pad portion 42A and the source connection portion 32B are adjacent to each other in the second direction Y. Note that the source pad portion 32A and the drain connection portion 42B do not have to be adjacent to each other in the second direction Y, and the drain pad portion 42A and the source connection portion 32B do not have to be adjacent to each other in the second direction Y.

[0037] 1 and 2 , the gate wiring unit 52 has a plurality of gate pad units 52A that are spaced apart from each other in the first direction X. The gate pad units 52A are electrically connected to the gate electrodes 51. The gate wiring unit 52 also has gate connection units 52B that connect two gate pad units 52A that are adjacent to each other in the first direction X. For example, the gate pad units 52A and the gate connection units 52B are arranged alternately in the first direction X.

[0038] 1 , for example, the gate pad portion 52A located at one end of the gate wiring portion 52 in the first direction X is connected to the third lead 73 via a sixth wire w6. The gate electrode 51 is electrically connected to the third lead 73 via the gate wiring portion 52 and the sixth wire w6. A gate potential is applied to the third lead 73 from an external circuit.

[0039] The current flowing through the gate electrode 51 is smaller than the current flowing through the drain electrode 41 and the source electrode 31. Therefore, the number of gate wiring portions 52 does not need to be less than the number of source wiring portions 32, and the number of gate wiring portions 52 does not need to be less than the number of drain wiring portions 42. For example, as shown in FIG. 1 , two gate wiring portions 52 can be arranged at both ends of the active region 100 in the second direction Y. A plurality of source wiring portions 32 and a plurality of drain wiring portions 42 are arranged between the two gate wiring portions 52 spaced apart in the second direction Y. In this case, as shown in FIG. 2 , the gate wiring portions 52 can be arranged so as not to intersect with the source electrode 31 and the drain electrode 41 in a plan view. This reduces the capacitance between the gate wiring portion 52 and the source electrode 31 and the capacitance between the gate wiring portion 52 and the drain electrode 41.

[0040] By arranging the gate wiring portion 52 for electrically connecting the gate electrode 51 to an external circuit on the active region 100, the planar size (chip size) of the semiconductor device 1 can be reduced.

[0041] When the gate wiring portion 52 is disposed so as to intersect with the source electrode 31 and the drain electrode 41 in a plan view, a capacitance Cgs is generated between the gate wiring portion 52 and the source electrode 31 in the third direction Z at the intersection of the gate wiring portion 52 and the source electrode 31. A capacitance Cgd is generated between the gate wiring portion 52 and the drain electrode 41 in the third direction Z at the intersection of the gate wiring portion 52 and the drain electrode 41.

[0042] According to this embodiment, the width of the gate connection portion 52B in the second direction Y is smaller than the width of the gate pad portion 52A in the second direction Y. The area of ​​one gate connection portion 52B is smaller than the area of ​​one gate pad portion 52A. This makes it possible to reduce the capacitance Cgs and capacitance Cgd compared to when the gate wiring portion 52 is formed only by the gate pad portion 52A.

[0043] According to this embodiment, the capacitance Cgs and capacitance Cgd can be reduced by providing a gate connection portion 52B that is smaller in width and / or area than the gate pad portion 52A while easily ensuring electrical connection between the gate electrode 51 and the third lead 73 in the gate pad portion 52A.

[0044] 2, the semiconductor device 1 may further include a first wire w1 connecting two adjacent source pad portions 32A in the first direction X. Connecting two adjacent source pad portions 32A with the first wire w1 and the source connection portion 32B reduces the wiring resistance of the source wiring portion 32. Note that bumps may be provided on the multiple source pad portions 32A, and upper layer wiring may be provided to connect the multiple bumps, thereby electrically connecting the multiple source pad portions 32A to each other.

[0045] The semiconductor device 1 may further include a second wire w2 connecting two adjacent drain pad portions 42A in the first direction X. Connecting two adjacent drain pad portions 42A with the second wire w2 and the drain connection portion 42B can reduce the wiring resistance of the drain wiring portion 42. Note that bumps may be provided on the multiple drain pad portions 42A, and upper layer wiring may be provided to connect the multiple bumps, thereby electrically connecting the multiple drain pad portions 42A to each other.

[0046] The semiconductor device 1 may further include a third wire w3 connecting two adjacent gate pad portions 52A in the first direction X. Connecting two adjacent gate pad portions 52A with the third wire w3 and the gate connection portion 52B reduces the wiring resistance of the gate wiring portion 52. Note that bumps may be provided on the multiple gate pad portions 52A, and upper layer wiring may be provided to connect the multiple bumps, thereby electrically connecting the multiple gate pad portions 52A to each other.

[0047] 4, the source wiring portion 32 may have at least two source pad portions 32A that are not connected by a source connection portion 32B. The two source pad portions 32A that are not connected by the source connection portion 32B are electrically connected by a first wire w1. The capacitances ds and gs described above are not generated in the portion where the source connection portion 32B is not provided.

[0048] The drain wiring portion 42 may have at least two drain pad portions 42A that are not connected by a drain connection portion 42B. The two drain pad portions 42A that are not connected by the drain connection portion 42B are electrically connected by a second wire w2. The capacitances ds and gd described above are not generated in the portion where the drain connection portion 42B is not provided.

[0049] The gate wiring portion 52 may have at least two gate pad portions 52A that are not connected by a gate connection portion 52B. The two gate pad portions 52A that are not connected by the gate connection portion 52B are electrically connected by a third wire w3. The capacitances gs and gd described above are not generated in the portion where the gate connection portion 52B is not provided.

[0050] As shown in Figure 5, the multiple source wiring portions 32 may have at least two source wiring portions 32 arranged adjacent to each other in the second direction Y, and the drain wiring portion 42 and the gate wiring portion 52 may not be located between the two source wiring portions 32.

[0051] The multiple drain wiring portions 42 may have at least two drain wiring portions 42 arranged adjacent to each other in the second direction Y, and the source wiring portion 32 and the gate wiring portion 52 may not be located between the two drain wiring portions 42.

[0052] The multiple gate wiring portions 52 may include at least two gate wiring portions 52 arranged adjacent to each other in the second direction Y, and the source wiring portion 32 and the drain wiring portion 42 may not be located between the two gate wiring portions 52.

[0053] It is not necessary that all of the source wiring portion 32, the drain wiring portion 42, and the gate wiring portion 52 are located on the active region 100, but by locating at least one of the source wiring portion 32, the drain wiring portion 42, and the gate wiring portion 52 on the active region 100, it is possible to reduce the planar size and the capacitance.

[0054] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0055] 1...semiconductor device, 10...substrate, 20...nitride semiconductor layer, 25...two-dimensional electron gas, 31...source electrode, 32...source wiring portion, 32A...source pad portion, 32B...source connection portion, 33...source via, 41...drain electrode, 42...drain wiring portion, 42A...drain pad portion, 42B...drain connection portion, 43...drain via, 51...gate electrode, 52...gate wiring portion, 52A...gate pad portion, 52B...gate connection portion, 61...gate insulating film, 62...insulating layer, 71...first lead, 72...second lead, 73...third lead, 100...active region

Claims

a gate electrode provided on the nitride semiconductor layer, positioned between the source electrode and the drain electrode adjacent to each other in the first direction and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a source wiring portion provided on the insulating layer, the source wiring portion having a plurality of source pad portions positioned apart from each other in the first direction and electrically connected to the source electrode, and a source connection portion connecting two of the source pad portions adjacent to each other in the first direction, wherein a width in the second direction of the source connection portion is smaller than a width in the second direction of the source pad portion.

2. The semiconductor device according to claim 1, wherein the nitride semiconductor layer includes an active region in which a two-dimensional electron gas is distributed, and the source electrode, the drain electrode, the gate electrode, and the source wiring portion are provided on the active region.

3. The semiconductor device according to claim 1 or 2, wherein, in a plan view, the source wiring portion intersects with the drain electrode.

4. The semiconductor device according to claim 1 or 2, wherein said source wiring section has at least two source pad sections which are not connected by said source connection section.

5. The semiconductor device according to claim 1 or 2, further comprising a first wire connecting two of the source pad portions adjacent to each other in the first direction.

6. The semiconductor device described in claim 1, further comprising: a drain wiring portion provided on the insulating layer, the drain wiring portion having a plurality of drain pad portions positioned apart from each other in the first direction and electrically connected to the drain electrode, and a drain connection portion connecting two of the drain pad portions adjacent to each other in the first direction, wherein the width in the second direction of the drain connection portions is smaller than the width in the second direction of the drain pad portions.

7. The semiconductor device according to claim 6, wherein, in a plan view, the drain wiring portion intersects with the source electrode.

8. The semiconductor device according to claim 6, comprising a plurality of the source wiring portions and a plurality of the drain wiring portions, the plurality of the source wiring portions and the plurality of the drain wiring portions having the source wiring portions and the drain wiring portions arranged alternately in the second direction.

9. A semiconductor device as described in claim 6, comprising a plurality of said source wiring portions, each of said plurality of source wiring portions having at least two of said source wiring portions arranged adjacent to each other in said second direction, and said drain wiring portion not being located between said two source wiring portions.

10. A semiconductor device as described in claim 6, comprising a plurality of the drain wiring portions, the plurality of the drain wiring portions having at least two of the drain wiring portions arranged adjacent to each other in the second direction, and the source wiring portion not being located between the two drain wiring portions.

11. The semiconductor device according to claim 6, wherein the source pad portion and the drain connection portion are adjacent to each other in the second direction, and the drain pad portion and the source connection portion are adjacent to each other in the second direction.

12. A semiconductor device comprising: a nitride semiconductor layer; a plurality of source electrodes provided on the nitride semiconductor layer, electrically connected to the nitride semiconductor layer, positioned apart from each other in a first direction, and extending in a second direction intersecting the first direction; a plurality of drain electrodes provided on the nitride semiconductor layer, electrically connected to the nitride semiconductor layer, positioned apart from each other in the first direction, and extending in the second direction; a gate electrode provided on the nitride semiconductor layer, positioned between the source electrode and the drain electrode adjacent to each other in the first direction, and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a drain wiring portion provided on the insulating layer, the drain wiring portion having a plurality of drain pad portions positioned apart from each other in the first direction and electrically connected to the drain electrode, and a drain connection portion connecting two of the drain pad portions adjacent to each other in the first direction, wherein a width in the second direction of the drain connection portion is smaller than a width in the second direction of the drain pad portion.

13. The semiconductor device according to claim 12, wherein the nitride semiconductor layer includes an active region in which a two-dimensional electron gas is distributed, and the source electrode, the drain electrode, the gate electrode, and the drain wiring portion are provided on the active region.

14. The semiconductor device according to claim 12 or 13, wherein, in a plan view, the drain wiring portion intersects with the source electrode.

15. The semiconductor device according to claim 12 or 13, wherein the drain wiring portion has at least two drain pad portions that are not connected by the drain connecting portion.

16. The semiconductor device according to claim 12 or 13, further comprising a second wire connecting two of the drain pad portions adjacent to each other in the first direction.

17. The semiconductor device described in claim 1 or 12, further comprising: a gate wiring section provided on the insulating layer, the gate wiring section being spaced apart from one another in the first direction and electrically connected to the gate electrode, and a gate connection section connecting two of the gate pad sections adjacent to each other in the first direction, wherein the width in the second direction of the gate connection section is smaller than the width in the second direction of the gate pad section.

18. The semiconductor device according to claim 17, further comprising two gate wiring portions spaced apart from each other in the second direction, and a plurality of source wiring portions and a plurality of drain wiring portions are disposed between the two gate wiring portions.

19. A semiconductor device comprising: a nitride semiconductor layer; a plurality of source electrodes provided on the nitride semiconductor layer, electrically connected to the nitride semiconductor layer, positioned apart from each other in a first direction, and extending in a second direction intersecting the first direction; a plurality of drain electrodes provided on the nitride semiconductor layer, electrically connected to the nitride semiconductor layer, positioned apart from each other in the first direction, and extending in the second direction; a gate electrode provided on the nitride semiconductor layer, positioned between the source electrode and the drain electrode adjacent to each other in the first direction, and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a gate wiring portion provided on the insulating layer, the gate wiring portion having a plurality of gate pad portions positioned apart from each other in the first direction and electrically connected to the gate electrode, and a gate connection portion connecting two of the gate pad portions adjacent to each other in the first direction, wherein a width in the second direction of the gate connection portion is smaller than a width in the second direction of the gate pad portion.

20. The semiconductor device according to claim 19, wherein the nitride semiconductor layer includes an active region in which a two-dimensional electron gas is distributed, and the source electrode, the drain electrode, the gate electrode, and the gate wiring portion are provided on the active region.

21. The semiconductor device according to claim 19, wherein the gate wiring portion has at least two gate pad portions that are not connected by the gate connection portion.

22. The semiconductor device according to claim 19 or 20, further comprising a third wire connecting two of the gate pad portions adjacent to each other in the first direction.

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