Multi-layer ceramic capacitor and method for manufacturing multi-layer ceramic capacitor

Abstract

In a multi-layer ceramic capacitor (1), a plurality of first internal electrode layers (12A) and a plurality of second internal electrode layers (12B) are alternately stacked in a stacking direction (DS) so as to sandwich a plurality of dielectric layers (11). A via conductor (13A) is electrically connected to the plurality of first internal electrode layers (12A). The via conductor (13A) extends from the inside of a capacitor body (10) to a first main surface (101), which is a surface, of the capacitor body (10), on one side in the stacking direction (DS). A base electrode layer (21) is provided to a portion of the via conductor (13A) on the first main surface (101). A plating layer (22) is provided on the base electrode layer (21) such that a surface (131), of the via conductor (13A), on which the base electrode layer (21) is not provided is exposed to the outside above the first main surface (101).

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor.

[0002] Patent Document 1 discloses a multilayer ceramic capacitor including a laminate in which dielectric layers and internal electrode layers composed mainly of a base metal are alternately stacked, and external electrodes having external electrode bodies formed on the surface of the laminate and plating layers formed on the surface of the external electrode bodies. The external electrode bodies are formed so that a portion of the external electrode bodies extends around the side surfaces of the laminate from the end faces. Patent Document 1 further states that "in order to avoid adverse effects such as deterioration of insulation resistance caused by the inclusion of hydrogen in the multilayer ceramic capacitor generated during the plating process, etc., it is desirable to reduce the absolute amount of hydrogen contained in the multilayer ceramic capacitor."

[0003] Japanese Patent Application Laid-Open No. 2016-066783

[0004] As semiconductor packages become more sophisticated, there is a demand for decoupling capacitors that can be placed near the semiconductor packages. As such capacitors, there is a need for multilayer ceramic capacitors that further have so-called via conductors that extend in the stacking direction of the laminate, which differ from the multilayer ceramic capacitor disclosed in Patent Document 1. Even in multilayer ceramic capacitors that have via conductors, it is desirable to suppress a decrease in the insulation resistance of the multilayer ceramic capacitor by allowing hydrogen generated during the formation of plating layers, etc., to be contained in the dielectric layers.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a multilayer ceramic capacitor having via conductors in which a decrease in insulation resistance due to hydrogen in the dielectric layers is suppressed.

[0006] A multilayer ceramic capacitor according to one aspect of the present invention includes a capacitor body and external electrodes. The capacitor body includes a plurality of dielectric layers, a plurality of first internal electrode layers, a plurality of second internal electrode layers, and via conductors. The first internal electrode layers and the second internal electrode layers are alternately stacked in the stacking direction with the plurality of dielectric layers sandwiched between them. The via conductors are electrically connected to the first internal electrode layers. The via conductors extend from the inside of the capacitor body to a first main surface, which is one surface of the capacitor body in the stacking direction. The external electrodes include a base electrode layer and a plating layer. The base electrode layer is provided on a portion of the via conductor on the first main surface. The plating layer is provided on the base electrode layer so that the surfaces of the via conductors on the first main surface, where the base electrode layer is not provided, are exposed to the outside.

[0007] A multilayer ceramic capacitor according to another aspect of the present invention includes a capacitor body and external electrodes. The capacitor body includes a plurality of dielectric layers, a plurality of first internal electrode layers, a plurality of second internal electrode layers, and via conductors. The first internal electrode layers and the second internal electrode layers are alternately stacked in the stacking direction with the plurality of dielectric layers sandwiched between them. The via conductors are electrically connected to the first internal electrode layers. The via conductors extend from the inside of the capacitor body to a first main surface, which is one surface of the capacitor body in the stacking direction. The external electrodes include a base electrode layer and a plating layer. The base electrode layer is provided on the first main surface so as not to expose the via conductors to the outside. The plating layer is provided on the base electrode layer so that at least a portion of a portion of the base electrode layer aligned with the via conductors in the stacking direction is exposed to the outside in the stacking direction.

[0008] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention includes: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and via conductors, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductors are electrically connected to the plurality of first internal electrode layers and extend from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; providing a base electrode layer on a portion of the via conductors on the first main surface; forming a plating layer on the base electrode layer so that surfaces of the via conductors on the first main surface not provided with the base electrode layer are exposed to the outside; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductors and extract it to the outside from the first main surface.

[0009] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention includes: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and via conductors, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductors are electrically connected to the plurality of first internal electrode layers and extend from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; providing a base electrode layer on the first main surface so that the via conductors are not exposed to the outside; forming a plating layer on the base electrode layer so that at least a portion of a portion of the base electrode layer aligned with the via conductors in the stacking direction is exposed to the outside in the stacking direction; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductors and the base electrode layer in the stacking direction and extract it to the outside.

[0010] According to the present invention, in a multilayer ceramic capacitor having via conductors, it is possible to suppress a decrease in insulation resistance due to hydrogen in the dielectric layers.

[0011] 1 is a plan view showing one side of a multilayer ceramic capacitor according to embodiment 1. FIG. 2 is a plan view showing the multilayer ceramic capacitor according to embodiment 1 from the other side. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 as viewed in the direction of the arrows III-III. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 3 as viewed in the direction of the arrows IV-IV. FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 3 as viewed in the direction of the arrows V-V. FIG. 6 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to embodiment 1. FIG. 7 is a cross-sectional view schematically showing a step of forming a plating layer in embodiment 1. FIG. 8 is a plan view showing a multilayer ceramic capacitor according to embodiment 2 from the second main surface side. FIG. 9 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 8 as viewed in the direction of the arrows IX-IX. FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 10 as viewed in the direction of the arrows XI-XI. FIG. 11 is a plan view of a multilayer ceramic capacitor according to embodiment 4 from the first main surface side. FIG. 12 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 12 as viewed in the direction of the arrows XIII-XIII. FIG. 13 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to embodiment 4. 10A to 10C are cross-sectional views schematically illustrating a step of forming a plating layer in embodiment 4.

[0012] Hereinafter, a multilayer ceramic capacitor, a method for manufacturing a multilayer ceramic capacitor, and a method for manufacturing a mounting structure of a multilayer ceramic capacitor according to each embodiment of the present invention will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding parts in the drawings will be designated by the same reference numerals, and the description thereof will not be repeated.

[0013] (Embodiment 1) Fig. 1 is a plan view showing one side of a multilayer ceramic capacitor according to embodiment 1. Fig. 2 is a plan view showing the multilayer ceramic capacitor according to embodiment 1 from the other side. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 as seen in the direction of the arrows along line III-III.

[0014] 1 to 3, the multilayer ceramic capacitor 1 includes a capacitor body 10, a plurality of first external electrodes 20A, and a plurality of second external electrodes 20B. In this embodiment, the first external electrode 20A is exemplified as the external electrode of the present invention.

[0015] The capacitor body 10 may have any shape. In this embodiment, the capacitor body 10 has a rectangular parallelepiped shape as a whole. The rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be regarded as a rectangular parallelepiped as a whole.

[0016] The capacitor body 10 has a first main surface 101, a second main surface 102, and a peripheral side surface 103. The first main surface 101 is a surface on one side of the capacitor body 10 in the stacking direction DS. The second main surface 102 is a surface on the other side of the capacitor body 10 in the stacking direction DS. In other words, the second main surface 102 is a surface of the capacitor body 10 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 may have a rectangular outer shape when viewed in the stacking direction DS. The peripheral side surface 103 connects the first main surface 101 and the second main surface 102.

[0017] The dimensions of the capacitor body 10 are arbitrary, but for example, when viewed from the first main surface 101 side, the vertical dimension of the rectangle can be 0.3 mm or more and 3.0 mm or less, the horizontal dimension can be 0.3 mm or more and 3.0 mm or less, and the dimension in the stacking direction DS can be 50 μm or more and 200 μm or less.

[0018] Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 3, as seen in the direction of the arrows IV-IV. Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 3, as seen in the direction of the arrows VV.

[0019] As shown in Figures 1 to 5, the capacitor body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, a plurality of first via conductors 13A, and a plurality of second via conductors 13B.

[0020] The plurality of dielectric layers 11 include a first outer layer portion 111 and a second outer layer portion 112. The first outer layer portion 111 is the dielectric layer 11 located closest to the first main surface 101 among the plurality of dielectric layers 11. The first outer layer portion 111 forms a part of the first main surface 101. The second outer layer portion 112 is the dielectric layer 11 located closest to the second main surface 102 among the plurality of dielectric layers 11. The second outer layer portion 112 forms the entire second main surface 102. The peripheral side surface 103 is entirely formed of the plurality of dielectric layers 11 including the first outer layer portion 111 and the second outer layer portion 112.

[0021] The dielectric layer 11 may be made of any material, and may be made of, for example, a ceramic material containing BaTiO3, CaTiO3, SrTiO3, SrZrO3, CaZrO3, etc. as a main component. A minor component selected from the group consisting of Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added to these main components in a smaller amount than the main component.

[0022] The plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B are alternately stacked in the stacking direction DS, with the plurality of dielectric layers 11 sandwiched between each other. In the multilayer ceramic capacitor 1, the first internal electrode layers 12A and the second internal electrode layers 12B face each other via the dielectric layers 11, thereby forming a capacitance. By stacking the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B as described above, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a high capacitance density in which a plurality of capacitor function sections are arranged side by side at high density.

[0023] Each of the first internal electrode layers 12A is integrally formed within the same layer (see FIG. 4). The first internal electrode layer 12A has a rectangular outer shape when viewed from the stacking direction DS. Each of the first internal electrode layers 12A has a plurality of first through holes 12Ah formed therein for inserting the second via conductors 13B therethrough.

[0024] Each of the second internal electrode layers 12B is integrally formed within the same layer (see FIG. 5). The second internal electrode layer 12B has substantially the same rectangular outer shape as the first internal electrode layer 12A when viewed from the stacking direction DS. Each of the second internal electrode layers 12B has a plurality of second through holes 12Bh formed therein for inserting the plurality of first via conductors 13A therethrough.

[0025] The material of the first internal electrode layer 12A and the second internal electrode layer 12B is arbitrary, and contains, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals, as a main component. In this embodiment, the first internal electrode layer 12A and the second internal electrode layer 12B contain Ni or an alloy containing Ni as a main component.

[0026] It is known that hydrogen easily diffuses in Ni or an alloy containing Ni. Therefore, in this embodiment, hydrogen can easily diffuse in the first internal electrode layer 12A and the second internal electrode layer 12B. Note that when "hydrogen" is mentioned in the description of this embodiment, "hydrogen" may include any of the states of hydrogen atoms, hydrogen ions, and hydrogen molecules. Furthermore, the hydrogen element constituting these may be any isotope.

[0027] The first internal electrode layers 12A and the second internal electrode layers 12B may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layers 11. In this case, the ratio of the common material contained in the first internal electrode layers 12A and the second internal electrode layers 12B is, for example, 20 vol % or less.

[0028] The thickness of each of the first internal electrode layers 12A and the second internal electrode layers 12B is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode layers 12A and the second internal electrode layers 12B is arbitrary, but can be, for example, about 10 layers or more and 150 layers or less in total.

[0029] Each of the plurality of first via conductors 13A is electrically connected to at least one of the plurality of first internal electrode layers 12A. In this embodiment, each of the plurality of first via conductors 13A is electrically connected to each of the plurality of first internal electrode layers 12A.

[0030] The multiple first via conductors 13A extend from the inside of the capacitor body 10 to the first main surface 101. The multiple first via conductors 13A extend along the stacking direction DS. The multiple first via conductors 13A are not exposed from the second main surface 102. The multiple first via conductors 13A pass through second through holes 12Bh formed in each of the multiple second internal electrode layers 12B. Therefore, the multiple first via conductors 13A are insulated from the multiple second internal electrode layers 12B.

[0031] Each of the plurality of second via conductors 13B is electrically connected to at least one of the plurality of second internal electrode layers 12B. In the present embodiment, each of the plurality of second via conductors 13B is electrically connected to each of the plurality of second internal electrode layers 12B.

[0032] The multiple second via conductors 13B extend from the inside of the capacitor body 10 to the first main surface 101. The multiple second via conductors 13B extend along the stacking direction DS. The second via conductors 13B are not exposed from the second main surface 102. The multiple second via conductors 13B pass through second through holes 12Bh formed in each of the multiple first internal electrode layers 12A. Therefore, the multiple second via conductors 13B are insulated from the multiple first internal electrode layers 12A.

[0033] The first and second via conductors 13A and 13B may have any shape, such as a cylindrical shape. In this case, the diameter of each of the first and second via conductors 13A and 13B is, for example, about 20 μm to 150 μm. The distance between adjacent first and second via conductors 13A and 13B, more specifically, the distance between the center of each first and second via conductor 13A and 13B, is, for example, about 50 μm to 500 μm.

[0034] The first via conductor 13A and the second via conductor 13B may be made of any material, such as a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals. In this embodiment, the first via conductor 13A and the second via conductor 13B contain Ni or an alloy containing Ni as a main component. Therefore, in this embodiment, hydrogen can easily diffuse in the first via conductor 13A and the second via conductor 13B.

[0035] The first via conductor 13A and the second via conductor 13B may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 11. In this case, the proportion of the common material contained in the first via conductor 13A and the second via conductor 13B is, for example, 20 vol % or less.

[0036] 1 and 3 , each of the multiple first external electrodes 20A includes a base electrode layer 21 and a plating layer 22. In this embodiment, each of the multiple first external electrodes 20A has a base electrode layer 21 having a similar configuration and a plating layer 22 having a similar configuration, corresponding to each of the multiple first via conductors 13A. Furthermore, each of the multiple second external electrodes 20B corresponding to each of the multiple second via conductors 13B also has a similar configuration to the first external electrode 20A corresponding to the first via conductor 13A. However, at least one of the multiple first external electrodes 20A may include the base electrode layer 21 and plating layer 22 described below.

[0037] The base electrode layer 21 is provided on a portion of a corresponding first via conductor 13A on the first principal surface 101. The base electrode layer 21 is provided on the first via conductor 13A and the first outer layer portion 111 so that at least a portion of a boundary 132 between the first via conductor 13A and the first outer layer portion 111 on the first principal surface 101 is not exposed to the outside. More specifically, the base electrode layer 21 is provided on the first via conductor 13A and the first outer layer portion 111 so that the entire boundary 132 is not exposed to the outside. As a result, the base electrode layer 21 has a cylindrical outer shape extending in the stacking direction DS. The base electrode layer 21 surrounds a surface 131 of the first via conductor 13A on the first principal surface 101 where the base electrode layer 21 is not provided.

[0038] It is preferable that the material constituting the base electrode layer 21 does not melt when the plating layer 22 is melted during the mounting of the multilayer ceramic capacitor 1. For this reason, the base electrode layer 21 is preferably made of a material having a higher melting point than the plating layer 22. In this embodiment, the base electrode layer 21 contains, as a main component, nickel (Ni) or an alloy containing Ni, or copper (Cu) or an alloy containing Cu.

[0039] The base electrode layer 21 may be a base plating layer or a baked electrode layer. In this embodiment, when the base electrode layer 21 is a base plating layer, the base electrode layer 21 contains Ni or Cu as a main component. When the base electrode layer 21 is a baked electrode layer, the base electrode layer 21 may contain a ceramic material. The ceramic material may be vitreous (amorphous). Methods for providing these base electrode layers 21 will be described later.

[0040] The thickness of the base electrode layer 21 in the stacking direction DS is not particularly limited. The thickness of the base electrode layer 21 may be 1 μm or more and 10 μm or less. The overall dimension of the base electrode layer 21 of the first external electrode 20A in the stacking direction DS can be adjusted by the thickness of the base electrode layer 21. The larger the overall dimension of the base electrode layer 21 of the first external electrode 20A in the stacking direction DS, the more firmly the multilayer ceramic capacitor 1 can be connected to an electronic component such as a semiconductor package component. This is because, when mounting the multilayer ceramic capacitor 1 on an electronic component, it becomes easier to inject an underfill resin between the first main surface 101 and the electronic component.

[0041] The plating layer 22 is provided on the base electrode layer 21 so that a surface 131 of the first via conductor 13A on which the base electrode layer 21 is not provided is exposed to the outside on the first main surface 101. In this embodiment, the plating layer 22 is provided on a surface of the base electrode layer 21 facing the stacking direction DS. The plating layer 22 has a cylindrical outer shape extending in the stacking direction DS. When viewed from the stacking direction DS, the plating layer 22 is arranged to surround the surface 131.

[0042] In the present embodiment, the plating layer 22 is not in contact with the first main surface 101. However, the plating layer 22 may be in contact with the first main surface 101 as long as at least a portion of the surface 131 is exposed to the outside. Specifically, the plating layer 22 may be in contact with the first outer layer portion 111, the first via conductor 13A, or both.

[0043] Furthermore, the plating layer 22 is provided only on the surface of the base electrode layer 21 facing the stacking direction DS. However, the plating layer 22 may also be provided on the side surface of the base electrode layer 21 facing a direction perpendicular to the stacking direction DS, as long as at least a portion of the surface 131 is exposed to the outside. The plating layer 22 may also be provided on the outer peripheral side surface or inner peripheral side surface of the cylindrical base electrode layer 21, or on both of these. Furthermore, the plating layer 22 may be provided to cover the entire base electrode layer 21 so that the base electrode layer 21 is not exposed to the outside.

[0044] The plating layer 22 includes at least an outermost plating layer 221. The outermost plating layer 221 is the outermost layer of the first external electrode 20A. In the present embodiment, the plating layer 22 is composed only of the outermost plating layer 221. The plating layer 22 may further include one or more base plating layers located between the outermost plating layer 221 and the base electrode layer 21.

[0045] The multilayer ceramic capacitor 1 can preferably be mounted to an electronic component by reflow soldering or heat bonding using flux. From this perspective, in this embodiment, the outermost plating layer 221 contains tin (Sn), which has a relatively low melting point. Specifically, the outermost plating layer 221 contains Sn or an alloy containing Sn as its main component. Examples of alloys containing Sn include Sn-Ag alloys and Sn-Bi alloys. The material constituting the undercoat plating layer is not particularly limited, but examples include Cu, Ni, and Au.

[0046] Next, a method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention will be described. Fig. 6 is a flow chart showing the method for manufacturing the multilayer ceramic capacitor according to the first embodiment.

[0047] 6, the method for manufacturing the multilayer ceramic capacitor according to the first embodiment includes a step S1 of preparing a capacitor body, a step S2 of providing a base electrode layer, a step S3 of forming a plating layer, and a step S4 of heating the capacitor body. Note that, although steps S1 and S2 may be performed simultaneously in parallel, steps S1 and S2, S3, and S4 are performed in this order.

[0048] First, in the capacitor body preparation step S1, the capacitor body 10 is prepared (see FIGS. 1 to 5). The specific method for preparing the capacitor body 10 is not particularly limited. In step S1 of this embodiment, a laminate is formed by stacking a plurality of ceramic green sheets corresponding to a plurality of dielectric layers 11 and conductive paste layers corresponding to a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B in a predetermined pattern. A plurality of through holes penetrating the laminate in the stacking direction are formed by laser irradiation. These through holes are then filled with conductive paste. As a result, a plurality of columnar conductive pastes corresponding to a plurality of first via conductors 13A and a plurality of second via conductors 13B of the capacitor body 10 are provided in the laminate. Furthermore, an outer layer ceramic green sheet corresponding to at least a portion of the second outer layer portion 112 is further stacked on the laminate so as to cover one side of the columnar conductive pastes. As a result, the columnar conductive pastes are not exposed on one surface (the surface corresponding to the second main surface 102) of the laminate.

[0049] The laminate having the plurality of columns of conductive paste and the outer ceramic green sheets is then fired to form the capacitor body 10.

[0050] In step S2 of providing a base electrode layer, a base electrode layer 21 is provided on each of the plurality of first via conductors 13A and the plurality of second via conductors 13B on first main surface 101 (see FIGS. 1 to 5).

[0051] When providing a base plating layer as base electrode layer 21, for example, a plating resist is used. For at least each of first via conductor 13A and second via conductor 13B, a plating resist is formed on at least surface 131 (see FIG. 3 ) by a patterning method. Then, with the plating resist formed, a base plating layer (base electrode layer 21) is provided for each of first via conductor 13A and second via conductor 13B by electrolytic plating or the like. After providing the base plating layer (base electrode layer 21), the plating resist is removed.

[0052] When a fired electrode layer is provided as base electrode layer 21, a conductive paste surface layer corresponding to the fired electrode layer (base electrode layer 21) is provided on first main surface 101 of capacitor body 10 so as to cover first via conductors 13A, and then fired to form the fired electrode layer (base electrode layer 21). The conductive paste surface layer may be provided on the laminate before firing capacitor body 10. In this case, firing of the laminate and firing of the conductive paste surface layer can be performed simultaneously.

[0053] In the step S3 of forming a plating layer, a plating layer 22 is formed on each of the base electrode layers 21 (see FIGS. 1 to 5).

[0054] 7 is a cross-sectional view schematically illustrating the step of forming a plating layer in embodiment 1. As shown in FIG. 7 , in step S3 of forming a plating layer, a plating resist 1000 is formed on at least the surface 131 by a patterning method. In this embodiment, the plating resist 1000 is provided so as to cover the side surfaces of each base electrode layer 21 that face in a direction perpendicular to the stacking direction DS. The plating resist may also be provided so as to cover the entire first main surface 101. Then, with the plating resist formed, a plating layer 22 is provided on the base electrode layer 21 using an electrolytic plating method or the like. After the plating layer 22 is provided, the plating resist 1000 is removed.

[0055] In step S4 of heating the capacitor body, after forming the plating layer 22, the capacitor body 10, the first external electrode 20A, and the second external electrode 20B are heated to diffuse the hydrogen contained in the plurality of dielectric layers 11 through the first via conductors 13A and remove it from the first main surface 101 to the outside. At this time, the capacitor body 10 is heated in a temperature range lower than the melting point of the material constituting the plating layer 22. In this embodiment, because the outermost plating layer 221 contains Sn, the capacitor body 10 is heated in a temperature range of approximately 230°C or lower. The lower limit of this temperature range is not particularly limited, but is preferably 100°C or higher, at which point moisture can also be evaporated.

[0056] Here, the diffusion path of hydrogen when hydrogen enters from the outside and then escapes again to the outside through the first main surface 101 during the manufacture of the multilayer ceramic capacitor 1 according to this embodiment will be described.

[0057] First, during the formation of the plating layer 22 and the underplating layer, hydrogen is generated as a side reaction of the plating. This hydrogen penetrates into the first via conductors 13A and the second via conductors 13B from the first main surface 101. In this embodiment, the first via conductors 13A, the second via conductors 13B, the first internal electrode layers 12A, and the second internal electrode layers 12B contain Ni or a Ni-containing alloy as a main component, so hydrogen easily diffuses within these components. Furthermore, the first via conductors 13A, the second via conductors 13B, the first internal electrode layers 12A, and the second internal electrode layers 12B occlude hydrogen. Hydrogen further diffuses from the first via conductors 13A, the second via conductors 13B, the first internal electrode layers 12A, and the second internal electrode layers 12B into the dielectric layer 11. Hydrogen in the dielectric layer 11 can cause a decrease in the insulation resistance of the multilayer ceramic capacitor 1.

[0058] The hydrogen diffused in the dielectric layer 11 attempts to escape to the outside again through the first via conductor 13A and the second via conductor 13B, which contain Ni or a Ni-containing alloy as a main component. In this embodiment, the outermost plating layer 221 of the plating layer 22 inhibits the release of hydrogen to the outside. This is because the plating layer 22 contains Sn in this embodiment. Sn is less permeable to hydrogen than Cu and Ni. The crystal structures of Cu and Ni are face-centered cubic, whereas the crystal structure of Sn is a hexagonal close-packed structure. Furthermore, when the base electrode layer 21 is copper (Cu) or an alloy containing Cu, the release of hydrogen to the outside is further inhibited. This is because Cu is less permeable to hydrogen than Ni. The smaller the heat of dissolution of hydrogen in a metal, the greater the solubility of hydrogen in the metal. The heats of dissolution of hydrogen in Cu and Ni are +42 kJ / mol and +16 kJ / mol, respectively.

[0059] However, in this embodiment, the surface 131 of the first via conductor 13A (and the second via conductor 13B) is exposed to the outside on the first main surface 101. Hydrogen easily diffuses inside Ni or an alloy containing Ni. This allows hydrogen to diffuse through the first via conductor 13A (and the second via conductor 13B), which contains Ni or an alloy containing Ni as its main component, and then escape to the outside again through this surface 131. Therefore, in this embodiment, the above-mentioned heating step S4 promotes the diffusion of the first via conductor 13A and the second via conductor 13B, thereby enabling hydrogen to be more efficiently extracted to the outside.

[0060] As described above, the multilayer ceramic capacitor 1 according to the first embodiment of the present invention includes a capacitor body 10 and a first external electrode 20A. The capacitor body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 12A, a plurality of second internal electrode layers 12B, and a first via conductor 13A. The first internal electrode layers 12A and the second internal electrode layers 12B are alternately stacked in the stacking direction DS, with a plurality of dielectric layers 11 sandwiched between each other. The first via conductor 13A is electrically connected to the plurality of first internal electrode layers 12A. The first via conductor 13A extends from the interior of the capacitor body 10 to a first main surface 101, which is one surface of the capacitor body 10 in the stacking direction DS. The first external electrode 20A includes a base electrode layer 21 and a plating layer 22. The base electrode layer 21 is provided on the first main surface 101 in a portion of the first via conductor 13A. The plating layer 22 is provided on the base electrode layer 21 so that the surface 131 of the first via conductor 13A on which the base electrode layer 21 is not provided is exposed to the outside on the first main surface 101 .

[0061] According to the above configuration, hydrogen that diffuses through first via conductor 13A and enters dielectric layer 11 during the formation of plating layer 22 diffuses through first via conductor 13A again to reach first main surface 101. The hydrogen can then easily escape from surface 131 of first via conductor 13A that is exposed to the outside. Therefore, in multilayer ceramic capacitor 1 having first via conductor 13A, a decrease in insulation resistance due to hydrogen in dielectric layer 11 can be suppressed.

[0062] Furthermore, in this embodiment, the plurality of dielectric layers 11 include a first outer layer portion 111 that forms the first principal surface 101. The base electrode layer 21 is provided on the first via conductor 13A and the first outer layer portion 111 so that at least a portion of a boundary 132 between the first via conductor 13A and the first outer layer portion 111 on the first principal surface 101 is not exposed to the outside.

[0063] The above configuration can prevent moisture from penetrating through the boundary into the inside of the capacitor body 10. This can prevent a decrease in the insulation resistance of the multilayer ceramic capacitor 1 due to moisture in the capacitor body 10.

[0064] Furthermore, in this embodiment, the base electrode layer 21 is provided on the first via conductor 13A and the first outer layer portion 111 so that the entire boundary 132 is not exposed to the outside. This configuration further prevents moisture from penetrating into the capacitor body 10 through the boundary.

[0065] Furthermore, in the present embodiment, the base electrode layer 21 may contain nickel (Ni). Hydrogen diffuses relatively easily in Ni. Therefore, with this configuration, hydrogen that diffuses through the first via conductor 13A and reaches the first main surface 101 can further diffuse through the base electrode layer 21 and easily escape to the outside.

[0066] Furthermore, in this embodiment, the base electrode layer 21 may contain copper (Cu). When the thickness of the base electrode layer 21 in the stacking direction DS is relatively thin, hydrogen diffuses relatively easily in the Cu of the base electrode layer 21. Therefore, according to the above configuration, hydrogen that diffuses through the first via conductor 13A and reaches the first main surface 101 can further diffuse through the base electrode layer 21 and easily escape to the outside. Furthermore, when the thickness of the base electrode layer 21 in the stacking direction DS is relatively thick, the overall dimension of the first external electrode 20A in the stacking direction DS also increases. This makes it easier to inject an underfill resin between the first main surface 101 and the electronic component when mounting the multilayer ceramic capacitor 1 on the electronic component by joining the first external electrode 20A to the electronic component. Note that when the thickness of the base electrode layer 21 in the stacking direction DS is relatively thick, hydrogen diffuses less easily in the Cu of the base electrode layer 21. However, as described above, hydrogen can easily escape from surface 131 of first via conductor 13A that is exposed to the outside.

[0067] Furthermore, in this embodiment, the base electrode layer 21 may contain a ceramic material. This configuration can improve adhesion between the base electrode layer 21 and the first outer layer portion 111, further preventing moisture from penetrating into the capacitor body 10 through the boundary 132. However, this configuration prevents hydrogen from escaping through the boundary 132. However, as described above, hydrogen can easily escape from the surface 131 of the first via conductor 13A that is exposed to the outside.

[0068] Furthermore, in this embodiment, the plating layer 22 includes an outermost plating layer 221 that is the outermost layer of the first external electrode 20A and contains tin (Sn).

[0069] According to the above configuration, the multilayer ceramic capacitor 1 can be easily mounted by melting the outermost plating layer 221 containing Sn and performing reflow soldering. Hydrogen is relatively difficult to diffuse into Sn. However, as described above, hydrogen can easily escape from the exposed surface 131 of the first via conductor 13A.

[0070] Furthermore, in this embodiment, the plurality of dielectric layers 11 include a second outer layer portion 112 that forms the entire second main surface 102, which is the surface on the other side in the stacking direction DS of the capacitor body 10.

[0071] According to the above configuration, the first via conductor 13A is not exposed on the second main surface 102. This prevents moisture from penetrating into the capacitor body 10 from the boundary between the second outer layer portion 112 and the first via conductor 13A on the second main surface 102. However, this configuration prevents hydrogen from escaping from the second main surface 102. However, as described above, hydrogen can easily escape from the surface 131 of the first via conductor 13A that is exposed to the outside.

[0072] The method for manufacturing the multilayer ceramic capacitor according to the first embodiment includes a capacitor body 10 including a plurality of dielectric layers 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, and a first via conductor 13A, wherein the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B are alternately stacked in a stacking direction DS with a plurality of dielectric layers 11 sandwiched between each other, and the first via conductor 13A is electrically connected to the plurality of first internal electrode layers 12A and extends from the inside of the capacitor body 10 to a first main surface 101 which is a surface on one side of the capacitor body 10 in the stacking direction DS. The method includes preparing a capacitor body (10) (S1), providing a base electrode layer (21) on a part of a first via conductor (13A) on a first main surface (101) (S2), forming a plating layer (22) on the base electrode layer (21) so that a surface (131) of the first via conductor (13A) on the first main surface (101) where the base electrode layer (21) is not provided is exposed to the outside, and after forming the plating layer (22) (S3), heating the capacitor body (10) to diffuse hydrogen contained in the plurality of dielectric layers (11) through the first via conductor (13A) and extract it to the outside from the first main surface (101) (S4).

[0073] According to the above configuration, hydrogen that diffuses through first via conductors 13A and enters dielectric layer 11 during formation of plating layer 22 (S3) diffuses to first main surface 101 via first via conductors 13A due to the heating (S4). Then, hydrogen can be easily released to the outside from first main surface 101. Therefore, in multilayer ceramic capacitor 1 having first via conductors 13A, a decrease in insulation resistance due to hydrogen in dielectric layer 11 can be suppressed.

[0074] Furthermore, in this embodiment, when the capacitor body 10 is heated after the plating layer 22 is formed (S4), the heating is performed in a temperature range lower than the melting point of the material that constitutes the plating layer 22.

[0075] According to the above configuration, it is possible to prevent the outer shape of the plating layer 22 from being changed by the heating, and therefore it is possible to prevent the mounting performance of the multilayer ceramic capacitor 1 from being deteriorated.

[0076] (Embodiment 2) Next, a multilayer ceramic capacitor according to embodiment 2 of the present invention will be described. The multilayer ceramic capacitor according to embodiment 2 partially differs from multilayer ceramic capacitor 1 according to embodiment 1 of the present invention in the configuration of the second main surface side. Therefore, the description of the configuration and effects similar to those of multilayer ceramic capacitor 1 according to embodiment 1 will not be repeated.

[0077] Fig. 8 is a plan view showing the multilayer ceramic capacitor according to embodiment 2 from the second main surface side, and Fig. 9 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 8 as viewed in the direction of the arrows IX-IX.

[0078] 8 and 9 , in the multilayer ceramic capacitor 1a according to the second preferred embodiment of the present invention, the capacitor body 10a further includes another first external electrode 20Ca. The first via conductor 13Aa extends from inside the capacitor body 10a to the second main surface 102, which is the other surface of the capacitor body 10a in the stacking direction DS. The other first external electrode 20Ca is provided in the first via conductor 13Aa on the second main surface 102.

[0079] According to the above configuration, other electronic components can also be connected to the second main surface 102 of the multilayer ceramic capacitor 1a. In this embodiment, the other first external electrode 20Ca is exemplified as the other external electrode of the present invention. The second via conductor 13Ba also extends from inside the capacitor body 10a to the second main surface 102, which is the other surface of the capacitor body 10a in the stacking direction DS. The other second external electrode 20Da is provided in the second via conductor 13Ba on the second main surface 102.

[0080] Furthermore, in this embodiment, the other first external electrodes 20Ca are provided on the second main surface 102 so that the first via conductors 13Aa are not exposed to the outside.

[0081] According to the above configuration, the other first external electrode 20Ca can be easily provided. Note that, for example, if the base electrode layer 21a of the other first external electrode 20Ca contains a metal other than Ni as a main component and hydrogen diffusion in the base electrode layer 21a is not easy, the above configuration will prevent hydrogen from escaping from the second main surface 102. However, even in this embodiment, hydrogen can easily escape from the surface 131 of the first via conductor 13Aa that is exposed to the outside on the first main surface 101 side. Furthermore, the other second external electrode 20Da is also provided on the second main surface 102 so that the second via conductor 13Ba is not exposed to the outside.

[0082] The multilayer ceramic capacitor 1a according to this embodiment includes a plurality of other first external electrodes 20Ca and a plurality of other second external electrodes 20Da. The plurality of other first external electrodes 20Ca include base electrode layers 21a and plating layers 22a having similar configurations, corresponding to the plurality of first via conductors 13Aa, respectively. Furthermore, the plurality of other second external electrodes 20Da corresponding to the plurality of second via conductors 13Ba also have the same configuration as the other first external electrode 20Ca corresponding to the first via conductor 13Aa. However, the configurations of these external electrodes may be different from each other. When the base electrode layer 21a of each of the plurality of other first external electrodes 20Ca and the plurality of other second external electrodes 20Da contains Ni, hydrogen can easily escape from the side surfaces of the base electrode layer 21a.

[0083] In the multilayer ceramic capacitor 1a of this embodiment, the base electrode layer 21a of the plurality of other first external electrodes 20Ca and the plurality of other second external electrodes 20Da can be provided by a method substantially similar to the method of providing the base electrode layer 21 on the first main surface 101 in the step S2 of providing the base electrode layer. Here, when the base electrode layer 21a is a base plating layer, it is not necessarily necessary to form a plating resist on the second main surface 102.

[0084] Next, a multilayer ceramic capacitor according to a third embodiment of the present invention will be described. The multilayer ceramic capacitor according to the third embodiment is partially different from the multilayer ceramic capacitor 1a according to the second embodiment of the present invention, mainly in the configuration of the other external electrodes. Therefore, the description of the same configuration and effects as those of the multilayer ceramic capacitor 1a according to the second embodiment will not be repeated.

[0085] Fig. 10 is a plan view showing the multilayer ceramic capacitor according to embodiment 3 from the second main surface side, and Fig. 11 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 10 as viewed in the direction of the arrows XI-XI.

[0086] As shown in Figures 10 and 11, in the multilayer ceramic capacitor 1b according to the third embodiment of the present invention, the other first external electrode 20Cb is provided on the second main surface 102 so that the first via conductor 13Ab is exposed to the outside.

[0087] According to the above configuration, hydrogen can easily escape from the surfaces 133b of the first via conductors 13Ab that are exposed to the outside on the second main surface 102. Note that the other second external electrodes 20Db are also provided on the second main surface 102 so that the second via conductors 13Bb are exposed to the outside.

[0088] In the present embodiment, the base electrode layer 21b and the plating layer 22b in each of the plurality of other first external electrodes 20Cb and the plurality of other second external electrodes 20Db arranged on the second main surface 102 side have the same configuration as the base electrode layer 21 and the plating layer 22 arranged on the first main surface 101 side. However, the configurations of these external electrodes may be different from each other.

[0089] (Embodiment 4) Next, a multilayer ceramic capacitor according to embodiment 4 of the present invention and a method for manufacturing the same will be described. The multilayer ceramic capacitor according to embodiment 4 is partially different from the multilayer ceramic capacitor 1 according to embodiment 1 of the present invention, mainly in the configuration of the external electrodes. Therefore, the description of the configuration and effects similar to those of the multilayer ceramic capacitor 1 according to embodiment 1 and the method for manufacturing the same will not be repeated.

[0090] Fig. 12 is a plan view showing the multilayer ceramic capacitor according to embodiment 4 from the first main surface side, and Fig. 13 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 12 as viewed in the direction of the arrows along line XIII-XIII.

[0091] 12 and 13 , in the multilayer ceramic capacitor 1c according to the fourth embodiment of the present invention, the base electrode layer 21c is provided on the first main surface 101 so as to prevent the first via conductors 13Ac from being exposed to the outside. The plating layer 22c is provided on the base electrode layer 21c so that at least a part of the portion 211c of the base electrode layer 21c that is aligned with the first via conductors 13Ac in the stacking direction DS is exposed to the outside in the stacking direction DS.

[0092] According to the above configuration, hydrogen that diffuses through the first via conductors 13Ac and enters the dielectric layer 11 during the formation of the plating layer 22c diffuses again in the first via conductors 13Ac and the base electrode layer 21c in the stacking direction DS and quickly reaches the surface 212c of the base electrode layer 21c that faces the stacking direction DS and is exposed to the outside. The hydrogen can then easily escape from the surface 212c. Therefore, in a multilayer ceramic capacitor 1 having the first via conductors 13Ac, a decrease in insulation resistance due to hydrogen in the dielectric layer 11 can be suppressed. Note that, when viewed from the stacking direction DS, the plating layer 22c is disposed so as to surround the surface 212c. In this embodiment, the side surfaces of the base electrode layer 21c are also exposed to the outside. This allows hydrogen to escape from the side surfaces of the base electrode layer 21c as well. Because hydrogen necessarily passes through the base electrode layer 21c when escaping to the outside, the base electrode layer 21c preferably contains Ni, which allows hydrogen to easily diffuse.

[0093] Furthermore, in this embodiment, at least a portion of the plating layer 22c is aligned with the first via conductor 13Ac in the stacking direction DS. This configuration prevents the conductive path from the first via conductor 13Ac to the plating layer 22c from becoming too long. More specifically, the plating layer 22c is positioned so as to cover a boundary 132 between the first via conductor 13Ac and the first outer layer portion 111 on the first main surface 101 (see FIG. 12 ).

[0094] Furthermore, in this embodiment, the base electrode layer 21c is provided on the first via conductor 13Ac and the first outer layer portion 111 so that the entire boundary 132 between the first via conductor 13Ac and the first outer layer portion 111 on the first main surface 101 is not exposed to the outside.

[0095] The above configuration can prevent moisture from entering the inside of the capacitor body 10 through the boundary 132. This can prevent a decrease in the insulation resistance of the multilayer ceramic capacitor 1 due to moisture in the capacitor body 10.

[0096] In this embodiment, each of the plurality of first external electrodes 20Ac has a base electrode layer 21c and a plating layer 22c having a similar configuration to each of the plurality of first via conductors 13Ac. Furthermore, each of the plurality of second external electrodes 20Bc corresponding to each of the plurality of second via conductors 13Bc also has a similar configuration to the first external electrode 20Ac corresponding to the first via conductor 13Ac.

[0097] Next, a method for manufacturing a multilayer ceramic capacitor according to a fourth embodiment of the present invention will be described. FIG. 14 is a flow chart showing the method for manufacturing the multilayer ceramic capacitor according to the fourth embodiment. As shown in FIGS. 12 to 14 , the method for manufacturing the multilayer ceramic capacitor according to the fourth embodiment includes providing a base electrode layer 21c on the first main surface 101 so as to prevent the first via conductors 13Ac from being exposed to the outside (S2c), forming a plating layer 22c on the base electrode layer 21c so that at least a portion of the portion 211c of the base electrode layer 21c aligned with the first via conductors 13Ac in the stacking direction DS is exposed to the outside in the stacking direction DS (S3c), and, after forming the plating layer 22c (S3c), heating the capacitor body 10 to diffuse hydrogen contained in the plurality of dielectric layers 11 through the first via conductors 13Ac and the base electrode layer 21c in the stacking direction DS and extract it to the outside (S4c).

[0098] According to the above configuration, hydrogen that diffuses through the first via conductors 13Ac and enters the dielectric layer 11 during the formation of the plating layer 22c (S3c) diffuses through the first via conductors 13Ac and the base electrode layer 21c in the stacking direction DS by the heating (S4c), and quickly diffuses to the surface of the base electrode layer 21c facing the stacking direction DS. The hydrogen can then be easily released from that surface to the outside. Therefore, in a multilayer ceramic capacitor having the first via conductors 13Ac, a decrease in insulation resistance due to hydrogen in the dielectric layer 11 can be suppressed.

[0099] Furthermore, in step S2c of providing a base electrode layer in this embodiment, when a base plating layer is provided as base electrode layer 21c, there is no need to use a plating resist, because first via conductors 13Ac do not need to be exposed to the outside.

[0100] 15 is a cross-sectional view schematically showing a step of forming a plating layer in embodiment 4. As shown in Fig. 15, in step S3c of forming a plating layer, a plating resist 1000c is formed on at least the surface 212c by a patterning method.

[0101] (Additional Note) As described above, the present embodiment includes the following disclosures.

[0102] <1> A multilayer ceramic capacitor comprising: a capacitor body; and external electrodes, wherein the capacitor body includes: a plurality of dielectric layers; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the plurality of dielectric layers sandwiched therebetween; and via conductors electrically connected to the plurality of first internal electrode layers and extending from inside the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the external electrodes include: a base electrode layer provided on the first main surface on a portion of the via conductor; and a plating layer provided on the base electrode layer so that surfaces of the via conductors on the first main surface not provided with the base electrode layer are exposed to the outside.

[0103] <2> The multilayer ceramic capacitor according to <1>, wherein the plurality of dielectric layers include a first outer layer portion that forms the first main surface, and the base electrode layer is provided on the via conductor and the first outer layer portion such that at least a portion of a boundary between the via conductor and the first outer layer portion on the first main surface is not exposed to the outside.

[0104] <3> The multilayer ceramic capacitor according to <2>, wherein the base electrode layer is provided on the via conductor and the first outer layer portion so that the entire boundary is not exposed to the outside.

[0105] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the base electrode layer contains nickel (Ni).

[0106] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the plating layer is an outermost layer of the external electrode and includes an outermost plating layer containing tin (Sn).

[0107] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the plurality of dielectric layers include a second outer layer portion that forms an entire second main surface, which is the other surface of the capacitor body in the stacking direction.

[0108] <7> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the capacitor body further includes another external electrode, the via conductor extends from inside the capacitor body to a second main surface which is the other surface of the capacitor body in the stacking direction, and the other external electrode is provided on the via conductor on the second main surface.

[0109] <8> The multilayer ceramic capacitor according to <7>, wherein the other external electrodes are provided on the second main surface so that the via conductors are not exposed to the outside.

[0110] <9> The multilayer ceramic capacitor according to <7>, wherein the other external electrode is provided on the second main surface so that the via conductor is exposed to the outside.

[0111] <10> A multilayer ceramic capacitor comprising: a capacitor body; and an external electrode, wherein the capacitor body comprises: a plurality of dielectric layers; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the plurality of dielectric layers sandwiched therebetween; and via conductors electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the external electrode comprises: a base electrode layer provided on the first main surface so as to prevent the via conductors from being exposed to the outside; and a plating layer provided on the base electrode layer so that at least a portion of a portion of the base electrode layer aligned with the via conductor in the stacking direction is exposed to the outside in the stacking direction.

[0112] <11> The multilayer ceramic capacitor according to <10>, wherein at least a portion of the plating layer is provided so as to be aligned with the via conductor in the stacking direction.

[0113] <12> The multilayer ceramic capacitor according to <10> or <11>, wherein the plurality of dielectric layers include a first outer layer portion that forms the first main surface, and the base electrode layer is provided on the via conductor and the first outer layer portion such that the entire boundary between the via conductor and the first outer layer portion on the first main surface is not exposed to the outside.

[0114] <13> A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and via conductors, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductors are electrically connected to the plurality of first internal electrode layers and extend from the inside of the capacitor body to a first main surface that is one surface of the capacitor body in the stacking direction; providing a base electrode layer on a portion of the via conductors on the first main surface; forming a plating layer on the base electrode layer so that surfaces of the via conductors on the first main surface that are not provided with the base electrode layer are exposed to the outside; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductors and extract it to the outside through the first main surface.

[0115] <14> The method for producing a multilayer ceramic capacitor according to <13>, wherein when the capacitor body is heated after forming the plating layer, the heating is performed in a temperature range lower than the melting point of a material constituting the plating layer.

[0116] <15> A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and via conductors, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductors are electrically connected to the plurality of first internal electrode layers and extend from the inside of the capacitor body to a first main surface that is one surface of the capacitor body in the stacking direction; providing a base electrode layer on the first main surface so that the via conductors are not exposed to the outside; forming a plating layer on the base electrode layer so that at least a part of a portion of the base electrode layer that is aligned with the via conductors in the stacking direction is exposed to the outside in the stacking direction; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductors and the base electrode layer in the stacking direction and extract it to the outside.

[0117] In the above description of the embodiments, combinable configurations may be combined with each other. The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0118] REFERENCE SIGNS LIST 1, 1a, 1b, 1c Multilayer ceramic capacitor, 10, 10a Capacitor body, 101 First main surface, 102 Second main surface, 103 Peripheral side surface, 11 Dielectric layer, 111 First outer layer portion, 112 Second outer layer portion, 12A First internal electrode layer, 12Ah First through hole, 12B Second internal electrode layer, 12Bh Second through hole, 13A, 13Aa, 13Ab, 13Ac First via conductor, 13B, 13Ba, 13Bb, 13Bc Second via conductor, 20A, 20Ac First external electrode, 20B, 20Bc Second external electrode, 20Ca, 20Cb Other first external electrodes, 20Da, 20Db Other second external electrodes, 21, 21a, 21b, 21c Base electrode layer, 22, 22a, 22b, 22c Plating layer, 221 outermost plating layer, 1000, 1000c plating resist.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body; and an external electrode, wherein the capacitor body includes: a plurality of dielectric layers; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the plurality of dielectric layers in between; and via conductors electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the external electrode includes: a base electrode layer provided on a portion of the via conductor on the first main surface; and a plating layer provided on the base electrode layer so that a surface of the via conductor on the first main surface not provided with the base electrode layer is exposed to the outside.

2. The multilayer ceramic capacitor according to claim 1, wherein the plurality of dielectric layers include a first outer layer portion forming the first principal surface, and the base electrode layer is provided on the via conductor and the first outer layer portion such that at least a portion of the boundary between the via conductor and the first outer layer portion on the first principal surface is not exposed to the outside.

3. The multilayer ceramic capacitor according to claim 2, wherein the base electrode layer is provided on the via conductor and the first outer layer portion such that the entire boundary is not exposed to the outside.

4. The multilayer ceramic capacitor according to claim 1, wherein the base electrode layer contains nickel (Ni).

5. A multilayer ceramic capacitor according to claim 1, wherein the plating layer includes an outermost plating layer which is the outermost layer of the external electrode and contains tin (Sn).

6. A multilayer ceramic capacitor as claimed in any one of claims 1 to 5, wherein the plurality of dielectric layers includes a second outer layer portion that forms the entirety of a second main surface, which is the other surface of the capacitor body in the stacking direction.

7. A multilayer ceramic capacitor as claimed in any one of claims 1 to 5, wherein the capacitor body further comprises another external electrode, the via conductor extends from inside the capacitor body to a second main surface which is the other surface of the capacitor body in the stacking direction, and the other external electrode is provided on the via conductor on the second main surface.

8. The multilayer ceramic capacitor according to claim 7, wherein the other external electrode is provided on the second main surface so as to prevent the via conductor from being exposed to the outside.

9. The multilayer ceramic capacitor according to claim 7, wherein the other external electrode is provided on the second main surface so that the via conductor is exposed to the outside.

10. A multilayer ceramic capacitor comprising: a capacitor body; and an external electrode, wherein the capacitor body comprises: a plurality of dielectric layers; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the plurality of dielectric layers sandwiched therebetween; and via conductors electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the external electrode comprises: a base electrode layer provided on the first main surface so as to prevent the via conductors from being exposed to the outside; and a plating layer provided on the base electrode layer so that at least a portion of the portion of the base electrode layer which is aligned with the via conductors in the stacking direction is exposed to the outside in the stacking direction.

11. The multilayer ceramic capacitor according to claim 10, wherein at least a portion of the plating layer is arranged to be aligned with the via conductor in the stacking direction.

12. A multilayer ceramic capacitor as described in claim 10 or claim 11, wherein the plurality of dielectric layers include a first outer layer portion forming the first main surface, and the base electrode layer is provided on the via conductor and the first outer layer portion such that the entire boundary between the via conductor and the first outer layer portion on the first main surface is not exposed to the outside.

13. A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and a via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductor is electrically connected to the plurality of first internal electrode layers and extends from inside the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; providing a base electrode layer on a portion of the via conductor on the first main surface; forming a plating layer on the base electrode layer so that a surface of the via conductor on the first main surface not provided with the base electrode layer is exposed to the outside; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductor and extract it to the outside from the first main surface.

14. The method for producing a multilayer ceramic capacitor according to claim 13, wherein when the capacitor body is heated after the plating layer is formed, the heating is performed in a temperature range lower than the melting point of the material that constitutes the plating layer.

15. A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a plurality of dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers, and a via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the plurality of dielectric layers sandwiched therebetween, and the via conductor is electrically connected to the plurality of first internal electrode layers and extends from inside the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; providing a base electrode layer on the first main surface so that the via conductor is not exposed to the outside; forming a plating layer on the base electrode layer so that at least a portion of a portion of the base electrode layer aligned with the via conductor in the stacking direction is exposed to the outside in the stacking direction; and after forming the plating layer, heating the capacitor body to diffuse hydrogen contained in the plurality of dielectric layers through the via conductors and the base electrode layer in the stacking direction and to remove it to the outside.

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