Abnormal voltage protection circuit, signal transmission device comprising abnormal voltage protection circuit, electronic equipment comprising signal transmission device, and vehicle comprising electronic equipment

Abstract

An abnormal voltage protection circuit 502 comprises voltage-current conversion circuits 507, 511, a current-voltage conversion circuit, and abnormal voltage detection circuits C3, C4. The voltage-current conversion circuits 507, 511 are configured to convert a monitored voltage VEE2 that is negative with respect to a reference voltage into current signals I1, I3. The current-voltage conversion circuit is configured to convert the current signals I1, I3 into voltage signals V7, V11 that are positive with respect to the reference voltage. The abnormal voltage detection circuits C3, C4 are configured to compare the voltage signals V7, V11 with threshold voltages V8, V12 to detect whether the monitored voltage VEE2 is equal to or higher than an upper-limit voltage V8, or equal to or lower than a lower-limit voltage V12.

Description

Abnormal voltage protection circuit, signal transmission device equipped with this abnormal voltage protection circuit, electronic device equipped with this signal transmission device, and vehicle equipped with this electronic device

[0001] The invention disclosed in this specification relates to an abnormal voltage protection circuit, a signal transmission device including this abnormal voltage protection circuit, an electronic device including this signal transmission device, and a vehicle including this electronic device.

[0002] Conventionally, signal transmission devices that transmit pulse signals while isolating input and output have been used in various applications (such as power supplies or motor drive devices). Such signal transmission devices may be equipped with an abnormal voltage protection circuit that monitors the power supply voltage and protects each circuit within the signal transmission device in the event of an abnormal state (overvoltage state or undervoltage state).

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2022-071390

[0005] [Summary] The abnormal voltage protection circuit disclosed in Patent Document 1 leaves room for further consideration regarding its protection function for a monitored voltage that is negative relative to a reference voltage.

[0006] The abnormal voltage protection circuit disclosed in this specification includes a voltage-current conversion circuit, a current-voltage conversion circuit, and an abnormal voltage detection circuit. The voltage-current conversion circuit is configured to convert a monitored voltage that is negative with respect to a reference voltage into a current signal. The current-voltage conversion circuit is configured to convert the current signal into a voltage signal that is positive with respect to the reference voltage. The abnormal voltage detection circuit is configured to compare the voltage signal with a threshold voltage to detect whether the monitored voltage is above an upper limit voltage or below a lower limit voltage.

[0007] The signal transmission device disclosed in this specification includes a first chip, a second chip, and a third chip. The third chip is configured to transmit signals while isolating the first chip from the second chip. The second chip is configured by integrating circuit elements including the abnormal voltage protection circuit configured as described above. The third chip transmits the detection result detected by the abnormal voltage detection circuit from the second chip to the first chip.

[0008] The electronic device disclosed in this specification includes a plurality of gate driver ICs and a control circuit. The plurality of gate driver ICs drive a plurality of switch elements, each of which is a power transistor, and the gates of each of the switch elements. The control circuit controls the plurality of gate driver ICs. At least one of the plurality of gate driver ICs is a signal transmission circuit having the above-described configuration. The first chip inputs an output signal to the control circuit via an output terminal and receives an input signal from the control circuit via an input terminal.

[0009] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is a diagram showing an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example layout of a transformer chip. FIG. 10 is a diagram showing the basic configuration of an electronic device incorporating a signal transmission device of the present disclosure. FIG. 11 is a diagram showing the internal configuration of a first overvoltage protection circuit. FIG. 12 is a diagram showing the internal configuration of a first undervoltage lockout circuit. FIG. 13 is a diagram showing the internal configuration of a second overvoltage lockout circuit. FIG. 14 is a diagram showing the internal configuration of a second undervoltage lockout circuit. FIG. 15 is a diagram showing the configuration of a second overvoltage protection circuit including a transistor. FIG. 16 is a block diagram illustrating an example implementation of the signal transmission device of the present disclosure.

[0010] [Detailed Description] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0022] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0026] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer Chip (Two-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0033] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0087] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0091] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0092] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0135] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel device including a plurality of transformers 21. However, a first functional device 45 that is a single-channel device including a single transformer 21 may also be employed.

[0137] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <Considerations on Abnormal Voltage Protection Function> The signal transmission device 200 as described above has an abnormal voltage protection circuit for the positive power supply voltage (the above-mentioned power supply voltage VCC2) of the secondary circuit system 200s. The abnormal voltage protection circuit includes an overvoltage protection circuit and an undervoltage lockout circuit.

[0156] An overvoltage protection circuit is a circuit that protects circuits that receive power from a positive power supply by stopping the supply of power from the positive power supply voltage when the monitored positive power supply voltage exceeds a predetermined upper limit. An undervoltage malfunction suppression circuit is a circuit that prevents circuits that receive power from the positive power supply from malfunctioning by stopping the supply of power from the positive power supply voltage when the monitored positive power supply voltage drops below a predetermined lower limit.

[0157] The above-described overvoltage protection circuit includes an overvoltage detection circuit that detects an overvoltage state. The above-described undervoltage malfunction prevention circuit includes an undervoltage detection circuit that detects an undervoltage state. Each of the overvoltage detection circuit and the undervoltage detection circuit compares the upper limit or the lower limit with the voltage value of the positive power supply voltage to be monitored, thereby detecting the overvoltage state or the undervoltage state, respectively.

[0158] Incidentally, some signal transmission devices 200 as described above are configured to receive power from a positive power supply voltage (a voltage that is positive relative to a reference voltage) and a negative power supply voltage (a voltage that is negative relative to the reference voltage). The reference voltage may be, for example, a ground voltage. In such a configuration, the abnormal voltage protection circuit as described above is installed to monitor the positive power supply voltage. Therefore, the upper and lower limit values ​​described above are both positive voltage values ​​relative to the reference voltage. This makes it relatively easy to generate the upper and lower limit voltages used in the overvoltage detection circuit and the undervoltage detection circuit, respectively.

[0159] On the other hand, when an abnormal voltage protection circuit is installed that monitors a negative power supply voltage, the upper and lower limits are both negative voltages relative to the reference voltage. This means that negative voltages must be generated as the upper and lower limits. This can complicate the circuit configuration of the abnormal voltage protection circuit.

[0160] To address these issues, the abnormal voltage protection circuit 502 of the present disclosure can be installed in the signal transmission device 200 described above, with the negative power supply voltage as the monitored voltage. Furthermore, the abnormal voltage protection circuit 502 is capable of detecting whether the monitored voltage is in an abnormal state (an overvoltage state exceeding an upper limit or an undervoltage state below a lower limit) with a relatively simple configuration. This prevents the circuit configuration from becoming too complicated. The abnormal voltage protection circuit 502 according to an embodiment of the present disclosure will be described in detail below. The following description will be given taking as examples a signal transmission device 200 equipped with the abnormal voltage protection circuit 502 and an electronic device 400 equipped with this signal transmission device 200.

[0161] 10 is a diagram showing the basic configuration of an electronic device 400 equipped with a signal transmission device 200 according to the present disclosure. The electronic device 400 of this configuration example is a type of motor drive device that converts DC power supplied from an in-vehicle battery (not shown) into AC power to drive a motor M (see FIG. 16 described below).

[0162] As shown in FIG. 10, the electronic device 400 includes a signal transmission device 200, an ECU (electronic control unit) 2, and a plurality of discrete components (a switch element SW, diodes D1 and D2, and resistors R1 and R2).

[0163] The signal transmission device 200 is a semiconductor integrated circuit device configured to transmit a gate drive signal from a primary circuit system (VCC1-GND1) to a secondary circuit system (VCC2-VEE2) while isolating the primary circuit system from the secondary circuit system.

[0164] The signal transmission device 200 has a plurality of external terminals (in this figure, a VCC1 terminal, an IN terminal, a VCC2 terminal, an OUT terminal, and first detection signal output terminal T1 to fourth detection signal output terminal T4) as means for establishing electrical connection with the outside of the device.

[0165] The VCC1 terminal is a power supply terminal for the primary circuit system. The primary circuit system receives power from a voltage source E1 via the VCC1 terminal. The VCC2 terminal is a power supply terminal for the secondary circuit system. The secondary circuit system receives power from a voltage source E2 via the VCC2 terminal.

[0166] The IN terminal is a control input terminal. The IN terminal receives an input signal IN from the ECU 2. The ECU 2 is a means for comprehensively controlling the motor drive device and the vehicle in which the motor drive device is installed. The ECU 2 drives the input signal IN by switching between a high level (based on VCC1) and a low level (based on GND1).

[0167] The OUT terminal is an output terminal that outputs a drive signal Ga for driving the switch element SW. The OUT terminal is connected to the gate terminal of the switch element SW via resistors R1 and R2 and diodes D1 and D2.

[0168] A high level (VCC2 reference) or low level (VEE2 reference) drive signal Ga is output from the OUT terminal.

[0169] The switch element SW is preferably a power semiconductor element capable of operating at high frequencies, such as an IGBT, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a SiC-MOSFET (Silicon Carbide-Metal Oxide Semiconductor FET), a SiC-SIT (SiC-Static Induction Transistor), or a GaN-MOSFET (Gallium Nitride-MOSFET). As shown in FIG. 10 , the electronic device 400 uses an IGBT as the switch element SW.

[0170] The gate signal Vge input to the gate terminal of the switch element SW changes in response to the drive signal Ga. That is, the signal transmission device 200 controls the drive of the switch element SW using the drive signal Ga.

[0171] Specifically, when the gate signal Vge is at a high level (exceeding the threshold voltage of the switch element SW), the switch element SW is turned on, and when the gate signal Vge is at a low level (not exceeding the threshold voltage of the switch element SW), the switch element SW is turned off.

[0172] The collector of the switch element SW is connected to a node n1, and the emitter of the switch element SW is connected to a node n2. Specific examples of the nodes n1 and n2 will be described later.

[0173] <Internal Configuration of Signal Transmission Device 200> Next, a detailed description will be given of the internal configuration of signal transmission device 200. Signal transmission device 200 is configured by sealing a first semiconductor chip 410, a second semiconductor chip 420, and a third semiconductor chip 430 in a single package.

[0174] The first semiconductor chip 410 corresponds to the aforementioned primary circuit system 200p. The first semiconductor chip 410 is a controller chip on which a controller having the function of generating each signal is integrated. The first semiconductor chip 410 is driven by receiving a power supply voltage VCC1 from a voltage source E1. The first semiconductor chip 410 generates a first internal signal S1 and a second internal signal S2 based on an input signal IN.

[0175] The second semiconductor chip 420 corresponds to the aforementioned secondary circuit system 200s. The second semiconductor chip 420 is a driver chip on which a driver for controlling the drive of the switch element SW is integrated. The second semiconductor chip 420 is driven by receiving a power supply voltage VCC2 from a voltage source E2. The second semiconductor chip 420 receives input of a first internal signal S1 and a second internal signal S2 from the first semiconductor chip 410 via a third semiconductor chip 430. The second semiconductor chip 420 generates a drive signal Ga based on the first internal signal S1 and the second internal signal S2.

[0176] The third semiconductor chip 430 is a transformer chip on which multiple transformers (in accordance with FIG. 10 , a first transformer 431, a second transformer 432, a third transformer 433, a fourth transformer 434, a fifth transformer 435, and a sixth transformer 436) are integrated. The third semiconductor chip 430 transmits the first internal signal S1 and the second internal signal S2 while providing DC insulation between the first semiconductor chip 410 and the second semiconductor chip 420.

[0177] The first semiconductor chip 410 includes a logic circuit 415 , a first transmission circuit 411 , and a second transmission circuit 412 .

[0178] The logic circuit 415 receives an input signal IN input from the ECU 2, generates a first internal signal S1 and a second internal signal S2, and inputs them to the first transmission circuit 411 and the second transmission circuit 412, respectively.

[0179] The first transmitting circuit 411 transmits the first internal signal S1 input from the logic circuit 415 to the first receiving circuit 421 via the first transformer 431 .

[0180] The second transmitting circuit 412 transmits the second internal signal S2 input from the logic circuit 415 to the second receiving circuit 422 via the second transformer 432 .

[0181] The second semiconductor chip 420 includes a first receiving circuit 421 , a second receiving circuit 422 , a logic circuit 425 , a driver circuit 424 , and an output circuit 501 .

[0182] The first receiving circuit 421 receives the first internal signal S1 from the first transmitting circuit 411 via the first transformer 431 and inputs the signal S1 to the logic circuit 425 .

[0183] The second receiving circuit 422 receives the second internal signal S2 from the second transmitting circuit 412 via the second transformer 432 and inputs the signal S2 to the logic circuit 425 .

[0184] The logic circuit 425 generates a driver control signal S3 based on the input first internal signal S1 and second internal signal S2, and inputs the driver control signal S3 to the driver circuit 424.

[0185] The driver circuit 424 generates the drive signals Gb and Gc based on the input driver control signal S3. The driver circuit 424 controls the output circuit 501 by the drive signals Gb and Gc.

[0186] The output circuit 501 includes a transistor P1 and a transistor N1. The transistor P1 is a P-channel MOSFET. The transistor N1 is an N-channel MOSFET.

[0187] The source of transistor P1 is connected to the VCC2 terminal. The drains of transistors P1 and N1 are both connected to the OUT terminal. The source of transistor N1 is connected to the VEE2 connection terminal. The gates of transistors P1 and N1 are connected to the driver circuit 424.

[0188] A drive signal Gb is input to the gate terminal of transistor P1. The on / off state of transistor P1 is controlled by the drive signal Gb. A drive signal Gc is input to the gate terminal of transistor N1. The on / off state of transistor N1 is controlled by the drive signal Gc. A high-level (VCC2 reference) or low-level (VEE2 reference) drive signal Ga is output from the OUT terminal depending on the on / off state of transistors P1 and N1.

[0189] Next, the basic operation of the signal transmission device 200 will be described. Assume that a high-level input signal IN is input to the IN terminal from the ECU 2. In response, the logic circuit 415 generates a pulse in the first internal signal S1. Specifically, the logic circuit 415 detects a positive edge (a rising edge from low level to high level) of the input signal IN and generates a pulse in the first internal signal S1.

[0190] Conversely, suppose that a low-level input signal IN is input to the IN terminal from the ECU 2. In response, the logic circuit 415 generates a pulse in the second internal signal S2. Specifically, the logic circuit 415 detects a negative edge (a falling edge from high level to low level) of the input signal IN and generates a pulse in the second internal signal S2.

[0191] When the logic circuit 425 receives a pulse of the first internal signal S1, it raises the driver control signal S3 to a high level. Conversely, when the logic circuit 425 receives a pulse of the second internal signal S2, it lowers the driver control signal S3 to a low level.

[0192] When the driver circuit 424 receives a high-level driver control signal S3, it causes the drive signal Gb to fall to a low level and the drive signal Gc to fall to a low level, turning on the transistor P1 and turning off the transistor N1. As a result, a high-level (VCC2 reference) drive signal Ga is output from the OUT terminal.

[0193] Conversely, when the driver circuit 424 receives a low-level driver control signal S3, it raises the drive signal Gb to a high level and also raises the drive signal Gc to a high level. This turns off the transistor P1 and turns on the transistor N1. Therefore, a low-level (VEE2 reference) drive signal Ga is output from the OUT terminal.

[0194] <Regarding the Abnormal Voltage Protection Circuit 502> Next, the configuration of the abnormal voltage protection circuit 502 will be described.

[0195] In addition to the above-described configuration, the second semiconductor chip 420 includes an abnormal voltage protection circuit 502 , a third transmission circuit 426 , a fourth transmission circuit 427 , a fifth transmission circuit 428 , and a sixth transmission circuit 429 .

[0196] The abnormal voltage protection circuit 502 includes a first overvoltage protection circuit 503 , a first undervoltage lockout circuit 504 , a second overvoltage protection circuit 505 , and a second undervoltage lockout circuit 506 .

[0197] The first overvoltage protection circuit 503 monitors the positive power supply voltage VCC2, detects whether the positive power supply voltage VCC2 is in an overvoltage state, and generates a detection signal S4 according to the detection result. The first overvoltage protection circuit 503 inputs the detection signal S4 to the third transmission circuit 426.

[0198] The first undervoltage lockout circuit 504 monitors the positive power supply voltage VCC2, detects whether the positive power supply voltage VCC2 is in an undervoltage state, and generates a detection signal S5 according to the detection result. The first undervoltage lockout circuit 504 inputs the detection signal S5 to the fourth transmission circuit 427. The detailed configurations of the first overvoltage protection circuit 503 and the first undervoltage lockout circuit 504 will be described later.

[0199] The second overvoltage protection circuit 505 monitors the negative power supply voltage VEE2, detects whether the negative power supply voltage VEE2 is in an overvoltage state, and generates a detection signal S6 according to the detection result. The second overvoltage protection circuit 505 inputs the detection signal S6 to the fifth transmission circuit 428.

[0200] The second undervoltage lockout circuit 506 monitors the negative power supply voltage VEE2, detects whether the negative power supply voltage VEE2 is in a low voltage state, and generates a detection signal S7 according to the detection result. The second undervoltage lockout circuit 506 inputs the detection signal S7 to the sixth transmission circuit 429. Detailed configurations of the second overvoltage protection circuit 505 and the second undervoltage lockout circuit 506 will be described later.

[0201] The third transmission circuit 426 inputs the detection signal S4 to the third semiconductor chip 430 (more specifically, the third transformer 433 described later). The fourth transmission circuit 427 inputs the detection signal S5 to the third semiconductor chip 430 (more specifically, the fourth transformer 434 described later). The fifth transmission circuit 428 inputs the detection signal S6 to the third semiconductor chip 430 (more specifically, the fifth transformer 435 described later). The sixth transmission circuit 429 inputs the detection signal S7 to the third semiconductor chip 430 (more specifically, the sixth transformer 436 described later).

[0202] In addition to the above-described configuration, the third semiconductor chip 430 includes a third transformer 433 , a fourth transformer 434 , a fifth transformer 435 , and a sixth transformer 436 .

[0203] The third transformer 433 transmits the input detection signal S4 to the first semiconductor chip 410 (more specifically, to a third receiving circuit 416 described later). The fourth transformer 434 transmits the input detection signal S5 to the first semiconductor chip 410 (more specifically, to a fourth receiving circuit 417 described later). The fifth transformer 435 transmits the input detection signal S6 to the first semiconductor chip 410 (more specifically, to a fifth receiving circuit 418 described later). The sixth transformer 436 transmits the input detection signal S7 to the first semiconductor chip 410 (more specifically, to a sixth receiving circuit 419 described later).

[0204] In addition to the above-described configuration, the first semiconductor chip 410 includes a third receiving circuit 416 , a fourth receiving circuit 417 , a fifth receiving circuit 418 , and a sixth receiving circuit 419 .

[0205] The third receiving circuit 416 receives the detection signal S4 from the third transformer 433. The third receiving circuit 416 outputs the received detection signal S4 to the outside via the first detection signal output terminal T1. The fourth receiving circuit 417 receives the detection signal S5 from the fourth transformer 434. The fourth receiving circuit 417 outputs the received detection signal S5 to the outside via the second detection signal output terminal T2. The fifth receiving circuit 418 receives the detection signal S6 from the fifth transformer 435. The fifth receiving circuit 418 outputs the received detection signal S6 to the outside via the third detection signal output terminal T3. The sixth receiving circuit 419 receives the detection signal S7 from the sixth transformer 436. The sixth receiving circuit 419 outputs the received detection signal S7 to the outside via the fourth detection signal output terminal T4.

[0206] The ECU 2 is connected to the first detection signal output terminal T1 to the fourth detection signal output terminal T4. The ECU 2 receives the detection signals S4 to S7 output from the first detection signal output terminal T1 to the fourth detection signal output terminal T4. The ECU 2 controls the signal transmission device 200 in accordance with the signal levels of the received detection signals S4 to S7.

[0207] <Operation of Abnormal Voltage Protection Circuit 502> Next, the operation of the abnormal voltage protection circuit 502 will be specifically described.

[0208] When the first overvoltage protection circuit 503 detects an overvoltage state of the positive power supply voltage VCC2, it raises the detection signal S4 to a high level. Conversely, when the first overvoltage protection circuit 503 does not detect an overvoltage state of the positive power supply voltage VCC2, it sets the detection signal S4 to a low level.

[0209] As described above, the ECU 2 receives the detection signal S4 via the third transmitting circuit 426, the third transformer 433, and the third receiving circuit 416. When the received detection signal S4 is at a high level (when the positive power supply voltage VCC2 is in an overvoltage state), the ECU 2 inputs a control signal to the IN terminal so as to turn off both of the transistors P1 and N1.

[0210] When the first VIN lockout circuit 504 detects an undervoltage state of the positive power supply voltage VCC2, it raises the detection signal S5 to a high level. Conversely, when the first VIN lockout circuit 504 does not detect an undervoltage state of the positive power supply voltage VCC2, it sets the detection signal S5 to a low level.

[0211] As described above, the ECU 2 receives the detection signal S5 via the fourth transmitting circuit 427, the fourth transformer 434, and the fourth receiving circuit 417. When the received detection signal S5 is at a high level (when the positive power supply voltage VCC2 is in a low voltage state), the ECU 2 inputs a control signal to the IN terminal so as to turn off both of the transistors P1 and N1.

[0212] When the second overvoltage protection circuit 505 detects an overvoltage state of the negative power supply voltage VEE2, it raises the detection signal S6 to a high level. Conversely, when the second overvoltage protection circuit 505 does not detect an overvoltage state of the negative power supply voltage VEE2, it sets the detection signal S6 to a low level.

[0213] As described above, the ECU 2 receives the detection signal S6 via the fifth transmitting circuit 428, the fifth transformer 435, and the fifth receiving circuit 418. When the received detection signal S6 is at a high level (when the negative power supply voltage VEE2 is in an overvoltage state), the ECU 2 inputs a control signal to the IN terminal so as to turn off both of the transistors P1 and N1.

[0214] When the second VIN lockout circuit 506 detects a low voltage state of the negative power supply voltage VEE2, it raises the detection signal S7 to a high level. Conversely, when the second VIN lockout circuit 506 does not detect a low voltage state of the negative power supply voltage VEE2, it sets the detection signal S7 to a low level.

[0215] As described above, the ECU 2 receives the detection signal S7 via the sixth transmitting circuit 429, the sixth transformer 436, and the sixth receiving circuit 419. When the received detection signal S7 is at a high level (when the negative power supply voltage VEE2 is in a low voltage state), the ECU 2 inputs a control signal to the IN terminal so as to turn off both of the transistors P1 and N1.

[0216] On the other hand, when all of the received detection signals S4 to S7 are at a low level, the ECU 2 inputs a control signal to the IN terminal so that the transistors P1 and N1 are driven normally.

[0217] <More detailed configuration of abnormal voltage protection circuit 502> Next, a more detailed configuration of the abnormal voltage protection circuit 502 (specifically, the first overvoltage protection circuit 503, the first undervoltage malfunction prevention circuit 504, the second overvoltage protection circuit 505, and the second undervoltage malfunction prevention circuit 506) will be described.

[0218] 11 is a diagram showing the internal configuration of the first overvoltage protection circuit 503. The first overvoltage protection circuit 503 includes resistors R3 and R4 and a first overvoltage detection circuit C1.

[0219] A first terminal of the resistor R3 is connected to the application terminal of the positive power supply voltage VCC2. A second terminal of the resistor R3 and a first terminal of the resistor R4 are connected to the non-inverting input terminal (+) of the first overvoltage detection circuit C1. A second terminal of the resistor R4 is connected to the ground terminal GND2.

[0220] A divided voltage V2, obtained by dividing a positive power supply voltage VCC2 by resistors R3 and R4, is input to the non-inverting input terminal (+) of the first overvoltage detection circuit C1. A first upper limit voltage V1 is input to the inverting input terminal (-) of the first overvoltage detection circuit C1. A constant voltage Vreg is input to the first overvoltage detection circuit C1 as a high-side drive power supply. A ground voltage GND2 is also input to the first overvoltage detection circuit C1 as a low-side drive power supply.

[0221] The first overvoltage detection circuit C1 compares the voltages input to its non-inverting input terminal (+) and inverting input terminal (-) and generates a detection signal S4 at either a high level or a low level depending on the comparison result. Specifically, when the divided voltage V2 is equal to or greater than the first upper limit voltage V1, the first overvoltage detection circuit C1 outputs a high level detection signal S4. Conversely, when the divided voltage V2 is less than the first upper limit voltage V1, the first overvoltage detection circuit C1 outputs a low level detection signal S4.

[0222] 12 is a diagram showing the internal configuration of the first undervoltage lockout circuit 504. The first undervoltage lockout circuit 504 includes resistors R5 and R6 and a first undervoltage detection circuit C2.

[0223] A first terminal of the resistor R5 is connected to the terminal to which the positive power supply voltage VCC2 is applied. A second terminal of the resistor R5 and a first terminal of the resistor R6 are connected to the inverting input terminal (-) of the first low voltage detection circuit C2. A second terminal of the resistor R6 is connected to the ground terminal GND2.

[0224] A first lower limit voltage V3 is input to the non-inverting input terminal (+) of the first low-voltage detection circuit C2. A divided voltage V4 obtained by dividing the positive power supply voltage VCC2 by resistors R5 and R6 is input to the inverting input terminal (-) of the first low-voltage detection circuit C2. A constant voltage Vreg is input to the first low-voltage detection circuit C2 as a high-side drive power supply. A ground voltage GND2 is also input to the first low-voltage detection circuit C2 as a low-side drive power supply.

[0225] The first low-voltage detection circuit C2 compares the voltages input to its non-inverting input terminal (+) and inverting input terminal (-) and generates a high-level or low-level detection signal S5 depending on the comparison result. Specifically, when the first lower limit voltage V3 is equal to or greater than the divided voltage V4 (in other words, when the divided voltage V4 is less than the first lower limit voltage V3), the first low-voltage detection circuit C2 outputs a high-level detection signal S5. Conversely, when the first lower limit voltage V3 is less than the divided voltage V4 (in other words, when the divided voltage V4 is equal to or greater than the first lower limit voltage V3), the first low-voltage detection circuit C2 outputs a low-level detection signal S5.

[0226] 13 is a diagram showing the internal configuration of the second overvoltage protection circuit 505. The second overvoltage protection circuit 505 includes a first voltage-current conversion circuit 507, a first current-voltage conversion circuit 508, and a second overvoltage detection circuit C3 (abnormal voltage detection circuit).

[0227] The first voltage-current converter circuit 507 converts the voltage of the negative power supply voltage VEE2 to be monitored into a current signal (current I1, which will be described later).

[0228] The first voltage-current conversion circuit 507 includes resistors R7, R8, and R9, an operational amplifier OP1, and a transistor N2.

[0229] A first terminal of the resistor R7 is connected to the ground terminal GND2. A second terminal of the resistor R7, together with a first terminal of a resistor R8, is connected to the first input terminal of the operational amplifier OP1. A second terminal of the resistor R8 is connected to the application terminal of the negative power supply voltage VEE2.

[0230] The transistor N2 is an N-channel MOSFET. The gate of the transistor N2 is connected to the output terminal of the operational amplifier OP1. The source of the transistor N2 is connected to the first terminal of the resistor R9 and the second input terminal of the operational amplifier OP1. The drain of the transistor N2 is connected to the application terminal of the first current-voltage conversion circuit 508 (more specifically, to the drain, gate, and gate of the transistor P2 and P3, which will be described later).

[0231] The second terminal of the resistor R9 is connected to the application terminal of the negative power supply voltage VEE2. The voltage of the connection node between the first terminal of the resistor R9 and the second input terminal of the operational amplifier OP1 is defined as a node voltage V6.

[0232] A divided voltage V5 is input to a first input terminal of the operational amplifier OP1. The divided voltage V5 is a voltage obtained by dividing the ground voltage GND2 and the negative power supply voltage VEE2 by resistors R7 and R8. A node voltage V6 is input to a second input terminal of the operational amplifier OP1 as a feedback input.

[0233] The operational amplifier OP1 inputs an output voltage corresponding to the difference between the input voltage at the first input terminal (specifically, the divided voltage V5) and the input voltage at the second input terminal (specifically, the node voltage V6) to the gate of the transistor N2. The voltage across the resistor R9 (= the node voltage V6) varies according to the gate voltage of the transistor N2 (= the output voltage of the operational amplifier OP1). More specifically, the operational amplifier OP1 controls the driving of the transistor N2 by the feedback input of the node voltage V6 so that the divided voltage V5 and the node voltage V6 coincide. As a result, a current I1 corresponding to the negative power supply voltage VEE2 and the resistance value of the resistor R9 is generated. The current I1 is input as a current signal to the first current-voltage conversion circuit 508.

[0234] The first current-voltage conversion circuit 508 converts an input current signal (current I1 in this diagram) into a voltage signal (node ​​voltage V7, described later). Specifically, the first current-voltage conversion circuit 508 includes a current mirror circuit 510 and a resistor R10.

[0235] The current mirror circuit 510 generates a mirror current (current I2 in this diagram) that mirrors an input current (current I1 in this diagram).

[0236] The current mirror circuit 510 includes transistors P2 and P3. The transistors P2 and P3 are P-channel MOSFETs. The gates of the transistors P2 and P3, together with the drain of the transistor P2, are connected to the drain of the transistor N2. The source of the transistor P2, together with the source of the transistor P3, is connected to the application terminal of the positive power supply voltage VCC2. The drain of the transistor P3, together with the first terminal of the resistor R10, is connected to the non-inverting input terminal (+) of the second overvoltage detection circuit C3.

[0237] The second terminal of the resistor R10 is connected to the ground terminal GND2. The voltage at the connection node between the first terminal of the resistor R10 and the non-inverting input terminal (+) of the second overvoltage detection circuit C3 is defined as a node voltage V7. When a current I2 flows through the resistor R10, a voltage across the resistor R10 (=node voltage V7) is generated.

[0238] The node voltage V7 is input to the non-inverting input terminal (+) of the second overvoltage detection circuit C3. The second upper limit voltage V8 is input to the inverting input terminal (-) of the second overvoltage detection circuit C3. The constant voltage Vreg is input to the second overvoltage detection circuit C3 as a high-side drive power supply. The ground voltage GND2 is input to the second overvoltage detection circuit C3 as a low-side drive power supply.

[0239] The second overvoltage detection circuit C3 compares the voltages input to its non-inverting input terminal (+) and inverting input terminal (-) and outputs a detection signal S6 at either a high level or a low level depending on the comparison result. Specifically, when the node voltage V7 is equal to or greater than the second upper limit voltage V8, the second overvoltage detection circuit C3 outputs a high level detection signal S6. Conversely, when the node voltage V7 is less than the second upper limit voltage V8, the second overvoltage detection circuit C3 outputs a low level detection signal S6.

[0240] 14 is a diagram showing the internal configuration of the second undervoltage lockout circuit 506. The second undervoltage lockout circuit 506 includes a second voltage-current converter circuit 511, a second current-voltage converter circuit 512, and a second undervoltage detection circuit C4 (abnormal voltage detection circuit).

[0241] The second voltage-current converter circuit 511 converts the negative power supply voltage VEE2 to be monitored into a current signal (current I3, which will be described later).

[0242] The second voltage-current conversion circuit 511 includes resistors R11, R12, and R13, an operational amplifier OP2, and a transistor N3.

[0243] A first terminal of the resistor R11 is connected to the ground terminal GND2. A second terminal of the resistor R11 and a first terminal of the resistor R12 are connected to a first input terminal of the operational amplifier OP2. A second terminal of the resistor R12 is connected to an application terminal of the negative power supply voltage VEE2.

[0244] The transistor N3 is an N-channel MOSFET. The gate of the transistor N3 is connected to the output terminal of the operational amplifier OP2. The source of the transistor N3 is connected to the first terminal of the resistor R13 and the second input terminal of the operational amplifier OP2. The drain of the transistor N3 is connected to the application terminal of the second current-voltage conversion circuit 512 (more specifically, to the drain, gate, and gate of the transistor P4 and P5, which will be described later).

[0245] A second terminal of the resistor R13 is connected to a terminal to which a negative power supply voltage VEE2 is applied. The voltage of the connection node between the first terminal of the resistor R13 and the second input terminal of the operational amplifier OP2 is defined as a node voltage V10.

[0246] A divided voltage V9 is input to a first input terminal of the operational amplifier OP2. The divided voltage V9 is a voltage obtained by dividing the ground voltage GND2 and the negative power supply voltage VEE2 by resistors R11 and R12. A node voltage V10 is input to a second input terminal of the operational amplifier OP2 as a feedback input.

[0247] The operational amplifier OP2 inputs an output voltage corresponding to the difference between the input voltage at the first input terminal (specifically, the divided voltage V9) and the input voltage at the second input terminal (specifically, the node voltage V10) to the gate of the transistor N3. More specifically, the operational amplifier OP2 controls the drive of the transistor N2 by the feedback input of the node voltage V10 so that the divided voltage V9 and the node voltage V10 match. As a result, a current I3 corresponding to the negative power supply voltage VEE2 and the resistance value of the resistor R13 is generated. The current I3 is input as a current signal to the second current-voltage conversion circuit 512.

[0248] The second current-voltage conversion circuit 512 converts an input current signal (current I3 in this diagram) into a voltage signal (node ​​voltage V11, described later). Specifically, the second current-voltage conversion circuit 512 includes a current mirror circuit 513 and a resistor R14.

[0249] The current mirror circuit 513 generates a current I4 by mirroring an input current (current I3 in this figure). The specific configuration of the current mirror circuit 513 is as follows.

[0250] The current mirror circuit 513 includes transistors P4 and P5. The transistors P4 and P5 are P-channel MOSFETs. The gates of the transistors P4 and P5, together with the drain of the transistor P4, are connected to the drain of the transistor N3. The source of the transistor P4, together with the source of the transistor P5, is connected to the application terminal of the positive power supply voltage VCC2. The drain of the transistor P5, together with the first terminal of the resistor R14, is connected to the inverting input terminal (-) of the second low-voltage detection circuit C4.

[0251] The second terminal of the resistor R14 is connected to the ground terminal GND2. The voltage at the connection node between the first terminal of the resistor R14 and the inverting input terminal (-) of the second low voltage detection circuit C4 is defined as a node voltage V11. When a current I4 flows through the resistor R14, a voltage across the resistor R14 (=node voltage V11) is generated.

[0252] The second low-voltage detection circuit C4 receives the second lower limit voltage V12 at its non-inverting input terminal (+) and the node voltage V11 at its inverting input terminal (-). The second low-voltage detection circuit C4 receives the constant voltage Vreg as a high-side drive power supply and the ground voltage GND2 as a low-side drive power supply.

[0253] The second low-voltage detection circuit C4 compares the voltages input to its non-inverting input terminal (+) and inverting input terminal (-) and generates a high-level or low-level detection signal S5 depending on the comparison result. Specifically, when the second lower limit voltage V12 is equal to or greater than the node voltage V11 (in other words, when the node voltage V11 is less than the second lower limit voltage V12), the second low-voltage detection circuit C4 outputs a high-level detection signal S6. Conversely, when the second lower limit voltage V12 is less than the node voltage V11 (in other words, when the node voltage V11 is equal to or greater than the second lower limit voltage V12), the second low-voltage detection circuit C4 outputs a low-level detection signal S7.

[0254] As described above, the second overvoltage protection circuit 505 converts the negative power supply voltage VEE2, which is the voltage to be monitored, into a current I1, and then converts the current I1 into a node voltage V7. Then, by detecting whether the node voltage V7 exceeds the second upper limit voltage V8, it is possible to detect whether the negative power supply voltage VEE2 exceeds a predetermined threshold voltage.

[0255] Furthermore, the current I1 converted from the negative voltage power supply VEE2 by the first voltage-to-current converter circuit 507 has a positive current value. The node voltage V7 converted from the current I1 by the first current-to-voltage converter circuit 508 has a positive voltage value. Therefore, the second upper limit voltage V8, which is compared with the node voltage V7, has a positive value relative to the reference voltage. Because the second upper limit voltage V8 has a positive voltage value relative to the reference voltage, it is relatively easy to generate. Therefore, with a simple circuit configuration, it is possible to detect whether the negative power supply voltage VEE2 exceeds a predetermined threshold voltage.

[0256] Similarly, the second undervoltage lockout circuit 506 converts the negative power supply voltage VEE2, which is the voltage to be monitored, into a current I3, and then converts the current I3 into a node voltage V11. By detecting whether the node voltage V11 has reached the second lower limit voltage V12, it is possible to detect whether the negative power supply voltage VEE2 has reached a predetermined threshold voltage.

[0257] Furthermore, the current I3 converted from the negative voltage power supply VEE2 by the second voltage-to-current converter circuit 511 has a positive current value. The node voltage V11 converted from the current I3 by the second current-to-voltage converter circuit 512 has a positive voltage value. Therefore, the second lower limit voltage V12, which is compared with the node voltage V11, has a positive value with respect to the reference voltage. Because the second lower limit voltage V12 has a positive voltage value with respect to the reference voltage, it is relatively easy to generate. Therefore, with a simple circuit configuration, it is possible to detect whether the negative power supply voltage VEE2 has reached a predetermined threshold voltage.

[0258] <Regarding the Clamp Circuit> In addition to the configuration described above, each of the first current-voltage conversion circuit 508 and the second current-voltage conversion circuit 512 can be configured to include a transistor N4 (clamp circuit). This configuration will be described using FIG. 15 , taking as an example a case where the first current-voltage conversion circuit 508 includes the transistor N4.

[0259] 15 is a diagram showing the configuration of a second overvoltage protection circuit 505 including a transistor N4. As shown in FIG. 15, the drain of the transistor N4 is connected to the drain of the transistor P3. The source of the transistor N4, together with the first terminal of the resistor R10, is connected to the non-inverting input terminal (+) of the second overvoltage detection circuit C3. The gate of the transistor N4, together with the application terminal of the constant voltage Vreg, is connected to the positive power supply input terminal of the second overvoltage detection circuit C3.

[0260] Transistor N4 maintains node voltage V7 at or below constant voltage Vreg. More specifically, when node voltage V7 is less than constant voltage Vreg, transistor N4 turns on and sets node voltage V7 to a voltage value corresponding to the output voltage of operational amplifier OP1 (more specifically, the current value of current I2 and the resistance value of resistor R10). When the output voltage of operational amplifier OP1 is relatively large and the voltage value converted from the current value of current I2 and the resistance value of resistor R10 reaches the gate voltage of transistor N4 (=constant voltage Vreg), transistor N4 is driven and node voltage V7 is maintained (clamped) at the gate voltage of transistor N4 (=constant voltage Vreg).

[0261] Therefore, even if the current I1 output by the first voltage-current conversion circuit 507 is a relatively large current value, it is possible to prevent an excessive voltage from being applied to the non-inverting input terminal (+) of the second overvoltage detection circuit C3, thereby preventing damage to the second overvoltage detection circuit C3.

[0262] If the second current-voltage conversion circuit 512 includes a transistor, the transistor (not shown) is disposed between the current mirror circuit 513 and the first end of the resistor R14. Similar to the transistor N4 described above, this transistor maintains the node voltage V11 at or below the constant voltage Vreg. Therefore, even if the current I1 output by the second voltage-current conversion circuit 511 is relatively large, application of an excessive voltage to the non-inverting input terminal (+) of the second undervoltage detection circuit C4 can be prevented. This prevents damage to the second overvoltage detection circuit C3.

[0263] 16 is a block diagram showing an implementation example of the signal transmission device 200 of the present disclosure. An electronic device 400 equipped with the signal transmission device 200 of the present disclosure can be suitably used in an engine vehicle or an electric vehicle 450. The electronic device 400 can be suitably used as a motor drive device that controls the drive of a motor M mounted on the vehicle 450.

[0264] As shown in FIG. 16, the motor M is a three-phase motor that is rotated and driven in accordance with three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0265] The electronic device 400 includes three insulated gate drivers 1H (u / v / w), three insulated gate drivers 1L (u / v / w), three high-side switch elements SWH (u / v / w), three low-side switch elements SWL (u / v / w), an ECU 2, and a smoothing capacitor 600.

[0266] The insulated gate drivers 1H(u / v / w) drive the high-side switch elements SWH(u / v / w) by generating upper gate drive signals (corresponding to the aforementioned output signals OUT) in response to upper gate control signals (corresponding to the aforementioned input signals IN) input from the ECU 2 while insulating the ECU 2 from the high-side switch elements SWH(u / v / w).

[0267] The insulated gate drivers 1L (u / v / w) drive the low-side switch elements SWL (u / v / w) by generating a low-side gate drive signal in response to a low-side gate control signal input from the ECU 2 while insulating the ECU 2 from the low-side switch elements SWL (u / v / w).

[0268] The high-side switch elements SWH(u / v / w) are gate-driven by respective insulated gate drivers 1H(u / v / w), and are connected between a power system power supply terminal (= an application terminal of the first motor drive voltage VD1) and each phase input terminal of the motor M.

[0269] The low-side switch elements SWL(u / v / w) are gate-driven by respective insulated gate drivers 1L(u / v / w), and are connected between the input terminals of each phase of the motor M and the power system ground terminal (= the terminal to which the second motor drive voltage VD2 is applied).

[0270] In this figure, IGBTs are used as the high-side switch element SWH (u / v / w) and the low-side switch element SWL (u / v / w), but as mentioned above, SiC-MOSFETs or Si-MOSFETs can also be used instead of IGBTs.

[0271] The ECU 2 controls the rotational driving of the motor M by driving the high-side switch element SWH(u / v / w) and the low-side switch element SWL(u / v / w) via the insulated gate drivers 1H(u / v / w) and 1L(u / v / w), respectively. The ECU 2 also has a function of monitoring the FLT1 terminal and the FLT2 terminal of each of the insulated gate drivers 1H(u / v / w) and 1L(u / v / w) to perform various safety controls.

[0272] A smoothing capacitor 600 is provided to smooth the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2. The smoothing capacitor 600 stabilizes the DC voltage (= the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2) that fluctuates in accordance with fluctuations in the power consumption of the motor M.

[0273] Here, the insulated gate drivers 1H (u / v / w) and 1L (u / v / w) can each suitably use the aforementioned signal transmission device 200. For example, the insulated gate driver 1H and the insulated gate driver 1L for one of the three phases (for example, the U phase in accordance with this figure) can be the aforementioned signal transmission device 200.

[0274] When the aforementioned signal transmission device 200 is used as the insulated gate driver 1H(u / v / w), the switch SW in Fig. 10 becomes the high-side switch SWH(u / v / w) in Fig. 16. In this case, the node n1 shown in Fig. 10 can be considered to be the application terminal of the first motor drive voltage VD1 in Fig. 16. Furthermore, the node n2 shown in Fig. 10 can be considered to be the connection terminal with the motor M in Fig. 16.

[0275] Furthermore, when the aforementioned signal transmission device 200 is used as the insulated gate driver 1L (u / v / w), the switch SW in Fig. 10 becomes the low-side switch SWL (u / v / w) in Fig. 16. In this case, the node n1 shown in Fig. 10 can be considered to be the connection end with the motor M in Fig. 16. Furthermore, the node n2 shown in Fig. 10 can be considered to be the application end of the second motor drive voltage VD2 in Fig. 16.

[0276] <Modifications> The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, in the above-described embodiments, the first voltage-current conversion circuit 507 and the second voltage-current conversion circuit 511 are described as separate components with different reference numerals for convenience of explanation, but a common configuration can be adopted in which these are treated as the same component. Similarly, the first current-voltage conversion circuit 508 and the second current-voltage conversion circuit 512 are described as separate components with different reference numerals, but a common configuration can be adopted in which these are treated as the same component.

[0277] Similarly, the configuration for generating the divided voltage V2 using the resistors R3 and R4 and the configuration for generating the divided voltage V4 using the resistors R5 and R6 can be the same and common configuration.

[0278] In this implementation example, insulated gate bipolar transistors (IGBTs) are used as the switch element SW, the high-side switch element SWH(u / v / w)u, and the low-side switch element SWL(u / v / w), but the configuration of the half-bridge output stage is not limited to this, and MOS field-effect transistors using SiC semiconductors or MOS field-effect transistors using Si semiconductors may also be used.

[0279] <Additional Notes> The abnormal voltage protection circuit (502) disclosed in the specification is configured to include voltage-to-current conversion circuits (507, 511) configured to convert a monitored voltage (VEE2) that is negative with respect to a reference voltage into a current signal (I1, I3), a current-to-voltage conversion circuit configured to convert the current signal (I1, I3) into a voltage signal (V7, V11) that is positive with respect to the reference voltage, and abnormal voltage detection circuits (C3, C4) configured to compare the voltage signal (V7, V11) with threshold voltages (V8, V12) and detect whether the monitored voltage (VEE2) is equal to or greater than an upper limit voltage (V8) or equal to or less than a lower limit voltage (V12) (first configuration).

[0280] The abnormal voltage protection circuit (502) according to the first configuration may be configured so that the reference voltage is the ground voltage (GND2) (second configuration).

[0281] Furthermore, in the abnormal voltage protection circuit (502) according to the first or second configuration, the abnormal voltage detection circuit (C3, C4) includes a first terminal for inputting a voltage signal (V7, V11), a second terminal for inputting a threshold voltage (V8, V12), a third terminal for inputting a positive power supply voltage (Vreg) that is positive with respect to a reference voltage, and a fourth terminal for inputting the reference voltage, and is configured to operate in response to the input of the positive power supply voltage (Vreg) and the reference voltage and to output a detection signal (S6, S7) corresponding to the potential difference between the voltage signal (V7, V11) and the threshold voltage (V8, V12), and is configured to include a clamp circuit (N4) that maintains the voltage value of the voltage signal (V7, V11) input to the first terminal at or below the positive power supply voltage (Vreg) (third configuration).

[0282] The signal transmission device (200) disclosed in the specification comprises a first chip (410), a second chip (420), and a third chip (430) configured to transmit signals while isolating the first chip (410) and the second chip (420) from each other, the second chip (420) being configured by integrating circuit elements including an abnormal voltage protection circuit (502) described in any one of the first to third configurations, and the third chip (430) being configured to transmit the detection results detected by the abnormal voltage detection circuit (C3, C4) from the second chip (420) to the first chip (410) (fourth configuration).

[0283] Furthermore, in the signal transmission device (200) relating to the fourth configuration, the first chip (410) may be configured to have an input terminal (IN) that receives an input signal as an external input, and output terminals (T1 to T4) that output output signals (S4 to S7) corresponding to the detection results to the outside (fifth configuration).

[0284] The electronic device disclosed in the specification includes a plurality of switch elements, each of which is a power transistor, a plurality of gate driver ICs that drive the gates of the plurality of switch elements, and a control circuit that controls the plurality of gate driver ICs, at least one of which is a signal transmission device (200) according to the fifth configuration, and a first chip (410) that is configured to input output signals (S4 to S7) to the control circuit via output terminals (T1 to T4) and to receive input signals from the control circuit via an input terminal (IN) (sixth configuration).

[0285] The vehicle (450) disclosed in the specification is configured to include an electronic device according to the sixth configuration (seventh configuration).

[0286] The abnormal voltage protection circuit (502) according to the first configuration can detect a state in which the monitored voltage (VEE2), which is negative with respect to the reference voltage, is equal to or greater than a predetermined upper limit voltage (V8) or equal to or less than a predetermined lower limit voltage (V12).

[0287] The abnormal voltage protection circuit (502) according to the second configuration can implement a protection function for the monitored voltage (VEE2) based on the ground voltage (GND2).

[0288] The abnormal voltage protection circuit (502) according to the third configuration can prevent the voltage signals (V7, V11) input to the first terminals from becoming excessive, thereby preventing the abnormal voltage detection circuits (C3, C4) from being damaged.

[0289] According to the signal transmission device (200) of the fourth configuration, when the monitored voltage (VEE2) that is negative with respect to the reference voltage is in an abnormal voltage state, it is possible to protect the circuitry within the third chip (430).

[0290] According to the signal transmission device (200) of the fifth configuration, it is possible to output the detection result to the outside, and also possible to input an input signal for realizing control according to this detection result.

[0291] According to the electronic device of the sixth configuration, it is possible to protect the signal transmission device (200) when the monitored voltage (VEE2) that is negative with respect to the reference voltage is in an abnormal voltage state.

[0292] According to the vehicle (450) of the seventh configuration, it is possible to protect the signal transmission device (200) when the monitored voltage (VEE2) that is negative with respect to the reference voltage is in an abnormal voltage state.

[0293] 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating main surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connection wiring 73 Lead-out wiring 74 First connection plug electrode 75 Second connection plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high-potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern 94 Second pattern 95 Third pattern 96 First periphery line 97 Second periphery line 98 First intermediate line 99 First connection line 100 Slit 130 Separation structure 140 Inorganic insulating layer141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer tip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 External terminal X First direction X21, X22, X23 Internal terminal Y Second direction Y21, Y22, Y23 Wiring Z: normal direction Z21, Z22, Z23: via 400: electronic device 410: first semiconductor chip 411: first transmission circuit 412: second transmission circuit 415: logic circuit 416: third reception circuit 417: fourth reception circuit 418: fifth reception circuit 419: sixth reception circuit420 Second semiconductor chip 421 First receiving circuit 422 Second receiving circuit 424 Driver circuit 425 Logic circuit 426 Third transmitting circuit 427 Fourth transmitting circuit 428 Fifth transmitting circuit 429 Sixth transmitting circuit 430 Third semiconductor chip 431 First transformer 432 Second transformer 433 Third transformer 434 Fourth transformer 435 Fifth transformer 436 Sixth transformer 450 Vehicle 501 Output circuit 502 Abnormal voltage protection circuit 503 First overvoltage protection circuit 504 First low voltage malfunction prevention circuit 505 Second overvoltage protection circuit 506 Second low voltage malfunction prevention circuit 507 First voltage-current conversion circuit 508 First current-voltage conversion circuit 510 Current mirror circuit 511 Second voltage-current conversion circuit 512 Second current-voltage conversion circuit 513 Current mirror circuit 518 Fifth receiving circuit 600 Smoothing capacitor C1 First overvoltage detection circuit C2 First low-voltage detection circuit C3 Second overvoltage detection circuit C4 Second low-voltage detection circuit D1, D2 Diodes E1 Voltage source E2 Voltage source GND2 Ground voltage Ga to Gc Drive signal I1 to I4 Current IN Input signal OP1 Operational amplifier OP2 Operational amplifier OUT Output signal N1 to N4 Transistors P1 to P5 Transistors R1 to R14 Resistors S1 First internal signal S2 Second internal signal S3 Driver control signal S4 to S7 Detection signals SW Switch element SWH High-side switch element SWL Low-side switch element T1 First detection signal output terminal T2 Second detection signal output terminal T3 Third detection signal output terminal T4 Fourth detection signal output terminal T21 to T26 External terminals U Drive voltage V1 First upper limit voltage V2 Divided voltage V3 First lower limit voltage V4 Divided voltage V5 Divided voltage V6 Node voltage V7 Node voltageV8 Second upper limit voltage V9 Divided voltage V10 Node voltage V11 Node voltage V12 Second lower limit voltage VCC2 Positive power supply voltage VEE2 Negative power supply voltage VD1 First motor drive voltage VD2 Second motor drive voltage

Claims

1. An abnormal voltage protection circuit comprising: a voltage-to-current conversion circuit configured to convert a monitored voltage that is negative with respect to a reference voltage into a current signal; a current-to-voltage conversion circuit configured to convert the current signal into a voltage signal that is positive with respect to the reference voltage; and an abnormal voltage detection circuit configured to compare the voltage signal with a threshold voltage and detect whether the monitored voltage is equal to or higher than an upper limit voltage or lower than a lower limit voltage.

2. The abnormal voltage protection circuit according to claim 1, wherein the reference voltage is a ground voltage.

3. The abnormal voltage detection circuit according to claim 1 or 2, comprising: a first terminal to which the voltage signal is input; a second terminal to which the threshold voltage is input; a third terminal to which a positive power supply voltage that is positive with respect to the reference voltage is input; and a fourth terminal to which the reference voltage is input, and is configured to operate in response to the input of the positive power supply voltage and the reference voltage and to output a detection signal corresponding to the potential difference between the voltage signal and the threshold voltage, and further comprising a clamp circuit that maintains the voltage value of the voltage signal input to the first terminal at or below the positive power supply voltage.

4. A signal transmission device comprising: a first chip, a second chip; and a third chip configured to transmit signals while isolating the first chip and the second chip from each other, wherein the second chip is configured by integrating circuit elements including an abnormal voltage protection circuit as defined in any one of claims 1 to 3, and the third chip transmits the detection result detected by the abnormal voltage detection circuit from the second chip to the first chip.

5. A signal transmission device as described in claim 4, wherein the first chip comprises: an input terminal for receiving an input signal as an external input; and an output terminal for externally outputting an output signal according to the detection result.

6. An electronic device comprising: a plurality of switch elements, each of which is a power transistor; a plurality of gate driver ICs that drive the gates of the respective switch elements; and a control circuit that controls the plurality of gate driver ICs, wherein at least one of the plurality of gate driver ICs is the signal transmission circuit described in claim 5, and the first chip inputs the output signal to the control circuit via the output terminal and receives the input signal from the control circuit via the input terminal.

7. A vehicle equipped with the electronic device according to claim 6.

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