Electronic device

Abstract

The present invention provides an electronic device having a semiconductor layer made of a gallium oxide-based material on an Si substrate. An electronic device comprises: a substrate (10) made of a Si single crystal; a semiconductor layer (11) provided in contact with the substrate (10) and made of a uniaxially oriented gallium oxide-based semiconductor; and a diode structure including a second semiconductor layer (12) made of a gallium oxide-based semiconductor provided on the semiconductor layer (11) or the semiconductor layer (11), and two electrodes (13, 14).

Description

Electronic Devices

[0001] The present disclosure relates to electronic devices.

[0002] Gallium oxide has been actively studied as a semiconductor material in recent years, and in particular, because of its wide band gap and high breakdown voltage, it has attracted attention as a semiconductor material for power devices.

[0003] As a growth substrate for growing gallium oxide crystals, it is known to use not only a gallium oxide substrate but also heterogeneous substrates such as a sapphire substrate, a SiC substrate, or a Si substrate.

[0004] It is technically difficult to grow gallium oxide epitaxially on a heterogeneous substrate, and in particular, it is extremely difficult to form gallium oxide on a Si substrate because the crystal structures of Si and gallium oxide are significantly different.

[0005] As a method for forming gallium oxide on a Si substrate, forming gallium oxide on a Si substrate via a buffer layer has been proposed. For example, Non-Patent Document 1 describes forming a buffer layer made of SiC on a Si substrate. Also, Non-Patent Documents 2 and 3 describe forming a buffer layer made of aluminum oxide on a Si substrate.

[0006] Study of the Anisotropic Elastoplastic Properties of β-Ga2O3 Films Synthesized on SiC / Si Substrates, AS Grashchenko et al., Phys. Solid State, 60, 852-857(2018)β-Ga2O3 on Si(001) grown by plasma-assisted MBE with γ-Ga2O3(111) buffer layer:Structural characterization, T. Hadamek et al. al., AIP Advances, 11, 045209(2021)β-Ga2O3 MOSFETs on the Si substrate fabricated by the ion-cutting process, YB Wang, et al., Sci. China:Phys., Mech. Astron., 63, 277311(2020)

[0007] The above-mentioned gallium oxide substrate, sapphire substrate, and SiC substrate are all expensive and not available in large diameters, which makes it difficult to mass-produce and reduce costs, making industrial device manufacturing difficult.

[0008] For industrial device manufacturing, it is desirable to use a Si substrate. However, currently, only methods using a buffer layer, as described in Non-Patent Documents 1-3, have been developed, and epitaxial growth of gallium oxide without a buffer layer has not been possible.

[0009] The inventors investigated the use of a silicon substrate as a growth substrate for gallium oxide to enable industrial device manufacturing. As a result of their extensive research, they discovered a method for directly epitaxially growing gallium oxide on a silicon substrate. Based on this discovery, the inventors have completed an electronic device with a novel configuration.

[0010] The present disclosure has been made in view of the above background, and aims to provide an electronic device having a semiconductor layer made of a gallium oxide-based material on a Si substrate.

[0011] One aspect of the present disclosure is an electronic device having: a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate; a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer; and a diode structure including two electrodes.

[0012] Another aspect of the present disclosure resides in an electronic device having a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate; a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer; and a Gunn diode structure including two electrodes.

[0013] Yet another aspect of the present disclosure resides in an electronic device having a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate; a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer; and a varistor structure including two electrodes.

[0014] According to the above aspect, an electronic device can be realized in which a gallium oxide layer is formed directly on a substrate made of single crystal Si.

[0015] Fig. 1 is a cross-sectional view showing the configuration of a lateral Schottky diode in embodiment 1, taken in a direction perpendicular to the main surface of the substrate. Fig. 2 is a cross-sectional view showing the configuration of a vertical Schottky diode in embodiment 2, taken in a direction perpendicular to the main surface of the substrate. Fig. 3 is a cross-sectional view showing the configuration of a Gunn diode in embodiment 3, taken in a direction perpendicular to the main surface of the substrate. Fig. 4 is a cross-sectional view showing the configuration of a varistor in embodiment 4, taken in a direction perpendicular to the main surface of the substrate. Fig. 5 is a cross-sectional view showing the configuration of a varistor in a modified form of embodiment 4, taken in a direction perpendicular to the main surface of the substrate.

[0016] The electronic device has a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and a diode structure including two electrodes. Here, the diode structure is a structure in which electrodes are provided on the p-side and n-side of a pn junction structure, or a Schottky junction structure in which two electrodes are provided on the semiconductor layer and at least one of the two electrodes is a Schottky electrode.

[0017] Another electronic device has a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and a Gunn diode structure including two electrodes. The Gunn diode structure is a structure in which two electrodes are provided on a semiconductor layer that exhibits the Gunn effect.

[0018] Another electronic device has a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and a varistor structure including two electrodes. The varistor structure is a structure in which two electrodes are provided on a semiconductor layer having nonlinear resistance.

[0019] Semiconductors are materials whose conductivity can be controlled, and gallium oxide-based semiconductors have a wide band gap, making it possible to control their properties from insulating to conductive.

[0020] In the above, the gallium oxide based semiconductor, that is, the gallium oxide based semiconductor forming the semiconductor layer and the gallium oxide based semiconductor forming the second semiconductor layer may be β-gallium oxide.

[0021] In the above, the main surface of the substrate may be a (100) plane, and the main surface of the semiconductor layer may be a (100) plane.

[0022] In the above, the

[001] direction of the substrate and the [0-11] direction of the semiconductor layer may coincide with each other.

[0023] 1 is a cross-sectional view showing the configuration of a lateral Schottky diode according to Embodiment 1, taken along a direction perpendicular to the main surface of the substrate. As shown in FIG. 1 , the lateral Schottky diode according to Embodiment 1 includes a substrate 10 made of single-crystal Si, a semiconductor layer 11 provided on and in contact with the substrate 10, a second semiconductor layer 12 provided on the semiconductor layer 11, a positive electrode 13, a negative electrode 14, and a guard ring 15. In Embodiment 1, the semiconductor layer 11 is an undoped layer containing a gallium oxide-based compound, and the second semiconductor layer 12 is an n-type layer made of an n-type gallium oxide-based compound. In Embodiment 1, the second semiconductor layer (n-type layer) 12, the positive electrode 13, and the negative electrode 14 form a diode structure.

[0024] The substrate 10 is a substrate made of a silicon single crystal in which silicon (Si) atoms are regularly arranged in a three-dimensional manner. Any conventionally known substrate can be used as the substrate 10. For example, a substrate grown by crystal growth using the Czochralski method or the floating zone (FZ) method can be used.

[0025] The main surface of the substrate 10 is preferably a (100) plane or a (111) plane. These planes make it easy to directly grow a gallium oxide crystal on the substrate 10. In particular, from the viewpoint of industrial feasibility, the main surface of the substrate 10 is preferably a (100) plane.

[0026] The surface of the substrate 10 may be modified, for example, by surface treatment with oxygen plasma.

[0027] The non-doped layer 11 is a layer made of non-doped β-gallium oxide, and is provided directly on the substrate 10 without a buffer layer therebetween. That is, the substrate 10 and the non-doped layer 11 are in contact with each other. The non-doped layer 11 is highly resistive, semi-insulating, or insulating. The thickness of the non-doped layer 11 is, for example, 100 nm to 100 μm.

[0028] The buffer layer is a layer inserted for the purpose of relaxing the lattice constant, and typically has a thickness of 20 nm or more. The buffer layer may be made of, for example, the following materials: the same material as the non-doped layer 11, a different material from the non-doped layer 11, a layer formed by gradually changing the composition of a mixed crystal of the same material as the non-doped layer 11 and a different material, or a superlattice structure in which the same material as the non-doped layer 11 and a different material are alternately stacked to a predetermined thickness. In the first embodiment, such a buffer layer is not provided between the substrate 10 and the non-doped layer 11.

[0029] The non-doped layer 11 is a layer provided to prevent current leakage to the substrate 10. By forming the non-doped β-gallium oxide using a predetermined growth method (for example, the PAMBE method), the crystal defect concentration and impurity concentration can be controlled to make the layer highly resistive, semi-insulating, or insulating.

[0030] Here, high resistance means, for example, a resistivity of 1×10 ４ ~1 x 10 ６ Ω cm. Furthermore, semi-insulating means that the resistivity is, for example, 1×10 ６ Insulating refers to a state in which almost no carriers exist, for example, when the carrier concentration is 1 / cm ３ The states are as follows: Insulating properties occur when the band gap is large and the Fermi level is near the center of the band gap. If the Fermi level is slightly off-center, it becomes semi-insulating; if it is further off-center, it becomes highly resistive; and if it is further off-center and close to the conductor or valence band, it becomes conductive. Because beta gallium oxide has a large band gap, it can be in a state ranging from insulating to conductive depending on the position of the Fermi level.

[0031] In embodiment 1, the β-gallium oxide is non-doped to provide high resistance, semi-insulating properties, or insulating properties, but the β-gallium oxide may also be doped with an impurity that forms a deep level, such as Fe, to provide high resistance, semi-insulating properties, or insulating properties.

[0032] The non-doped layer 11 is a uniaxially oriented epitaxial layer on the substrate 10. Here, uniaxial orientation means that at least one of the crystal axes of the β-gallium oxide in the non-doped layer 11 is aligned with one of the crystal axes of Si in the substrate 10. As long as the layer is uniaxially oriented in this way, it may be single crystal or polycrystal. Whether the non-doped layer 11 is uniaxially oriented or not can be confirmed, for example, by the diffraction pattern of X-ray diffraction. Furthermore, whether it is single crystal or polycrystal can also be confirmed by the diffraction pattern of X-ray diffraction.

[0033] When the main surface of the substrate 10 is a (100) plane and the non-doped layer 11 is single crystal, the main surface of the non-doped layer 11 is preferably a (100) plane. The (100) plane of Si and the (100) plane of β-gallium oxide have good lattice matching, allowing the non-doped layer 11 to be formed with high quality. The (100) plane of Si and the (100) plane of β-gallium oxide may form an angle of 10 degrees or less. The crystal plane of the non-doped layer 11 can be identified, for example, by a diffraction peak in θ-2θ measurement of X-ray diffraction.

[0034] Furthermore, it is preferable that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 coincide with each other. This is from the viewpoint of epitaxial growth of the non-doped layer 11. Here, "coincidence" does not mean perfect coincidence, but merely refers to substantial coincidence. For example, if the

[001] direction of Si in the substrate 10 and the

[001] direction of β-gallium oxide in the non-doped layer 11 form an angle of about 23 to 28°, it can be said that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 substantially coincide with each other.

[0035] The n-type layer 12 is a layer made of n-type β-gallium oxide provided on the non-doped layer 11. The thickness of the n-type layer 12 is, for example, 10 nm to 100 μm. The n-type impurity added to form the n-type layer 12 may be Si or Sn. The n-type impurity concentration may be, for example, 1×10 １６ ~1 x 10 ２１ cm －３ Other aspects such as crystal planes and crystal axes are the same as those of the non-doped layer 11.

[0036] The positive electrode 13 is an electrode provided on and in contact with the n-type layer 12. The positive electrode 13 is in Schottky contact with the n-type layer 12. The material of the positive electrode 13 is Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni / Au, Ni / Pt, Pt / Au, Pt / Ti / Au, Pt / Au / Ni, Ti / Au / Ni, ITO, or the like.

[0037] The negative electrode 14 is an electrode provided on and in contact with the n-type layer 12, in a region spaced apart from the positive electrode 13. The negative electrode 14 is in ohmic contact with the n-type layer 12. The material of the negative electrode 14 is Ti, Ti / Au, Ti / Al / Au, Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ti / Au / Ni, Sn, or the like.

[0038] The guard ring 15 is provided on and in contact with the n-type layer 12, and is provided in a ring shape in the peripheral region of the device. The guard ring 15 is in Schottky contact with the n-type layer 12. The provision of the guard ring 15 can alleviate electric field concentration on the surface of the n-type layer 12. The material of the guard ring 15 is, for example, the same material as that of the positive electrode 13.

[0039] As described above, in the lateral Schottky diode of the first embodiment, the positive electrode 13 is in Schottky contact with the n-type layer 12, thereby realizing a diode. Furthermore, the first embodiment is a lateral type in which conduction is achieved in a direction parallel to the main surface of the substrate 10. Furthermore, since the n-type layer 12 is made of gallium oxide, the breakdown voltage (breakdown voltage) can be increased. Furthermore, since Si is used as the substrate 10, the diameter can be increased, which is advantageous for mass production and cost reduction.

[0040] Next, a method for manufacturing the lateral Schottky diode according to the first embodiment will be described.

[0041] First, a substrate 10, which is a Si single crystal substrate, is prepared. The substrate 10 is then placed in a furnace and heated to a growth temperature. Thereafter, the pressure in the furnace is reduced to a growth pressure. The ranges of the growth temperature and growth pressure will be described later.

[0042] The surface of the substrate 10 may be treated with oxygen plasma before the formation of the non-doped layer 11. This can reduce the surface roughness of the substrate 10, making it easier to grow gallium oxide on the substrate 10.

[0043] Next, a non-doped layer 11 made of β-gallium oxide is formed on the substrate 10 by plasma-assisted molecular beam epitaxy (PAMBE). In the PAMBE method, a mixed gas containing oxygen and ozone is turned into plasma and supplied to the substrate 10, and gallium is evaporated and a molecular beam is irradiated onto the substrate 10. By turning the mixed gas containing oxygen and ozone into plasma, the ozone is decomposed to generate oxygen molecules and oxygen radicals. The oxygen radicals are formed by singlet oxygen atoms O( １ D) and triplet oxygen atom O( ３ P), and singlet oxygen atoms transition to triplet oxygen atoms at a predetermined rate. These oxygen radicals react with the gallium molecular beam on the substrate surface, causing β-gallium oxide crystal growth on the surface of the substrate 10.

[0044] The growth pressure is preferably 0.001 Pa or more and 0.01 Pa or less. The growth temperature (substrate temperature) is preferably 0° C. or more and 600° C. or less. If the growth temperature and growth pressure are within these ranges, the non-doped layer 11 can be grown with good crystallinity.

[0045] A mixed gas containing oxygen and ozone can be generated by using an ozonizer to convert oxygen into plasma and then converting part of the oxygen into ozone.

[0046] In the mixed gas containing oxygen and ozone, the ratio of ozone to the total of oxygen and ozone is preferably 10% by volume or more. Although there is no particular upper limit, when the mixed gas containing oxygen and ozone is generated using an ozonizer, it is usually 50% by volume or less. The mixed gas containing oxygen and ozone may be mixed with an inert gas such as Ar and supplied. This makes it easier to generate plasma.

[0047] Next, an n-type layer 12 made of n-type β-gallium oxide is formed by the PAMBE method on the non-doped layer 11. The n-type layer 12 can be formed under the same growth conditions as the non-doped layer 11, except that it is doped with an n-type impurity.

[0048] Next, the positive electrode 13, the negative electrode 14, and the guard ring 15 are formed by a method such as vapor deposition on the n-type layer 12. In this way, the lateral Schottky diode of the first embodiment is manufactured.

[0049] 2 is a cross-sectional view showing the configuration of a vertical Schottky diode according to Embodiment 2, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 2, the vertical Schottky diode according to Embodiment 2 includes a substrate 20, a semiconductor layer 21, a positive electrode 22, a negative electrode 23, and a guard ring 24. In Embodiment 2, the semiconductor layer 21, the positive electrode 22, and the negative electrode 23 form a diode structure.

[0050] The substrate 20 is a high-concentration n-type single crystal Si substrate. The n-type impurity concentration is, for example, 1×10 １８ ~1 x 10 ２２ cm －３ The other configurations are the same as those of the substrate 10 in the first embodiment.

[0051] The semiconductor layer 21 is a layer made of β-gallium oxide, and is provided directly on the substrate 20 without a buffer layer therebetween. That is, the substrate 20 and the semiconductor layer 21 are in contact with each other. The thickness of the semiconductor layer 21 is, for example, 100 nm to 100 μm. The other configurations are the same as those of the non-doped layer 11 and the n-type layer 12 in the first embodiment.

[0052] The positive electrode 22 is an electrode provided on and in contact with the semiconductor layer 21. The positive electrode 22 is in Schottky contact with the semiconductor layer 21. The material of the positive electrode 22 is the same as that of the positive electrode 12 in the first embodiment.

[0053] The negative electrode 23 is an electrode provided in contact with the back surface (the surface opposite to the semiconductor layer 21 side) of the substrate 20. The negative electrode 23 is in ohmic contact with the substrate 20. The material of the negative electrode 23 is the same as that of the negative electrode 13 in the first embodiment.

[0054] The guard ring 24 is provided on and in contact with the semiconductor layer 21, and is provided in a ring shape in the peripheral region of the element. The guard ring 24 is in Schottky contact with the semiconductor layer 21. The material of the guard ring 24 is the same as that of the guard ring 14 in the first embodiment.

[0055] In the vertical Schottky diode of the second embodiment, the positive electrode 22 is in Schottky contact with the semiconductor layer 21, as in the first embodiment, thereby realizing a diode. Moreover, the second embodiment is a vertical type in which conduction is achieved in a direction perpendicular to the main surface of the substrate. Furthermore, since the semiconductor layer 21 is made of gallium oxide, the breakdown voltage can be increased.

[0056] 3 is a cross-sectional view showing the configuration of a vertical Gunn diode in embodiment 3, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 3, the Gunn diode in embodiment 3 has a substrate 30, a semiconductor layer 31, a positive electrode 32, and a negative electrode 33. In embodiment 3, the semiconductor layer 31, the positive electrode 32, and the negative electrode 33 form a Gunn diode structure.

[0057] The substrate 30 is a high-concentration n-type Si single crystal substrate, similar to the substrate 20 in the second embodiment, and other configurations such as the crystal plane are similar to those in the first embodiment.

[0058] The semiconductor layer 31 is a layer made of β-gallium oxide and is provided directly on the substrate 30 without a buffer layer therebetween. That is, the substrate 30 and the semiconductor layer 31 are in contact with each other. The semiconductor layer 31 may be undoped or may be doped with an n-type impurity. The thickness of the semiconductor layer 31 is set according to the oscillation frequency. Other configurations are the same as those of the undoped layer 11 and the n-type layer 12 in the first embodiment.

[0059] In order to make good contact with the positive electrode 32, the semiconductor layer 31 may have a two-layer structure consisting of, in order from the substrate 30 side, a low-concentration n-type layer and a high-concentration n-type layer.

[0060] The positive electrode 32 is an electrode provided on and in contact with the semiconductor layer 31. The positive electrode 32 is in ohmic contact with the semiconductor layer 21. The material of the positive electrode 32 is the same as that of the negative electrode 13 in the first embodiment and the negative electrode 23 in the second embodiment.

[0061] The negative electrode 33 is an electrode provided in contact with the back surface (the surface opposite to the semiconductor layer 31 side) of the substrate 30. The negative electrode 33 is in ohmic contact with the substrate 30. The material of the negative electrode 33 is the same as that of the negative electrode 13 in the first embodiment and the negative electrode 23 in the second embodiment.

[0062] Next, the operation of the Gunn diode in the third embodiment will be described.

[0063] Gallium oxide, like gallium arsenide used in general Gunn diodes, has two conduction bands with different energies and wavenumbers. The conduction band with the lower energy has higher electron mobility than the other conduction band. Therefore, gallium oxide exhibits negative resistance in a certain voltage range. As a result of gallium oxide having these physical properties, Gunn diodes can be realized.

[0064] That is, when a voltage in a range that exhibits negative resistance is applied, a high electric field region is generated in the semiconductor layer 31, and the current decreases. The generated high electric field region moves toward the positive electrode 32 due to the external voltage. When it reaches the end on the positive electrode 32 side, the high electric field region disappears and the current increases. Thereafter, a high electric field region is generated again on the negative electrode 33 side. The generation and movement of the high electric field region occurs periodically in the semiconductor layer 31, resulting in periodic fluctuations in the current. Furthermore, as can be seen from this operating principle, the frequency of the current can be set by the thickness of the semiconductor layer 31.

[0065] As described above, according to the Gunn diode of the third embodiment, the semiconductor layer 31 is made of gallium oxide, so that the operating voltage can be increased.

[0066] (Embodiment 4) Fig. 4 is a cross-sectional view showing the configuration of a varistor in embodiment 4, taken in a direction perpendicular to the main surface of the substrate. As shown in Fig. 4, the varistor in embodiment 4 has a substrate 40, a semiconductor layer 41, a p-type region 45, a positive electrode 42, and a negative electrode 43. In embodiment 4, the semiconductor layer 41, p-type region 45, positive electrode 42, and negative electrode 43 form the varistor structure.

[0067] The substrate 40 is a high-concentration n-type Si single crystal substrate, similar to the substrate 20 in the second embodiment, and other configurations such as the crystal plane are similar to those in the first embodiment.

[0068] The semiconductor layer 41 is a layer made of undoped β-gallium oxide, and is provided directly on the substrate 40 without a buffer layer therebetween. That is, the substrate 40 and the semiconductor layer 41 are in contact with each other. The thickness of the semiconductor layer 41 is, for example, 100 nm to 100 μm. The other configurations are the same as those of the undoped layer 11 and the n-type layer 12 in the first embodiment.

[0069] The semiconductor layer 41 is preferably polycrystalline. This is because it improves the nonlinear resistance and the withstand voltage of the varistor. For the same reason, the semiconductor layer 41 may be made of semi-insulating gallium oxide. Gallium oxide can be made semi-insulating by doping it with impurities such as Fe, Si, and Mg.

[0070] The p-type region 45 is a p-type region formed in a predetermined region near the surface of the semiconductor layer 41. The p-type region 45 can be formed by implanting Ni ions into the surface of the semiconductor layer 41. When Ni ions are implanted into the surface of the semiconductor layer 41, nickel oxide, which is a p-type semiconductor, can be formed on the surface of the semiconductor layer 41. Of course, the p-type region may also be formed by other conventionally known methods.

[0071] The positive electrode 42 is an electrode provided on and in contact with the p-type region 45. The positive electrode 42 is in ohmic contact with the p-type region 45. The material of the positive electrode 42 is the same as that of the positive electrode 12 in the first embodiment.

[0072] The negative electrode 43 is provided in contact with the back surface (the surface opposite to the semiconductor layer 41 side) of the substrate 40. The negative electrode 43 is in ohmic contact with the substrate 40. The material of the negative electrode 43 is the same as that of the positive electrode 42.

[0073] As described above, in the fourth embodiment, a varistor having a p-type region 45 and a polarity is realized. In other words, an IV characteristic similar to that of a diode can be realized. Furthermore, since gallium oxide is used, the breakdown voltage can be improved, and the surge resistance can be improved when both a forward voltage and a reverse voltage are applied.

[0074] (Modification of Embodiment 4) Figure 5 is a cross-sectional view showing the configuration of a varistor in a modification of Embodiment 4, taken along a direction perpendicular to the main surface of the substrate. As shown in Figure 5, the varistor in this modification of Embodiment 4 has a configuration in which the p-type region 45 is omitted from the varistor in Embodiment 4. The varistor in Embodiment 4 has a polarity because it has the p-type region 45, but can be made bipolar by omitting the p-type region 45. In other words, the IV characteristics show that no current flows until a large voltage is applied, both when a forward voltage is applied and when a reverse voltage is applied.

[0075] (Other Modifications) In the first and second embodiments, a lateral Schottky diode and a vertical Schottky diode are shown as examples of diodes, but other diodes that control current and voltage can also be realized. For example, diodes having pn junctions, such as pn diodes, pin diodes, Zener diodes, avalanche diodes, tunnel diodes, and varactors, can also be realized in the present disclosure. The p-type region in these diodes may be realized by Ni ion implantation, as in the fourth embodiment. Thermoelectric elements, piezoelectric elements, Hall elements, magnetoresistive elements, and the like can also be realized.

[0076] Furthermore, as the first embodiment shows an electronic device with a horizontal structure and the second to fourth embodiments show electronic devices with a vertical structure, the present disclosure can be applied to both vertical and horizontal structures.

[0077] The gallium oxide in each embodiment may be a gallium oxide-based semiconductor. Here, the gallium oxide-based semiconductor is a semiconductor in which a part of Ga in gallium oxide is replaced with Al or In (Al ２ｘ Ga ２ｙ In ２－２ｘ－２ｙ O ３ , 0≦x≦1, 0<y≦1). In addition, although gallium oxide is in the β phase in each embodiment, it may have a crystal structure other than the β phase. That is, five crystal structures of gallium oxide are known, namely, α, β, γ, δ, and ε, and any of these crystal structures may be used. For example, it may be the α phase. However, the β phase is preferred in terms of compatibility with the Si substrate.

[0078] Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present invention. This application is based on a Japanese patent application (Patent Application No. 2023-150628) filed on September 18, 2023, the contents of which are incorporated herein by reference.

[0079] 10, 20, 30, 40: Substrate 11: Non-doped layer (semiconductor layer) 12: N-type layer (second semiconductor layer) 21, 31, 41: Semiconductor layer 13, 22, 32, 42: Positive electrode 14, 23, 33, 43: Negative electrode 15, 24: Guard ring 45: P-type region

Claims

1. An electronic device having a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and a diode structure including two electrodes.

2. An electronic device having a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and a Gunn diode structure including two electrodes.

3. An electronic device having a varistor structure including: a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide semiconductor provided on and in contact with the substrate; a second semiconductor layer made of a gallium oxide semiconductor provided on the semiconductor layer or on the semiconductor layer; and two electrodes.

4. The electronic device according to any one of claims 1 to 3, wherein the gallium oxide based semiconductor is β-gallium oxide.

5. The electronic device according to claim 4, wherein the primary surface of the substrate is a (100) surface.

6. The electronic device according to claim 5, wherein the primary surface of the semiconductor layer is a (100) surface.

7. The electronic device according to claim 4, wherein the [001] direction of said substrate and the [0-11] direction of said semiconductor layer coincide with each other.

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