Electronic device

Abstract

The present invention provides an electronic device in which a semiconductor layer comprising a gallium oxide–based material is provided on a Si substrate. The electronic device includes: a substrate (10) that comprises a Si single crystal; a semiconductor layer (non-doped layer) (11) that is provided on the substrate (10) in contact with the substrate (10) and comprises a uniaxially oriented gallium oxide–based semiconductor; and a transistor structure that includes a second semiconductor layer (n-type layer) (12) comprising the semiconductor layer or a gallium oxide–based semiconductor provided on the semiconductor layer, and three electrodes (a gate electrode (13), a source electrode (14), and a drain electrode (15)).

Description

Electronic Devices

[0001] The present disclosure relates to electronic devices.

[0002] Gallium oxide has been actively studied as a semiconductor material in recent years, and in particular, because of its wide band gap and high breakdown voltage, it has attracted attention as a semiconductor material for power devices.

[0003] As a growth substrate for growing gallium oxide crystals, it is known to use not only a gallium oxide substrate but also heterogeneous substrates such as a sapphire substrate, a SiC substrate, or a Si substrate.

[0004] It is technically difficult to grow gallium oxide epitaxially on a heterogeneous substrate, and in particular, it is extremely difficult to form gallium oxide on a Si substrate because the crystal structures of Si and gallium oxide are significantly different.

[0005] As a method for forming gallium oxide on a Si substrate, forming gallium oxide on a Si substrate via a buffer layer has been proposed. For example, Non-Patent Document 1 describes forming a buffer layer made of SiC on a Si substrate. Also, Non-Patent Documents 2 and 3 describe forming a buffer layer made of aluminum oxide on a Si substrate.

[0006] Study of the Anisotropic Elastoplastic Properties of β-Ga2O3 Films Synthesized on SiC / Si Substrates, AS Grashchenko et al., Phys. Solid State, 60, 852-857(2018)β-Ga2O3 on Si(001) grown by plasma-assisted MBE with γ-Ga2O3(111) buffer layer:Structural characterization, T. Hadamek et al. al., AIP Advances, 11, 045209(2021)β-Ga2O3 MOSFETs on the Si substrate fabricated by the ion-cutting process, YB Wang, et al., Sci. China:Phys., Mech. Astron., 63, 277311(2020)

[0007] The above-mentioned gallium oxide substrate, sapphire substrate, and SiC substrate are all expensive and not available in large diameters, which makes it difficult to mass-produce and reduce costs, making industrial device manufacturing difficult.

[0008] For industrial device manufacturing, it is desirable to use a Si substrate. However, currently, only methods using a buffer layer, as described in Non-Patent Documents 1-3, have been developed, and epitaxial growth of gallium oxide without a buffer layer has not been possible.

[0009] The inventors investigated the use of a silicon substrate as a growth substrate for gallium oxide to enable industrial device manufacturing. As a result of their extensive research, they discovered a method for directly epitaxially growing gallium oxide on a silicon substrate. Based on this discovery, the inventors have completed an electronic device with a novel configuration.

[0010] The present disclosure has been made in view of the above background, and aims to provide an electronic device having a semiconductor layer made of a gallium oxide-based material on a Si substrate.

[0011] One aspect of the present disclosure is an electronic device having a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate; a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer; and a transistor structure including three electrodes.

[0012] According to the above aspect, an electronic device can be realized in which a gallium oxide layer is formed directly on a substrate made of single crystal Si.

[0013] FIG. 1 is a cross-sectional view showing the configuration of a MESFET according to embodiment 1, taken in a direction perpendicular to the main surface of a substrate. FIG. 2 is a cross-sectional view showing the configuration of an HFET according to embodiment 2, taken in a direction perpendicular to the main surface of a substrate. FIG. 3 is a cross-sectional view showing the configuration of a JFET according to embodiment 3, taken in a direction perpendicular to the main surface of a substrate. FIG. 4 is a cross-sectional view showing the configuration of a buried-gate FET according to embodiment 4, taken in a direction perpendicular to the main surface of a substrate. FIG. 5 is a cross-sectional view showing the configuration of a bipolar transistor according to embodiment 5, taken in a direction perpendicular to the main surface of a substrate. FIG. 6 is a cross-sectional view showing the configuration of a MISFET according to embodiment 6, taken in a direction perpendicular to the main surface of a substrate.

[0014] The electronic device has a transistor structure including a substrate made of single crystal silicon, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a second semiconductor layer made of a gallium oxide-based semiconductor provided on the semiconductor layer or on the semiconductor layer, and three electrodes. The transistor structure is a field-effect transistor structure or a bipolar transistor structure. The field-effect transistor structure has a gate structure having a gate electrode in the semiconductor layer, and source and drain electrodes connected to the semiconductor layer, and generates an electric field in the semiconductor layer via the gate electrode to control the current between the source and drain electrodes. The bipolar transistor structure has an npn junction structure or a pnp junction structure, and has a collector electrode, base electrode, and emitter electrode connected to each layer, and controls the collector current by the base current.

[0015] Semiconductors are materials whose conductivity can be controlled, and gallium oxide-based semiconductors have a wide band gap, making it possible to control their properties from insulating to conductive.

[0016] The field effect transistor structure may be a MESFET (Metal Semiconductor Field Effect Transistor) structure, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure, a JFET (Junction Field Effect Transistor) structure, or an HFET (Heterojunction Field Effect Transistor) structure.

[0017] In the above, the gallium oxide based semiconductor, that is, the gallium oxide based semiconductor forming the semiconductor layer and the gallium oxide based semiconductor forming the second semiconductor layer may be β-gallium oxide.

[0018] In the above, the main surface of the substrate may be a (100) plane, and the main surface of the semiconductor layer may be a (100) plane.

[0019] In the above, the

[001] direction of the substrate and the [0-11] direction of the semiconductor layer may coincide with each other.

[0020] 1 is a cross-sectional view showing the configuration of a MESFET according to Embodiment 1, taken along a direction perpendicular to the main surface of the substrate. As shown in FIG. 1 , the MESFET according to Embodiment 1 includes a substrate 10 made of single crystal Si, a semiconductor layer 11 provided on and in contact with the substrate 10, a second semiconductor layer 12 provided on the semiconductor layer 11, a gate electrode 13, a source electrode 14, and a drain electrode 15. In Embodiment 1, the semiconductor layer 11 is an undoped layer containing a gallium oxide-based compound, and the second semiconductor layer 12 is an n-type layer made of an n-type gallium oxide-based compound. In Embodiment 1, the second semiconductor layer (n-type layer) 12, the gate electrode 13, the source electrode 14, and the drain electrode 15 form a field-effect transistor (FET) structure.

[0021] The substrate 10 is a substrate made of a silicon single crystal in which silicon (Si) atoms are regularly arranged in a three-dimensional manner. Any conventionally known substrate can be used as the substrate 10. For example, a substrate grown by crystal growth using the Czochralski method or the floating zone (FZ) method can be used.

[0022] The main surface of the substrate 10 is preferably a (100) plane or a (111) plane. These crystal planes make it easy to directly grow gallium oxide crystals on the substrate 10. In particular, from the viewpoint of industrial feasibility, the main surface of the substrate 10 is preferably a (100) plane.

[0023] The surface of the substrate 10 may be modified, for example, by surface treatment with oxygen plasma.

[0024] The non-doped layer 11 is a layer made of non-doped β-gallium oxide, and is provided directly on the substrate 10 without a buffer layer therebetween. That is, the substrate 10 and the non-doped layer 11 are in contact with each other. The non-doped layer 11 is highly resistive, semi-insulating, or insulating. The thickness of the non-doped layer 11 is, for example, 100 nm to 100 μm.

[0025] The buffer layer is a layer inserted for the purpose of relaxing the lattice constant, and typically has a thickness of 20 nm or more. The buffer layer may be made of, for example, the following materials: the same material as the non-doped layer 11, a different material from the non-doped layer 11, a layer formed by gradually changing the composition of a mixed crystal of the same material as the non-doped layer 11 and a different material, or a superlattice structure in which the same material as the non-doped layer 11 and a different material are alternately stacked to a predetermined thickness. In the first embodiment, such a buffer layer is not provided between the substrate 10 and the non-doped layer 11.

[0026] The non-doped layer 11 is a layer provided to prevent current leakage to the substrate 10. By forming the non-doped β-gallium oxide using a predetermined growth method (for example, the PAMBE method), the crystal defect concentration and impurity concentration can be controlled to make the layer highly resistive, semi-insulating, or insulating.

[0027] Here, high resistance means, for example, a resistivity of 1×10 ４ ~1 x 10 ６ Ω cm. Furthermore, semi-insulating means that the resistivity is, for example, 1×10 ６ Insulating refers to a state in which almost no carriers exist, for example, when the carrier concentration is 1 / cm ３ The states are as follows: Insulating properties occur when the band gap is large and the Fermi level is near the center of the band gap. If the Fermi level is slightly off-center, it becomes semi-insulating; if it is further off-center, it becomes highly resistive; and if it is further off-center and close to the conductor or valence band, it becomes conductive. Because beta gallium oxide has a large band gap, it can be in a state ranging from insulating to conductive depending on the position of the Fermi level.

[0028] In embodiment 1, the β-gallium oxide is non-doped to provide high resistance, semi-insulating properties, or insulating properties, but the β-gallium oxide may also be doped with an impurity that forms a deep level, such as Fe, to provide high resistance, semi-insulating properties, or insulating properties.

[0029] The non-doped layer 11 is a uniaxially oriented epitaxial layer on the substrate 10. Here, uniaxial orientation means that at least one of the crystal axes of the β-gallium oxide in the non-doped layer 11 is aligned with one of the crystal axes of Si in the substrate 10. As long as the layer is uniaxially oriented in this way, it may be single crystal or polycrystal. Whether the non-doped layer 11 is uniaxially oriented or not can be confirmed, for example, by the diffraction pattern of X-ray diffraction. Furthermore, whether it is single crystal or polycrystal can also be confirmed by the diffraction pattern of X-ray diffraction.

[0030] When the main surface of the substrate 10 is a (100) plane and the non-doped layer 11 is single crystal, the main surface of the non-doped layer 11 is preferably a (100) plane. The (100) plane of Si and the (100) plane of β-gallium oxide have good lattice matching, allowing the non-doped layer 11 to be formed with high quality. The (100) plane of Si and the (100) plane of β-gallium oxide may form an angle of 10 degrees or less. The crystal plane of the non-doped layer 11 can be identified, for example, by a diffraction peak in θ-2θ measurement of X-ray diffraction.

[0031] Furthermore, it is preferable that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 coincide with each other. This is from the viewpoint of epitaxial growth of the non-doped layer 11. Here, "coincidence" does not mean perfect coincidence, but merely refers to substantial coincidence. For example, if the

[001] direction of Si in the substrate 10 and the

[001] direction of β-gallium oxide in the non-doped layer 11 form an angle of about 23 to 28°, it can be said that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 substantially coincide with each other.

[0032] The n-type layer 12 is a layer made of n-type β-gallium oxide provided on the non-doped layer 11. The thickness of the n-type layer 12 is, for example, 10 nm to 10 μm. The n-type impurity added to form the n-type layer 12 may be Si or Sn. The n-type impurity concentration may be, for example, 1×10 １６ ~1 x 10 ２１ cm －３ Other aspects such as crystal plane are the same as those of the non-doped layer 11.

[0033] Gate electrode 13 is an electrode provided in contact with a predetermined region on n-type layer 12. Gate electrode 13 is in Schottky contact with n-type layer 12. Materials for gate electrode 13 include Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni / Au, Ni / Pt, Pt / Au, Pt / Ti / Au, Pt / Au / Ni, Ti / Au / Ni, and ITO.

[0034] The source electrode 14 and the drain electrode 15 are electrodes provided on and in contact with the n-type layer 12. The source electrode 14 and the drain electrode 15 are provided to face each other with the gate electrode 13 sandwiched therebetween in a plan view. The source electrode 14 and the drain electrode 15 are in ohmic contact with the n-type layer 12. The source electrode 14 and the drain electrode 15 may be made of a material such as Ti, Ti / Au, Ti / Al / Au, Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ti / Au / Ni, or Sn.

[0035] Next, the operation of the MESFET in embodiment 1 will be described. In embodiment 1, a depletion layer is formed on the surface of n-type layer 12 directly below gate electrode 13 due to Schottky contact of gate electrode 13 with n-type layer 12. The extent of this depletion layer can be controlled by applying a voltage to gate electrode 13, thereby controlling the current between source electrode 14 and drain electrode 15. In this way, a MESFET is realized in embodiment 1.

[0036] As described above, in the MESFET according to the first embodiment, the non-doped layer 11 and the n-type layer 12 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 10 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction.

[0037] Next, a method for manufacturing the MESFET according to the first embodiment will be described.

[0038] First, a substrate 10, which is a Si single crystal substrate, is prepared. The substrate 10 is then placed in a furnace and heated to a growth temperature. Thereafter, the pressure in the furnace is reduced to a growth pressure. The ranges of the growth temperature and growth pressure will be described later.

[0039] The surface of the substrate 10 may be treated with oxygen plasma before the formation of the non-doped layer 11. This can reduce the surface roughness of the substrate 10, making it easier to grow gallium oxide on the substrate 10.

[0040] Next, a non-doped layer 11 made of β-gallium oxide is formed on the substrate 10 by plasma-assisted molecular beam epitaxy (PAMBE). In the PAMBE method, a mixed gas containing oxygen and ozone is turned into plasma and supplied to the substrate 10, and gallium is evaporated and a molecular beam is irradiated onto the substrate 10. By turning the mixed gas containing oxygen and ozone into plasma, the ozone is decomposed to generate oxygen molecules and oxygen radicals. The oxygen radicals are formed by singlet oxygen atoms O( １ D) and triplet oxygen atom O( ３ P), and singlet oxygen atoms transition to triplet oxygen atoms at a predetermined rate. These oxygen radicals react with the gallium molecular beam on the substrate surface, causing β-gallium oxide crystal growth on the surface of the substrate 10.

[0041] The growth pressure is preferably 0.001 Pa or more and 0.01 Pa or less. The growth temperature (substrate temperature) is preferably 0° C. or more and 600° C. or less. If the growth temperature and growth pressure are within these ranges, the non-doped layer 11 can be grown with good crystallinity.

[0042] A mixed gas containing oxygen and ozone can be generated by using an ozonizer to convert oxygen into plasma and then converting part of the oxygen into ozone.

[0043] In the mixed gas containing oxygen and ozone, the ratio of ozone to the total of oxygen and ozone is preferably 10% by volume or more. Although there is no particular upper limit, when the mixed gas containing oxygen and ozone is generated using an ozonizer, it is usually 50% by volume or less. The mixed gas containing oxygen and ozone may be mixed with an inert gas such as Ar and supplied. This makes it easier to generate plasma.

[0044] Next, n-type layer 12 is formed on non-doped layer 11. The method for forming n-type layer 12 may be any conventionally known method, such as CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), sputtering, etc. Non-doped layer 11 and n-type layer 12 may be grown continuously using the PAMBE method similar to that used for non-doped layer 11.

[0045] Next, the gate electrode 13, the source electrode 14, and the drain electrode 15 are formed by a method such as vapor deposition on the n-type layer 12. In this way, the MESFET of the first embodiment is manufactured.

[0046] 2 is a cross-sectional view showing the configuration of an HFET according to Embodiment 2, taken along a direction perpendicular to the main surface of the substrate. The HFET according to Embodiment 2 includes a substrate 20, a non-doped layer 21 as a semiconductor layer, an n-type layer 22 as a second semiconductor layer, a barrier layer 23, a gate electrode 24, a source electrode 25, and a drain electrode 26. The n-type layer 22, the barrier layer 23, the gate electrode 24, the source electrode 25, and the drain electrode 26 together form an FET structure.

[0047] The substrate 20 is a substrate made of single crystal Si, and the other configurations are the same as those of the substrate 10 in the first embodiment.

[0048] The non-doped layer 21 is a layer made of non-doped β-gallium oxide and is provided directly on the substrate 20 without a buffer layer therebetween. The non-doped layer 21 is highly resistive, semi-insulating, or insulating. That is, the substrate 20 and the non-doped layer 21 are in contact with each other. The other configurations are the same as those of the non-doped layer 11 in the first embodiment.

[0049] The n-type layer 22 is a layer made of n-type β-gallium oxide provided on the non-doped layer 21. The n-type impurity concentration of the n-type layer 22 is, for example, 1×10 １７ ~1 x 10 ２１ cm －３ The thickness of the n-type layer 22 is, for example, 100 nm to 10 μm.

[0050] The barrier layer 23 is a semiconductor layer provided on and in contact with the n-type layer 22. The material of the barrier layer 23 may be any material as long as it has a band gap energy larger than that of the n-type layer, but a gallium oxide-based semiconductor is preferred. For example, an Al-based barrier layer 23 is formed by substituting Al for part of the Ga in gallium oxide. ２ｘ Ga ２（１－ｘ） O ３ (0<x<1) is used. In this case, the Al composition x is preferably 0.1 to 0.4. The barrier layer 23 may be undoped or may be n-type. The thickness of the barrier layer 23 is, for example, 5 to 200 nm.

[0051] The gate electrode 24 is an electrode provided on and in contact with the barrier layer 23. The gate electrode 24 is in Schottky contact with the barrier layer 23. The material of the gate electrode 24 is the same as that of the gate electrode 13 in the first embodiment.

[0052] The source electrode 25 and the drain electrode 26 are electrodes provided on and in contact with the barrier layer 23. The source electrode 25 and the drain electrode 26 are provided to face each other with the gate electrode 24 sandwiched therebetween in a plan view. The source electrode 25 and the drain electrode 26 are in ohmic contact with the barrier layer 23. The materials of the source electrode 25 and the drain electrode 26 are the same as those of the source electrode 14 and the drain electrode 15 in the first embodiment.

[0053] Although the gate structure of the HFET in the second embodiment is a Schottky gate type, an insulated gate HFET or a pn junction gate HFET can also be realized. In the case of an insulated gate type, the gate structure can be the same as that of the sixth embodiment described later. In the case of a pn junction gate type, the gate structure can be the same as that of the third embodiment described later.

[0054] Next, the operation of the HFET in embodiment 2 will be described. In embodiment 2, the barrier layer 23 is formed on the n-type layer 22 in contact therewith, forming a heterojunction. Therefore, two-dimensional electron gas is formed in the n-type layer 22 near the interface with the barrier layer 23. A current flows between the source electrode 25 and the drain electrode 26 using this two-dimensional electron gas as a channel.

[0055] Here, a depletion layer is formed in the barrier layer 23 immediately below the gate electrode 24 due to Schottky contact of the gate electrode 24 with the barrier layer 23. The range of this depletion layer can be controlled by applying a voltage to the gate electrode 24, and expanding the depletion layer can eliminate the two-dimensional electron gas immediately below the gate electrode 24. Therefore, the current between the source electrode 25 and the drain electrode 26 can be controlled by applying a voltage to the gate electrode 24. In this way, an HFET is realized in the second embodiment.

[0056] As described above, in the HFET according to the second embodiment, the non-doped layer 21 and the n-type layer 22 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 20 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction.

[0057] 3 is a cross-sectional view showing the configuration of a JFET according to Embodiment 3, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 3, the JFET according to Embodiment 3 includes a substrate 30, a non-doped layer 31 as a semiconductor layer, an n-type layer 32 as a second semiconductor layer, a p-type region 33, a gate electrode 34, a source electrode 35, and a drain electrode 36. The n-type layer 32, the p-type region 33, the gate electrode 34, the source electrode 35, and the drain electrode 36 form an FET structure.

[0058] The substrate 30 is a substrate made of single crystal Si. The crystal plane and the like are the same as those of the substrate 10 in the first embodiment.

[0059] The non-doped layer 31 is a layer made of non-doped β-gallium oxide and is provided directly on the substrate 30 without a buffer layer therebetween. The non-doped layer 31 is highly resistive, semi-insulating, or insulating. That is, the substrate 30 and the non-doped layer 31 are in contact with each other. The other configurations are the same as those of the non-doped layer 11 in the first embodiment.

[0060] The n-type layer 32 is a layer made of n-type β-gallium oxide provided on the non-doped layer 31. The n-type impurity concentration of the n-type layer 32 is, for example, 1×10 １７ ~1 x 10 ２１ cm －３ The thickness of the n-type layer 32 is, for example, 100 nm to 100 μm.

[0061] The p-type region 33 is a p-type semiconductor region provided in a partial region of the surface of the n-type layer 32. The p-type region 33 can be formed, for example, by implanting Ni ions into the surface of the n-type layer 32. When Ni ions are implanted into the surface of the n-type layer 32 made of β-gallium oxide, NiO is formed on the surface of the n-type layer 32. Since NiO is a p-type semiconductor, this becomes the p-type region 33. The thickness of the p-type region 33 is thinner than the n-type layer 32, and is, for example, 5 nm to 1 μm.

[0062] The gate electrode 34 is an electrode provided on and in contact with the p-type region 33. The gate electrode 34 is in Schottky contact with the p-type region 33. The material of the gate electrode 34 is the same as that of the gate electrode 13 in the first embodiment.

[0063] The source electrode 35 and the drain electrode 36 are electrodes provided on and in contact with the n-type layer 32. The source electrode 35 and the drain electrode 36 are provided so as to face each other with the gate electrode 34 sandwiched therebetween in a plan view. The source electrode 35 and the drain electrode 36 are in ohmic contact with the n-type layer 32. The materials of the source electrode 35 and the drain electrode 36 are the same as those of the source electrode 14 and the drain electrode 15 in the first embodiment.

[0064] Next, the operation of the JFET in embodiment 3 will be described. In embodiment 3, a pn junction is formed between the n-type layer 32 and the p-type region 33. Therefore, if a voltage is applied to the gate electrode 34 so that this pn junction is reverse biased, a depletion layer can be expanded from the pn junction interface, and the current between the source electrode 35 and the drain electrode 36 can be controlled. In this way, a JFET is realized in embodiment 3.

[0065] As described above, in the JFET according to the third embodiment, the non-doped layer 31 and the n-type layer 32 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 30 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction.

[0066] 4 is a cross-sectional view showing the configuration of a buried-gate FET according to the fourth embodiment, taken along a direction perpendicular to the main surface of the substrate. As shown in FIG. 4, the buried-gate FET includes a substrate 40, a low-concentration n-type layer 41 as a semiconductor layer, a high-concentration n-type layer 42 as a second semiconductor layer, a buried gate region 43, a source electrode 44, a drain electrode 46, a guard ring 45, and a gate electrode (not shown). Of these, the low-concentration n-type layer 41, the high-concentration n-type layer 42, the buried gate region 43, the source electrode 44, the drain electrode 46, and the gate electrode form an FET structure.

[0067] The substrate 40 is a high-concentration n-type single crystal Si substrate. The n-type impurity concentration is, for example, 1×10 １９ ~1 x 10 ２２ cm －３ The other configurations are the same as those of the substrate 10 in the first embodiment.

[0068] The low-concentration n-type layer 41 is a layer made of n-type β-gallium oxide, and is provided directly on the substrate 40 without a buffer layer therebetween. That is, the substrate 40 and the low-concentration n-type layer 41 are in contact with each other. The n-type impurity concentration of the low-concentration n-type layer 41 is, for example, 1×10 １５ ~1 x 10 １８ cm －３ The thickness is, for example, 0.1 to 10 μm. The configuration other than the n-type impurity concentration and thickness is the same as that of the non-doped layer 11 in the first embodiment.

[0069] The high-concentration n-type layer 42 is a layer made of n-type β-gallium oxide provided on the low-concentration n-type layer 41. The n-type impurity concentration of the high-concentration n-type layer 42 is higher than the n-type impurity concentration of the low-concentration n-type layer 41. The n-type impurity concentration of the high-concentration n-type layer 42 is, for example, 1×10 １８ ~1 x 10 ２２ cm －３ The thickness of the high-concentration n-type layer 42 is, for example, 100 nm to 10 μm.

[0070] The buried gate region 43 is a p-type region buried between the low-concentration n-type layer 41 and the high-concentration n-type layer 42. The buried gate region 43 is a layer made of p-type β-gallium oxide formed by selective growth. Alternatively, it may be realized by ion implantation, similar to the p-type region 33 in embodiment 3. As shown in FIG. 4 , a plurality of buried gate regions 43 are arranged at predetermined intervals in a direction parallel to the main surface of the substrate 40. The buried gate region 43 is exposed by etching in a region not shown and is connected to a gate electrode not shown. The gate electrode is in ohmic contact with the buried gate region 43. The buried gate region 43 and the gate electrode may be indirectly connected. The material of the gate electrode is the same as that of the source electrode 44 and the drain electrode 46.

[0071] The source electrode 44 is an electrode provided on and in contact with the high-concentration n-type layer 42. The source electrode 44 is in ohmic contact with the high-concentration n-type layer 42. The material of the source electrode 44 is the same as that of the source electrode 14 in the first embodiment.

[0072] The drain electrode 46 is an electrode provided in contact with the back surface (the surface opposite to the low-concentration n-type layer 41) of the substrate 40. The drain electrode 46 is in ohmic contact with the substrate 40. The material of the drain electrode 46 is the same as that of the drain electrode 15 in the first embodiment.

[0073] The guard ring 45 is provided in contact with the high-concentration n-type layer 42 and is annularly disposed in the peripheral region of the device. The guard ring 45 is in Schottky contact with the high-concentration n-type layer 42. The guard ring 45 is made of a material that forms a Schottky junction with the high-concentration n-type layer 42.

[0074] The buried gate FET of embodiment 4 has a structure in which a Schottky contact buried gate region 43 is buried in a semiconductor layer, and is conductive in the vertical direction. The operating principle is the same as that of the MESFET of embodiment 1. The region of the low-concentration n-type layer 41 and the high-concentration n-type layer 42 sandwiched between adjacent buried gate regions 43 forms a channel, and the current flowing through the channel can be controlled by a depletion layer extending from the buried gate region 43.

[0075] As described above, in the buried-gate FET according to the fourth embodiment, the low-concentration n-type layer 41 and the high-concentration n-type layer 42 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 40 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction.

[0076] 5 is a cross-sectional view showing the configuration of a bipolar transistor according to Embodiment 5, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 5, the bipolar transistor according to Embodiment 5 includes a substrate 50, a non-doped layer 51 as a semiconductor layer, a first n-type layer 52 as a second semiconductor layer, a second n-type layer 53, a p-type layer 54, a third n-type layer 55, an emitter electrode 56, a base electrode 57, a collector electrode 58, and sidewalls 59. The first n-type layer 52, the second n-type layer 53, the p-type layer 54, the third n-type layer 55, the emitter electrode 56, the base electrode 57, and the collector electrode 58 form a bipolar transistor structure.

[0077] The substrate 50 is a substrate made of single crystal silicon, and the other configurations are the same as those of the substrate 10 in the first embodiment.

[0078] The non-doped layer 51 is a layer made of non-doped β-gallium oxide and is provided directly on the substrate 50 without a buffer layer therebetween. That is, the substrate 50 and the non-doped layer 51 are in contact with each other. The non-doped layer 51 is highly resistive, semi-insulating, or insulating. The other configurations are the same as those of the non-doped layer 11 in the first embodiment.

[0079] The first n-type layer 52 is a layer made of n-type β-gallium oxide provided on the non-doped layer 51. The n-type impurity concentration of the first n-type layer 52 is, for example, 1×10 １８ ~1 x 10 ２１ cm －３ be.

[0080] The second n-type layer 53 is a layer made of n-type β-gallium oxide provided on the first n-type layer 52. The n-type impurity concentration of the second n-type layer 53 is lower than the n-type impurity concentration of the first n-type layer 52, and is, for example, 1×10 １６ ~1 x 10 １８ cm －３ is.

[0081] The p-type layer 54 is a layer made of p-type β-gallium oxide provided on the second n-type layer 53. A semiconductor other than β-gallium oxide may be used. For example, NiO may be used as in the third embodiment.

[0082] The third n-type layer 55 is a layer made of n-type β-gallium oxide provided on the p-type layer 54. The n-type impurity concentration of the third n-type layer 55 is higher than the n-type impurity concentration of the second n-type layer 53, and is, for example, 1×10 １８ ~1 x 10 ２１ cm －３ is.

[0083] A first groove reaching the first n-type layer 52 and a second groove reaching the p-type layer 54 are provided in a partial area of ​​the surface of the third n-type layer 55 .

[0084] The emitter electrode 56 is an electrode provided on the third n-type layer 55. The emitter electrode 56 is in ohmic contact with the third n-type layer 55. The material of the emitter electrode 56 is the same as that of the source electrode 14 in the first embodiment.

[0085] The base electrode 57 is an electrode provided on the p-type layer 54 exposed at the bottom surface of the second groove. The base electrode 57 is in ohmic contact with the p-type layer 54. The material of the p-type layer 54 is the same as that of the source electrode 14 in the first embodiment.

[0086] The collector electrode 58 is an electrode provided on the first n-type layer 52 exposed at the bottom surface of the first groove. The collector electrode 58 is in ohmic contact with the first n-type layer 52. The material of the collector electrode 58 is the same as that of the source electrode 14 in the first embodiment.

[0087] The sidewalls 59 are insulating films formed to cover the side surfaces of the third n-type layer 55 and the emitter electrode 56. The material of the sidewalls 59 is, for example, SiO ２ and Si ３ N ４ And so on.

[0088] As described above, in the bipolar transistor of the fifth embodiment, the non-doped layer 51, the first n-type layer 52, the second n-type layer 53, the p-type layer 54, and the third n-type layer 55 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 50 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction.

[0089] 6 is a cross-sectional view showing the configuration of a MISFET according to Embodiment 6, taken along a direction perpendicular to the main surface of a substrate. As shown in Fig. 6, the MISFET according to Embodiment 6 includes a substrate 60, a non-doped layer 61 as a semiconductor layer, an n-type layer 62 as a second semiconductor layer, a gate electrode 63, a source electrode 64, a drain electrode 65, and a gate insulating film 66. Of these, the n-type layer 62, the gate electrode 63, the source electrode 64, the drain electrode 65, and the gate insulating film 66 form an FET structure.

[0090] The substrate 60, the non-doped layer 61, and the n-type layer 62 are the same as the substrate 10, the non-doped layer 11, and the n-type layer 12 in the first embodiment.

[0091] The gate insulating film 66 is a layer made of an insulator and provided in contact with a partial region on the n-type layer 62. The material of the gate insulating film 66 is Al. ２ O ３ , Si ３ N ４ , SiO ２ , ZrO ２ , HfO ２, BeO, AlN, mixed crystals thereof, etc. Also, a laminate of a plurality of these materials may be used. Also, amorphous Si, amorphous SiC, polycrystalline GaN, etc. may be used.

[0092] The gate electrode 63 is an electrode provided on and in contact with the gate insulating film 66. The material of the gate electrode 63 is Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni / Au, Ni / Pt, Pt / Au, W / Au, Pt / Ti / Au, Pt / Au / Ni, Ti / Au / Ni, ITO, or the like.

[0093] The source electrode 64 and the drain electrode 65 are electrodes provided on and in contact with the n-type layer 62. The source electrode 64 and the drain electrode 65 are provided so as to face each other with the gate electrode 63 sandwiched therebetween in a plan view. The source electrode 64 and the drain electrode 65 are in ohmic contact with the n-type layer 62. The materials of the source electrode 64 and the drain electrode 65 are the same as those of the source electrode 14 and the drain electrode 15 in the first embodiment.

[0094] As described above, in the MISFET according to the sixth embodiment, the non-doped layer 61 and the n-type layer 62 are made of gallium oxide, which improves the breakdown voltage. Furthermore, since Si is used as the substrate 60, the diameter can be increased, which is advantageous in terms of mass productivity and cost reduction.

[0095] (Modifications) In the embodiments, a MESFET, an HFET, a JFET, a buried gate FET, a bipolar transistor, and a MISFET are shown, but the present disclosure is not limited to these field effect transistors and bipolar transistors. Any three-terminal electronic device in which a current or voltage between two terminals is controlled by another terminal may be used. For example, the present disclosure can also implement a metal oxide semiconductor field effect transistor (MOSFET), a thyristor, an insulated gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), a static induction transistor (SIT), a static induction thyristor, a heterojunction bipolar transistor (HBT), and the like. Furthermore, the present disclosure is applicable to both vertical and horizontal electronic devices.

[0096] The gallium oxide in each embodiment may be a gallium oxide-based semiconductor. Here, the gallium oxide-based semiconductor is a semiconductor in which a part of Ga in gallium oxide is replaced with Al or In (Al ２ｘ Ga ２ｙ In ２－２ｘ－２ｙ O ３ , 0≦x≦1, 0<y≦1). In addition, although gallium oxide is in the β phase in each embodiment, it may have a crystal structure other than the β phase. That is, five crystal structures of gallium oxide are known, namely, α, β, γ, δ, and ε, and any of these crystal structures may be used. For example, it may be the α phase. However, the β phase is preferred in terms of compatibility with the Si substrate.

[0097] Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present invention. This application is based on a Japanese patent application (Patent Application No. 2023-150629) filed on September 18, 2023, the contents of which are incorporated herein by reference.

[0098] 10, 20, 30, 40, 50, 60: Substrate 11, 21, 31, 51, 61: Non-doped layer (semiconductor layer) 12, 22, 32, 62: N-type layer (second semiconductor layer) 13, 24, 34, 63: Gate electrode 14, 25, 35, 44, 64: Source electrode 15, 26, 36, 46, 65: Drain electrode 23: Barrier layer 33: P-type region 41: Low-concentration N-type layer (semiconductor layer) 42: High-concentration N-type layer (second semiconductor layer) 43: Buried gate region 45: Guard ring 52: First N-type layer (second semiconductor layer) 53: Second N-type layer 54: P-type layer 55: Third N-type layer 56: Emitter electrode 57: Base electrode 58: Collector electrode 59: Sidewall 66: Gate insulating film

Claims

1. An electronic device comprising: a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with said substrate; a second semiconductor layer made of a gallium oxide-based semiconductor provided on said semiconductor layer or on said semiconductor layer; and a transistor structure including three electrodes.

2. The electronic device of claim 1, wherein the transistor structure is a field effect transistor structure.

3. The electronic device of claim 2, wherein said field effect transistor structure is a MESFET structure.

4. The electronic device according to claim 2, wherein the field effect transistor structure is a MISFET structure.

5. The electronic device of claim 2, wherein the field effect transistor structure is a JFET structure.

6. The electronic device of claim 2, wherein the field effect transistor structure is an HFET structure.

7. The electronic device of claim 1, wherein the transistor structure is a bipolar transistor structure.

8. The electronic device according to any one of claims 1 to 7, wherein the gallium oxide based semiconductor is β-gallium oxide.

9. The electronic device according to claim 8, wherein the primary surface of the substrate is a (100) surface.

10. The electronic device according to claim 9, wherein the primary surface of the semiconductor layer is a (100) surface.

11. The electronic device according to claim 8, wherein the [001] direction of the substrate and the [0-11] direction of the semiconductor layer coincide with each other.

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