Template substrate, method for producing same, semiconductor substrate, method for producing same, apparatus for producing template substrate, and method for producing semiconductor device

Abstract

The present invention reduces the silicon concentration of a nitride semiconductor region when the nitride semiconductor region is formed by using a template substrate. This template substrate comprises: a base substrate; a mask pattern located on the base substrate and including a silicon-containing silicon-based mask and a first opening; an aluminum-containing semiconductor mask located on the silicon-based mask; and a seed part having an Al-based semiconductor layer that includes a main component of the semiconductor mask and overlaps the first opening.

Description

Template substrate and method for manufacturing the same, semiconductor substrate and method for manufacturing the same, template substrate manufacturing apparatus, and semiconductor device manufacturing method

[0001] The present disclosure relates to a template substrate and the like.

[0002] Patent Document 1 discloses a method (ELO method) in which a mask pattern including a mask portion and an opening is formed on a base substrate including a seed layer, and a nitride semiconductor layer is laterally grown on the mask portion using the seed layer exposed in the opening as a growth starting point.

[0003] Japanese Patent Application Publication No. 2013-251304

[0004] In one aspect of the present disclosure, a template substrate includes a base substrate, a mask pattern located on the base substrate and including a first mask containing silicon and a first opening, a second mask located on the first mask and including aluminum and a semiconductor, and a seed portion having a semiconductor layer containing the main component of the second mask and overlapping the first opening.

[0005] FIG. 1 is a cross-sectional view showing a configuration of a template substrate according to an embodiment of the present disclosure. FIG. 2 is a plan view showing a configuration of a template substrate according to an embodiment of the present disclosure. FIG. 3 is a flowchart showing an example of a method for manufacturing a template substrate according to an embodiment of the present disclosure. FIG. 4 is a block diagram showing an apparatus for manufacturing a template substrate according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure. FIG. 6 is a plan view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure. FIG. 7 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 8 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing a schematic configuration of a template substrate according to Example 1. FIG. 10 is a cross-sectional view showing an example of a configuration of a base substrate. FIG. 11 is a cross-sectional view showing an example of a configuration of a template substrate. FIG. 12 is a cross-sectional view showing an example of lateral growth of a nitride semiconductor portion. FIG. 13 is a cross-sectional view showing a schematic configuration of a template substrate according to Example 2. FIG. 14 is a cross-sectional view showing a schematic configuration of a template substrate according to Example 3. FIG. 15 is a cross-sectional view showing a schematic configuration of a semiconductor substrate according to Example 4. FIG. 16 is a plan view showing a schematic configuration of a semiconductor substrate according to Example 4. FIG. 17 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to Example 4. FIG. 10 is a cross-sectional view showing another configuration of a semiconductor substrate in Example 5. FIG. 11 is a cross-sectional view showing another configuration of a semiconductor substrate in Example 5. FIG. 12 is a plan view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in Example 6. FIG. 13 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in Example 6. FIG. 14 is a schematic view showing an example of a configuration of an electronic device. FIG. 15 is a schematic view showing another example of a configuration of an electronic device.

[0006] [Template Substrate] FIG. 1 is a cross-sectional view illustrating the configuration of a template substrate according to an embodiment of the present disclosure. FIG. 2 is a plan view illustrating the configuration of a template substrate according to an embodiment of the present disclosure. As shown in FIGS. 1 and 2 , the template substrate TS includes a base substrate BS, a mask pattern 6 positioned on the base substrate BS and including a silicon-based mask 5 (sometimes referred to as a first mask) containing silicon and a first opening K1, a semiconductor mask SM (sometimes referred to as a second mask) positioned on the silicon-based mask 5 and including aluminum and a semiconductor, and a seed portion S having a semiconductor layer AS containing the main component of the semiconductor mask SM and overlapping the first opening K1. Below, we will describe a case where the main component of the semiconductor mask SM is a semiconductor containing aluminum. In this case, the semiconductor layer AS is referred to as an aluminum-based semiconductor layer AS (hereinafter abbreviated as an Al-based semiconductor layer AS). The main component refers to the component (molecule, single atom) with the largest content (in moles) of components (when a component contains only one component, that component is used). The semiconductor mask SM may be mainly composed of a nitride semiconductor, and the semiconductor mask SM and the Al-based semiconductor layer AS may contain aluminum gallium nitride (the composition ratio of gallium to aluminum does not matter) or aluminum nitride as their main components. By using the template substrate TS, a nitride semiconductor portion with a low silicon concentration can be obtained.

[0007] In the template substrate TS of this embodiment, the seed portion S may include a covering layer C that includes a nitride semiconductor and covers the upper surface AST of the Al-based semiconductor layer AS. The template substrate TS can be used to grow a GaN-based semiconductor by, for example, an epitaxial lateral overgrowth (ELO) method to form a semiconductor portion that includes a nitride semiconductor (nitride semiconductor portion). The template substrate TS can also be called a growth substrate.

[0008] A nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example, and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0009] The mask pattern 6 may include a first opening K1 and a second opening K2 adjacent to each other in the first direction (X direction), and a silicon-based mask 5 located between the first opening K1 and the second opening K2. The template substrate TS may have a first seed portion S1 overlapping the first opening K1 and a second seed portion S2 overlapping the second opening K2 located on a base substrate BS. In the template substrate TS of this embodiment, the first seed portion S1 may include a first covering layer C1 covering an upper surface AST of the first Al-based semiconductor layer AS1, and the second seed portion S2 may include a second covering layer C2 covering an upper surface AST of the second Al-based semiconductor layer AS2.

[0010] Hereinafter, the first opening K1 and the second opening K2 may be collectively referred to as opening K, the first Al-based semiconductor layer AS1 and the second Al-based semiconductor layer AS2 as Al-based semiconductor layer AS, the first seed portion S1 and the second seed portion S2 as seed portion S, and the first coating layer C1 and the second coating layer C2 as coating layer C.

[0011] 1, multiple layers are stacked on a main substrate 1, and the stacking direction (thickness direction) can be referred to as the "upward direction" (Z direction). In other words, the direction from the base substrate BS to the semiconductor mask SM is referred to as the "upward direction." Also, viewing a substrate-like object such as the template substrate TS with a line of sight parallel to the substrate normal (including perspective views) can be referred to as a "planar view."

[0012] 1, the mask pattern 6 is provided with first openings K1 and second openings K2 whose longitudinal directions are in a second direction (Y direction) perpendicular to the first direction (X direction). The number and shape of the openings K in the mask pattern 6 are not particularly limited. The mask pattern 6 may have a plurality of openings K periodically arranged in the <11-20> direction (a-axis direction) of the nitride semiconductor.

[0013] 1 , the base substrate BS may include a main substrate 1 and an underlayer 4 located on the main substrate 1. The template substrate TS may have an Al-based semiconductor layer AS located on the underlayer 4.

[0014] The base substrate BS is a substrate that serves as a support base (base) for various upper layers. The main substrate 1 may be, for example, a heterogeneous substrate having a lattice constant different from that of a nitride semiconductor. Examples of the heterogeneous substrate include a silicon substrate, a silicon carbide substrate, a sapphire substrate, an aluminum nitride substrate, and a ScAlMgO ４ Examples include a substrate.

[0015] In the template substrate TS of FIG. 1 , for example, aluminum nitride is used for the base layer 4, an inorganic compound film containing silicon is used for the silicon-based mask 5, the base layer 4 is exposed in the opening K, and a seed portion S is provided at a position overlapping the opening K in a planar view. Using the ELO method, a nitride semiconductor can be grown laterally (in the X direction) above a semiconductor mask SM located on the silicon-based mask 5, using the seed portion S as a growth starting point. The surface of the seed portion S may serve as a seed region J (the growth starting point of the semiconductor layer), and the surface (top surface SMT) of the semiconductor mask SM may serve as a growth inhibition region DA. The growth inhibition region DA and the seed portion S may be aligned in the a-axis direction of the nitride semiconductor. The width (length in the a-axis direction) of the growth inhibition region DA may be five times or more the width (length in the a-axis direction) of the top surface of the seed portion S.

[0016] The underlayer 4 has the function of, for example, reducing the possibility of the main substrate 1 and the seed portion S coming into contact and melting with each other. For example, if a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is located on the surface of the seed portion S facing the main substrate 1, the silicon substrate and the GaN-based semiconductor will melt when they come into contact, so providing the underlayer 4 between them reduces this melting. The underlayer 4 may have at least one of the effects of increasing the crystallinity of the seed portion S and alleviating internal stress in the seed portion S. The underlayer 4 may have a single-layer structure, a multilayer structure, or a multilayer structure including a periodic structure. For example, the underlayer 4 may be made of a GaN-based semiconductor containing Al, aluminum nitride (AlN), or silicon carbide (SiC).

[0017] In one embodiment, the template substrate TS may have a main substrate 1 that is any one of a silicon wafer, a silicon carbide wafer, or a sapphire wafer, and an underlayer 4 that includes aluminum nitride. The template substrate TS may have a mask pattern 6 that includes a second opening K2, and a silicon-based mask 5 and a semiconductor mask SM that are located between the first opening K1 and the second opening K2 in a plan view.

[0018] The silicon-based mask 5 may be, for example, a silicon oxide film or a silicon nitride film. The material of the silicon-based mask 5 may be silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxide (SiO ２ ), silicon oxynitride (SiON), etc. The silicon-based mask 5 may be a single layer film made of these materials, or may be a multilayer film (laminated film) made by combining these materials.

[0019] The Al-based semiconductor layer AS and the semiconductor mask SM may be formed, for example, as follows after forming a mask pattern 6 on the base substrate BS. That is, a film formation process is performed using a source gas of a material (a material containing aluminum) that undergoes relatively easy crystal growth on the surface of the base substrate BS exposed at the opening K but that undergoes relatively difficult crystal growth on the silicon-based mask 5. The Al-based semiconductor layer AS may be formed with high crystallinity by the crystal growth of the material on the surface of the base substrate BS exposed at the opening K, while the semiconductor mask SM may be formed with low crystallinity by the deposition of the material on the silicon-based mask 5. The Al-based semiconductor layer AS and the semiconductor mask SM may also be formed by a sputtering method or the like.

[0020] While the Al-based semiconductor layer AS and the semiconductor mask SM have the same main component, their properties differ due to the different growth conditions as described above. Therefore, the Al-based semiconductor layer AS may be thicker than the semiconductor mask SM. The Al-based semiconductor layer AS may have a thickness of, for example, 10 nm or more, or may have a thickness of 50 nm or more, with an upper limit of, for example, 1000 nm. The semiconductor mask SM may have a thickness of, for example, about 10 nm, or may have a thickness of 1 nm or more, with an upper limit of, for example, 100 nm. The ratio of the thickness of the Al-based semiconductor layer AS to the thickness of the semiconductor mask SM may be 5 or more, or may be 10 to 200.

[0021] Furthermore, since the semiconductor mask SM is formed on the silicon-based mask 5, on which crystal growth is difficult, it has a rougher surface than the Al-based semiconductor layer AS and the silicon-based mask 5. Therefore, the surface roughness of the semiconductor mask SM may be greater than the surface roughness of the Al-based semiconductor layer AS. The surface roughness of the semiconductor mask SM may be greater than the surface roughness of the silicon-based mask 5. The semiconductor mask SM may have lower crystallinity than the Al-based semiconductor layer AS. The semiconductor mask SM may include an amorphous structure. The surface roughness of the semiconductor mask SM and the Al-based semiconductor layer AS can be evaluated, for example, by capturing an electron microscope (TEM, etc.) image of a cross section of the template substrate TS perpendicular to the X or Y direction. For example, image analysis can confirm that the surface roughness of the semiconductor mask SM on the template substrate TS is greater than the surface roughness of the Al-based semiconductor layer AS. Furthermore, it can be confirmed that the surface roughness of the semiconductor mask SM on the template substrate TS is greater than the surface roughness of the silicon-based mask 5.

[0022] The Al-based semiconductor layer AS may have a shape that fills the first opening K1. Since the Al-based semiconductor layer AS has a shape that fills the opening K, the top surface AST of the Al-based semiconductor layer AS may be located higher than the top surface 5T of the silicon-based mask 5. In the template substrate TS, the semiconductor mask SM and the Al-based semiconductor layer AS may be connected to each other. The relative positional relationship between the top surface AST of the Al-based semiconductor layer AS and the top surface 5T of the silicon-based mask 5 may vary depending on the thickness of the silicon-based mask 5. In the example shown in FIG. 1 and other figures, the top surface AST of the Al-based semiconductor layer AS is located higher than the top surface 5T of the silicon-based mask 5, but this is not limiting, and the top surface AST of the Al-based semiconductor layer AS may be located lower than the top surface 5T of the silicon-based mask 5. By forming the semiconductor mask SM on the sidewall of the silicon-based mask 5 that forms the opening K, the semiconductor mask SM and the Al-based semiconductor layer AS may be connected to each other.

[0023] 1, the upper surface of the seed portion S may be the upper surface CT of the covering layer C. Without being limited to the example shown in Fig. 1, the template substrate TS may not be provided with the covering layer C, in which case the upper surface of the seed portion S may be the upper surface AST of the Al-based semiconductor layer AS. Furthermore, the template substrate TS may have the covering layer C connected to the surface of the base substrate BS exposed at the opening K, and the Al-based semiconductor layer AS may be located on the covering layer C.

[0024] In the template substrate TS, the upper surface (upper surface CT or upper surface AST) of the seed portion S may be located at a higher position than the upper surface SMT of the semiconductor mask SM. The relative positional relationship between the upper surface AST of the Al-based semiconductor layer AS and the upper surface SMT of the semiconductor mask SM may vary depending on the thickness of the silicon-based mask 5. By providing the seed portion S with the covering layer C, it is possible to easily position the upper surface (upper surface CT or upper surface AST) of the seed portion S at a higher position than the upper surface SMT of the semiconductor mask SM.

[0025] The surface roughness of the covering layer C may be smaller than the surface roughness of the Al-based semiconductor layer AS. A small surface roughness of the covering layer C makes it easier to effectively improve the quality of the semiconductor layer grown using the seed portion S as a growth starting point. The covering layer C may be contained within the opening K in plan view, or may slightly protrude laterally from the opening K. As described above, the surface roughness of the covering layer C and the Al-based semiconductor layer AS can also be evaluated based on an electron microscope (TEM, etc.) image taken of a cross section perpendicular to the X direction or Y direction of the template substrate TS, for example.

[0026] The covering layer C may not contain aluminum, or may have a lower aluminum content than the Al-based semiconductor layer AS. The covering layer C may be made of a material that grows on the Al-based semiconductor layer AS and serves as a growth starting point for the semiconductor layer. For example, a GaN-based semiconductor such as GaN, AlGaN, AlInN, or AlGaInN may be used for the covering layer C. The method for forming the covering layer C is not particularly limited, and the covering layer C may be formed using, for example, an MOCVD method, a sputtering method, a PSD (Pulse Sputter Deposition) method, or a laser ablation method.

[0027] Furthermore, the covering layer C may be thicker than the Al-based semiconductor layer AS. Since the semiconductor mask SM is also formed during the formation of the Al-based semiconductor layer AS, increasing the thickness of the Al-based semiconductor layer AS also increases the thickness of the semiconductor mask SM. If the thick semiconductor mask SM interferes with the lateral growth of the semiconductor layer, which begins at the seed portion S, the quality of the semiconductor layer may be reduced. By adjusting the height of the upper surface of the seed portion S using the covering layer C, the thickness of the Al-based semiconductor layer AS can be made relatively thin, and as a result, the thickness of the semiconductor mask SM can be made relatively thin. The covering layer C may have a thickness of, for example, 10 nm or more, or may have a thickness of 100 nm or more, with an upper limit of, for example, 3 μm. The ratio of the thickness of the covering layer C to the thickness of the Al-based semiconductor layer AS may be greater than 1, and may be 1.5 to 100.

[0028] When the template substrate TS in this embodiment is used to grow a semiconductor layer laterally using the seed portion S as the growth starting point, the semiconductor mask SM is located on the silicon-based mask 5, so that the amount of silicon incidentally incorporated (auto-doped) into the semiconductor layer from the silicon-based mask 5 can be effectively reduced.

[0029] The constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may be silicon-free or substantially silicon-free. The term "substantially silicon-free" for a certain material means that trace amounts of silicon may be unavoidably mixed into the material due to unavoidable impurities in the source gas or contamination within the film-forming apparatus. Furthermore, the constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may contain silicon within an acceptable concentration range as long as they have the function of reducing the amount of silicon introduced into the semiconductor layer from the silicon-based mask 5 when the semiconductor mask SM is positioned on top of the silicon-based mask 5. For example, the constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may contain silicon in an amount of 1% or less by molar ratio in their composition.

[0030] The silicon-based mask 5 may include at least one of silicon nitride and silicon oxide, and the semiconductor mask SM and the Al-based semiconductor layer AS may include aluminum gallium nitride. In the aluminum gallium nitride, the Al composition ratio to Ga and Al may be 0.01 or greater. Furthermore, in the aluminum gallium nitride, the Al composition ratio to Ga and Al may be 0.01 or greater and 1.0 or less, or 0.05 or greater and 0.5 or less. By increasing the Al composition ratio in the aluminum gallium nitride, the thickness of the semiconductor mask SM formed on the silicon-based mask 5 becomes relatively large. As a result, the effect of reducing the amount of silicon incidentally incorporated into the semiconductor layer from the silicon-based mask 5 can be enhanced. The aluminum gallium nitride may have a graded structure in which the Al composition gradually changes in the thickness direction. The semiconductor mask SM and the Al-based semiconductor layer AS may be primarily composed of aluminum gallium nitride. The semiconductor mask SM and the Al-based semiconductor layer AS may be made of the same material (e.g., an aluminum-based nitride semiconductor such as AlGaN).

[0031] The constituent materials of the semiconductor mask SM and the Al-based semiconductor layer AS are not particularly limited as long as they have a seed region J in the seed portion S as described above and the surface of the semiconductor mask SM functions as a growth inhibition region DA, but examples thereof include AlGaN, AlInN, AlGaInN, and AlN.

[0032] [Manufacturing of Template Substrate] Figure 3 is a flowchart illustrating an example of a method for manufacturing a template substrate according to an embodiment of the present disclosure. Figure 4 is a cross-sectional view illustrating an example of a method for manufacturing a template substrate according to an embodiment of the present disclosure. The method for manufacturing the template substrate illustrated in Figures 3 and 4 includes the steps of: preparing a base substrate BS (step S10); forming a silicon-based mask 5 containing silicon and a mask pattern 6 including a first opening K1 located on the base substrate BS (step S20); and forming a semiconductor mask SM containing aluminum located on the silicon-based mask 5; and forming a seed portion S having an Al-based semiconductor layer AS containing a main component of the semiconductor mask SM and overlapping the first opening K1 (step S30). As shown in Figure 3 , the method for manufacturing the template substrate may include the steps of forming the semiconductor mask SM and the Al-based semiconductor layer AS (step S31) and forming a covering layer C containing a nitride semiconductor and covering an upper surface AST of the Al-based semiconductor layer AS (step S32).

[0033] 5 is a block diagram showing a template substrate manufacturing apparatus according to an embodiment of the present disclosure. The template substrate manufacturing apparatus 30 includes an apparatus M10 that performs step S10 of FIG. 3, an apparatus M20 that performs step S20 of FIG. 3, an apparatus M30 that performs step S30 of FIG. 3, and a control device MC that controls the apparatuses M10, M20, and M30. The apparatuses M10 and M20 may each include a sputtering apparatus. The apparatus M30 may include a metal-organic chemical vapor deposition (MOCVD) apparatus. The apparatus M30 may perform the above-described steps S31 and S32.

[0034] [Semiconductor Substrate] Fig. 6 is a cross-sectional view showing the configuration of a semiconductor substrate according to an embodiment of the present disclosure. Fig. 7 is a plan view showing the configuration of a semiconductor substrate according to an embodiment of the present disclosure. As shown in Figs. 6 and 7, the semiconductor substrate 10 includes a template substrate TS, and a first nitride semiconductor portion 8A located above a first opening K1 and a semiconductor mask SM.

[0035] The first nitride semiconductor portion 8A contains a nitride semiconductor as a main component. The first nitride semiconductor portion 8A may be doped (e.g., n-type containing donors) or non-doped. The semiconductor substrate refers to a substrate containing a nitride semiconductor, and the base substrate BS of the template substrate TS may contain a semiconductor other than a nitride semiconductor (e.g., silicon, silicon carbide), or may not contain a semiconductor. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate.

[0036] As described above, in the template substrate TS, the surface (upper surface SMT) of the semiconductor mask SM has a relatively low crystallinity and therefore functions as a growth inhibition region DA. On the other hand, the surface of the seed portion S is configured with an Al-based semiconductor layer AS containing the main component of the semiconductor mask SM or a covering layer C containing a nitride semiconductor, and has a relatively high crystallinity, so functions as a seed region J. In the template substrate TS, the growth inhibition region DA and the seed region J (surface of the seed portion S), which are aligned in the first direction (X direction), may each have a shape with the second direction (Y direction) as their longitudinal direction.

[0037] In the semiconductor substrate 10, the first nitride semiconductor portion 8A has a first base portion B1 located above the first seed portion S1 and a first wing portion F1 connected to the first base portion B1 and located above the semiconductor mask SM. Of the first nitride semiconductor portion 8A, the first base portion B1 located above the first seed portion S1 (in other words, above the first opening K1) is a dislocation inheritance portion with many threading dislocations, while the first wing portion F1 located above the semiconductor mask SM is a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion. The first wing portion F1 may have a threading dislocation density that is 1 / 10 or less of that of the first base portion B1, which is a dislocation inheritance portion. The threading dislocation density of the first wing portion F1, which is a low-defect portion, may be, for example, 5×10 ６ [pcs / cm ２ ] can be as follows.

[0038] The threading dislocations are dislocations (defects) that extend in the c-axis direction (<0001> direction) of the first nitride semiconductor portion 8A (nitride semiconductor portion 8 described later). The threading dislocation density can be determined, for example, by performing CL (Cathode Luminescence) measurement on the surface of the first nitride semiconductor portion 8A and counting the number of black dots in the CL measurement image.

[0039] In the semiconductor substrate 10 of this embodiment, the mask pattern 6 may include the second opening K2, and in plan view, the silicon-based mask 5 and the semiconductor mask SM may be located between the first and second openings K1 and K2, and a second nitride semiconductor portion 8C may be located above the second opening K2 and the semiconductor mask SM, with a gap GP located between the first and second nitride semiconductor portions 8A and 8C. The second nitride semiconductor portion 8C has a second base portion B2 located above the second seed portion S2 and a second wing portion F2 connected to the second base portion B2 and located above the semiconductor mask SM. The first wing portion F1 and the second wing portion F2 may be aligned in the first direction (X direction) with the gap GP interposed therebetween.

[0040] In the following, the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C may be collectively referred to as the nitride semiconductor portion 8, the first base portion B1 and the second base portion B2 may be collectively referred to as the base portion B, and the first wing portion F1 and the second wing portion F2 may be collectively referred to as the wing portion F.

[0041] The first direction (X direction) may be the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8 (nitride semiconductor crystal such as GaN). The second direction (Y direction) orthogonal to the first direction may be the m-axis direction (<1-100> direction) of the nitride semiconductor portion 8. The thickness direction (Z direction) of the semiconductor substrate 10 may be the c-axis direction (<0001> direction) of the nitride semiconductor portion 8.

[0042] In the semiconductor substrate 10 of this embodiment, the nitride semiconductor portion 8 (first nitride semiconductor portion 8A) has a silicon concentration of 5×10 １８ / cm ３The nitride semiconductor portion 8 is formed by lateral growth using the seed portion S as a growth starting point, with the semiconductor mask SM positioned on the silicon-based mask 5. This makes it possible to suppress the phenomenon in which impurities liberated from the silicon-based mask 5 are taken into the nitride semiconductor portion 8 during growth. Therefore, the amount of silicon liberated from the silicon-based mask 5 and taken into the nitride semiconductor portion 8 is effectively reduced.

[0043] Furthermore, for example, if impurities segregate on the surface of the nitride semiconductor portion 8, problems may arise, such as making it difficult to form an upper layer film on the nitride semiconductor portion 8 or generating defects at the interface with the upper layer film. If the film formation conditions for lateral growth are restricted to avoid these problems, it may become difficult to form a semiconductor portion with a large aspect ratio (ratio of width to thickness), reducing the degree of freedom in semiconductor portion shape for device design. In contrast, the semiconductor substrate 10 of this embodiment includes the semiconductor mask SM located on the silicon-based mask 5, thereby effectively reducing the possibility of impurities liberated from the silicon-based mask 5 segregating on the surface of the nitride semiconductor portion 8. The aspect ratio of the nitride semiconductor portion 8 may be, for example, 5.0 or more, 10.0 or more, or 20.0 or more.

[0044] As will be described later, when an active section (active layer) including, for example, a light emitting section is formed above the nitride semiconductor section 8, the light emitting section can be arranged above the wing section F, which is a low defect section (so as to overlap with the wing section F in a planar view).

[0045] 8 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. As shown in FIG. 8, the method for manufacturing a semiconductor substrate 10 includes a step S110 of preparing a template substrate TS and a step S120 of forming a first opening K1 and a first nitride semiconductor portion 8A located above a semiconductor mask SM.

[0046] FIG. 9 is a flowchart illustrating an example of a method for manufacturing a semiconductor device 25 according to an embodiment of the present disclosure. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device 25 according to an embodiment of the present disclosure. As shown in FIGS. 9 and 10 , a semiconductor substrate 10 may be located on a first nitride semiconductor portion 8A and include a functional layer (device layer) 9 including an active layer. The method for manufacturing the semiconductor device 25 includes a step S210 of preparing a semiconductor substrate 10 and a step S220 of forming a functional layer 9 located on the first nitride semiconductor portion 8A and including an active layer. The functional layer 9 may include an active layer, a p-type layer, and electrodes (e.g., an anode and a cathode). The active layer may have a quantum well structure. The nitride semiconductor portion 8, the active layer, and the p-type layer may be GaN-based semiconductors, and these may be formed consecutively in an MOCVD apparatus.

[0047] In the semiconductor substrate 10, the width of the gap GP between the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C may be 10 μm or less, 4 μm or less, or 3 μm or less. By having the gap GP, the semiconductor substrate 10 can reduce the internal stress of the nitride semiconductor portion 8. This can reduce cracks and defects (dislocations) that occur in the nitride semiconductor portion 8. This effect is particularly effective when the main substrate 1 is a heterogeneous substrate.

[0048] Specific examples of the semiconductor device 25 include a light emitter (such as an LED chip or a semiconductor laser chip), a light emitting element in which a light emitter is submounted, a light emitting module in which a light emitting element is packaged, etc. The semiconductor device is not limited to a light emitting semiconductor device, and may be, for example, a light receiving element (photo diode) or a transistor (including a power transistor or a high electron mobility transistor).

[0049] 11 is a cross-sectional view schematically illustrating the configuration of a template substrate in Example 1. As shown in Fig. 11 , the template substrate TS in Example 1 includes a base substrate BS, a mask pattern 6 located on the base substrate BS, a semiconductor mask SM located on a silicon-based mask 5, and a seed portion S overlapping with an opening K.

[0050] 12 is a cross-sectional view showing an example of the configuration of a base substrate. The base substrate BS may include a main substrate 1 and an underlayer 4 on the main substrate 1. The base substrate BS may also have a metal layer (Al layer) between the main substrate 1 and the underlayer 4. The Al layer and an AlN layer serving as the underlayer 4 may be formed successively by sputtering. The base substrate BS may be formed of a free-standing single-crystal substrate (e.g., a wafer cut from a bulk crystal) of GaN, SiC, or the like, in which case a mask pattern 6 may be disposed on the single-crystal substrate.

[0051] The main substrate 1 may be a silicon substrate, a silicon carbide substrate (4H—SiC, 6H—SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, or the like. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, or the 6H—SiC (0001) or 4H—SiC (0001) surface of a SiC substrate. The main substrate 1 may also be 3C-SiC. These are merely examples, and the main substrate 1 may have a material and a surface orientation that satisfy the following two conditions; the specific material and surface orientation of the main substrate 1 are not necessarily limited. That is, the main substrate 1 may be, first, capable of manufacturing a template substrate TS by forming a seed portion S including a mask pattern 6, a semiconductor mask SM, and an Al-based semiconductor layer AS above a base substrate BS including the main substrate 1. The main substrate 1 may be, second, capable of growing a nitride semiconductor portion 8 using the template substrate TS. By using an inexpensive substrate as the main substrate 1, the manufacturing costs of the template substrate TS and the semiconductor substrate 10 can be effectively reduced.

[0052] The underlayer 4 may be a GaN-based semiconductor containing aluminum, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. An AlN layer, which is an example of the underlayer 4, can be formed to a thickness of approximately 10 nm to 5 μm using, for example, an MOCVD apparatus. The underlayer 4 may also be a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). When a silicon substrate is used as the main substrate 1, it is desirable that the underlayer 4 in contact with the silicon substrate does not contain gallium to suppress meltback. The underlayer 4 may also be formed by a sputtering method. Deposition using a sputtering apparatus (such as pulse sputter deposition (PSD) or pulse laser deposition (PLD)) can improve the efficiency of the manufacturing process.

[0053] The mask pattern 6 on the template substrate TS is formed on the base substrate BS using a material that suppresses vertical growth (growth in the c-axis direction) of the nitride semiconductor. A low-crystalline semiconductor mask SM is then formed on the silicon-based mask 5, and a seed portion S is positioned so as to fill the opening K. This allows lateral growth (e.g., growth in the a-axis direction) of the nitride semiconductor from the seed portion S over the semiconductor mask SM. In the mask pattern 6, the silicon-based mask 5 can be, for example, a single-layer film including one of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiON), or a stacked film including at least two of these. The thickness of the silicon-based mask 5 can be, for example, 0.1 nm or more and 5 μm or less, for example, 10 nm or more and 1 μm or less. The width Wm (size in the X direction) of the silicon-based mask 5 can be, for example, 10 μm or more and 20 μm or more and 500 μm or less.

[0054] The opening K of the mask pattern 6 may have a longitudinal shape with the first direction (X direction) as its width direction and the second direction (Y direction) as its longitudinal direction. The mask pattern 6 may have a plurality of openings K arranged in the first direction. The opening K may have a tapered shape (a shape in which the width narrows downward). The width Wk of the opening K may be, for example, 0.1 μm or more and 20 μm or less. The width Wk of the opening K may be smaller than the width Wm of the silicon-based mask 5. The ratio of the thickness of the silicon-based mask 5 to the width Wk (size in the X direction) of the opening K may be 3.0 or less. The smaller the width Wk of the opening K, the fewer the number of threading dislocations propagating from the opening K to the nitride semiconductor portion 8. Furthermore, the wing portion F (low-defect portion) may be larger.

[0055] In the template substrate TS, the seed portion S is positioned so as to fill the opening K of the mask pattern 6. The seed portion S is formed above the main substrate 1 and serves as a starting point for the growth of the nitride semiconductor portion 8. The seed portion S includes at least an Al-based semiconductor layer AS and may also have a covering layer C (see FIG. 1). The top surface ST of the seed portion S is higher than the top surface SMT of the semiconductor mask SM and has a relatively high degree of flatness. This makes it easier to improve the quality of the nitride semiconductor portion 8 grown from the seed portion S. The seed portion S may be contained within the opening K in a plan view, or may protrude slightly laterally beyond the opening K.

[0056] The Al-based semiconductor layer AS included in the seed portion S and the semiconductor mask SM are made of the same material. In the first embodiment, the aluminum-containing material is Al Ｘ Ga １－Ｘ N (X: 0.05 or more) can be used. For example, the thickness of the semiconductor mask SM can be set to about 10 nm, and the thickness of the Al-based semiconductor layer AS can be set to about 300 nm.

[0057] FIG. 13 is a cross-sectional view showing an example of the configuration of a template substrate. As shown in FIG. 13 , the template substrate TS may have a configuration in which an underlayer 4 (e.g., AlN) and a mask pattern 6 are formed in this order on a main substrate 1 (e.g., a silicon substrate). Alternatively, the template substrate TS may have a configuration in which a multi-layer underlayer 4 (including a lower layer 2 and an upper layer 3) and a mask pattern 6 are formed in this order on the main substrate 1. The underlayer 4 may be formed locally (e.g., in a stripe pattern) so as to overlap with the opening K of the mask pattern 6 in a planar view. The template substrate TS may have a configuration in which the mask pattern 6 is formed on the main substrate 1 (e.g., a SiC bulk crystal substrate or a GaN bulk crystal substrate). The template substrate TS has a seed portion S at a position overlapping the opening K, and a semiconductor mask SM is positioned on a silicon-based mask 5.

[0058] For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the upper layer 3, a lower layer 2 including at least one of an AlN layer and a SiC (silicon carbide) layer may be provided to reduce the possibility of the two (the main substrate and the seed portion) fusing together. The lower layer 2 improves the crystallinity and flatness of the upper layer 3. The lower layer 2 may be planar as shown in FIG. 13 or patterned. The thickness of the lower layer 2 may be, for example, approximately 10 nm to 500 nm. The silicon carbide used for the lower layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (4C-SiC).

[0059] The upper layer 3 can be made of a GaN-based semiconductor, AlN, SiC, or the like. The presence of the upper layer 3 can improve the crystallinity and flatness of the seed portion S. The upper layer 3 can be made of a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN layer, or the like formed at a low temperature (500°C or less). The thickness of the upper layer 3 can be approximately 10 nm to 500 nm. At least one of the lower layer 2 (e.g., aluminum nitride) and the upper layer 3 (e.g., GaN-based semiconductor) can also be formed using a sputtering device.

[0060] The underlayer 4 may include a strain relaxation layer. Examples of the strain relaxation layer include an AlGaN superlattice structure and a graded structure in which the Al composition of AlGaN changes stepwise. The strain relaxation layer can relieve stress in the longitudinal direction of the nitride semiconductor portion 8. At least one of the lower layer portion 2 and the upper layer portion 3 may include a strain relaxation layer.

[0061] When a main substrate 1 that does not fuse with the upper layer 3 is used, it is possible to configure the structure without providing the lower layer 2. Also, when an upper layer 3 that is less reactive with the main substrate 1 is used, it is possible to configure the structure without providing the lower layer 2. Similarly, when the seed portion S and the main substrate 1 are made of materials that do not fuse with each other, it is possible to configure the structure without providing the underlayer 4.

[0062] Examples of materials for forming the seed region J (see FIG. 2) in the seed portion S include GaN-based semiconductors, aluminum nitride (AlN), silicon carbide (SiC), and graphene. Silicon carbide is preferably hexagonal 6H-SiC or 4H-SiC. The seed portion S may contain a nitride semiconductor formed at a low temperature of 600°C or less. This can reduce warping of the semiconductor substrate 10 due to stress in the seed portion S. The seed portion S can also be formed using a sputtering device. Using a sputtering device has the advantages of low-temperature film formation, large-area film formation, and reduced costs.

[0063] As an example of the template substrate TS, a silicon substrate is used as the main substrate 1, an AlN layer (about 30 nm to 300 nm, for example, 150 nm) is used as the lower layer 2 of the underlayer 4, a GaN-based graded layer is used as the underlayer 4, and a silicon oxide film (SiO ２ The GaN graded layer may be, for example, a first layer of Al ０．６ Ga ０．４ It may include an N layer (eg, 300 nm) and a second GaN layer (eg, 1 to 2 μm).

[0064] For example, a silicon oxide film having a thickness of approximately 100 nm to 4 μm (preferably approximately 150 nm to 2 μm) is formed on the entire surface of the underlayer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned using photolithography to form a resist with multiple stripe-shaped openings. Then, portions of the silicon oxide film are removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form multiple openings K, and the resist is then removed by organic cleaning to form the mask pattern 6. The silicon-based mask 5 can also be formed using a sputtering device or an electron beam deposition (EBD) device.

[0065] Here, a small amount of silicon oxide film may decompose and evaporate during the formation of the nitride semiconductor portion 8, and may be incorporated into the nitride semiconductor portion 8. However, in the template substrate TS, by having a semiconductor mask SM (for example, a low-crystalline AlGaN layer) on the silicon-based mask 5, the amount of silicon incorporated into the nitride semiconductor portion 8 can be effectively reduced.

[0066] Since silicon nitride and silicon oxynitride films are less likely to decompose or evaporate under high temperature conditions than silicon oxide films, the silicon-based mask 5 may be a single-layer film of silicon nitride or silicon oxynitride, or may be a laminate film in which a silicon oxide film and a silicon nitride film are formed in this order on the base substrate BS. Also, the oxygen and nitrogen compositions of SiON may be controlled to form a desired oxynitride film.

[0067] For example, the silicon-based mask 5 may be a silicon oxide film (SiO ２ A layered mask in which a silicon oxide film (SiN) and a silicon nitride film (SiN) are formed in this order can be used. The silicon oxide film and the silicon nitride film are each formed using a CVD (plasma enhanced chemical vapor deposition) method, and the silicon oxide film can be formed to a thickness of, for example, 0.3 μm, and the silicon nitride film can be formed to a thickness of, for example, 70 nm. As another example, the silicon nitride film can be formed using a sputtering device or a PECVD device. The thickness of the silicon nitride film can be about 5 nm to 4 μm.

[0068] For example, by using a GaN substrate (bulk crystal of GaN) or a 6H—SiC substrate as the main substrate 1, the main substrate 1 can be used as the base substrate BS without providing the underlayer 4. In this case, a mask pattern 6 can be formed on the main substrate 1, and a seed portion S can be formed so as to connect to the upper surface of the main substrate 1 exposed at the opening K.

[0069] 14 is a cross-sectional view showing an example of lateral growth of a nitride semiconductor portion. In this example, a mask pattern 6 has a tapered opening K. The semiconductor substrate 10 in Example 1 has a first nitride semiconductor portion 8A and a second nitride semiconductor portion 8C formed by the ELO method above a template substrate TS.

[0070] The nitride semiconductor portion 8 can be grown laterally as follows. An initial growth portion SL may be formed on the seed portion S positioned so as to overlap the opening K, and then the nitride semiconductor portion 8 may be grown laterally from the initial growth portion SL. The initial growth portion SL serves as the starting point for the lateral growth of the nitride semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the nitride semiconductor portion 8 in the Z direction (c-axis direction) or the X direction (a-axis direction). The initial growth portion SL may have a thickness of, for example, 0.5 μm or more and 4.0 μm or less.

[0071] 14 , the back surface portion BP of the nitride semiconductor portion 8 is in contact with the semiconductor mask SM, but this is not limiting, and the semiconductor substrate 10 may have a gap between the back surface portion BP and the semiconductor mask SM. The first nitride semiconductor portion 8A may have a first base portion B1 located above the opening K and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located above the gap. When the top surface ST of the seed portion S is higher than the top surface SMT of the semiconductor mask SM, depending on the position of the top surface ST, the initial growth portion SL may not be in contact with the semiconductor mask SM on the side surface of the seed portion S, and the nitride semiconductor portion 8 can grow laterally from the initial growth portion SL.

[0072] The covering layer C (see FIG. 6 ) on the seed portion S may function as the initial growth portion SL. For example, the nitride semiconductor as the covering layer C may be formed so that the seed portion S protrudes from the silicon-based mask 5, and the nitride semiconductor portion 8 can be grown laterally from the covering layer C.

[0073] In the semiconductor substrate 10, by adjusting the growth conditions, the nitride semiconductor portion 8 can be grown laterally at high speed and with high crystallinity while suppressing growth in the c-axis direction (thickness direction). This allows the nitride semiconductor portion 8 (crystal of a nitride semiconductor such as GaN) with low defects to be formed thinly and widely at low cost, and also reduces the consumption of raw materials.

[0074] For the wing portion F, the ratio (WF / d1) of the width WF (size in the X direction) to the thickness d1 can be, for example, 2.0 or more. WF / d1 can be 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By making WF / d1 2.0 or more, the internal stress of the nitride semiconductor portion 8 can be easily reduced. As a result, warpage of the wafer can be reduced. The width WF of the wing portion F may be, for example, 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The thickness d1 may be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

[0075] In Example 1, the width Wm of the silicon-based mask 5 was 50 μm, the width Wk of the opening K was 5 μm, the lateral width of the nitride semiconductor portion 8 was 53 μm, the width (size in the X direction) of the wing portion F was 24 μm, and the layer thickness of the nitride semiconductor portion 8 was 5 μm. The aspect ratio of the nitride semiconductor portion 8 was 53 μm / 5 μm=10.6, which is an extremely high aspect ratio.

[0076] Second Embodiment FIG. 15 is a cross-sectional view schematically illustrating the configuration of a template substrate according to a second embodiment. As shown in FIG. 15 , the template substrate TS according to the second embodiment does not need to have a covering layer C on the seed portion S. The template substrate TS may have an exposed Al-based semiconductor layer AS. For example, by using AlGaN as the constituent material of the semiconductor mask SM and the Al-based semiconductor layer AS, the Al-based semiconductor layer AS can be an AlGaN layer with relatively high crystallinity. The nitride semiconductor portion 8 can be grown using this Al-based semiconductor layer AS as a growth starting point.

[0077] 15, the upper surface AST of the Al-based semiconductor layer AS is higher than the upper surface SMT of the semiconductor mask SM, but this is not limiting, and the upper surface AST may be lower than the upper surface SMT. The upper surface AST may be lower than the upper surface 5T of the silicon-based mask 5. Using the upper surface AST of the Al-based semiconductor layer AS as a seed region J, the nitride semiconductor portion 8 can be grown by the ELO method.

[0078] 16 is a cross-sectional view schematically illustrating the configuration of a template substrate in Example 3. As shown in Fig. 16, in Example 3, the seed portion S may include a covering layer C located on a base substrate BS and an Al-based semiconductor layer AS covering an upper surface CT of the covering layer C. The upper surface CT of the covering layer C may be located lower or higher than the upper surface SMT of the semiconductor mask SM.

[0079] The template substrate TS in Example 3 may be manufactured, for example, by forming a mask pattern 6 on a base substrate BS, then growing a coating layer C on the surface of the base substrate BS exposed at, for example, an opening K, and then forming an Al-based semiconductor layer AS and a semiconductor mask SM.

[0080] As in the second embodiment, for example, by using AlGaN as the constituent material of the semiconductor mask SM and the Al-based semiconductor layer AS, the nitride semiconductor portion 8 can be grown using the Al-based semiconductor layer AS as a growth starting point.

[0081] Example 4 Fig. 17 is a cross-sectional view schematically showing the configuration of a semiconductor substrate in Example 4. Fig. 18 is a cross-sectional view schematically showing the configuration of a semiconductor substrate in Example 4. In Fig. 17, a black dot shown at the position indicated by the lead line of symbol JD indicates a space (gap JD) between the wing portion F and the template substrate TS.

[0082] As shown in FIGS. 17 and 18 , in the semiconductor substrate 10 of Example 4, a gap JD may exist between the semiconductor mask SM and the first nitride semiconductor portion 8A. The gap JD can also be considered a space sandwiched between the growth inhibition region DA and the first wing portion F1. The first wing portion F1 is spaced apart from the semiconductor mask SM, which functions as the growth inhibition region DA. The seed region J (the upper surface ST of the seed portion S) is located above the growth inhibition region DA. The first nitride semiconductor portion 8A has a first base portion B1 located on the seed portion S and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA across the gap JD. The first wing portion F1 may have an edge E1 located above the semiconductor mask SM.

[0083] The semiconductor substrate 10 may include a growth inhibiting film 7 in contact with the seed portion S at a position above the semiconductor mask SM. The growth inhibiting film 7 may be in contact with the upper surface SMT (growth inhibiting region DA) of the semiconductor mask SM. The growth inhibiting film 7 may also be in contact with the side surface SS of the seed portion S. This inhibits the growth of the nitride semiconductor portion 8 from the side surface SS, making it easier to form a void JD.

[0084] The growth suppression film 7 may include a first film portion 71 in contact with the side surface SS of the seed portion S and a second film portion 72 in contact with the top surface ST of the seed portion S. The seed portion S includes an Al-based semiconductor layer AS (see FIG. 1 , etc.). Thus, the semiconductor substrate 10 may include at least one of a growth suppression film (second film portion 72) located above the Al-based semiconductor layer AS and a growth suppression film (first film portion 71) located on the side surface of the Al-based semiconductor layer AS. The growth suppression film 7 does not need to be a complete film and may be a film including one or more minute openings (an imperfectly shaped film). The growth suppression film 7 may have a uniform shape within its surface or may have a partially defective shape (a hole or a shape significantly thinner than the surrounding area). Forming the second film portion 72 suppresses threading dislocations and the like passing through the seed portion S, thereby improving the surface flatness and crystallinity of the top surface ST of the seed portion S.

[0085] The top surface ST of the seed portion S has a growth origin PG of the nitride semiconductor portion 8, and the growth origin PG may not contact the growth inhibitor film 7 or may contact a portion where the growth inhibitor film 7 is locally thin. A corner SC where the top surface ST and side surface SS of the seed portion S intersect may be included in the growth origin PG. The corner SC may be located above the semiconductor mask SM. That is, the seed portion S may protrude laterally from the opening K in a planar view, and the corner SC and the semiconductor mask SM may overlap in a planar view.

[0086] The thickness of the growth inhibiting film 7 may be thinner than the silicon-based mask 5 and may be thinner than the semiconductor mask SM. This makes it easier for the wing portions F to grow from the seed portions S while suppressing growth on the semiconductor mask SM. The thickness of the growth inhibiting film 7 may be ⅓ or less of the thickness of the silicon-based mask 5. The thickness of the growth inhibiting film 7 may be ⅓ or less of the thickness of the semiconductor mask SM. The thickness of the growth inhibiting film 7 may be about 1 nm, and it can be formed as a very thin film.

[0087] The growth inhibiting film 7 may be made of, for example, SiN, or may be made of SiON, SiGaO, or SiGaON depending on the film formation conditions. In Example 4, the growth inhibiting film 7 may contain silicon, and in this case, it was found that evaporation of silicon from the growth inhibiting film 7 is limited during the formation of the nitride semiconductor portion 8. This is thought to be because the thickness of the growth inhibiting film 7 is thin as described above, and because the constituent material of the semiconductor mask SM and the constituent material of the growth inhibiting film 7 can form a mixed crystal on the semiconductor mask SM.

[0088] The ratio of the width WJ in the X direction to the thickness TJ of the gap JD (aspect ratio of the gap) may be 5.0 or more. In this case, the crystallinity is high (the defect density is low), and a wide first wing portion F1 can be quickly formed. Furthermore, the flatness of the first wing portion F1 is improved. The first wing portion F1 has a silicon concentration of 5×10 １８ / cm ３ It can be as follows:

[0089] The thickness (height) TJ of the gap JD is the distance from the upper surface of the growth suppression film 7 on the semiconductor mask SM (equivalent to the upper surface SMT of the semiconductor mask SM) to the lower surface (back surface) of the nitride semiconductor portion 8. The width WJ of the gap JD is the distance in the X direction from the side surface of the seed portion S to the edge E1 of the nitride semiconductor portion 8.

[0090] The thickness TJ of the gap JD may be 5 μm or less, 2 μm or less, 1 μm or less, 0.6 μm or less, or 0.3 μm or less. The thickness TJ of the gap JD is preferably 0.05 μm (50 nm) or more. The aspect ratio of the gap JD can be 5.0 or more, 10 or more, 20 or more, 30 or more, 50 or more, or 100 or more. This allows the functional layer 9 (see FIG. 10 ) to be formed on the wide wing portion F while suppressing the backside rotation phenomenon, resulting in the formation of a high-quality (e.g., high light extraction efficiency) semiconductor device. The aspect ratio of the gap J may be, for example, 100 to 1000. This reduces the risk of the nitride semiconductor portion 8 warping upward due to gravity. The width of the gap GP may be greater than the thickness of the gap JD. Furthermore, the backside rotation phenomenon can be more effectively suppressed by setting the width of the gap GP to 30 μm or less, or 10 μm or less.

[0091] The first wing portion F1 may have the same shape as that of the above-described Example 1. The width of the first wing portion F1 is preferably 80.0 μm or less, which reduces the risk of the nitride semiconductor portion 8 warping upward due to gravity.

[0092] 19 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 4. As shown in Fig. 19, first, a template substrate TS is prepared. Next, using, for example, an MOCVD apparatus, the film formation temperature is set to about 1000°C or less, and SiH ４ (silane) and NH ３ A thin SiN film (for example, about 1 nm thick) is formed by supplying ammonia (ammonia) to the seed portion S. As a result, a growth suppression film 7 is formed on the upper surface ST and side surface SS of the seed portion S.

[0093] Next, the film formation temperature is increased to 250° C., and TMG (trimethylgallium) and ammonia are supplied to form the nitride semiconductor portion 8. At this time, the growth suppression film 7 significantly affects the formation of the nitride semiconductor portion 8, and the wing portions F are formed in a state where they are floating above the semiconductor mask SM. In other words, the back surfaces of the wing portions F of the nitride semiconductor portion 8 are completely separated from the semiconductor mask SM.

[0094] Furthermore, for example, both corners (two corners SC aligned in the X direction) of the seed portion S may become growth starting points PG, causing lateral film growth from both sides. In this case, a void may be formed in the first base portion B1 (particularly the central portion). In this manner, the first base portion B1 may include a void, which relieves stress from the template substrate TS. The void may be located above the second film portion 72 of the growth suppression film 7.

[0095] After the seed portion S on the template substrate TS is formed using an MOCVD apparatus, the growth suppression film 7 may be formed subsequently.

[0096] 20 is a cross-sectional view showing another configuration of the semiconductor substrate in Example 4. In the example shown in FIG. 17 , the height of the back surface BP of the nitride semiconductor portion 8 is formed to be approximately the same height as the top surface ST of the seed portion S, but in the example shown in FIG. 20 , the height of the back surface BP of the nitride semiconductor portion 8 is set to a position (lower position) below the top surface ST of the seed portion S. By controlling the film formation conditions of the nitride semiconductor portion 8 (film formation temperature, film formation time, gas flow rate, etc.), the shape of the formed nitride semiconductor portion 8 can be changed. In both the examples shown in FIG. 17 and FIG. 20 , the effects of Example 4 can be obtained.

[0097] Fifth Embodiment FIGS. 21 to 23 are cross-sectional views showing another configuration of a semiconductor substrate according to a fifth embodiment. As shown in FIGS. 21 to 23, the semiconductor substrate 10 may include a template substrate TS and a nitride semiconductor portion 8. The template substrate TS includes a base substrate BS, a mask pattern 6 located on the base substrate BS and including a silicon-based mask 5 containing silicon and a first opening K1, a semiconductor mask SM located on the silicon-based mask 5 and including aluminum, and a seed portion S having an Al-based semiconductor layer AS containing the main component of the semiconductor mask SM and overlapping the first opening K1. A continuous layer SF containing an Al-based nitride semiconductor (e.g., aluminum gallium nitride) may be formed to cover the mask pattern 6, thereby forming a semiconductor mask SM (low crystallinity) on the silicon-based mask 5 and an Al-based semiconductor layer AS (high crystallinity) thicker than the semiconductor mask SM, overlapping the first opening K1. A covering portion C may be provided to cover the upper surface of the Al-based semiconductor layer AS. An edge 8E of the nitride semiconductor portion 8 may be located above the semiconductor mask SM.

[0098] 22 , a raised portion 8R protruding from a seed portion S may be provided in the nitride semiconductor portion 8, and a growth suppression film 7 may be provided in contact with the side and top surfaces of the raised portion 8R, thereby floating the wings F of the nitride semiconductor portion 8 above the semiconductor mask SM (a gap JD may be provided between the wings F and the semiconductor mask SM). This reduces warping of the semiconductor substrate 10. As shown in FIG. 23 , a template substrate TS may be used on which a continuous layer SF of an Al-based nitride semiconductor (semiconductor mask SM and Al-based semiconductor layer AS) is formed while a raised portion 4T is formed on the surface of the underlayer 4 and its side surfaces are covered with a mask portion 5, thereby floating the wings F of the nitride semiconductor portion 8 above the semiconductor mask SM.

[0099] Sixth Embodiment Figure 24 is a plan view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in a sixth embodiment. Figure 25 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in a sixth embodiment. In the sixth embodiment, an example of manufacturing a semiconductor device 25 using the semiconductor substrate 10 of the fourth embodiment will be described. When manufacturing a semiconductor substrate 10 and a semiconductor device 25 using the template substrate TS of the first to third embodiments, a known method can be used, which can be easily understood with reference to the following description. For example, the base B and the functional layer 9 on the seed portion S can be removed, and the growth suppression film 7, the semiconductor mask SM, and the silicon-based mask 5 can be removed to separate the semiconductor device 25 from the template substrate TS.

[0100] 24 and 25 , a functional layer (device layer) 9 may be formed on the first nitride semiconductor portion 8A. For example, the functional layer 9 of an LED, a laser, a PD (light receiving element), a power device, or the like can be formed using MOCVD, MBE, sputtering, or the like. The active region (e.g., light emitting region ES) of the functional layer 9 may be formed above the first wing portion F1 (device region), which is a low-defect portion (low-dislocation portion) (so as to overlap the first wing portion F1 in a plan view).

[0101] Next, electrodes EA and EC (e.g., anode and cathode) are formed on the functional layer 9, and predetermined portions of the first nitride semiconductor portion 8A and the functional layer 9 are removed to perform element division. Specifically, separation grooves BM parallel to the X direction are formed in the first nitride semiconductor portion 8A and the functional layer 9, and the first nitride semiconductor portion 8A and the functional layer 9 located on the seed portion S are removed except for two paired tether portions TZ, thereby forming an element region PA. The two tether portions TZ are portions of both ends of the element region PA facing each other in the Y direction that are connected to the seed portion S.

[0102] Next, the element region PA (including the wing portion F, the functional layer 9, and the electrodes EA and EC) is separated from the template substrate TS to form the semiconductor device 25. Because there is a gap JD below the wing portion F, by applying downward pressure to the element region PA with a pressure member YS having adhesive properties (such as an adhesive plate, adhesive sheet, or adhesive substrate), the two tether portions TZ are easily broken, and the semiconductor device 25 is separated from the template substrate TS.

[0103] Specifically, the semiconductor device 25 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap JD also functions effectively in element isolation, and the semiconductor device 25 can be peeled off from the template substrate TS without being damaged.

[0104] [Other Configuration Examples] In the above-described Examples 1 to 6, examples have been described in which a gap GP exists between the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C, but the present invention is not limited to this. The nitride semiconductor portions 8 (first wing portion F1 and second wing portion F2) grown from adjacent seed portions S may be in contact (meet) with each other on the semiconductor mask SM. The semiconductor substrate 10 may not have a gap GP. Multiple nitride semiconductor portions 8 may be formed by removing the semiconductor crystal at the meeting portion.

[0105] FIG. 26 is a schematic diagram showing an example of the configuration of an electronic device. The electronic device 55 in FIG. 26 includes a semiconductor device 25 including a nitride semiconductor portion 8, a drive substrate 23 on which the semiconductor device 25 is mounted, and a control circuit 27 that controls the drive substrate 23. FIG. 27 is a schematic diagram showing another example of the configuration of an electronic device. The element region (element portion) PA does not need to be peeled off from the template substrate TS. The electronic device 55 in FIG. 27 includes a semiconductor substrate 10 including the template substrate TS and the element region PA, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 27 that controls the drive substrate 23. In this case, the main substrate 1 included in the template substrate TS may be an optically transparent substrate (e.g., a sapphire substrate). Examples of the electronic device 55 include a light-emitting device, a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a measurement device, an illumination device, a communication device, an information processing device, and a power control device.

[0106] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0107] [Summary] The template substrate in aspect 1 of the present disclosure includes a base substrate, a mask pattern located on the base substrate and including a silicon-based mask containing silicon and a first opening, a semiconductor mask located on the silicon-based mask and including aluminum, and a seed portion having an Al-based semiconductor layer containing a main component of the semiconductor mask and overlapping the first opening.

[0108] In a second aspect of the present disclosure, the template substrate is the first aspect, wherein the Al-based semiconductor layer is thicker than the semiconductor mask.

[0109] The template substrate according to aspect 3 of the present disclosure is the template substrate according to aspect 1 or 2, wherein the seed portion includes a covering layer that includes a nitride semiconductor and covers an upper surface of the Al-based semiconductor layer.

[0110] A template substrate according to Aspect 4 of the present disclosure is any one of Aspects 1 to 3, wherein the Al-based semiconductor layer has a shape that fills the first opening.

[0111] A template substrate in aspect 5 of the present disclosure is any one of aspects 1 to 4, wherein the base substrate comprises a main substrate and an underlayer located on the main substrate, and the Al-based semiconductor layer is located on the underlayer.

[0112] A sixth aspect of the present disclosure provides a template substrate according to any one of the first to fifth aspects, wherein the surface roughness of the semiconductor mask is greater than the surface roughness of the Al-based semiconductor layer.

[0113] A seventh aspect of the present disclosure provides a template substrate according to any one of the first to sixth aspects, wherein the surface roughness of the semiconductor mask is greater than the surface roughness of the silicon-based mask.

[0114] A template substrate according to an eighth aspect of the present disclosure is any one of the first to seventh aspects, wherein an upper surface of the seed portion is located higher than an upper surface of the semiconductor mask.

[0115] A template substrate in Aspect 9 of the present disclosure is any one of Aspects 1 to 8, wherein the seed portion includes a covering layer containing a nitride semiconductor and covering an upper surface of the Al-based semiconductor layer, and the surface roughness of the covering layer is smaller than the surface roughness of the Al-based semiconductor layer.

[0116] A tenth aspect of the present disclosure provides a template substrate according to any one of the first to ninth aspects, wherein the semiconductor mask has lower crystallinity than the Al-based semiconductor layer.

[0117] In an eleventh aspect of the present disclosure, the template substrate is the same as any one of the first to tenth aspects, wherein the semiconductor mask includes an amorphous structure.

[0118] A template substrate in aspect 12 of the present disclosure is any one of aspects 1 to 11, wherein the seed portion includes a covering layer containing a nitride semiconductor and covering an upper surface of the Al-based semiconductor layer, and the covering layer does not contain aluminum or has an aluminum content lower than that of the Al-based semiconductor layer.

[0119] A template substrate in aspect 13 of the present disclosure is any one of aspects 1 to 12, wherein the seed portion includes a covering layer that includes a nitride semiconductor and covers an upper surface of the Al-based semiconductor layer, and the covering layer is thicker than the Al-based semiconductor layer.

[0120] A template substrate according to a fourteenth aspect of the present disclosure is any one of the first to thirteenth aspects, wherein the semiconductor mask and the Al-based semiconductor layer are connected to each other.

[0121] A template substrate according to Aspect 15 of the present disclosure is any one of Aspects 1 to 14, in which the Al-based semiconductor layer is exposed.

[0122] A template substrate according to aspect 16 of the present disclosure is any one of aspects 1 to 15, wherein the silicon-based mask includes at least one of silicon nitride and silicon oxide, and the semiconductor mask and the Al-based semiconductor layer include aluminum gallium nitride.

[0123] A template substrate in aspect 17 of the present disclosure is any one of aspects 1 to 16, wherein the base substrate comprises a main substrate and an underlayer located on the main substrate, the main substrate being any one of a silicon wafer, a silicon carbide wafer, and a sapphire wafer, and the underlayer includes aluminum nitride.

[0124] In aspect 18 of the present disclosure, the template substrate is any one of aspects 1 to 17, wherein the mask pattern includes a second opening, and in a planar view, the silicon-based mask and the semiconductor mask are positioned between the first and second openings.

[0125] A template substrate in aspect 19 of the present disclosure is any one of aspects 1 to 18, wherein the semiconductor mask and the Al-based semiconductor layer contain aluminum gallium nitride, and the aluminum gallium nitride has a composition ratio of Al to Ga and Al of 0.05 or more.

[0126] A semiconductor substrate according to a twentieth aspect of the present disclosure includes the template substrate according to any one of the first to nineteenth aspects, and a first nitride semiconductor portion located above the first opening and the semiconductor mask.

[0127] In aspect 21 of the present disclosure, the semiconductor substrate is the same as aspect 20, except that the mask pattern includes a second opening, and in a planar view, the silicon-based mask and the semiconductor mask are located between the first and second openings, and a second nitride semiconductor portion is located above the second opening and the semiconductor mask, and a gap is located between the first and second nitride semiconductor portions.

[0128] A semiconductor substrate according to a twenty-second aspect of the present disclosure is the semiconductor substrate according to the twenty-first or twenty-first aspect, wherein a gap exists between the semiconductor mask and the first nitride semiconductor portion.

[0129] The semiconductor substrate in aspect 23 of the present disclosure is any one of aspects 20 to 22, and further comprises at least one of a growth suppression film located above the Al-based semiconductor layer and a growth suppression film located on a side of the Al-based semiconductor layer.

[0130] In a semiconductor substrate according to Aspect 24 of the present disclosure, in any one of Aspects 20 to 23, the first nitride semiconductor portion has a silicon concentration of 5×10 １８ / cm ３ The following is the result.

[0131] The semiconductor substrate according to Aspect 25 of the present disclosure is the semiconductor substrate according to any one of Aspects 20 to 24, further comprising a functional layer located on the first nitride semiconductor portion and including an active layer.

[0132] A method for manufacturing a template substrate in aspect 26 of the present disclosure includes the steps of: preparing a base substrate; forming a mask pattern located on the base substrate and including a silicon-based mask containing silicon and a first opening; and forming a semiconductor mask located on the silicon-based mask and including aluminum; and a seed portion having an Al-based semiconductor layer containing a main component of the semiconductor mask and overlapping the first opening.

[0133] The method for manufacturing a template substrate according to Aspect 27 of the present disclosure is the method according to Aspect 26, further comprising forming a covering layer containing a nitride semiconductor and covering an upper surface of the Al-based semiconductor layer.

[0134] The template substrate manufacturing apparatus according to aspect 28 of the present disclosure performs each step in aspect 26 or 27.

[0135] A method for manufacturing a semiconductor substrate in aspect 29 of the present disclosure includes a step of preparing a template substrate in any one of aspects 1 to 19, and a step of forming a first nitride semiconductor portion located above the first opening and the semiconductor mask.

[0136] A method for manufacturing a semiconductor substrate in aspect 30 of the present disclosure includes the steps of preparing a semiconductor substrate in any one of aspects 20 to 25, and forming a functional layer located on the first nitride semiconductor portion and including an active layer.

[0137] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 5 Silicon-based mask 6 Mask pattern 7 Growth suppression film 8 Nitride semiconductor portion 8A First nitride semiconductor portion 8C Second nitride semiconductor portion 9 Functional layer 10 Semiconductor substrate 25 Semiconductor device 30 Template substrate manufacturing apparatus AS Al-based semiconductor layer BS Base substrate B1 First base portion B2 Second base portion C1 First covering layer C2 Second covering layer DA Growth suppression region F1 First wing portion F2 Second wing portion J Seed region JD Void K1 First opening K2 Second opening SM Semiconductor mask S1 First seed portion S2 Second seed portion TS Template substrate

Claims

1. A template substrate comprising: a base substrate; a mask pattern located on the base substrate and including a first mask and a first opening; a second mask located on the first mask and including aluminum and a semiconductor; and a seed portion having a semiconductor layer including a main component of the second mask and overlapping the first opening.

2. The template substrate of claim 1, wherein the semiconductor layer is thicker than the second mask.

3. The template substrate according to claim 1 or 2, wherein the seed portion is provided with a covering layer that includes a nitride semiconductor and covers an upper surface of the semiconductor layer.

4. The template substrate according to claim 1, wherein the semiconductor layer is shaped to fill the first opening.

5. The template substrate according to any one of claims 1 to 4, wherein the base substrate comprises a main substrate and an underlayer located on the main substrate, and the semiconductor layer is located on the underlayer.

6. The template substrate according to claim 1, wherein the surface roughness of the second mask is greater than the surface roughness of the semiconductor layer.

7. The template substrate according to claim 1, wherein the surface roughness of the second mask is greater than the surface roughness of the first mask.

8. The template substrate according to claim 1, wherein an upper surface of the seed portion is located higher than an upper surface of the second mask.

9. The template substrate according to claim 3, wherein the surface roughness of the covering layer is less than the surface roughness of the semiconductor layer.

10. The template substrate according to claim 1, wherein the second mask has lower crystallinity than the semiconductor layer.

11. The template substrate according to any one of claims 1 to 10, wherein the second mask comprises an amorphous structure.

12. The template substrate of claim 3, wherein the covering layer is aluminum-free or has a lower aluminum content than the semiconductor layer.

13. The template substrate of claim 3, wherein the covering layer is thicker than the semiconductor layer.

14. The template substrate of claim 1, wherein the second mask and the semiconductor layer are contiguous.

15. The template substrate according to any one of claims 1 to 14, wherein the semiconductor layer is exposed.

16. The template substrate of any one of claims 1 to 15, wherein the first mask includes at least one of silicon nitride and silicon oxide, and the second mask and the semiconductor layer include aluminum gallium nitride.

17. The template substrate according to claim 5, wherein the main substrate is one of a silicon wafer, a silicon carbide wafer, and a sapphire wafer, and the underlayer includes aluminum nitride.

18. A template substrate according to any one of claims 1 to 17, wherein the mask pattern includes a second opening, and the first mask and the second mask are located between the first and second openings in a plan view.

19. The template substrate according to claim 16, wherein in the aluminum gallium nitride, the composition ratio of Al to Ga and Al is 0.05 or more.

20. A semiconductor substrate comprising: a template substrate according to any one of claims 1 to 19; and a first nitride semiconductor portion located above the first opening and the second mask.

21. The semiconductor substrate of claim 20, wherein the mask pattern includes a second opening, the first mask and the second mask are located between the first and second openings in a planar view, and a second nitride semiconductor portion is located above the second opening and the second mask, and a gap is located between the first and second nitride semiconductor portions.

22. The semiconductor substrate according to claim 20 or 21, wherein a gap exists between the second mask and the first nitride semiconductor portion.

23. The semiconductor substrate according to any one of claims 20 to 22, comprising at least one of a growth suppression film located above the semiconductor layer and a growth suppression film located on a side surface of the semiconductor layer.

24. In the first nitride semiconductor portion, the silicon concentration of the back surface portion facing the second mask is 5×10 １８ / cm ３ 24. The semiconductor substrate according to claim 20, wherein:

25. The semiconductor wafer according to claim 20, further comprising a functional layer including an active layer, the functional layer being located on the first nitride semiconductor portion.

26. A method for manufacturing a template substrate, comprising: a step of preparing a base substrate; a step of forming a mask pattern located on the base substrate and including a first mask and a first opening; and a step of forming a second mask located on the first mask and including aluminum and a semiconductor, and a seed portion having a semiconductor layer including a main component of the second mask and overlapping the first opening.

27. The method for producing a template substrate according to claim 26, further comprising the step of forming a covering layer containing a nitride semiconductor and covering an upper surface of the semiconductor layer.

28. A template substrate manufacturing apparatus which performs each of the steps recited in claim 26 or 27.

29. A method for manufacturing a semiconductor substrate, comprising: preparing a template substrate according to any one of claims 1 to 19; and forming a first nitride semiconductor portion located above the first opening and the second mask.

30. A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate according to any one of claims 20 to 25; and forming a functional layer, including an active layer, located on the first nitride semiconductor portion.

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